1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
34 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35 (port) == PORT_B ? (b) : (c))
37 #define _MASKED_FIELD(mask, value) ({ \
38 if (__builtin_constant_p(mask)) \
39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40 if (__builtin_constant_p(value)) \
41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
43 BUILD_BUG_ON_MSG((value) & ~(mask), \
44 "Incorrect value for mask"); \
45 (mask) << 16 | (value); })
46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
51 /* PCI config space */
53 #define HPLLCC 0xc0 /* 85x only */
54 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
55 #define GC_CLOCK_133_200 (0 << 0)
56 #define GC_CLOCK_100_200 (1 << 0)
57 #define GC_CLOCK_100_133 (2 << 0)
58 #define GC_CLOCK_133_266 (3 << 0)
59 #define GC_CLOCK_133_200_2 (4 << 0)
60 #define GC_CLOCK_133_266_2 (5 << 0)
61 #define GC_CLOCK_166_266 (6 << 0)
62 #define GC_CLOCK_166_250 (7 << 0)
65 #define GCFGC 0xf0 /* 915+ only */
66 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
67 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
68 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
69 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
70 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
71 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
72 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
73 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
74 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
75 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
76 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
77 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
78 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
79 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
80 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
81 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
82 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
83 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
84 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
85 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
86 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
87 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
90 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
91 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
92 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
93 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
94 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
96 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
99 /* Graphics reset regs */
100 #define I915_GDRST 0xc0 /* PCI config register */
101 #define GRDOM_FULL (0<<2)
102 #define GRDOM_RENDER (1<<2)
103 #define GRDOM_MEDIA (3<<2)
104 #define GRDOM_MASK (3<<2)
105 #define GRDOM_RESET_STATUS (1<<1)
106 #define GRDOM_RESET_ENABLE (1<<0)
108 #define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
109 #define ILK_GRDOM_FULL (0<<1)
110 #define ILK_GRDOM_RENDER (1<<1)
111 #define ILK_GRDOM_MEDIA (3<<1)
112 #define ILK_GRDOM_MASK (3<<1)
113 #define ILK_GRDOM_RESET_ENABLE (1<<0)
115 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
116 #define GEN6_MBC_SNPCR_SHIFT 21
117 #define GEN6_MBC_SNPCR_MASK (3<<21)
118 #define GEN6_MBC_SNPCR_MAX (0<<21)
119 #define GEN6_MBC_SNPCR_MED (1<<21)
120 #define GEN6_MBC_SNPCR_LOW (2<<21)
121 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
123 #define VLV_G3DCTL 0x9024
124 #define VLV_GSCKGCTL 0x9028
126 #define GEN6_MBCTL 0x0907c
127 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
128 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
129 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
130 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
131 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
133 #define GEN6_GDRST 0x941c
134 #define GEN6_GRDOM_FULL (1 << 0)
135 #define GEN6_GRDOM_RENDER (1 << 1)
136 #define GEN6_GRDOM_MEDIA (1 << 2)
137 #define GEN6_GRDOM_BLT (1 << 3)
139 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
140 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
141 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
142 #define PP_DIR_DCLV_2G 0xffffffff
144 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
145 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
147 #define GEN8_R_PWR_CLK_STATE 0x20C8
148 #define GEN8_RPCS_ENABLE (1 << 31)
149 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
150 #define GEN8_RPCS_S_CNT_SHIFT 15
151 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
152 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
153 #define GEN8_RPCS_SS_CNT_SHIFT 8
154 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
155 #define GEN8_RPCS_EU_MAX_SHIFT 4
156 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
157 #define GEN8_RPCS_EU_MIN_SHIFT 0
158 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
160 #define GAM_ECOCHK 0x4090
161 #define BDW_DISABLE_HDC_INVALIDATION (1<<25)
162 #define ECOCHK_SNB_BIT (1<<10)
163 #define ECOCHK_DIS_TLB (1<<8)
164 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
165 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
166 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
167 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
168 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
169 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
170 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
171 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
173 #define GAC_ECO_BITS 0x14090
174 #define ECOBITS_SNB_BIT (1<<13)
175 #define ECOBITS_PPGTT_CACHE64B (3<<8)
176 #define ECOBITS_PPGTT_CACHE4B (0<<8)
178 #define GAB_CTL 0x24000
179 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
181 #define GEN6_STOLEN_RESERVED 0x1082C0
182 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
183 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
184 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
185 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
186 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
187 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
188 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
189 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
190 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
191 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
192 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
193 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
194 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
195 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
196 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
200 #define VGA_ST01_MDA 0x3ba
201 #define VGA_ST01_CGA 0x3da
203 #define VGA_MSR_WRITE 0x3c2
204 #define VGA_MSR_READ 0x3cc
205 #define VGA_MSR_MEM_EN (1<<1)
206 #define VGA_MSR_CGA_MODE (1<<0)
208 #define VGA_SR_INDEX 0x3c4
210 #define VGA_SR_DATA 0x3c5
212 #define VGA_AR_INDEX 0x3c0
213 #define VGA_AR_VID_EN (1<<5)
214 #define VGA_AR_DATA_WRITE 0x3c0
215 #define VGA_AR_DATA_READ 0x3c1
217 #define VGA_GR_INDEX 0x3ce
218 #define VGA_GR_DATA 0x3cf
220 #define VGA_GR_MEM_READ_MODE_SHIFT 3
221 #define VGA_GR_MEM_READ_MODE_PLANE 1
223 #define VGA_GR_MEM_MODE_MASK 0xc
224 #define VGA_GR_MEM_MODE_SHIFT 2
225 #define VGA_GR_MEM_A0000_AFFFF 0
226 #define VGA_GR_MEM_A0000_BFFFF 1
227 #define VGA_GR_MEM_B0000_B7FFF 2
228 #define VGA_GR_MEM_B0000_BFFFF 3
230 #define VGA_DACMASK 0x3c6
231 #define VGA_DACRX 0x3c7
232 #define VGA_DACWX 0x3c8
233 #define VGA_DACDATA 0x3c9
235 #define VGA_CR_INDEX_MDA 0x3b4
236 #define VGA_CR_DATA_MDA 0x3b5
237 #define VGA_CR_INDEX_CGA 0x3d4
238 #define VGA_CR_DATA_CGA 0x3d5
241 * Instruction field definitions used by the command parser
243 #define INSTR_CLIENT_SHIFT 29
244 #define INSTR_CLIENT_MASK 0xE0000000
245 #define INSTR_MI_CLIENT 0x0
246 #define INSTR_BC_CLIENT 0x2
247 #define INSTR_RC_CLIENT 0x3
248 #define INSTR_SUBCLIENT_SHIFT 27
249 #define INSTR_SUBCLIENT_MASK 0x18000000
250 #define INSTR_MEDIA_SUBCLIENT 0x2
251 #define INSTR_26_TO_24_MASK 0x7000000
252 #define INSTR_26_TO_24_SHIFT 24
255 * Memory interface instructions used by the kernel
257 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
258 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
259 #define MI_GLOBAL_GTT (1<<22)
261 #define MI_NOOP MI_INSTR(0, 0)
262 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
263 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
264 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
265 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
266 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
267 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
268 #define MI_FLUSH MI_INSTR(0x04, 0)
269 #define MI_READ_FLUSH (1 << 0)
270 #define MI_EXE_FLUSH (1 << 1)
271 #define MI_NO_WRITE_FLUSH (1 << 2)
272 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
273 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
274 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
275 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
276 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
277 #define MI_ARB_ENABLE (1<<0)
278 #define MI_ARB_DISABLE (0<<0)
279 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
280 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
281 #define MI_SUSPEND_FLUSH_EN (1<<0)
282 #define MI_SET_APPID MI_INSTR(0x0e, 0)
283 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
284 #define MI_OVERLAY_CONTINUE (0x0<<21)
285 #define MI_OVERLAY_ON (0x1<<21)
286 #define MI_OVERLAY_OFF (0x2<<21)
287 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
288 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
289 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
290 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
291 /* IVB has funny definitions for which plane to flip. */
292 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
293 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
294 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
295 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
296 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
297 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
299 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
300 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
301 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
302 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
303 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
304 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
305 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
306 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
307 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
308 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
309 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
310 #define MI_SEMAPHORE_UPDATE (1<<21)
311 #define MI_SEMAPHORE_COMPARE (1<<20)
312 #define MI_SEMAPHORE_REGISTER (1<<18)
313 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
314 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
315 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
316 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
317 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
318 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
319 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
320 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
321 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
322 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
323 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
324 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
325 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
326 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
327 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
328 #define MI_MM_SPACE_GTT (1<<8)
329 #define MI_MM_SPACE_PHYSICAL (0<<8)
330 #define MI_SAVE_EXT_STATE_EN (1<<3)
331 #define MI_RESTORE_EXT_STATE_EN (1<<2)
332 #define MI_FORCE_RESTORE (1<<1)
333 #define MI_RESTORE_INHIBIT (1<<0)
334 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
335 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
336 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
337 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
338 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
339 #define MI_SEMAPHORE_POLL (1<<15)
340 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
341 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
342 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
343 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
344 #define MI_USE_GGTT (1 << 22) /* g4x+ */
345 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
346 #define MI_STORE_DWORD_INDEX_SHIFT 2
347 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
348 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
349 * simply ignores the register load under certain conditions.
350 * - One can actually load arbitrary many arbitrary registers: Simply issue x
351 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
353 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
354 #define MI_LRI_FORCE_POSTED (1<<12)
355 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
356 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
357 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
358 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
359 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
360 #define MI_INVALIDATE_TLB (1<<18)
361 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
362 #define MI_FLUSH_DW_OP_MASK (3<<14)
363 #define MI_FLUSH_DW_NOTIFY (1<<8)
364 #define MI_INVALIDATE_BSD (1<<7)
365 #define MI_FLUSH_DW_USE_GTT (1<<2)
366 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
367 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
368 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
369 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
370 #define MI_BATCH_NON_SECURE (1)
371 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
372 #define MI_BATCH_NON_SECURE_I965 (1<<8)
373 #define MI_BATCH_PPGTT_HSW (1<<8)
374 #define MI_BATCH_NON_SECURE_HSW (1<<13)
375 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
376 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
377 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
378 #define MI_BATCH_RESOURCE_STREAMER (1<<10)
380 #define MI_PREDICATE_SRC0 (0x2400)
381 #define MI_PREDICATE_SRC1 (0x2408)
383 #define MI_PREDICATE_RESULT_2 (0x2214)
384 #define LOWER_SLICE_ENABLED (1<<0)
385 #define LOWER_SLICE_DISABLED (0<<0)
388 * 3D instructions used by the kernel
390 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
392 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
393 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
394 #define SC_UPDATE_SCISSOR (0x1<<1)
395 #define SC_ENABLE_MASK (0x1<<0)
396 #define SC_ENABLE (0x1<<0)
397 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
398 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
399 #define SCI_YMIN_MASK (0xffff<<16)
400 #define SCI_XMIN_MASK (0xffff<<0)
401 #define SCI_YMAX_MASK (0xffff<<16)
402 #define SCI_XMAX_MASK (0xffff<<0)
403 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
404 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
405 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
406 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
407 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
408 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
409 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
410 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
411 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
413 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
414 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
415 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
416 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
417 #define BLT_WRITE_A (2<<20)
418 #define BLT_WRITE_RGB (1<<20)
419 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
420 #define BLT_DEPTH_8 (0<<24)
421 #define BLT_DEPTH_16_565 (1<<24)
422 #define BLT_DEPTH_16_1555 (2<<24)
423 #define BLT_DEPTH_32 (3<<24)
424 #define BLT_ROP_SRC_COPY (0xcc<<16)
425 #define BLT_ROP_COLOR_COPY (0xf0<<16)
426 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
427 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
428 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
429 #define ASYNC_FLIP (1<<22)
430 #define DISPLAY_PLANE_A (0<<20)
431 #define DISPLAY_PLANE_B (1<<20)
432 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
433 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
434 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
435 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
436 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
437 #define PIPE_CONTROL_CS_STALL (1<<20)
438 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
439 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
440 #define PIPE_CONTROL_QW_WRITE (1<<14)
441 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
442 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
443 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
444 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
445 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
446 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
447 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
448 #define PIPE_CONTROL_NOTIFY (1<<8)
449 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
450 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
451 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
452 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
453 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
454 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
455 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
456 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
459 * Commands used only by the command parser
461 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
462 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
463 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
464 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
465 #define MI_PREDICATE MI_INSTR(0x0C, 0)
466 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
467 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
468 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
469 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
470 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
471 #define MI_CLFLUSH MI_INSTR(0x27, 0)
472 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
473 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
474 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
475 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
476 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
477 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
478 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
480 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
481 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
482 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
483 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
484 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
485 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
486 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
487 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
488 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
489 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
490 #define GFX_OP_3DSTATE_SO_DECL_LIST \
491 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
493 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
494 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
495 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
496 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
497 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
498 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
499 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
500 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
501 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
502 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
504 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
506 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
507 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
510 * Registers used only by the command parser
512 #define BCS_SWCTRL 0x22200
514 #define GPGPU_THREADS_DISPATCHED 0x2290
515 #define HS_INVOCATION_COUNT 0x2300
516 #define DS_INVOCATION_COUNT 0x2308
517 #define IA_VERTICES_COUNT 0x2310
518 #define IA_PRIMITIVES_COUNT 0x2318
519 #define VS_INVOCATION_COUNT 0x2320
520 #define GS_INVOCATION_COUNT 0x2328
521 #define GS_PRIMITIVES_COUNT 0x2330
522 #define CL_INVOCATION_COUNT 0x2338
523 #define CL_PRIMITIVES_COUNT 0x2340
524 #define PS_INVOCATION_COUNT 0x2348
525 #define PS_DEPTH_COUNT 0x2350
527 /* There are the 4 64-bit counter registers, one for each stream output */
528 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
530 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
532 #define GEN7_3DPRIM_END_OFFSET 0x2420
533 #define GEN7_3DPRIM_START_VERTEX 0x2430
534 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
535 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
536 #define GEN7_3DPRIM_START_INSTANCE 0x243C
537 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
539 #define GEN7_GPGPU_DISPATCHDIMX 0x2500
540 #define GEN7_GPGPU_DISPATCHDIMY 0x2504
541 #define GEN7_GPGPU_DISPATCHDIMZ 0x2508
543 #define OACONTROL 0x2360
545 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
546 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
547 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
548 _GEN7_PIPEA_DE_LOAD_SL, \
549 _GEN7_PIPEB_DE_LOAD_SL)
554 #define DEBUG_RESET_I830 0x6070
555 #define DEBUG_RESET_FULL (1<<7)
556 #define DEBUG_RESET_RENDER (1<<8)
557 #define DEBUG_RESET_DISPLAY (1<<9)
562 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
563 #define IOSF_DEVFN_SHIFT 24
564 #define IOSF_OPCODE_SHIFT 16
565 #define IOSF_PORT_SHIFT 8
566 #define IOSF_BYTE_ENABLES_SHIFT 4
567 #define IOSF_BAR_SHIFT 1
568 #define IOSF_SB_BUSY (1<<0)
569 #define IOSF_PORT_BUNIT 0x3
570 #define IOSF_PORT_PUNIT 0x4
571 #define IOSF_PORT_NC 0x11
572 #define IOSF_PORT_DPIO 0x12
573 #define IOSF_PORT_DPIO_2 0x1a
574 #define IOSF_PORT_GPIO_NC 0x13
575 #define IOSF_PORT_CCK 0x14
576 #define IOSF_PORT_CCU 0xA9
577 #define IOSF_PORT_GPS_CORE 0x48
578 #define IOSF_PORT_FLISDSI 0x1B
579 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
580 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
582 /* See configdb bunit SB addr map */
583 #define BUNIT_REG_BISOC 0x11
585 #define PUNIT_REG_DSPFREQ 0x36
586 #define DSPFREQSTAT_SHIFT_CHV 24
587 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
588 #define DSPFREQGUAR_SHIFT_CHV 8
589 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
590 #define DSPFREQSTAT_SHIFT 30
591 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
592 #define DSPFREQGUAR_SHIFT 14
593 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
594 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
595 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
596 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
597 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
598 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
599 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
600 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
601 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
602 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
603 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
604 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
605 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
606 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
607 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
608 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
610 /* See the PUNIT HAS v0.8 for the below bits */
611 enum punit_power_well {
612 PUNIT_POWER_WELL_RENDER = 0,
613 PUNIT_POWER_WELL_MEDIA = 1,
614 PUNIT_POWER_WELL_DISP2D = 3,
615 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
616 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
617 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
618 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
619 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
620 PUNIT_POWER_WELL_DPIO_RX0 = 10,
621 PUNIT_POWER_WELL_DPIO_RX1 = 11,
622 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
624 PUNIT_POWER_WELL_NUM,
627 enum skl_disp_power_wells {
637 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
638 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
640 #define PUNIT_REG_PWRGT_CTRL 0x60
641 #define PUNIT_REG_PWRGT_STATUS 0x61
642 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
643 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
644 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
645 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
646 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
648 #define PUNIT_REG_GPU_LFM 0xd3
649 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
650 #define PUNIT_REG_GPU_FREQ_STS 0xd8
651 #define GPLLENABLE (1<<4)
652 #define GENFREQSTATUS (1<<0)
653 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
654 #define PUNIT_REG_CZ_TIMESTAMP 0xce
656 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
657 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
659 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
660 #define FB_GFX_FREQ_FUSE_MASK 0xff
661 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
662 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
663 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
665 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
666 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
668 #define PUNIT_REG_DDR_SETUP2 0x139
669 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
670 #define FORCE_DDR_LOW_FREQ (1 << 1)
671 #define FORCE_DDR_HIGH_FREQ (1 << 0)
673 #define PUNIT_GPU_STATUS_REG 0xdb
674 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
675 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
676 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
677 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
679 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
680 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
681 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
683 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
684 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
685 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
686 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
687 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
688 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
689 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
690 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
691 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
692 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
694 #define VLV_TURBO_SOC_OVERRIDE 0x04
695 #define VLV_OVERRIDE_EN 1
696 #define VLV_SOC_TDP_EN (1 << 1)
697 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
698 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
700 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
702 /* vlv2 north clock has */
703 #define CCK_FUSE_REG 0x8
704 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
705 #define CCK_REG_DSI_PLL_FUSE 0x44
706 #define CCK_REG_DSI_PLL_CONTROL 0x48
707 #define DSI_PLL_VCO_EN (1 << 31)
708 #define DSI_PLL_LDO_GATE (1 << 30)
709 #define DSI_PLL_P1_POST_DIV_SHIFT 17
710 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
711 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
712 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
713 #define DSI_PLL_MUX_MASK (3 << 9)
714 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
715 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
716 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
717 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
718 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
719 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
720 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
721 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
722 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
723 #define DSI_PLL_LOCK (1 << 0)
724 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
725 #define DSI_PLL_LFSR (1 << 31)
726 #define DSI_PLL_FRACTION_EN (1 << 30)
727 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
728 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
729 #define DSI_PLL_USYNC_CNT_SHIFT 18
730 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
731 #define DSI_PLL_N1_DIV_SHIFT 16
732 #define DSI_PLL_N1_DIV_MASK (3 << 16)
733 #define DSI_PLL_M1_DIV_SHIFT 0
734 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
735 #define CCK_CZ_CLOCK_CONTROL 0x62
736 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
737 #define CCK_TRUNK_FORCE_ON (1 << 17)
738 #define CCK_TRUNK_FORCE_OFF (1 << 16)
739 #define CCK_FREQUENCY_STATUS (0x1f << 8)
740 #define CCK_FREQUENCY_STATUS_SHIFT 8
741 #define CCK_FREQUENCY_VALUES (0x1f << 0)
746 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
747 * ports. DPIO is the name given to such a display PHY. These PHYs
748 * don't follow the standard programming model using direct MMIO
749 * registers, and instead their registers must be accessed trough IOSF
750 * sideband. VLV has one such PHY for driving ports B and C, and CHV
751 * adds another PHY for driving port D. Each PHY responds to specific
754 * Each display PHY is made up of one or two channels. Each channel
755 * houses a common lane part which contains the PLL and other common
756 * logic. CH0 common lane also contains the IOSF-SB logic for the
757 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
758 * must be running when any DPIO registers are accessed.
760 * In addition to having their own registers, the PHYs are also
761 * controlled through some dedicated signals from the display
762 * controller. These include PLL reference clock enable, PLL enable,
763 * and CRI clock selection, for example.
765 * Eeach channel also has two splines (also called data lanes), and
766 * each spline is made up of one Physical Access Coding Sub-Layer
767 * (PCS) block and two TX lanes. So each channel has two PCS blocks
768 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
769 * data/clock pairs depending on the output type.
771 * Additionally the PHY also contains an AUX lane with AUX blocks
772 * for each channel. This is used for DP AUX communication, but
773 * this fact isn't really relevant for the driver since AUX is
774 * controlled from the display controller side. No DPIO registers
775 * need to be accessed during AUX communication,
777 * Generally on VLV/CHV the common lane corresponds to the pipe and
778 * the spline (PCS/TX) corresponds to the port.
780 * For dual channel PHY (VLV/CHV):
782 * pipe A == CMN/PLL/REF CH0
784 * pipe B == CMN/PLL/REF CH1
786 * port B == PCS/TX CH0
788 * port C == PCS/TX CH1
790 * This is especially important when we cross the streams
791 * ie. drive port B with pipe B, or port C with pipe A.
793 * For single channel PHY (CHV):
795 * pipe C == CMN/PLL/REF CH0
797 * port D == PCS/TX CH0
799 * On BXT the entire PHY channel corresponds to the port. That means
800 * the PLL is also now associated with the port rather than the pipe,
801 * and so the clock needs to be routed to the appropriate transcoder.
802 * Port A PLL is directly connected to transcoder EDP and port B/C
803 * PLLs can be routed to any transcoder A/B/C.
805 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
806 * digital port D (CHV) or port A (BXT).
809 * Dual channel PHY (VLV/CHV/BXT)
810 * ---------------------------------
812 * | CMN/PLL/REF | CMN/PLL/REF |
813 * |---------------|---------------| Display PHY
814 * | PCS01 | PCS23 | PCS01 | PCS23 |
815 * |-------|-------|-------|-------|
816 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
817 * ---------------------------------
818 * | DDI0 | DDI1 | DP/HDMI ports
819 * ---------------------------------
821 * Single channel PHY (CHV/BXT)
825 * |---------------| Display PHY
830 * | DDI2 | DP/HDMI port
835 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
836 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
837 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
838 #define DPIO_SFR_BYPASS (1<<1)
839 #define DPIO_CMNRST (1<<0)
841 #define DPIO_PHY(pipe) ((pipe) >> 1)
842 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
845 * Per pipe/PLL DPIO regs
847 #define _VLV_PLL_DW3_CH0 0x800c
848 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
849 #define DPIO_POST_DIV_DAC 0
850 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
851 #define DPIO_POST_DIV_LVDS1 2
852 #define DPIO_POST_DIV_LVDS2 3
853 #define DPIO_K_SHIFT (24) /* 4 bits */
854 #define DPIO_P1_SHIFT (21) /* 3 bits */
855 #define DPIO_P2_SHIFT (16) /* 5 bits */
856 #define DPIO_N_SHIFT (12) /* 4 bits */
857 #define DPIO_ENABLE_CALIBRATION (1<<11)
858 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
859 #define DPIO_M2DIV_MASK 0xff
860 #define _VLV_PLL_DW3_CH1 0x802c
861 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
863 #define _VLV_PLL_DW5_CH0 0x8014
864 #define DPIO_REFSEL_OVERRIDE 27
865 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
866 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
867 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
868 #define DPIO_PLL_REFCLK_SEL_MASK 3
869 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
870 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
871 #define _VLV_PLL_DW5_CH1 0x8034
872 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
874 #define _VLV_PLL_DW7_CH0 0x801c
875 #define _VLV_PLL_DW7_CH1 0x803c
876 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
878 #define _VLV_PLL_DW8_CH0 0x8040
879 #define _VLV_PLL_DW8_CH1 0x8060
880 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
882 #define VLV_PLL_DW9_BCAST 0xc044
883 #define _VLV_PLL_DW9_CH0 0x8044
884 #define _VLV_PLL_DW9_CH1 0x8064
885 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
887 #define _VLV_PLL_DW10_CH0 0x8048
888 #define _VLV_PLL_DW10_CH1 0x8068
889 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
891 #define _VLV_PLL_DW11_CH0 0x804c
892 #define _VLV_PLL_DW11_CH1 0x806c
893 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
895 /* Spec for ref block start counts at DW10 */
896 #define VLV_REF_DW13 0x80ac
898 #define VLV_CMN_DW0 0x8100
901 * Per DDI channel DPIO regs
904 #define _VLV_PCS_DW0_CH0 0x8200
905 #define _VLV_PCS_DW0_CH1 0x8400
906 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
907 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
908 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
909 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
910 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
912 #define _VLV_PCS01_DW0_CH0 0x200
913 #define _VLV_PCS23_DW0_CH0 0x400
914 #define _VLV_PCS01_DW0_CH1 0x2600
915 #define _VLV_PCS23_DW0_CH1 0x2800
916 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
917 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
919 #define _VLV_PCS_DW1_CH0 0x8204
920 #define _VLV_PCS_DW1_CH1 0x8404
921 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
922 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
923 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
924 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
925 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
926 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
928 #define _VLV_PCS01_DW1_CH0 0x204
929 #define _VLV_PCS23_DW1_CH0 0x404
930 #define _VLV_PCS01_DW1_CH1 0x2604
931 #define _VLV_PCS23_DW1_CH1 0x2804
932 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
933 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
935 #define _VLV_PCS_DW8_CH0 0x8220
936 #define _VLV_PCS_DW8_CH1 0x8420
937 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
938 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
939 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
941 #define _VLV_PCS01_DW8_CH0 0x0220
942 #define _VLV_PCS23_DW8_CH0 0x0420
943 #define _VLV_PCS01_DW8_CH1 0x2620
944 #define _VLV_PCS23_DW8_CH1 0x2820
945 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
946 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
948 #define _VLV_PCS_DW9_CH0 0x8224
949 #define _VLV_PCS_DW9_CH1 0x8424
950 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
951 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
952 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
953 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
954 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
955 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
956 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
958 #define _VLV_PCS01_DW9_CH0 0x224
959 #define _VLV_PCS23_DW9_CH0 0x424
960 #define _VLV_PCS01_DW9_CH1 0x2624
961 #define _VLV_PCS23_DW9_CH1 0x2824
962 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
963 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
965 #define _CHV_PCS_DW10_CH0 0x8228
966 #define _CHV_PCS_DW10_CH1 0x8428
967 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
968 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
969 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
970 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
971 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
972 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
973 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
974 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
975 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
977 #define _VLV_PCS01_DW10_CH0 0x0228
978 #define _VLV_PCS23_DW10_CH0 0x0428
979 #define _VLV_PCS01_DW10_CH1 0x2628
980 #define _VLV_PCS23_DW10_CH1 0x2828
981 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
982 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
984 #define _VLV_PCS_DW11_CH0 0x822c
985 #define _VLV_PCS_DW11_CH1 0x842c
986 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
987 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
988 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
989 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
990 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
992 #define _VLV_PCS01_DW11_CH0 0x022c
993 #define _VLV_PCS23_DW11_CH0 0x042c
994 #define _VLV_PCS01_DW11_CH1 0x262c
995 #define _VLV_PCS23_DW11_CH1 0x282c
996 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
997 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
999 #define _VLV_PCS01_DW12_CH0 0x0230
1000 #define _VLV_PCS23_DW12_CH0 0x0430
1001 #define _VLV_PCS01_DW12_CH1 0x2630
1002 #define _VLV_PCS23_DW12_CH1 0x2830
1003 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1004 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1006 #define _VLV_PCS_DW12_CH0 0x8230
1007 #define _VLV_PCS_DW12_CH1 0x8430
1008 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1009 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1010 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1011 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1012 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1013 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1015 #define _VLV_PCS_DW14_CH0 0x8238
1016 #define _VLV_PCS_DW14_CH1 0x8438
1017 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1019 #define _VLV_PCS_DW23_CH0 0x825c
1020 #define _VLV_PCS_DW23_CH1 0x845c
1021 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1023 #define _VLV_TX_DW2_CH0 0x8288
1024 #define _VLV_TX_DW2_CH1 0x8488
1025 #define DPIO_SWING_MARGIN000_SHIFT 16
1026 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1027 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1028 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1030 #define _VLV_TX_DW3_CH0 0x828c
1031 #define _VLV_TX_DW3_CH1 0x848c
1032 /* The following bit for CHV phy */
1033 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1034 #define DPIO_SWING_MARGIN101_SHIFT 16
1035 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1036 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1038 #define _VLV_TX_DW4_CH0 0x8290
1039 #define _VLV_TX_DW4_CH1 0x8490
1040 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1041 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1042 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1043 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1044 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1046 #define _VLV_TX3_DW4_CH0 0x690
1047 #define _VLV_TX3_DW4_CH1 0x2a90
1048 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1050 #define _VLV_TX_DW5_CH0 0x8294
1051 #define _VLV_TX_DW5_CH1 0x8494
1052 #define DPIO_TX_OCALINIT_EN (1<<31)
1053 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1055 #define _VLV_TX_DW11_CH0 0x82ac
1056 #define _VLV_TX_DW11_CH1 0x84ac
1057 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1059 #define _VLV_TX_DW14_CH0 0x82b8
1060 #define _VLV_TX_DW14_CH1 0x84b8
1061 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1063 /* CHV dpPhy registers */
1064 #define _CHV_PLL_DW0_CH0 0x8000
1065 #define _CHV_PLL_DW0_CH1 0x8180
1066 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1068 #define _CHV_PLL_DW1_CH0 0x8004
1069 #define _CHV_PLL_DW1_CH1 0x8184
1070 #define DPIO_CHV_N_DIV_SHIFT 8
1071 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1072 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1074 #define _CHV_PLL_DW2_CH0 0x8008
1075 #define _CHV_PLL_DW2_CH1 0x8188
1076 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1078 #define _CHV_PLL_DW3_CH0 0x800c
1079 #define _CHV_PLL_DW3_CH1 0x818c
1080 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1081 #define DPIO_CHV_FIRST_MOD (0 << 8)
1082 #define DPIO_CHV_SECOND_MOD (1 << 8)
1083 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1084 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1085 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1087 #define _CHV_PLL_DW6_CH0 0x8018
1088 #define _CHV_PLL_DW6_CH1 0x8198
1089 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1090 #define DPIO_CHV_INT_COEFF_SHIFT 8
1091 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1092 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1094 #define _CHV_PLL_DW8_CH0 0x8020
1095 #define _CHV_PLL_DW8_CH1 0x81A0
1096 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1097 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1098 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1100 #define _CHV_PLL_DW9_CH0 0x8024
1101 #define _CHV_PLL_DW9_CH1 0x81A4
1102 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1103 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1104 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1105 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1107 #define _CHV_CMN_DW0_CH0 0x8100
1108 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1109 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1110 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1111 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1113 #define _CHV_CMN_DW5_CH0 0x8114
1114 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1115 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1116 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1117 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1118 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1119 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1120 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1121 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1123 #define _CHV_CMN_DW13_CH0 0x8134
1124 #define _CHV_CMN_DW0_CH1 0x8080
1125 #define DPIO_CHV_S1_DIV_SHIFT 21
1126 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1127 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1128 #define DPIO_CHV_K_DIV_SHIFT 4
1129 #define DPIO_PLL_FREQLOCK (1 << 1)
1130 #define DPIO_PLL_LOCK (1 << 0)
1131 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1133 #define _CHV_CMN_DW14_CH0 0x8138
1134 #define _CHV_CMN_DW1_CH1 0x8084
1135 #define DPIO_AFC_RECAL (1 << 14)
1136 #define DPIO_DCLKP_EN (1 << 13)
1137 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1138 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1139 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1140 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1141 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1142 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1143 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1144 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1145 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1147 #define _CHV_CMN_DW19_CH0 0x814c
1148 #define _CHV_CMN_DW6_CH1 0x8098
1149 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1150 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1151 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1152 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1154 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1156 #define CHV_CMN_DW28 0x8170
1157 #define DPIO_CL1POWERDOWNEN (1 << 23)
1158 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1159 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1160 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1161 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1162 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1164 #define CHV_CMN_DW30 0x8178
1165 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1166 #define DPIO_LRC_BYPASS (1 << 3)
1168 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1169 (lane) * 0x200 + (offset))
1171 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1172 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1173 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1174 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1175 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1176 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1177 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1178 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1179 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1180 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1181 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1182 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1183 #define DPIO_FRC_LATENCY_SHFIT 8
1184 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1185 #define DPIO_UPAR_SHIFT 30
1187 /* BXT PHY registers */
1188 #define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))
1190 #define BXT_P_CR_GT_DISP_PWRON 0x138090
1191 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1193 #define _PHY_CTL_FAMILY_EDP 0x64C80
1194 #define _PHY_CTL_FAMILY_DDI 0x64C90
1195 #define COMMON_RESET_DIS (1 << 31)
1196 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1197 _PHY_CTL_FAMILY_EDP)
1199 /* BXT PHY PLL registers */
1200 #define _PORT_PLL_A 0x46074
1201 #define _PORT_PLL_B 0x46078
1202 #define _PORT_PLL_C 0x4607c
1203 #define PORT_PLL_ENABLE (1 << 31)
1204 #define PORT_PLL_LOCK (1 << 30)
1205 #define PORT_PLL_REF_SEL (1 << 27)
1206 #define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1208 #define _PORT_PLL_EBB_0_A 0x162034
1209 #define _PORT_PLL_EBB_0_B 0x6C034
1210 #define _PORT_PLL_EBB_0_C 0x6C340
1211 #define PORT_PLL_P1_SHIFT 13
1212 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1213 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1214 #define PORT_PLL_P2_SHIFT 8
1215 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1216 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1217 #define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \
1218 _PORT_PLL_EBB_0_B, \
1221 #define _PORT_PLL_EBB_4_A 0x162038
1222 #define _PORT_PLL_EBB_4_B 0x6C038
1223 #define _PORT_PLL_EBB_4_C 0x6C344
1224 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1225 #define PORT_PLL_RECALIBRATE (1 << 14)
1226 #define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \
1227 _PORT_PLL_EBB_4_B, \
1230 #define _PORT_PLL_0_A 0x162100
1231 #define _PORT_PLL_0_B 0x6C100
1232 #define _PORT_PLL_0_C 0x6C380
1234 #define PORT_PLL_M2_MASK 0xFF
1236 #define PORT_PLL_N_SHIFT 8
1237 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1238 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1240 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1242 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1244 #define PORT_PLL_PROP_COEFF_MASK 0xF
1245 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1246 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1247 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1248 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1250 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1252 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1253 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1255 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1256 #define PORT_PLL_DCO_AMP_DEFAULT 15
1257 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1258 #define PORT_PLL_DCO_AMP(x) ((x)<<10)
1259 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1262 #define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4)
1264 /* BXT PHY common lane registers */
1265 #define _PORT_CL1CM_DW0_A 0x162000
1266 #define _PORT_CL1CM_DW0_BC 0x6C000
1267 #define PHY_POWER_GOOD (1 << 16)
1268 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1271 #define _PORT_CL1CM_DW9_A 0x162024
1272 #define _PORT_CL1CM_DW9_BC 0x6C024
1273 #define IREF0RC_OFFSET_SHIFT 8
1274 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1275 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1278 #define _PORT_CL1CM_DW10_A 0x162028
1279 #define _PORT_CL1CM_DW10_BC 0x6C028
1280 #define IREF1RC_OFFSET_SHIFT 8
1281 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1282 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1285 #define _PORT_CL1CM_DW28_A 0x162070
1286 #define _PORT_CL1CM_DW28_BC 0x6C070
1287 #define OCL1_POWER_DOWN_EN (1 << 23)
1288 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1289 #define SUS_CLK_CONFIG 0x3
1290 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1293 #define _PORT_CL1CM_DW30_A 0x162078
1294 #define _PORT_CL1CM_DW30_BC 0x6C078
1295 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1296 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1299 /* Defined for PHY0 only */
1300 #define BXT_PORT_CL2CM_DW6_BC 0x6C358
1301 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1303 /* BXT PHY Ref registers */
1304 #define _PORT_REF_DW3_A 0x16218C
1305 #define _PORT_REF_DW3_BC 0x6C18C
1306 #define GRC_DONE (1 << 22)
1307 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1310 #define _PORT_REF_DW6_A 0x162198
1311 #define _PORT_REF_DW6_BC 0x6C198
1313 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1316 #define GRC_CODE_SHIFT 23
1317 #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
1318 #define GRC_CODE_FAST_SHIFT 16
1319 #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
1320 #define GRC_CODE_SLOW_SHIFT 8
1321 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1322 #define GRC_CODE_NOM_MASK 0xFF
1323 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1326 #define _PORT_REF_DW8_A 0x1621A0
1327 #define _PORT_REF_DW8_BC 0x6C1A0
1328 #define GRC_DIS (1 << 15)
1329 #define GRC_RDY_OVRD (1 << 1)
1330 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1333 /* BXT PHY PCS registers */
1334 #define _PORT_PCS_DW10_LN01_A 0x162428
1335 #define _PORT_PCS_DW10_LN01_B 0x6C428
1336 #define _PORT_PCS_DW10_LN01_C 0x6C828
1337 #define _PORT_PCS_DW10_GRP_A 0x162C28
1338 #define _PORT_PCS_DW10_GRP_B 0x6CC28
1339 #define _PORT_PCS_DW10_GRP_C 0x6CE28
1340 #define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \
1341 _PORT_PCS_DW10_LN01_B, \
1342 _PORT_PCS_DW10_LN01_C)
1343 #define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \
1344 _PORT_PCS_DW10_GRP_B, \
1345 _PORT_PCS_DW10_GRP_C)
1346 #define TX2_SWING_CALC_INIT (1 << 31)
1347 #define TX1_SWING_CALC_INIT (1 << 30)
1349 #define _PORT_PCS_DW12_LN01_A 0x162430
1350 #define _PORT_PCS_DW12_LN01_B 0x6C430
1351 #define _PORT_PCS_DW12_LN01_C 0x6C830
1352 #define _PORT_PCS_DW12_LN23_A 0x162630
1353 #define _PORT_PCS_DW12_LN23_B 0x6C630
1354 #define _PORT_PCS_DW12_LN23_C 0x6CA30
1355 #define _PORT_PCS_DW12_GRP_A 0x162c30
1356 #define _PORT_PCS_DW12_GRP_B 0x6CC30
1357 #define _PORT_PCS_DW12_GRP_C 0x6CE30
1358 #define LANESTAGGER_STRAP_OVRD (1 << 6)
1359 #define LANE_STAGGER_MASK 0x1F
1360 #define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \
1361 _PORT_PCS_DW12_LN01_B, \
1362 _PORT_PCS_DW12_LN01_C)
1363 #define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \
1364 _PORT_PCS_DW12_LN23_B, \
1365 _PORT_PCS_DW12_LN23_C)
1366 #define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \
1367 _PORT_PCS_DW12_GRP_B, \
1368 _PORT_PCS_DW12_GRP_C)
1370 /* BXT PHY TX registers */
1371 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1372 ((lane) & 1) * 0x80)
1374 #define _PORT_TX_DW2_LN0_A 0x162508
1375 #define _PORT_TX_DW2_LN0_B 0x6C508
1376 #define _PORT_TX_DW2_LN0_C 0x6C908
1377 #define _PORT_TX_DW2_GRP_A 0x162D08
1378 #define _PORT_TX_DW2_GRP_B 0x6CD08
1379 #define _PORT_TX_DW2_GRP_C 0x6CF08
1380 #define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \
1381 _PORT_TX_DW2_GRP_B, \
1383 #define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \
1384 _PORT_TX_DW2_LN0_B, \
1386 #define MARGIN_000_SHIFT 16
1387 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1388 #define UNIQ_TRANS_SCALE_SHIFT 8
1389 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1391 #define _PORT_TX_DW3_LN0_A 0x16250C
1392 #define _PORT_TX_DW3_LN0_B 0x6C50C
1393 #define _PORT_TX_DW3_LN0_C 0x6C90C
1394 #define _PORT_TX_DW3_GRP_A 0x162D0C
1395 #define _PORT_TX_DW3_GRP_B 0x6CD0C
1396 #define _PORT_TX_DW3_GRP_C 0x6CF0C
1397 #define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \
1398 _PORT_TX_DW3_GRP_B, \
1400 #define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \
1401 _PORT_TX_DW3_LN0_B, \
1403 #define SCALE_DCOMP_METHOD (1 << 26)
1404 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
1406 #define _PORT_TX_DW4_LN0_A 0x162510
1407 #define _PORT_TX_DW4_LN0_B 0x6C510
1408 #define _PORT_TX_DW4_LN0_C 0x6C910
1409 #define _PORT_TX_DW4_GRP_A 0x162D10
1410 #define _PORT_TX_DW4_GRP_B 0x6CD10
1411 #define _PORT_TX_DW4_GRP_C 0x6CF10
1412 #define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \
1413 _PORT_TX_DW4_LN0_B, \
1415 #define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \
1416 _PORT_TX_DW4_GRP_B, \
1418 #define DEEMPH_SHIFT 24
1419 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1421 #define _PORT_TX_DW14_LN0_A 0x162538
1422 #define _PORT_TX_DW14_LN0_B 0x6C538
1423 #define _PORT_TX_DW14_LN0_C 0x6C938
1424 #define LATENCY_OPTIM_SHIFT 30
1425 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1426 #define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \
1427 _PORT_TX_DW14_LN0_B, \
1428 _PORT_TX_DW14_LN0_C) + \
1429 _BXT_LANE_OFFSET(lane))
1431 /* UAIMI scratch pad register 1 */
1432 #define UAIMI_SPR1 0x4F074
1433 /* SKL VccIO mask */
1434 #define SKL_VCCIO_MASK 0x1
1435 /* SKL balance leg register */
1436 #define DISPIO_CR_TX_BMU_CR0 0x6C00C
1437 /* I_boost values */
1438 #define BALANCE_LEG_SHIFT(port) (8+3*(port))
1439 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1440 /* Balance leg disable bits */
1441 #define BALANCE_LEG_DISABLE_SHIFT 23
1445 * [0-7] @ 0x2000 gen2,gen3
1446 * [8-15] @ 0x3000 945,g33,pnv
1448 * [0-15] @ 0x3000 gen4,gen5
1450 * [0-15] @ 0x100000 gen6,vlv,chv
1451 * [0-31] @ 0x100000 gen7+
1453 #define FENCE_REG(i) (0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
1454 #define I830_FENCE_START_MASK 0x07f80000
1455 #define I830_FENCE_TILING_Y_SHIFT 12
1456 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1457 #define I830_FENCE_PITCH_SHIFT 4
1458 #define I830_FENCE_REG_VALID (1<<0)
1459 #define I915_FENCE_MAX_PITCH_VAL 4
1460 #define I830_FENCE_MAX_PITCH_VAL 6
1461 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
1463 #define I915_FENCE_START_MASK 0x0ff00000
1464 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1466 #define FENCE_REG_965_LO(i) (0x03000 + (i) * 8)
1467 #define FENCE_REG_965_HI(i) (0x03000 + (i) * 8 + 4)
1468 #define I965_FENCE_PITCH_SHIFT 2
1469 #define I965_FENCE_TILING_Y_SHIFT 1
1470 #define I965_FENCE_REG_VALID (1<<0)
1471 #define I965_FENCE_MAX_PITCH_VAL 0x0400
1473 #define FENCE_REG_GEN6_LO(i) (0x100000 + (i) * 8)
1474 #define FENCE_REG_GEN6_HI(i) (0x100000 + (i) * 8 + 4)
1475 #define GEN6_FENCE_PITCH_SHIFT 32
1476 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1479 /* control register for cpu gtt access */
1480 #define TILECTL 0x101000
1481 #define TILECTL_SWZCTL (1 << 0)
1482 #define TILECTL_TLBPF (1 << 1)
1483 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1484 #define TILECTL_BACKSNOOP_DIS (1 << 3)
1487 * Instruction and interrupt control regs
1489 #define PGTBL_CTL 0x02020
1490 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1491 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1492 #define PGTBL_ER 0x02024
1493 #define PRB0_BASE (0x2030-0x30)
1494 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1495 #define PRB2_BASE (0x2050-0x30) /* gen3 */
1496 #define SRB0_BASE (0x2100-0x30) /* gen2 */
1497 #define SRB1_BASE (0x2110-0x30) /* gen2 */
1498 #define SRB2_BASE (0x2120-0x30) /* 830 */
1499 #define SRB3_BASE (0x2130-0x30) /* 830 */
1500 #define RENDER_RING_BASE 0x02000
1501 #define BSD_RING_BASE 0x04000
1502 #define GEN6_BSD_RING_BASE 0x12000
1503 #define GEN8_BSD2_RING_BASE 0x1c000
1504 #define VEBOX_RING_BASE 0x1a000
1505 #define BLT_RING_BASE 0x22000
1506 #define RING_TAIL(base) ((base)+0x30)
1507 #define RING_HEAD(base) ((base)+0x34)
1508 #define RING_START(base) ((base)+0x38)
1509 #define RING_CTL(base) ((base)+0x3c)
1510 #define RING_SYNC_0(base) ((base)+0x40)
1511 #define RING_SYNC_1(base) ((base)+0x44)
1512 #define RING_SYNC_2(base) ((base)+0x48)
1513 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1514 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1515 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1516 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1517 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1518 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1519 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1520 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1521 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1522 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1523 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1524 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1525 #define GEN6_NOSYNC 0
1526 #define RING_PSMI_CTL(base) ((base)+0x50)
1527 #define RING_MAX_IDLE(base) ((base)+0x54)
1528 #define RING_HWS_PGA(base) ((base)+0x80)
1529 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
1530 #define RING_RESET_CTL(base) ((base)+0xd0)
1531 #define RESET_CTL_REQUEST_RESET (1 << 0)
1532 #define RESET_CTL_READY_TO_RESET (1 << 1)
1534 #define HSW_GTT_CACHE_EN 0x4024
1535 #define GTT_CACHE_EN_ALL 0xF0007FFF
1536 #define GEN7_WR_WATERMARK 0x4028
1537 #define GEN7_GFX_PRIO_CTRL 0x402C
1538 #define ARB_MODE 0x4030
1539 #define ARB_MODE_SWIZZLE_SNB (1<<4)
1540 #define ARB_MODE_SWIZZLE_IVB (1<<5)
1541 #define GEN7_GFX_PEND_TLB0 0x4034
1542 #define GEN7_GFX_PEND_TLB1 0x4038
1543 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1544 #define GEN7_LRA_LIMITS(i) (0x403C + (i) * 4)
1545 #define GEN7_LRA_LIMITS_REG_NUM 13
1546 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1547 #define GEN7_GFX_MAX_REQ_COUNT 0x4074
1549 #define GAMTARBMODE 0x04a08
1550 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
1551 #define ARB_MODE_SWIZZLE_BDW (1<<1)
1552 #define RENDER_HWS_PGA_GEN7 (0x04080)
1553 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
1554 #define RING_FAULT_GTTSEL_MASK (1<<11)
1555 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1556 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1557 #define RING_FAULT_VALID (1<<0)
1558 #define DONE_REG 0x40b0
1559 #define GEN8_PRIVATE_PAT_LO 0x40e0
1560 #define GEN8_PRIVATE_PAT_HI (0x40e0 + 4)
1561 #define BSD_HWS_PGA_GEN7 (0x04180)
1562 #define BLT_HWS_PGA_GEN7 (0x04280)
1563 #define VEBOX_HWS_PGA_GEN7 (0x04380)
1564 #define RING_ACTHD(base) ((base)+0x74)
1565 #define RING_ACTHD_UDW(base) ((base)+0x5c)
1566 #define RING_NOPID(base) ((base)+0x94)
1567 #define RING_IMR(base) ((base)+0xa8)
1568 #define RING_HWSTAM(base) ((base)+0x98)
1569 #define RING_TIMESTAMP(base) ((base)+0x358)
1570 #define TAIL_ADDR 0x001FFFF8
1571 #define HEAD_WRAP_COUNT 0xFFE00000
1572 #define HEAD_WRAP_ONE 0x00200000
1573 #define HEAD_ADDR 0x001FFFFC
1574 #define RING_NR_PAGES 0x001FF000
1575 #define RING_REPORT_MASK 0x00000006
1576 #define RING_REPORT_64K 0x00000002
1577 #define RING_REPORT_128K 0x00000004
1578 #define RING_NO_REPORT 0x00000000
1579 #define RING_VALID_MASK 0x00000001
1580 #define RING_VALID 0x00000001
1581 #define RING_INVALID 0x00000000
1582 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1583 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1584 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1586 #define GEN7_TLB_RD_ADDR 0x4700
1589 #define PRB0_TAIL 0x02030
1590 #define PRB0_HEAD 0x02034
1591 #define PRB0_START 0x02038
1592 #define PRB0_CTL 0x0203c
1593 #define PRB1_TAIL 0x02040 /* 915+ only */
1594 #define PRB1_HEAD 0x02044 /* 915+ only */
1595 #define PRB1_START 0x02048 /* 915+ only */
1596 #define PRB1_CTL 0x0204c /* 915+ only */
1598 #define IPEIR_I965 0x02064
1599 #define IPEHR_I965 0x02068
1600 #define GEN7_SC_INSTDONE 0x07100
1601 #define GEN7_SAMPLER_INSTDONE 0x0e160
1602 #define GEN7_ROW_INSTDONE 0x0e164
1603 #define I915_NUM_INSTDONE_REG 4
1604 #define RING_IPEIR(base) ((base)+0x64)
1605 #define RING_IPEHR(base) ((base)+0x68)
1607 * On GEN4, only the render ring INSTDONE exists and has a different
1608 * layout than the GEN7+ version.
1609 * The GEN2 counterpart of this register is GEN2_INSTDONE.
1611 #define RING_INSTDONE(base) ((base)+0x6c)
1612 #define RING_INSTPS(base) ((base)+0x70)
1613 #define RING_DMA_FADD(base) ((base)+0x78)
1614 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
1615 #define RING_INSTPM(base) ((base)+0xc0)
1616 #define RING_MI_MODE(base) ((base)+0x9c)
1617 #define INSTPS 0x02070 /* 965+ only */
1618 #define GEN4_INSTDONE1 0x0207c /* 965+ only, aka INSTDONE_2 on SNB */
1619 #define ACTHD_I965 0x02074
1620 #define HWS_PGA 0x02080
1621 #define HWS_ADDRESS_MASK 0xfffff000
1622 #define HWS_START_ADDRESS_SHIFT 4
1623 #define PWRCTXA 0x2088 /* 965GM+ only */
1624 #define PWRCTX_EN (1<<0)
1625 #define IPEIR 0x02088
1626 #define IPEHR 0x0208c
1627 #define GEN2_INSTDONE 0x02090
1628 #define NOPID 0x02094
1629 #define HWSTAM 0x02098
1630 #define DMA_FADD_I8XX 0x020d0
1631 #define RING_BBSTATE(base) ((base)+0x110)
1632 #define RING_BBADDR(base) ((base)+0x140)
1633 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
1635 #define ERROR_GEN6 0x040a0
1636 #define GEN7_ERR_INT 0x44040
1637 #define ERR_INT_POISON (1<<31)
1638 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
1639 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1640 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1641 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1642 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1643 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1644 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
1645 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1646 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
1648 #define GEN8_FAULT_TLB_DATA0 0x04b10
1649 #define GEN8_FAULT_TLB_DATA1 0x04b14
1651 #define FPGA_DBG 0x42300
1652 #define FPGA_DBG_RM_NOCLAIM (1<<31)
1654 #define DERRMR 0x44050
1655 /* Note that HBLANK events are reserved on bdw+ */
1656 #define DERRMR_PIPEA_SCANLINE (1<<0)
1657 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1658 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1659 #define DERRMR_PIPEA_VBLANK (1<<3)
1660 #define DERRMR_PIPEA_HBLANK (1<<5)
1661 #define DERRMR_PIPEB_SCANLINE (1<<8)
1662 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1663 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1664 #define DERRMR_PIPEB_VBLANK (1<<11)
1665 #define DERRMR_PIPEB_HBLANK (1<<13)
1666 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1667 #define DERRMR_PIPEC_SCANLINE (1<<14)
1668 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1669 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1670 #define DERRMR_PIPEC_VBLANK (1<<21)
1671 #define DERRMR_PIPEC_HBLANK (1<<22)
1674 /* GM45+ chicken bits -- debug workaround bits that may be required
1675 * for various sorts of correct behavior. The top 16 bits of each are
1676 * the enables for writing to the corresponding low bit.
1678 #define _3D_CHICKEN 0x02084
1679 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1680 #define _3D_CHICKEN2 0x0208c
1681 /* Disables pipelining of read flushes past the SF-WIZ interface.
1682 * Required on all Ironlake steppings according to the B-Spec, but the
1683 * particular danger of not doing so is not specified.
1685 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1686 #define _3D_CHICKEN3 0x02090
1687 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1688 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1689 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1690 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1692 #define MI_MODE 0x0209c
1693 # define VS_TIMER_DISPATCH (1 << 6)
1694 # define MI_FLUSH_ENABLE (1 << 12)
1695 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1696 # define MODE_IDLE (1 << 9)
1697 # define STOP_RING (1 << 8)
1699 #define GEN6_GT_MODE 0x20d0
1700 #define GEN7_GT_MODE 0x7008
1701 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1702 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1703 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1704 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1705 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
1706 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1707 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1708 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
1710 #define GFX_MODE 0x02520
1711 #define GFX_MODE_GEN7 0x0229c
1712 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
1713 #define GFX_RUN_LIST_ENABLE (1<<15)
1714 #define GFX_INTERRUPT_STEERING (1<<14)
1715 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1716 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
1717 #define GFX_REPLAY_MODE (1<<11)
1718 #define GFX_PSMI_GRANULARITY (1<<10)
1719 #define GFX_PPGTT_ENABLE (1<<9)
1720 #define GEN8_GFX_PPGTT_48B (1<<7)
1722 #define GFX_FORWARD_VBLANK_MASK (3<<5)
1723 #define GFX_FORWARD_VBLANK_NEVER (0<<5)
1724 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
1725 #define GFX_FORWARD_VBLANK_COND (2<<5)
1727 #define VLV_DISPLAY_BASE 0x180000
1728 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1730 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1731 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
1732 #define SCPD0 0x0209c /* 915+ only */
1737 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
1738 #define GINT_DIS (1<<22)
1739 #define GCFG_DIS (1<<8)
1740 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
1741 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1742 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1743 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1744 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1745 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
1746 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1747 #define VLV_PCBR_ADDR_SHIFT 12
1749 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1753 #define GM45_ERROR_PAGE_TABLE (1<<5)
1754 #define GM45_ERROR_MEM_PRIV (1<<4)
1755 #define I915_ERROR_PAGE_TABLE (1<<4)
1756 #define GM45_ERROR_CP_PRIV (1<<3)
1757 #define I915_ERROR_MEMORY_REFRESH (1<<1)
1758 #define I915_ERROR_INSTRUCTION (1<<0)
1759 #define INSTPM 0x020c0
1760 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
1761 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1762 will not assert AGPBUSY# and will only
1763 be delivered when out of C3. */
1764 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1765 #define INSTPM_TLB_INVALIDATE (1<<9)
1766 #define INSTPM_SYNC_FLUSH (1<<5)
1767 #define ACTHD 0x020c8
1768 #define MEM_MODE 0x020cc
1769 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1770 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1771 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1772 #define FW_BLC 0x020d8
1773 #define FW_BLC2 0x020dc
1774 #define FW_BLC_SELF 0x020e0 /* 915+ only */
1775 #define FW_BLC_SELF_EN_MASK (1<<31)
1776 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1777 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
1778 #define MM_BURST_LENGTH 0x00700000
1779 #define MM_FIFO_WATERMARK 0x0001F000
1780 #define LM_BURST_LENGTH 0x00000700
1781 #define LM_FIFO_WATERMARK 0x0000001F
1782 #define MI_ARB_STATE 0x020e4 /* 915+ only */
1784 /* Make render/texture TLB fetches lower priorty than associated data
1785 * fetches. This is not turned on by default
1787 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1789 /* Isoch request wait on GTT enable (Display A/B/C streams).
1790 * Make isoch requests stall on the TLB update. May cause
1791 * display underruns (test mode only)
1793 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1795 /* Block grant count for isoch requests when block count is
1796 * set to a finite value.
1798 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1799 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1800 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1801 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1802 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1804 /* Enable render writes to complete in C2/C3/C4 power states.
1805 * If this isn't enabled, render writes are prevented in low
1806 * power states. That seems bad to me.
1808 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1810 /* This acknowledges an async flip immediately instead
1811 * of waiting for 2TLB fetches.
1813 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1815 /* Enables non-sequential data reads through arbiter
1817 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1819 /* Disable FSB snooping of cacheable write cycles from binner/render
1822 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1824 /* Arbiter time slice for non-isoch streams */
1825 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1826 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1827 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1828 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1829 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1830 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1831 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1832 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1833 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1835 /* Low priority grace period page size */
1836 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1837 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1839 /* Disable display A/B trickle feed */
1840 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1842 /* Set display plane priority */
1843 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1844 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1846 #define MI_STATE 0x020e4 /* gen2 only */
1847 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1848 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1850 #define CACHE_MODE_0 0x02120 /* 915+ only */
1851 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1852 #define CM0_IZ_OPT_DISABLE (1<<6)
1853 #define CM0_ZR_OPT_DISABLE (1<<5)
1854 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1855 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
1856 #define CM0_COLOR_EVICT_DISABLE (1<<3)
1857 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
1858 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1859 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1860 #define GFX_FLSH_CNTL_GEN6 0x101008
1861 #define GFX_FLSH_CNTL_EN (1<<0)
1862 #define ECOSKPD 0x021d0
1863 #define ECO_GATING_CX_ONLY (1<<3)
1864 #define ECO_FLIP_DONE (1<<0)
1866 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
1867 #define RC_OP_FLUSH_ENABLE (1<<0)
1868 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1869 #define CACHE_MODE_1 0x7004 /* IVB+ */
1870 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1871 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1872 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
1874 #define GEN6_BLITTER_ECOSKPD 0x221d0
1875 #define GEN6_BLITTER_LOCK_SHIFT 16
1876 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1878 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1879 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
1880 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1881 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1883 /* Fuse readout registers for GT */
1884 #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
1885 #define CHV_FGT_DISABLE_SS0 (1 << 10)
1886 #define CHV_FGT_DISABLE_SS1 (1 << 11)
1887 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1888 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1889 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1890 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1891 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1892 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1893 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1894 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1896 #define GEN8_FUSE2 0x9120
1897 #define GEN8_F2_SS_DIS_SHIFT 21
1898 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
1899 #define GEN8_F2_S_ENA_SHIFT 25
1900 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
1902 #define GEN9_F2_SS_DIS_SHIFT 20
1903 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1905 #define GEN8_EU_DISABLE0 0x9134
1906 #define GEN8_EU_DIS0_S0_MASK 0xffffff
1907 #define GEN8_EU_DIS0_S1_SHIFT 24
1908 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
1910 #define GEN8_EU_DISABLE1 0x9138
1911 #define GEN8_EU_DIS1_S1_MASK 0xffff
1912 #define GEN8_EU_DIS1_S2_SHIFT 16
1913 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
1915 #define GEN8_EU_DISABLE2 0x913c
1916 #define GEN8_EU_DIS2_S2_MASK 0xff
1918 #define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
1920 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
1921 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1922 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1923 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1924 #define GEN6_BSD_GO_INDICATOR (1 << 4)
1926 /* On modern GEN architectures interrupt control consists of two sets
1927 * of registers. The first set pertains to the ring generating the
1928 * interrupt. The second control is for the functional block generating the
1929 * interrupt. These are PM, GT, DE, etc.
1931 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1932 * GT interrupt bits, so we don't need to duplicate the defines.
1934 * These defines should cover us well from SNB->HSW with minor exceptions
1935 * it can also work on ILK.
1937 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1938 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1939 #define GT_BLT_USER_INTERRUPT (1 << 22)
1940 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1941 #define GT_BSD_USER_INTERRUPT (1 << 12)
1942 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1943 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1944 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1945 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1946 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1947 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1948 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1949 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1951 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1952 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1954 #define GT_PARITY_ERROR(dev) \
1955 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1956 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1958 /* These are all the "old" interrupts */
1959 #define ILK_BSD_USER_INTERRUPT (1<<5)
1961 #define I915_PM_INTERRUPT (1<<31)
1962 #define I915_ISP_INTERRUPT (1<<22)
1963 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1964 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1965 #define I915_MIPIC_INTERRUPT (1<<19)
1966 #define I915_MIPIA_INTERRUPT (1<<18)
1967 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1968 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1969 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1970 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
1971 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1972 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
1973 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1974 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
1975 #define I915_HWB_OOM_INTERRUPT (1<<13)
1976 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
1977 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
1978 #define I915_MISC_INTERRUPT (1<<11)
1979 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1980 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
1981 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1982 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
1983 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1984 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
1985 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1986 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1987 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1988 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1989 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1990 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1991 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
1992 #define I915_DEBUG_INTERRUPT (1<<2)
1993 #define I915_WINVALID_INTERRUPT (1<<1)
1994 #define I915_USER_INTERRUPT (1<<1)
1995 #define I915_ASLE_INTERRUPT (1<<0)
1996 #define I915_BSD_USER_INTERRUPT (1<<25)
1998 #define GEN6_BSD_RNCID 0x12198
2000 #define GEN7_FF_THREAD_MODE 0x20a0
2001 #define GEN7_FF_SCHED_MASK 0x0077070
2002 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2003 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2004 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2005 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2006 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2007 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2008 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2009 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2010 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2011 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
2012 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2013 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2014 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2015 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
2018 * Framebuffer compression (915+ only)
2021 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
2022 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
2023 #define FBC_CONTROL 0x03208
2024 #define FBC_CTL_EN (1<<31)
2025 #define FBC_CTL_PERIODIC (1<<30)
2026 #define FBC_CTL_INTERVAL_SHIFT (16)
2027 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2028 #define FBC_CTL_C3_IDLE (1<<13)
2029 #define FBC_CTL_STRIDE_SHIFT (5)
2030 #define FBC_CTL_FENCENO_SHIFT (0)
2031 #define FBC_COMMAND 0x0320c
2032 #define FBC_CMD_COMPRESS (1<<0)
2033 #define FBC_STATUS 0x03210
2034 #define FBC_STAT_COMPRESSING (1<<31)
2035 #define FBC_STAT_COMPRESSED (1<<30)
2036 #define FBC_STAT_MODIFIED (1<<29)
2037 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
2038 #define FBC_CONTROL2 0x03214
2039 #define FBC_CTL_FENCE_DBL (0<<4)
2040 #define FBC_CTL_IDLE_IMM (0<<2)
2041 #define FBC_CTL_IDLE_FULL (1<<2)
2042 #define FBC_CTL_IDLE_LINE (2<<2)
2043 #define FBC_CTL_IDLE_DEBUG (3<<2)
2044 #define FBC_CTL_CPU_FENCE (1<<1)
2045 #define FBC_CTL_PLANE(plane) ((plane)<<0)
2046 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
2047 #define FBC_TAG(i) (0x03300 + (i) * 4)
2049 #define FBC_STATUS2 0x43214
2050 #define FBC_COMPRESSION_MASK 0x7ff
2052 #define FBC_LL_SIZE (1536)
2054 /* Framebuffer compression for GM45+ */
2055 #define DPFC_CB_BASE 0x3200
2056 #define DPFC_CONTROL 0x3208
2057 #define DPFC_CTL_EN (1<<31)
2058 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
2059 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
2060 #define DPFC_CTL_FENCE_EN (1<<29)
2061 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
2062 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
2063 #define DPFC_SR_EN (1<<10)
2064 #define DPFC_CTL_LIMIT_1X (0<<6)
2065 #define DPFC_CTL_LIMIT_2X (1<<6)
2066 #define DPFC_CTL_LIMIT_4X (2<<6)
2067 #define DPFC_RECOMP_CTL 0x320c
2068 #define DPFC_RECOMP_STALL_EN (1<<27)
2069 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
2070 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2071 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2072 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2073 #define DPFC_STATUS 0x3210
2074 #define DPFC_INVAL_SEG_SHIFT (16)
2075 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
2076 #define DPFC_COMP_SEG_SHIFT (0)
2077 #define DPFC_COMP_SEG_MASK (0x000003ff)
2078 #define DPFC_STATUS2 0x3214
2079 #define DPFC_FENCE_YOFF 0x3218
2080 #define DPFC_CHICKEN 0x3224
2081 #define DPFC_HT_MODIFY (1<<31)
2083 /* Framebuffer compression for Ironlake */
2084 #define ILK_DPFC_CB_BASE 0x43200
2085 #define ILK_DPFC_CONTROL 0x43208
2086 #define FBC_CTL_FALSE_COLOR (1<<10)
2087 /* The bit 28-8 is reserved */
2088 #define DPFC_RESERVED (0x1FFFFF00)
2089 #define ILK_DPFC_RECOMP_CTL 0x4320c
2090 #define ILK_DPFC_STATUS 0x43210
2091 #define ILK_DPFC_FENCE_YOFF 0x43218
2092 #define ILK_DPFC_CHICKEN 0x43224
2093 #define ILK_FBC_RT_BASE 0x2128
2094 #define ILK_FBC_RT_VALID (1<<0)
2095 #define SNB_FBC_FRONT_BUFFER (1<<1)
2097 #define ILK_DISPLAY_CHICKEN1 0x42000
2098 #define ILK_FBCQ_DIS (1<<22)
2099 #define ILK_PABSTRETCH_DIS (1<<21)
2103 * Framebuffer compression for Sandybridge
2105 * The following two registers are of type GTTMMADR
2107 #define SNB_DPFC_CTL_SA 0x100100
2108 #define SNB_CPU_FENCE_ENABLE (1<<29)
2109 #define DPFC_CPU_FENCE_OFFSET 0x100104
2111 /* Framebuffer compression for Ivybridge */
2112 #define IVB_FBC_RT_BASE 0x7020
2114 #define IPS_CTL 0x43408
2115 #define IPS_ENABLE (1 << 31)
2117 #define MSG_FBC_REND_STATE 0x50380
2118 #define FBC_REND_NUKE (1<<2)
2119 #define FBC_REND_CACHE_CLEAN (1<<1)
2124 #define GPIOA 0x5010
2125 #define GPIOB 0x5014
2126 #define GPIOC 0x5018
2127 #define GPIOD 0x501c
2128 #define GPIOE 0x5020
2129 #define GPIOF 0x5024
2130 #define GPIOG 0x5028
2131 #define GPIOH 0x502c
2132 # define GPIO_CLOCK_DIR_MASK (1 << 0)
2133 # define GPIO_CLOCK_DIR_IN (0 << 1)
2134 # define GPIO_CLOCK_DIR_OUT (1 << 1)
2135 # define GPIO_CLOCK_VAL_MASK (1 << 2)
2136 # define GPIO_CLOCK_VAL_OUT (1 << 3)
2137 # define GPIO_CLOCK_VAL_IN (1 << 4)
2138 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2139 # define GPIO_DATA_DIR_MASK (1 << 8)
2140 # define GPIO_DATA_DIR_IN (0 << 9)
2141 # define GPIO_DATA_DIR_OUT (1 << 9)
2142 # define GPIO_DATA_VAL_MASK (1 << 10)
2143 # define GPIO_DATA_VAL_OUT (1 << 11)
2144 # define GPIO_DATA_VAL_IN (1 << 12)
2145 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2147 #define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2148 #define GMBUS_RATE_100KHZ (0<<8)
2149 #define GMBUS_RATE_50KHZ (1<<8)
2150 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2151 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2152 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
2153 #define GMBUS_PIN_DISABLED 0
2154 #define GMBUS_PIN_SSC 1
2155 #define GMBUS_PIN_VGADDC 2
2156 #define GMBUS_PIN_PANEL 3
2157 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2158 #define GMBUS_PIN_DPC 4 /* HDMIC */
2159 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2160 #define GMBUS_PIN_DPD 6 /* HDMID */
2161 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
2162 #define GMBUS_PIN_1_BXT 1
2163 #define GMBUS_PIN_2_BXT 2
2164 #define GMBUS_PIN_3_BXT 3
2165 #define GMBUS_NUM_PINS 7 /* including 0 */
2166 #define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2167 #define GMBUS_SW_CLR_INT (1<<31)
2168 #define GMBUS_SW_RDY (1<<30)
2169 #define GMBUS_ENT (1<<29) /* enable timeout */
2170 #define GMBUS_CYCLE_NONE (0<<25)
2171 #define GMBUS_CYCLE_WAIT (1<<25)
2172 #define GMBUS_CYCLE_INDEX (2<<25)
2173 #define GMBUS_CYCLE_STOP (4<<25)
2174 #define GMBUS_BYTE_COUNT_SHIFT 16
2175 #define GMBUS_BYTE_COUNT_MAX 256U
2176 #define GMBUS_SLAVE_INDEX_SHIFT 8
2177 #define GMBUS_SLAVE_ADDR_SHIFT 1
2178 #define GMBUS_SLAVE_READ (1<<0)
2179 #define GMBUS_SLAVE_WRITE (0<<0)
2180 #define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */
2181 #define GMBUS_INUSE (1<<15)
2182 #define GMBUS_HW_WAIT_PHASE (1<<14)
2183 #define GMBUS_STALL_TIMEOUT (1<<13)
2184 #define GMBUS_INT (1<<12)
2185 #define GMBUS_HW_RDY (1<<11)
2186 #define GMBUS_SATOER (1<<10)
2187 #define GMBUS_ACTIVE (1<<9)
2188 #define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2189 #define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2190 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2191 #define GMBUS_NAK_EN (1<<3)
2192 #define GMBUS_IDLE_EN (1<<2)
2193 #define GMBUS_HW_WAIT_EN (1<<1)
2194 #define GMBUS_HW_RDY_EN (1<<0)
2195 #define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2196 #define GMBUS_2BYTE_INDEX_EN (1<<31)
2199 * Clock control & power management
2201 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2202 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2203 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2204 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2208 #define VGA_PD 0x6010
2209 #define VGA0_PD_P2_DIV_4 (1 << 7)
2210 #define VGA0_PD_P1_DIV_2 (1 << 5)
2211 #define VGA0_PD_P1_SHIFT 0
2212 #define VGA0_PD_P1_MASK (0x1f << 0)
2213 #define VGA1_PD_P2_DIV_4 (1 << 15)
2214 #define VGA1_PD_P1_DIV_2 (1 << 13)
2215 #define VGA1_PD_P1_SHIFT 8
2216 #define VGA1_PD_P1_MASK (0x1f << 8)
2217 #define DPLL_VCO_ENABLE (1 << 31)
2218 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
2219 #define DPLL_DVO_2X_MODE (1 << 30)
2220 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
2221 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
2222 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
2223 #define DPLL_VGA_MODE_DIS (1 << 28)
2224 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2225 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2226 #define DPLL_MODE_MASK (3 << 26)
2227 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2228 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2229 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2230 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2231 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2232 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
2233 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
2234 #define DPLL_LOCK_VLV (1<<15)
2235 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
2236 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2237 #define DPLL_SSC_REF_CLK_CHV (1<<13)
2238 #define DPLL_PORTC_READY_MASK (0xf << 4)
2239 #define DPLL_PORTB_READY_MASK (0xf)
2241 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
2243 /* Additional CHV pll/phy registers */
2244 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
2245 #define DPLL_PORTD_READY_MASK (0xf)
2246 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
2247 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
2248 #define PHY_LDO_DELAY_0NS 0x0
2249 #define PHY_LDO_DELAY_200NS 0x1
2250 #define PHY_LDO_DELAY_600NS 0x2
2251 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
2252 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
2253 #define PHY_CH_SU_PSR 0x1
2254 #define PHY_CH_DEEP_PSR 0x7
2255 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2256 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
2257 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
2258 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2259 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
2260 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
2263 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2264 * this field (only one bit may be set).
2266 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2267 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
2268 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2269 /* i830, required in DVO non-gang */
2270 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
2271 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2272 #define PLL_REF_INPUT_DREFCLK (0 << 13)
2273 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2274 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2275 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2276 #define PLL_REF_INPUT_MASK (3 << 13)
2277 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
2279 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2280 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2281 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2282 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2283 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2286 * Parallel to Serial Load Pulse phase selection.
2287 * Selects the phase for the 10X DPLL clock for the PCIe
2288 * digital display port. The range is 4 to 13; 10 or more
2289 * is just a flip delay. The default is 6
2291 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2292 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2294 * SDVO multiplier for 945G/GM. Not used on 965.
2296 #define SDVO_MULTIPLIER_MASK 0x000000ff
2297 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
2298 #define SDVO_MULTIPLIER_SHIFT_VGA 0
2300 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2301 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2302 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2303 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2306 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2308 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2310 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2311 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
2312 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2313 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2314 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2316 * SDVO/UDI pixel multiplier.
2318 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2319 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2320 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2321 * dummy bytes in the datastream at an increased clock rate, with both sides of
2322 * the link knowing how many bytes are fill.
2324 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2325 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2326 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2327 * through an SDVO command.
2329 * This register field has values of multiplication factor minus 1, with
2330 * a maximum multiplier of 5 for SDVO.
2332 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2333 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2335 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2336 * This best be set to the default value (3) or the CRT won't work. No,
2337 * I don't entirely understand what this does...
2339 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2340 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
2342 #define _FPA0 0x06040
2343 #define _FPA1 0x06044
2344 #define _FPB0 0x06048
2345 #define _FPB1 0x0604c
2346 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
2347 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
2348 #define FP_N_DIV_MASK 0x003f0000
2349 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
2350 #define FP_N_DIV_SHIFT 16
2351 #define FP_M1_DIV_MASK 0x00003f00
2352 #define FP_M1_DIV_SHIFT 8
2353 #define FP_M2_DIV_MASK 0x0000003f
2354 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
2355 #define FP_M2_DIV_SHIFT 0
2356 #define DPLL_TEST 0x606c
2357 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2358 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2359 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2360 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2361 #define DPLLB_TEST_N_BYPASS (1 << 19)
2362 #define DPLLB_TEST_M_BYPASS (1 << 18)
2363 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2364 #define DPLLA_TEST_N_BYPASS (1 << 3)
2365 #define DPLLA_TEST_M_BYPASS (1 << 2)
2366 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2367 #define D_STATE 0x6104
2368 #define DSTATE_GFX_RESET_I830 (1<<6)
2369 #define DSTATE_PLL_D3_OFF (1<<3)
2370 #define DSTATE_GFX_CLOCK_GATING (1<<1)
2371 #define DSTATE_DOT_CLOCK_GATING (1<<0)
2372 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
2373 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2374 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2375 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2376 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2377 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2378 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2379 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2380 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2381 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2382 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2383 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2384 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2385 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2386 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2387 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2388 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2389 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2390 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2391 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2392 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2393 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2394 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2395 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2396 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2397 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2398 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2399 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2400 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
2402 * This bit must be set on the 830 to prevent hangs when turning off the
2405 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2406 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2407 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2408 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2409 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2411 #define RENCLK_GATE_D1 0x6204
2412 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2413 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2414 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2415 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2416 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2417 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2418 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2419 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2420 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
2421 /* This bit must be unset on 855,865 */
2422 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
2423 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2424 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
2425 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
2426 /* This bit must be set on 855,865. */
2427 # define SV_CLOCK_GATE_DISABLE (1 << 0)
2428 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2429 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2430 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2431 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2432 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2433 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2434 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2435 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2436 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2437 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2438 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2439 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2440 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2441 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2442 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2443 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2444 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2446 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
2447 /* This bit must always be set on 965G/965GM */
2448 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2449 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2450 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2451 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2452 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2453 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
2454 /* This bit must always be set on 965G */
2455 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2456 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2457 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2458 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2459 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2460 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2461 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2462 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2463 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2464 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2465 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2466 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2467 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2468 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2469 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2470 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2471 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2472 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2473 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2475 #define RENCLK_GATE_D2 0x6208
2476 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2477 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2478 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2480 #define VDECCLK_GATE_D 0x620C /* g4x only */
2481 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2483 #define RAMCLK_GATE_D 0x6210 /* CRL only */
2484 #define DEUC 0x6214 /* CRL only */
2486 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
2487 #define FW_CSPWRDWNEN (1<<15)
2489 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2491 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2492 #define CDCLK_FREQ_SHIFT 4
2493 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2494 #define CZCLK_FREQ_MASK 0xf
2496 #define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)
2497 #define PFI_CREDIT_63 (9 << 28) /* chv only */
2498 #define PFI_CREDIT_31 (8 << 28) /* chv only */
2499 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2500 #define PFI_CREDIT_RESEND (1 << 27)
2501 #define VGA_FAST_MODE_DISABLE (1 << 14)
2503 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2508 #define PALETTE_A_OFFSET 0xa000
2509 #define PALETTE_B_OFFSET 0xa800
2510 #define CHV_PALETTE_C_OFFSET 0xc000
2511 #define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
2512 dev_priv->info.display_mmio_offset + (i) * 4)
2514 /* MCH MMIO space */
2519 * This mirrors the MCHBAR MMIO space whose location is determined by
2520 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2521 * every way. It is not accessible from the CP register read instructions.
2523 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2526 #define MCHBAR_MIRROR_BASE 0x10000
2528 #define MCHBAR_MIRROR_BASE_SNB 0x140000
2530 #define CTG_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x34)
2531 #define ELK_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x48)
2532 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
2533 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
2535 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2536 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2538 /* 915-945 and GM965 MCH register controlling DRAM channel access */
2540 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2541 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2542 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2543 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
2544 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2545 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2546 #define DCC2 0x10204
2547 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2549 /* Pineview MCH register contains DDR3 setting */
2550 #define CSHRDDR3CTL 0x101a8
2551 #define CSHRDDR3CTL_DDR3 (1 << 2)
2553 /* 965 MCH register controlling DRAM channel configuration */
2554 #define C0DRB3 0x10206
2555 #define C1DRB3 0x10606
2557 /* snb MCH registers for reading the DRAM channel configuration */
2558 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2559 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2560 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2561 #define MAD_DIMM_ECC_MASK (0x3 << 24)
2562 #define MAD_DIMM_ECC_OFF (0x0 << 24)
2563 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2564 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2565 #define MAD_DIMM_ECC_ON (0x3 << 24)
2566 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2567 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2568 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2569 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2570 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2571 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2572 #define MAD_DIMM_A_SELECT (0x1 << 16)
2573 /* DIMM sizes are in multiples of 256mb. */
2574 #define MAD_DIMM_B_SIZE_SHIFT 8
2575 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2576 #define MAD_DIMM_A_SIZE_SHIFT 0
2577 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2579 /* snb MCH registers for priority tuning */
2580 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2581 #define MCH_SSKPD_WM0_MASK 0x3f
2582 #define MCH_SSKPD_WM0_VAL 0xc
2584 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2586 /* Clocking configuration register */
2587 #define CLKCFG 0x10c00
2588 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2589 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2590 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2591 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2592 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2593 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2594 /* Note, below two are guess */
2595 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2596 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2597 #define CLKCFG_FSB_MASK (7 << 0)
2598 #define CLKCFG_MEM_533 (1 << 4)
2599 #define CLKCFG_MEM_667 (2 << 4)
2600 #define CLKCFG_MEM_800 (3 << 4)
2601 #define CLKCFG_MEM_MASK (7 << 4)
2603 #define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38)
2604 #define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f)
2606 #define TSC1 0x11001
2609 #define TSFS 0x11020
2610 #define TSFS_SLOPE_MASK 0x0000ff00
2611 #define TSFS_SLOPE_SHIFT 8
2612 #define TSFS_INTR_MASK 0x000000ff
2614 #define CRSTANDVID 0x11100
2615 #define PXVFREQ(i) (0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2616 #define PXVFREQ_PX_MASK 0x7f000000
2617 #define PXVFREQ_PX_SHIFT 24
2618 #define VIDFREQ_BASE 0x11110
2619 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2620 #define VIDFREQ2 0x11114
2621 #define VIDFREQ3 0x11118
2622 #define VIDFREQ4 0x1111c
2623 #define VIDFREQ_P0_MASK 0x1f000000
2624 #define VIDFREQ_P0_SHIFT 24
2625 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2626 #define VIDFREQ_P0_CSCLK_SHIFT 20
2627 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2628 #define VIDFREQ_P0_CRCLK_SHIFT 16
2629 #define VIDFREQ_P1_MASK 0x00001f00
2630 #define VIDFREQ_P1_SHIFT 8
2631 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2632 #define VIDFREQ_P1_CSCLK_SHIFT 4
2633 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2634 #define INTTOEXT_BASE_ILK 0x11300
2635 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2636 #define INTTOEXT_MAP3_SHIFT 24
2637 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2638 #define INTTOEXT_MAP2_SHIFT 16
2639 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2640 #define INTTOEXT_MAP1_SHIFT 8
2641 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2642 #define INTTOEXT_MAP0_SHIFT 0
2643 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2644 #define MEMSWCTL 0x11170 /* Ironlake only */
2645 #define MEMCTL_CMD_MASK 0xe000
2646 #define MEMCTL_CMD_SHIFT 13
2647 #define MEMCTL_CMD_RCLK_OFF 0
2648 #define MEMCTL_CMD_RCLK_ON 1
2649 #define MEMCTL_CMD_CHFREQ 2
2650 #define MEMCTL_CMD_CHVID 3
2651 #define MEMCTL_CMD_VMMOFF 4
2652 #define MEMCTL_CMD_VMMON 5
2653 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2654 when command complete */
2655 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2656 #define MEMCTL_FREQ_SHIFT 8
2657 #define MEMCTL_SFCAVM (1<<7)
2658 #define MEMCTL_TGT_VID_MASK 0x007f
2659 #define MEMIHYST 0x1117c
2660 #define MEMINTREN 0x11180 /* 16 bits */
2661 #define MEMINT_RSEXIT_EN (1<<8)
2662 #define MEMINT_CX_SUPR_EN (1<<7)
2663 #define MEMINT_CONT_BUSY_EN (1<<6)
2664 #define MEMINT_AVG_BUSY_EN (1<<5)
2665 #define MEMINT_EVAL_CHG_EN (1<<4)
2666 #define MEMINT_MON_IDLE_EN (1<<3)
2667 #define MEMINT_UP_EVAL_EN (1<<2)
2668 #define MEMINT_DOWN_EVAL_EN (1<<1)
2669 #define MEMINT_SW_CMD_EN (1<<0)
2670 #define MEMINTRSTR 0x11182 /* 16 bits */
2671 #define MEM_RSEXIT_MASK 0xc000
2672 #define MEM_RSEXIT_SHIFT 14
2673 #define MEM_CONT_BUSY_MASK 0x3000
2674 #define MEM_CONT_BUSY_SHIFT 12
2675 #define MEM_AVG_BUSY_MASK 0x0c00
2676 #define MEM_AVG_BUSY_SHIFT 10
2677 #define MEM_EVAL_CHG_MASK 0x0300
2678 #define MEM_EVAL_BUSY_SHIFT 8
2679 #define MEM_MON_IDLE_MASK 0x00c0
2680 #define MEM_MON_IDLE_SHIFT 6
2681 #define MEM_UP_EVAL_MASK 0x0030
2682 #define MEM_UP_EVAL_SHIFT 4
2683 #define MEM_DOWN_EVAL_MASK 0x000c
2684 #define MEM_DOWN_EVAL_SHIFT 2
2685 #define MEM_SW_CMD_MASK 0x0003
2686 #define MEM_INT_STEER_GFX 0
2687 #define MEM_INT_STEER_CMR 1
2688 #define MEM_INT_STEER_SMI 2
2689 #define MEM_INT_STEER_SCI 3
2690 #define MEMINTRSTS 0x11184
2691 #define MEMINT_RSEXIT (1<<7)
2692 #define MEMINT_CONT_BUSY (1<<6)
2693 #define MEMINT_AVG_BUSY (1<<5)
2694 #define MEMINT_EVAL_CHG (1<<4)
2695 #define MEMINT_MON_IDLE (1<<3)
2696 #define MEMINT_UP_EVAL (1<<2)
2697 #define MEMINT_DOWN_EVAL (1<<1)
2698 #define MEMINT_SW_CMD (1<<0)
2699 #define MEMMODECTL 0x11190
2700 #define MEMMODE_BOOST_EN (1<<31)
2701 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2702 #define MEMMODE_BOOST_FREQ_SHIFT 24
2703 #define MEMMODE_IDLE_MODE_MASK 0x00030000
2704 #define MEMMODE_IDLE_MODE_SHIFT 16
2705 #define MEMMODE_IDLE_MODE_EVAL 0
2706 #define MEMMODE_IDLE_MODE_CONT 1
2707 #define MEMMODE_HWIDLE_EN (1<<15)
2708 #define MEMMODE_SWMODE_EN (1<<14)
2709 #define MEMMODE_RCLK_GATE (1<<13)
2710 #define MEMMODE_HW_UPDATE (1<<12)
2711 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2712 #define MEMMODE_FSTART_SHIFT 8
2713 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2714 #define MEMMODE_FMAX_SHIFT 4
2715 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2716 #define RCBMAXAVG 0x1119c
2717 #define MEMSWCTL2 0x1119e /* Cantiga only */
2718 #define SWMEMCMD_RENDER_OFF (0 << 13)
2719 #define SWMEMCMD_RENDER_ON (1 << 13)
2720 #define SWMEMCMD_SWFREQ (2 << 13)
2721 #define SWMEMCMD_TARVID (3 << 13)
2722 #define SWMEMCMD_VRM_OFF (4 << 13)
2723 #define SWMEMCMD_VRM_ON (5 << 13)
2724 #define CMDSTS (1<<12)
2725 #define SFCAVM (1<<11)
2726 #define SWFREQ_MASK 0x0380 /* P0-7 */
2727 #define SWFREQ_SHIFT 7
2728 #define TARVID_MASK 0x001f
2729 #define MEMSTAT_CTG 0x111a0
2730 #define RCBMINAVG 0x111a0
2731 #define RCUPEI 0x111b0
2732 #define RCDNEI 0x111b4
2733 #define RSTDBYCTL 0x111b8
2734 #define RS1EN (1<<31)
2735 #define RS2EN (1<<30)
2736 #define RS3EN (1<<29)
2737 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2738 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2739 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2740 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2741 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2742 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2743 #define RSX_STATUS_MASK (7<<20)
2744 #define RSX_STATUS_ON (0<<20)
2745 #define RSX_STATUS_RC1 (1<<20)
2746 #define RSX_STATUS_RC1E (2<<20)
2747 #define RSX_STATUS_RS1 (3<<20)
2748 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2749 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2750 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2751 #define RSX_STATUS_RSVD2 (7<<20)
2752 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2753 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2754 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
2755 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2756 #define RS1CONTSAV_MASK (3<<14)
2757 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2758 #define RS1CONTSAV_RSVD (1<<14)
2759 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2760 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2761 #define NORMSLEXLAT_MASK (3<<12)
2762 #define SLOW_RS123 (0<<12)
2763 #define SLOW_RS23 (1<<12)
2764 #define SLOW_RS3 (2<<12)
2765 #define NORMAL_RS123 (3<<12)
2766 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2767 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2768 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2769 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2770 #define RS_CSTATE_MASK (3<<4)
2771 #define RS_CSTATE_C367_RS1 (0<<4)
2772 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2773 #define RS_CSTATE_RSVD (2<<4)
2774 #define RS_CSTATE_C367_RS2 (3<<4)
2775 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2776 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2777 #define VIDCTL 0x111c0
2778 #define VIDSTS 0x111c8
2779 #define VIDSTART 0x111cc /* 8 bits */
2780 #define MEMSTAT_ILK 0x111f8
2781 #define MEMSTAT_VID_MASK 0x7f00
2782 #define MEMSTAT_VID_SHIFT 8
2783 #define MEMSTAT_PSTATE_MASK 0x00f8
2784 #define MEMSTAT_PSTATE_SHIFT 3
2785 #define MEMSTAT_MON_ACTV (1<<2)
2786 #define MEMSTAT_SRC_CTL_MASK 0x0003
2787 #define MEMSTAT_SRC_CTL_CORE 0
2788 #define MEMSTAT_SRC_CTL_TRB 1
2789 #define MEMSTAT_SRC_CTL_THM 2
2790 #define MEMSTAT_SRC_CTL_STDBY 3
2791 #define RCPREVBSYTUPAVG 0x113b8
2792 #define RCPREVBSYTDNAVG 0x113bc
2793 #define PMMISC 0x11214
2794 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2795 #define SDEW 0x1124c
2796 #define CSIEW0 0x11250
2797 #define CSIEW1 0x11254
2798 #define CSIEW2 0x11258
2799 #define PEW(i) (0x1125c + (i) * 4) /* 5 registers */
2800 #define DEW(i) (0x11270 + (i) * 4) /* 3 registers */
2801 #define MCHAFE 0x112c0
2802 #define CSIEC 0x112e0
2803 #define DMIEC 0x112e4
2804 #define DDREC 0x112e8
2805 #define PEG0EC 0x112ec
2806 #define PEG1EC 0x112f0
2807 #define GFXEC 0x112f4
2808 #define RPPREVBSYTUPAVG 0x113b8
2809 #define RPPREVBSYTDNAVG 0x113bc
2811 #define ECR_GPFE (1<<31)
2812 #define ECR_IMONE (1<<30)
2813 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2814 #define OGW0 0x11608
2815 #define OGW1 0x1160c
2824 #define PXW(i) (0x11664 + (i) * 4) /* 4 registers */
2825 #define PXWL(i) (0x11680 + (i) * 4) /* 8 registers */
2826 #define LCFUSE02 0x116c0
2827 #define LCFUSE_HIV_MASK 0x000000ff
2828 #define CSIPLL0 0x12c10
2829 #define DDRMPLL1 0X12c20
2830 #define PEG_BAND_GAP_DATA 0x14d68
2832 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
2833 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2835 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2836 #define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070)
2837 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2838 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
2839 #define BXT_RP_STATE_CAP 0x138170
2842 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2843 * 8300) freezing up around GPU hangs. Looks as if even
2844 * scheduling/timer interrupts start misbehaving if the RPS
2845 * EI/thresholds are "bad", leading to a very sluggish or even
2848 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
2849 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2850 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
2851 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2852 (IS_BROXTON(dev_priv) ? \
2853 INTERVAL_0_833_US(us) : \
2854 INTERVAL_1_33_US(us)) : \
2855 INTERVAL_1_28_US(us))
2858 * Logical Context regs
2861 #define CCID_EN (1<<0)
2863 * Notes on SNB/IVB/VLV context size:
2864 * - Power context is saved elsewhere (LLC or stolen)
2865 * - Ring/execlist context is saved on SNB, not on IVB
2866 * - Extended context size already includes render context size
2867 * - We always need to follow the extended context size.
2868 * SNB BSpec has comments indicating that we should use the
2869 * render context size instead if execlists are disabled, but
2870 * based on empirical testing that's just nonsense.
2871 * - Pipelined/VF state is saved on SNB/IVB respectively
2872 * - GT1 size just indicates how much of render context
2873 * doesn't need saving on GT1
2875 #define CXT_SIZE 0x21a0
2876 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
2877 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
2878 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
2879 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
2880 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
2881 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2882 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2883 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2884 #define GEN7_CXT_SIZE 0x21a8
2885 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
2886 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
2887 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
2888 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
2889 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
2890 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
2891 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2892 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2893 /* Haswell does have the CXT_SIZE register however it does not appear to be
2894 * valid. Now, docs explain in dwords what is in the context object. The full
2895 * size is 70720 bytes, however, the power context and execlist context will
2896 * never be saved (power context is stored elsewhere, and execlists don't work
2897 * on HSW) - so the final size, including the extra state required for the
2898 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
2900 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
2901 /* Same as Haswell, but 72064 bytes now. */
2902 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2904 #define CHV_CLK_CTL1 0x101100
2905 #define VLV_CLK_CTL2 0x101104
2906 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2912 #define OVADD 0x30000
2913 #define DOVSTA 0x30008
2914 #define OC_BUF (0x3<<20)
2915 #define OGAMC5 0x30010
2916 #define OGAMC4 0x30014
2917 #define OGAMC3 0x30018
2918 #define OGAMC2 0x3001c
2919 #define OGAMC1 0x30020
2920 #define OGAMC0 0x30024
2923 * Display engine regs
2926 /* Pipe A CRC regs */
2927 #define _PIPE_CRC_CTL_A 0x60050
2928 #define PIPE_CRC_ENABLE (1 << 31)
2929 /* ivb+ source selection */
2930 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2931 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2932 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
2933 /* ilk+ source selection */
2934 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2935 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2936 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2937 /* embedded DP port on the north display block, reserved on ivb */
2938 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2939 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
2940 /* vlv source selection */
2941 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2942 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2943 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2944 /* with DP port the pipe source is invalid */
2945 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2946 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2947 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2948 /* gen3+ source selection */
2949 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2950 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2951 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2952 /* with DP/TV port the pipe source is invalid */
2953 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2954 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2955 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2956 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2957 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2958 /* gen2 doesn't have source selection bits */
2959 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
2961 #define _PIPE_CRC_RES_1_A_IVB 0x60064
2962 #define _PIPE_CRC_RES_2_A_IVB 0x60068
2963 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
2964 #define _PIPE_CRC_RES_4_A_IVB 0x60070
2965 #define _PIPE_CRC_RES_5_A_IVB 0x60074
2967 #define _PIPE_CRC_RES_RED_A 0x60060
2968 #define _PIPE_CRC_RES_GREEN_A 0x60064
2969 #define _PIPE_CRC_RES_BLUE_A 0x60068
2970 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2971 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
2973 /* Pipe B CRC regs */
2974 #define _PIPE_CRC_RES_1_B_IVB 0x61064
2975 #define _PIPE_CRC_RES_2_B_IVB 0x61068
2976 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
2977 #define _PIPE_CRC_RES_4_B_IVB 0x61070
2978 #define _PIPE_CRC_RES_5_B_IVB 0x61074
2980 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2981 #define PIPE_CRC_RES_1_IVB(pipe) \
2982 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2983 #define PIPE_CRC_RES_2_IVB(pipe) \
2984 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2985 #define PIPE_CRC_RES_3_IVB(pipe) \
2986 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
2987 #define PIPE_CRC_RES_4_IVB(pipe) \
2988 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
2989 #define PIPE_CRC_RES_5_IVB(pipe) \
2990 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
2992 #define PIPE_CRC_RES_RED(pipe) \
2993 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2994 #define PIPE_CRC_RES_GREEN(pipe) \
2995 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2996 #define PIPE_CRC_RES_BLUE(pipe) \
2997 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2998 #define PIPE_CRC_RES_RES1_I915(pipe) \
2999 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3000 #define PIPE_CRC_RES_RES2_G4X(pipe) \
3001 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
3003 /* Pipe A timing regs */
3004 #define _HTOTAL_A 0x60000
3005 #define _HBLANK_A 0x60004
3006 #define _HSYNC_A 0x60008
3007 #define _VTOTAL_A 0x6000c
3008 #define _VBLANK_A 0x60010
3009 #define _VSYNC_A 0x60014
3010 #define _PIPEASRC 0x6001c
3011 #define _BCLRPAT_A 0x60020
3012 #define _VSYNCSHIFT_A 0x60028
3013 #define _PIPE_MULT_A 0x6002c
3015 /* Pipe B timing regs */
3016 #define _HTOTAL_B 0x61000
3017 #define _HBLANK_B 0x61004
3018 #define _HSYNC_B 0x61008
3019 #define _VTOTAL_B 0x6100c
3020 #define _VBLANK_B 0x61010
3021 #define _VSYNC_B 0x61014
3022 #define _PIPEBSRC 0x6101c
3023 #define _BCLRPAT_B 0x61020
3024 #define _VSYNCSHIFT_B 0x61028
3025 #define _PIPE_MULT_B 0x6102c
3027 #define TRANSCODER_A_OFFSET 0x60000
3028 #define TRANSCODER_B_OFFSET 0x61000
3029 #define TRANSCODER_C_OFFSET 0x62000
3030 #define CHV_TRANSCODER_C_OFFSET 0x63000
3031 #define TRANSCODER_EDP_OFFSET 0x6f000
3033 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
3034 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3035 dev_priv->info.display_mmio_offset)
3037 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
3038 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
3039 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
3040 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
3041 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
3042 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
3043 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
3044 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
3045 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
3046 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
3048 /* VLV eDP PSR registers */
3049 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
3050 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
3051 #define VLV_EDP_PSR_ENABLE (1<<0)
3052 #define VLV_EDP_PSR_RESET (1<<1)
3053 #define VLV_EDP_PSR_MODE_MASK (7<<2)
3054 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
3055 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
3056 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
3057 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
3058 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
3059 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
3060 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
3061 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
3062 #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
3064 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3065 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3066 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
3067 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
3068 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
3069 #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)
3071 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3072 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
3073 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
3074 #define VLV_EDP_PSR_CURR_STATE_MASK 7
3075 #define VLV_EDP_PSR_DISABLED (0<<0)
3076 #define VLV_EDP_PSR_INACTIVE (1<<0)
3077 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
3078 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
3079 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
3080 #define VLV_EDP_PSR_EXIT (5<<0)
3081 #define VLV_EDP_PSR_IN_TRANS (1<<7)
3082 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
3084 /* HSW+ eDP PSR registers */
3085 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
3086 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
3087 #define EDP_PSR_ENABLE (1<<31)
3088 #define BDW_PSR_SINGLE_FRAME (1<<30)
3089 #define EDP_PSR_LINK_STANDBY (1<<27)
3090 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3091 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3092 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3093 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3094 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3095 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3096 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3097 #define EDP_PSR_TP1_TP2_SEL (0<<11)
3098 #define EDP_PSR_TP1_TP3_SEL (1<<11)
3099 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3100 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3101 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3102 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3103 #define EDP_PSR_TP1_TIME_500us (0<<4)
3104 #define EDP_PSR_TP1_TIME_100us (1<<4)
3105 #define EDP_PSR_TP1_TIME_2500us (2<<4)
3106 #define EDP_PSR_TP1_TIME_0us (3<<4)
3107 #define EDP_PSR_IDLE_FRAME_SHIFT 0
3109 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
3110 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
3111 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
3112 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
3113 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
3114 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
3116 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
3117 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
3118 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3119 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3120 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3121 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3122 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3123 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3124 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3125 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
3126 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3127 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3128 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3129 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3130 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3131 #define EDP_PSR_STATUS_COUNT_SHIFT 16
3132 #define EDP_PSR_STATUS_COUNT_MASK 0xf
3133 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3134 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3135 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3136 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3137 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3138 #define EDP_PSR_STATUS_IDLE_MASK 0xf
3140 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
3141 #define EDP_PSR_PERF_CNT_MASK 0xffffff
3143 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
3144 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3145 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3146 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3148 #define EDP_PSR2_CTL 0x6f900
3149 #define EDP_PSR2_ENABLE (1<<31)
3150 #define EDP_SU_TRACK_ENABLE (1<<30)
3151 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3152 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3153 #define EDP_PSR2_TP2_TIME_500 (0<<8)
3154 #define EDP_PSR2_TP2_TIME_100 (1<<8)
3155 #define EDP_PSR2_TP2_TIME_2500 (2<<8)
3156 #define EDP_PSR2_TP2_TIME_50 (3<<8)
3157 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
3158 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3159 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3160 #define EDP_PSR2_IDLE_MASK 0xf
3162 /* VGA port control */
3163 #define ADPA 0x61100
3164 #define PCH_ADPA 0xe1100
3165 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
3167 #define ADPA_DAC_ENABLE (1<<31)
3168 #define ADPA_DAC_DISABLE 0
3169 #define ADPA_PIPE_SELECT_MASK (1<<30)
3170 #define ADPA_PIPE_A_SELECT 0
3171 #define ADPA_PIPE_B_SELECT (1<<30)
3172 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3173 /* CPT uses bits 29:30 for pch transcoder select */
3174 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3175 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3176 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3177 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3178 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3179 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3180 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3181 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3182 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3183 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3184 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3185 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3186 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3187 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3188 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3189 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3190 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3191 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3192 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3193 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
3194 #define ADPA_SETS_HVPOLARITY 0
3195 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
3196 #define ADPA_VSYNC_CNTL_ENABLE 0
3197 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
3198 #define ADPA_HSYNC_CNTL_ENABLE 0
3199 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3200 #define ADPA_VSYNC_ACTIVE_LOW 0
3201 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3202 #define ADPA_HSYNC_ACTIVE_LOW 0
3203 #define ADPA_DPMS_MASK (~(3<<10))
3204 #define ADPA_DPMS_ON (0<<10)
3205 #define ADPA_DPMS_SUSPEND (1<<10)
3206 #define ADPA_DPMS_STANDBY (2<<10)
3207 #define ADPA_DPMS_OFF (3<<10)
3210 /* Hotplug control (945+ only) */
3211 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
3212 #define PORTB_HOTPLUG_INT_EN (1 << 29)
3213 #define PORTC_HOTPLUG_INT_EN (1 << 28)
3214 #define PORTD_HOTPLUG_INT_EN (1 << 27)
3215 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
3216 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
3217 #define TV_HOTPLUG_INT_EN (1 << 18)
3218 #define CRT_HOTPLUG_INT_EN (1 << 9)
3219 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3220 PORTC_HOTPLUG_INT_EN | \
3221 PORTD_HOTPLUG_INT_EN | \
3222 SDVOC_HOTPLUG_INT_EN | \
3223 SDVOB_HOTPLUG_INT_EN | \
3225 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
3226 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3227 /* must use period 64 on GM45 according to docs */
3228 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3229 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3230 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3231 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3232 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3233 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3234 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3235 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3236 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3237 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3238 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3239 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
3241 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
3243 * HDMI/DP bits are g4x+
3245 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3246 * Please check the detailed lore in the commit message for for experimental
3249 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3250 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
3251 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
3252 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
3253 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3254 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
3255 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
3256 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
3257 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
3258 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3259 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
3260 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
3261 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3262 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
3263 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
3264 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3265 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
3266 /* CRT/TV common between gen3+ */
3267 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
3268 #define TV_HOTPLUG_INT_STATUS (1 << 10)
3269 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3270 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3271 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3272 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
3273 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3274 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3275 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
3276 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3278 /* SDVO is different across gen3/4 */
3279 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3280 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
3282 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3283 * since reality corrobates that they're the same as on gen3. But keep these
3284 * bits here (and the comment!) to help any other lost wanderers back onto the
3287 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3288 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3289 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3290 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
3291 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3292 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3293 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3294 PORTB_HOTPLUG_INT_STATUS | \
3295 PORTC_HOTPLUG_INT_STATUS | \
3296 PORTD_HOTPLUG_INT_STATUS)
3298 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3299 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3300 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3301 PORTB_HOTPLUG_INT_STATUS | \
3302 PORTC_HOTPLUG_INT_STATUS | \
3303 PORTD_HOTPLUG_INT_STATUS)
3305 /* SDVO and HDMI port control.
3306 * The same register may be used for SDVO or HDMI */
3307 #define GEN3_SDVOB 0x61140
3308 #define GEN3_SDVOC 0x61160
3309 #define GEN4_HDMIB GEN3_SDVOB
3310 #define GEN4_HDMIC GEN3_SDVOC
3311 #define VLV_HDMIB (VLV_DISPLAY_BASE + GEN4_HDMIB)
3312 #define VLV_HDMIC (VLV_DISPLAY_BASE + GEN4_HDMIC)
3313 #define CHV_HDMID (VLV_DISPLAY_BASE + 0x6116C)
3314 #define PCH_SDVOB 0xe1140
3315 #define PCH_HDMIB PCH_SDVOB
3316 #define PCH_HDMIC 0xe1150
3317 #define PCH_HDMID 0xe1160
3319 #define PORT_DFT_I9XX 0x61150
3320 #define DC_BALANCE_RESET (1 << 25)
3321 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
3322 #define DC_BALANCE_RESET_VLV (1 << 31)
3323 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3324 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
3325 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
3326 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
3328 /* Gen 3 SDVO bits: */
3329 #define SDVO_ENABLE (1 << 31)
3330 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3331 #define SDVO_PIPE_SEL_MASK (1 << 30)
3332 #define SDVO_PIPE_B_SELECT (1 << 30)
3333 #define SDVO_STALL_SELECT (1 << 29)
3334 #define SDVO_INTERRUPT_ENABLE (1 << 26)
3336 * 915G/GM SDVO pixel multiplier.
3337 * Programmed value is multiplier - 1, up to 5x.
3338 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3340 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
3341 #define SDVO_PORT_MULTIPLY_SHIFT 23
3342 #define SDVO_PHASE_SELECT_MASK (15 << 19)
3343 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3344 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3345 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3346 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3347 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3348 #define SDVO_DETECTED (1 << 2)
3349 /* Bits to be preserved when writing */
3350 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3351 SDVO_INTERRUPT_ENABLE)
3352 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3354 /* Gen 4 SDVO/HDMI bits: */
3355 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
3356 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
3357 #define SDVO_ENCODING_SDVO (0 << 10)
3358 #define SDVO_ENCODING_HDMI (2 << 10)
3359 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3360 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
3361 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
3362 #define SDVO_AUDIO_ENABLE (1 << 6)
3363 /* VSYNC/HSYNC bits new with 965, default is to be set */
3364 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3365 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3367 /* Gen 5 (IBX) SDVO/HDMI bits: */
3368 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
3369 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3371 /* Gen 6 (CPT) SDVO/HDMI bits: */
3372 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3373 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
3375 /* CHV SDVO/HDMI bits: */
3376 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3377 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3380 /* DVO port control */
3381 #define DVOA 0x61120
3382 #define DVOB 0x61140
3383 #define DVOC 0x61160
3384 #define DVO_ENABLE (1 << 31)
3385 #define DVO_PIPE_B_SELECT (1 << 30)
3386 #define DVO_PIPE_STALL_UNUSED (0 << 28)
3387 #define DVO_PIPE_STALL (1 << 28)
3388 #define DVO_PIPE_STALL_TV (2 << 28)
3389 #define DVO_PIPE_STALL_MASK (3 << 28)
3390 #define DVO_USE_VGA_SYNC (1 << 15)
3391 #define DVO_DATA_ORDER_I740 (0 << 14)
3392 #define DVO_DATA_ORDER_FP (1 << 14)
3393 #define DVO_VSYNC_DISABLE (1 << 11)
3394 #define DVO_HSYNC_DISABLE (1 << 10)
3395 #define DVO_VSYNC_TRISTATE (1 << 9)
3396 #define DVO_HSYNC_TRISTATE (1 << 8)
3397 #define DVO_BORDER_ENABLE (1 << 7)
3398 #define DVO_DATA_ORDER_GBRG (1 << 6)
3399 #define DVO_DATA_ORDER_RGGB (0 << 6)
3400 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3401 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3402 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3403 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3404 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3405 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3406 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3407 #define DVO_PRESERVE_MASK (0x7<<24)
3408 #define DVOA_SRCDIM 0x61124
3409 #define DVOB_SRCDIM 0x61144
3410 #define DVOC_SRCDIM 0x61164
3411 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3412 #define DVO_SRCDIM_VERTICAL_SHIFT 0
3414 /* LVDS port control */
3415 #define LVDS 0x61180
3417 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3418 * the DPLL semantics change when the LVDS is assigned to that pipe.
3420 #define LVDS_PORT_EN (1 << 31)
3421 /* Selects pipe B for LVDS data. Must be set on pre-965. */
3422 #define LVDS_PIPEB_SELECT (1 << 30)
3423 #define LVDS_PIPE_MASK (1 << 30)
3424 #define LVDS_PIPE(pipe) ((pipe) << 30)
3425 /* LVDS dithering flag on 965/g4x platform */
3426 #define LVDS_ENABLE_DITHER (1 << 25)
3427 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
3428 #define LVDS_VSYNC_POLARITY (1 << 21)
3429 #define LVDS_HSYNC_POLARITY (1 << 20)
3431 /* Enable border for unscaled (or aspect-scaled) display */
3432 #define LVDS_BORDER_ENABLE (1 << 15)
3434 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3437 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3438 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3439 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3441 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3442 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3445 #define LVDS_A3_POWER_MASK (3 << 6)
3446 #define LVDS_A3_POWER_DOWN (0 << 6)
3447 #define LVDS_A3_POWER_UP (3 << 6)
3449 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3452 #define LVDS_CLKB_POWER_MASK (3 << 4)
3453 #define LVDS_CLKB_POWER_DOWN (0 << 4)
3454 #define LVDS_CLKB_POWER_UP (3 << 4)
3456 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3457 * setting for whether we are in dual-channel mode. The B3 pair will
3458 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3460 #define LVDS_B0B3_POWER_MASK (3 << 2)
3461 #define LVDS_B0B3_POWER_DOWN (0 << 2)
3462 #define LVDS_B0B3_POWER_UP (3 << 2)
3464 /* Video Data Island Packet control */
3465 #define VIDEO_DIP_DATA 0x61178
3466 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3467 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3468 * of the infoframe structure specified by CEA-861. */
3469 #define VIDEO_DIP_DATA_SIZE 32
3470 #define VIDEO_DIP_VSC_DATA_SIZE 36
3471 #define VIDEO_DIP_CTL 0x61170
3473 #define VIDEO_DIP_ENABLE (1 << 31)
3474 #define VIDEO_DIP_PORT(port) ((port) << 29)
3475 #define VIDEO_DIP_PORT_MASK (3 << 29)
3476 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
3477 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
3478 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
3479 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
3480 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
3481 #define VIDEO_DIP_SELECT_AVI (0 << 19)
3482 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3483 #define VIDEO_DIP_SELECT_SPD (3 << 19)
3484 #define VIDEO_DIP_SELECT_MASK (3 << 19)
3485 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
3486 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3487 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
3488 #define VIDEO_DIP_FREQ_MASK (3 << 16)
3489 /* HSW and later: */
3490 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3491 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
3492 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
3493 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3494 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
3495 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3497 /* Panel power sequencing */
3498 #define PP_STATUS 0x61200
3499 #define PP_ON (1 << 31)
3501 * Indicates that all dependencies of the panel are on:
3505 * - LVDS/DVOB/DVOC on
3507 #define PP_READY (1 << 30)
3508 #define PP_SEQUENCE_NONE (0 << 28)
3509 #define PP_SEQUENCE_POWER_UP (1 << 28)
3510 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
3511 #define PP_SEQUENCE_MASK (3 << 28)
3512 #define PP_SEQUENCE_SHIFT 28
3513 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
3514 #define PP_SEQUENCE_STATE_MASK 0x0000000f
3515 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3516 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3517 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3518 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3519 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3520 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3521 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3522 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3523 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
3524 #define PP_CONTROL 0x61204
3525 #define POWER_TARGET_ON (1 << 0)
3526 #define PP_ON_DELAYS 0x61208
3527 #define PP_OFF_DELAYS 0x6120c
3528 #define PP_DIVISOR 0x61210
3531 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
3532 #define PFIT_ENABLE (1 << 31)
3533 #define PFIT_PIPE_MASK (3 << 29)
3534 #define PFIT_PIPE_SHIFT 29
3535 #define VERT_INTERP_DISABLE (0 << 10)
3536 #define VERT_INTERP_BILINEAR (1 << 10)
3537 #define VERT_INTERP_MASK (3 << 10)
3538 #define VERT_AUTO_SCALE (1 << 9)
3539 #define HORIZ_INTERP_DISABLE (0 << 6)
3540 #define HORIZ_INTERP_BILINEAR (1 << 6)
3541 #define HORIZ_INTERP_MASK (3 << 6)
3542 #define HORIZ_AUTO_SCALE (1 << 5)
3543 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3544 #define PFIT_FILTER_FUZZY (0 << 24)
3545 #define PFIT_SCALING_AUTO (0 << 26)
3546 #define PFIT_SCALING_PROGRAMMED (1 << 26)
3547 #define PFIT_SCALING_PILLAR (2 << 26)
3548 #define PFIT_SCALING_LETTER (3 << 26)
3549 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3551 #define PFIT_VERT_SCALE_SHIFT 20
3552 #define PFIT_VERT_SCALE_MASK 0xfff00000
3553 #define PFIT_HORIZ_SCALE_SHIFT 4
3554 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3556 #define PFIT_VERT_SCALE_SHIFT_965 16
3557 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3558 #define PFIT_HORIZ_SCALE_SHIFT_965 0
3559 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3561 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3563 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3564 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3565 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3566 _VLV_BLC_PWM_CTL2_B)
3568 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3569 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3570 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3573 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3574 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3575 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3576 _VLV_BLC_HIST_CTL_B)
3578 /* Backlight control */
3579 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3580 #define BLM_PWM_ENABLE (1 << 31)
3581 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3582 #define BLM_PIPE_SELECT (1 << 29)
3583 #define BLM_PIPE_SELECT_IVB (3 << 29)
3584 #define BLM_PIPE_A (0 << 29)
3585 #define BLM_PIPE_B (1 << 29)
3586 #define BLM_PIPE_C (2 << 29) /* ivb + */
3587 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3588 #define BLM_TRANSCODER_B BLM_PIPE_B
3589 #define BLM_TRANSCODER_C BLM_PIPE_C
3590 #define BLM_TRANSCODER_EDP (3 << 29)
3591 #define BLM_PIPE(pipe) ((pipe) << 29)
3592 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3593 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3594 #define BLM_PHASE_IN_ENABLE (1 << 25)
3595 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3596 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3597 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3598 #define BLM_PHASE_IN_COUNT_SHIFT (8)
3599 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3600 #define BLM_PHASE_IN_INCR_SHIFT (0)
3601 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3602 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3604 * This is the most significant 15 bits of the number of backlight cycles in a
3605 * complete cycle of the modulated backlight control.
3607 * The actual value is this field multiplied by two.
3609 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3610 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3611 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3613 * This is the number of cycles out of the backlight modulation cycle for which
3614 * the backlight is on.
3616 * This field must be no greater than the number of cycles in the complete
3617 * backlight modulation cycle.
3619 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3620 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3621 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3622 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3624 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
3625 #define BLM_HISTOGRAM_ENABLE (1 << 31)
3627 /* New registers for PCH-split platforms. Safe where new bits show up, the
3628 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3629 #define BLC_PWM_CPU_CTL2 0x48250
3630 #define BLC_PWM_CPU_CTL 0x48254
3632 #define HSW_BLC_PWM2_CTL 0x48350
3634 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3635 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3636 #define BLC_PWM_PCH_CTL1 0xc8250
3637 #define BLM_PCH_PWM_ENABLE (1 << 31)
3638 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3639 #define BLM_PCH_POLARITY (1 << 29)
3640 #define BLC_PWM_PCH_CTL2 0xc8254
3642 #define UTIL_PIN_CTL 0x48400
3643 #define UTIL_PIN_ENABLE (1 << 31)
3645 #define UTIL_PIN_PIPE(x) ((x) << 29)
3646 #define UTIL_PIN_PIPE_MASK (3 << 29)
3647 #define UTIL_PIN_MODE_PWM (1 << 24)
3648 #define UTIL_PIN_MODE_MASK (0xf << 24)
3649 #define UTIL_PIN_POLARITY (1 << 22)
3651 /* BXT backlight register definition. */
3652 #define _BXT_BLC_PWM_CTL1 0xC8250
3653 #define BXT_BLC_PWM_ENABLE (1 << 31)
3654 #define BXT_BLC_PWM_POLARITY (1 << 29)
3655 #define _BXT_BLC_PWM_FREQ1 0xC8254
3656 #define _BXT_BLC_PWM_DUTY1 0xC8258
3658 #define _BXT_BLC_PWM_CTL2 0xC8350
3659 #define _BXT_BLC_PWM_FREQ2 0xC8354
3660 #define _BXT_BLC_PWM_DUTY2 0xC8358
3662 #define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
3663 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
3664 #define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
3665 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
3666 #define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
3667 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3669 #define PCH_GTC_CTL 0xe7000
3670 #define PCH_GTC_ENABLE (1 << 31)
3672 /* TV port control */
3673 #define TV_CTL 0x68000
3674 /* Enables the TV encoder */
3675 # define TV_ENC_ENABLE (1 << 31)
3676 /* Sources the TV encoder input from pipe B instead of A. */
3677 # define TV_ENC_PIPEB_SELECT (1 << 30)
3678 /* Outputs composite video (DAC A only) */
3679 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3680 /* Outputs SVideo video (DAC B/C) */
3681 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3682 /* Outputs Component video (DAC A/B/C) */
3683 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3684 /* Outputs Composite and SVideo (DAC A/B/C) */
3685 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3686 # define TV_TRILEVEL_SYNC (1 << 21)
3687 /* Enables slow sync generation (945GM only) */
3688 # define TV_SLOW_SYNC (1 << 20)
3689 /* Selects 4x oversampling for 480i and 576p */
3690 # define TV_OVERSAMPLE_4X (0 << 18)
3691 /* Selects 2x oversampling for 720p and 1080i */
3692 # define TV_OVERSAMPLE_2X (1 << 18)
3693 /* Selects no oversampling for 1080p */
3694 # define TV_OVERSAMPLE_NONE (2 << 18)
3695 /* Selects 8x oversampling */
3696 # define TV_OVERSAMPLE_8X (3 << 18)
3697 /* Selects progressive mode rather than interlaced */
3698 # define TV_PROGRESSIVE (1 << 17)
3699 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3700 # define TV_PAL_BURST (1 << 16)
3701 /* Field for setting delay of Y compared to C */
3702 # define TV_YC_SKEW_MASK (7 << 12)
3703 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3704 # define TV_ENC_SDP_FIX (1 << 11)
3706 * Enables a fix for the 915GM only.
3708 * Not sure what it does.
3710 # define TV_ENC_C0_FIX (1 << 10)
3711 /* Bits that must be preserved by software */
3712 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3713 # define TV_FUSE_STATE_MASK (3 << 4)
3714 /* Read-only state that reports all features enabled */
3715 # define TV_FUSE_STATE_ENABLED (0 << 4)
3716 /* Read-only state that reports that Macrovision is disabled in hardware*/
3717 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3718 /* Read-only state that reports that TV-out is disabled in hardware. */
3719 # define TV_FUSE_STATE_DISABLED (2 << 4)
3720 /* Normal operation */
3721 # define TV_TEST_MODE_NORMAL (0 << 0)
3722 /* Encoder test pattern 1 - combo pattern */
3723 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
3724 /* Encoder test pattern 2 - full screen vertical 75% color bars */
3725 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
3726 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3727 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
3728 /* Encoder test pattern 4 - random noise */
3729 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
3730 /* Encoder test pattern 5 - linear color ramps */
3731 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
3733 * This test mode forces the DACs to 50% of full output.
3735 * This is used for load detection in combination with TVDAC_SENSE_MASK
3737 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3738 # define TV_TEST_MODE_MASK (7 << 0)
3740 #define TV_DAC 0x68004
3741 # define TV_DAC_SAVE 0x00ffff00
3743 * Reports that DAC state change logic has reported change (RO).
3745 * This gets cleared when TV_DAC_STATE_EN is cleared
3747 # define TVDAC_STATE_CHG (1 << 31)
3748 # define TVDAC_SENSE_MASK (7 << 28)
3749 /* Reports that DAC A voltage is above the detect threshold */
3750 # define TVDAC_A_SENSE (1 << 30)
3751 /* Reports that DAC B voltage is above the detect threshold */
3752 # define TVDAC_B_SENSE (1 << 29)
3753 /* Reports that DAC C voltage is above the detect threshold */
3754 # define TVDAC_C_SENSE (1 << 28)
3756 * Enables DAC state detection logic, for load-based TV detection.
3758 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3759 * to off, for load detection to work.
3761 # define TVDAC_STATE_CHG_EN (1 << 27)
3762 /* Sets the DAC A sense value to high */
3763 # define TVDAC_A_SENSE_CTL (1 << 26)
3764 /* Sets the DAC B sense value to high */
3765 # define TVDAC_B_SENSE_CTL (1 << 25)
3766 /* Sets the DAC C sense value to high */
3767 # define TVDAC_C_SENSE_CTL (1 << 24)
3768 /* Overrides the ENC_ENABLE and DAC voltage levels */
3769 # define DAC_CTL_OVERRIDE (1 << 7)
3770 /* Sets the slew rate. Must be preserved in software */
3771 # define ENC_TVDAC_SLEW_FAST (1 << 6)
3772 # define DAC_A_1_3_V (0 << 4)
3773 # define DAC_A_1_1_V (1 << 4)
3774 # define DAC_A_0_7_V (2 << 4)
3775 # define DAC_A_MASK (3 << 4)
3776 # define DAC_B_1_3_V (0 << 2)
3777 # define DAC_B_1_1_V (1 << 2)
3778 # define DAC_B_0_7_V (2 << 2)
3779 # define DAC_B_MASK (3 << 2)
3780 # define DAC_C_1_3_V (0 << 0)
3781 # define DAC_C_1_1_V (1 << 0)
3782 # define DAC_C_0_7_V (2 << 0)
3783 # define DAC_C_MASK (3 << 0)
3786 * CSC coefficients are stored in a floating point format with 9 bits of
3787 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3788 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3789 * -1 (0x3) being the only legal negative value.
3791 #define TV_CSC_Y 0x68010
3792 # define TV_RY_MASK 0x07ff0000
3793 # define TV_RY_SHIFT 16
3794 # define TV_GY_MASK 0x00000fff
3795 # define TV_GY_SHIFT 0
3797 #define TV_CSC_Y2 0x68014
3798 # define TV_BY_MASK 0x07ff0000
3799 # define TV_BY_SHIFT 16
3801 * Y attenuation for component video.
3803 * Stored in 1.9 fixed point.
3805 # define TV_AY_MASK 0x000003ff
3806 # define TV_AY_SHIFT 0
3808 #define TV_CSC_U 0x68018
3809 # define TV_RU_MASK 0x07ff0000
3810 # define TV_RU_SHIFT 16
3811 # define TV_GU_MASK 0x000007ff
3812 # define TV_GU_SHIFT 0
3814 #define TV_CSC_U2 0x6801c
3815 # define TV_BU_MASK 0x07ff0000
3816 # define TV_BU_SHIFT 16
3818 * U attenuation for component video.
3820 * Stored in 1.9 fixed point.
3822 # define TV_AU_MASK 0x000003ff
3823 # define TV_AU_SHIFT 0
3825 #define TV_CSC_V 0x68020
3826 # define TV_RV_MASK 0x0fff0000
3827 # define TV_RV_SHIFT 16
3828 # define TV_GV_MASK 0x000007ff
3829 # define TV_GV_SHIFT 0
3831 #define TV_CSC_V2 0x68024
3832 # define TV_BV_MASK 0x07ff0000
3833 # define TV_BV_SHIFT 16
3835 * V attenuation for component video.
3837 * Stored in 1.9 fixed point.
3839 # define TV_AV_MASK 0x000007ff
3840 # define TV_AV_SHIFT 0
3842 #define TV_CLR_KNOBS 0x68028
3843 /* 2s-complement brightness adjustment */
3844 # define TV_BRIGHTNESS_MASK 0xff000000
3845 # define TV_BRIGHTNESS_SHIFT 24
3846 /* Contrast adjustment, as a 2.6 unsigned floating point number */
3847 # define TV_CONTRAST_MASK 0x00ff0000
3848 # define TV_CONTRAST_SHIFT 16
3849 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3850 # define TV_SATURATION_MASK 0x0000ff00
3851 # define TV_SATURATION_SHIFT 8
3852 /* Hue adjustment, as an integer phase angle in degrees */
3853 # define TV_HUE_MASK 0x000000ff
3854 # define TV_HUE_SHIFT 0
3856 #define TV_CLR_LEVEL 0x6802c
3857 /* Controls the DAC level for black */
3858 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3859 # define TV_BLACK_LEVEL_SHIFT 16
3860 /* Controls the DAC level for blanking */
3861 # define TV_BLANK_LEVEL_MASK 0x000001ff
3862 # define TV_BLANK_LEVEL_SHIFT 0
3864 #define TV_H_CTL_1 0x68030
3865 /* Number of pixels in the hsync. */
3866 # define TV_HSYNC_END_MASK 0x1fff0000
3867 # define TV_HSYNC_END_SHIFT 16
3868 /* Total number of pixels minus one in the line (display and blanking). */
3869 # define TV_HTOTAL_MASK 0x00001fff
3870 # define TV_HTOTAL_SHIFT 0
3872 #define TV_H_CTL_2 0x68034
3873 /* Enables the colorburst (needed for non-component color) */
3874 # define TV_BURST_ENA (1 << 31)
3875 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3876 # define TV_HBURST_START_SHIFT 16
3877 # define TV_HBURST_START_MASK 0x1fff0000
3878 /* Length of the colorburst */
3879 # define TV_HBURST_LEN_SHIFT 0
3880 # define TV_HBURST_LEN_MASK 0x0001fff
3882 #define TV_H_CTL_3 0x68038
3883 /* End of hblank, measured in pixels minus one from start of hsync */
3884 # define TV_HBLANK_END_SHIFT 16
3885 # define TV_HBLANK_END_MASK 0x1fff0000
3886 /* Start of hblank, measured in pixels minus one from start of hsync */
3887 # define TV_HBLANK_START_SHIFT 0
3888 # define TV_HBLANK_START_MASK 0x0001fff
3890 #define TV_V_CTL_1 0x6803c
3892 # define TV_NBR_END_SHIFT 16
3893 # define TV_NBR_END_MASK 0x07ff0000
3895 # define TV_VI_END_F1_SHIFT 8
3896 # define TV_VI_END_F1_MASK 0x00003f00
3898 # define TV_VI_END_F2_SHIFT 0
3899 # define TV_VI_END_F2_MASK 0x0000003f
3901 #define TV_V_CTL_2 0x68040
3902 /* Length of vsync, in half lines */
3903 # define TV_VSYNC_LEN_MASK 0x07ff0000
3904 # define TV_VSYNC_LEN_SHIFT 16
3905 /* Offset of the start of vsync in field 1, measured in one less than the
3906 * number of half lines.
3908 # define TV_VSYNC_START_F1_MASK 0x00007f00
3909 # define TV_VSYNC_START_F1_SHIFT 8
3911 * Offset of the start of vsync in field 2, measured in one less than the
3912 * number of half lines.
3914 # define TV_VSYNC_START_F2_MASK 0x0000007f
3915 # define TV_VSYNC_START_F2_SHIFT 0
3917 #define TV_V_CTL_3 0x68044
3918 /* Enables generation of the equalization signal */
3919 # define TV_EQUAL_ENA (1 << 31)
3920 /* Length of vsync, in half lines */
3921 # define TV_VEQ_LEN_MASK 0x007f0000
3922 # define TV_VEQ_LEN_SHIFT 16
3923 /* Offset of the start of equalization in field 1, measured in one less than
3924 * the number of half lines.
3926 # define TV_VEQ_START_F1_MASK 0x0007f00
3927 # define TV_VEQ_START_F1_SHIFT 8
3929 * Offset of the start of equalization in field 2, measured in one less than
3930 * the number of half lines.
3932 # define TV_VEQ_START_F2_MASK 0x000007f
3933 # define TV_VEQ_START_F2_SHIFT 0
3935 #define TV_V_CTL_4 0x68048
3937 * Offset to start of vertical colorburst, measured in one less than the
3938 * number of lines from vertical start.
3940 # define TV_VBURST_START_F1_MASK 0x003f0000
3941 # define TV_VBURST_START_F1_SHIFT 16
3943 * Offset to the end of vertical colorburst, measured in one less than the
3944 * number of lines from the start of NBR.
3946 # define TV_VBURST_END_F1_MASK 0x000000ff
3947 # define TV_VBURST_END_F1_SHIFT 0
3949 #define TV_V_CTL_5 0x6804c
3951 * Offset to start of vertical colorburst, measured in one less than the
3952 * number of lines from vertical start.
3954 # define TV_VBURST_START_F2_MASK 0x003f0000
3955 # define TV_VBURST_START_F2_SHIFT 16
3957 * Offset to the end of vertical colorburst, measured in one less than the
3958 * number of lines from the start of NBR.
3960 # define TV_VBURST_END_F2_MASK 0x000000ff
3961 # define TV_VBURST_END_F2_SHIFT 0
3963 #define TV_V_CTL_6 0x68050
3965 * Offset to start of vertical colorburst, measured in one less than the
3966 * number of lines from vertical start.
3968 # define TV_VBURST_START_F3_MASK 0x003f0000
3969 # define TV_VBURST_START_F3_SHIFT 16
3971 * Offset to the end of vertical colorburst, measured in one less than the
3972 * number of lines from the start of NBR.
3974 # define TV_VBURST_END_F3_MASK 0x000000ff
3975 # define TV_VBURST_END_F3_SHIFT 0
3977 #define TV_V_CTL_7 0x68054
3979 * Offset to start of vertical colorburst, measured in one less than the
3980 * number of lines from vertical start.
3982 # define TV_VBURST_START_F4_MASK 0x003f0000
3983 # define TV_VBURST_START_F4_SHIFT 16
3985 * Offset to the end of vertical colorburst, measured in one less than the
3986 * number of lines from the start of NBR.
3988 # define TV_VBURST_END_F4_MASK 0x000000ff
3989 # define TV_VBURST_END_F4_SHIFT 0
3991 #define TV_SC_CTL_1 0x68060
3992 /* Turns on the first subcarrier phase generation DDA */
3993 # define TV_SC_DDA1_EN (1 << 31)
3994 /* Turns on the first subcarrier phase generation DDA */
3995 # define TV_SC_DDA2_EN (1 << 30)
3996 /* Turns on the first subcarrier phase generation DDA */
3997 # define TV_SC_DDA3_EN (1 << 29)
3998 /* Sets the subcarrier DDA to reset frequency every other field */
3999 # define TV_SC_RESET_EVERY_2 (0 << 24)
4000 /* Sets the subcarrier DDA to reset frequency every fourth field */
4001 # define TV_SC_RESET_EVERY_4 (1 << 24)
4002 /* Sets the subcarrier DDA to reset frequency every eighth field */
4003 # define TV_SC_RESET_EVERY_8 (2 << 24)
4004 /* Sets the subcarrier DDA to never reset the frequency */
4005 # define TV_SC_RESET_NEVER (3 << 24)
4006 /* Sets the peak amplitude of the colorburst.*/
4007 # define TV_BURST_LEVEL_MASK 0x00ff0000
4008 # define TV_BURST_LEVEL_SHIFT 16
4009 /* Sets the increment of the first subcarrier phase generation DDA */
4010 # define TV_SCDDA1_INC_MASK 0x00000fff
4011 # define TV_SCDDA1_INC_SHIFT 0
4013 #define TV_SC_CTL_2 0x68064
4014 /* Sets the rollover for the second subcarrier phase generation DDA */
4015 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
4016 # define TV_SCDDA2_SIZE_SHIFT 16
4017 /* Sets the increent of the second subcarrier phase generation DDA */
4018 # define TV_SCDDA2_INC_MASK 0x00007fff
4019 # define TV_SCDDA2_INC_SHIFT 0
4021 #define TV_SC_CTL_3 0x68068
4022 /* Sets the rollover for the third subcarrier phase generation DDA */
4023 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
4024 # define TV_SCDDA3_SIZE_SHIFT 16
4025 /* Sets the increent of the third subcarrier phase generation DDA */
4026 # define TV_SCDDA3_INC_MASK 0x00007fff
4027 # define TV_SCDDA3_INC_SHIFT 0
4029 #define TV_WIN_POS 0x68070
4030 /* X coordinate of the display from the start of horizontal active */
4031 # define TV_XPOS_MASK 0x1fff0000
4032 # define TV_XPOS_SHIFT 16
4033 /* Y coordinate of the display from the start of vertical active (NBR) */
4034 # define TV_YPOS_MASK 0x00000fff
4035 # define TV_YPOS_SHIFT 0
4037 #define TV_WIN_SIZE 0x68074
4038 /* Horizontal size of the display window, measured in pixels*/
4039 # define TV_XSIZE_MASK 0x1fff0000
4040 # define TV_XSIZE_SHIFT 16
4042 * Vertical size of the display window, measured in pixels.
4044 * Must be even for interlaced modes.
4046 # define TV_YSIZE_MASK 0x00000fff
4047 # define TV_YSIZE_SHIFT 0
4049 #define TV_FILTER_CTL_1 0x68080
4051 * Enables automatic scaling calculation.
4053 * If set, the rest of the registers are ignored, and the calculated values can
4054 * be read back from the register.
4056 # define TV_AUTO_SCALE (1 << 31)
4058 * Disables the vertical filter.
4060 * This is required on modes more than 1024 pixels wide */
4061 # define TV_V_FILTER_BYPASS (1 << 29)
4062 /* Enables adaptive vertical filtering */
4063 # define TV_VADAPT (1 << 28)
4064 # define TV_VADAPT_MODE_MASK (3 << 26)
4065 /* Selects the least adaptive vertical filtering mode */
4066 # define TV_VADAPT_MODE_LEAST (0 << 26)
4067 /* Selects the moderately adaptive vertical filtering mode */
4068 # define TV_VADAPT_MODE_MODERATE (1 << 26)
4069 /* Selects the most adaptive vertical filtering mode */
4070 # define TV_VADAPT_MODE_MOST (3 << 26)
4072 * Sets the horizontal scaling factor.
4074 * This should be the fractional part of the horizontal scaling factor divided
4075 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
4077 * (src width - 1) / ((oversample * dest width) - 1)
4079 # define TV_HSCALE_FRAC_MASK 0x00003fff
4080 # define TV_HSCALE_FRAC_SHIFT 0
4082 #define TV_FILTER_CTL_2 0x68084
4084 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4086 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4088 # define TV_VSCALE_INT_MASK 0x00038000
4089 # define TV_VSCALE_INT_SHIFT 15
4091 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4093 * \sa TV_VSCALE_INT_MASK
4095 # define TV_VSCALE_FRAC_MASK 0x00007fff
4096 # define TV_VSCALE_FRAC_SHIFT 0
4098 #define TV_FILTER_CTL_3 0x68088
4100 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4102 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4104 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4106 # define TV_VSCALE_IP_INT_MASK 0x00038000
4107 # define TV_VSCALE_IP_INT_SHIFT 15
4109 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4111 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4113 * \sa TV_VSCALE_IP_INT_MASK
4115 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4116 # define TV_VSCALE_IP_FRAC_SHIFT 0
4118 #define TV_CC_CONTROL 0x68090
4119 # define TV_CC_ENABLE (1 << 31)
4121 * Specifies which field to send the CC data in.
4123 * CC data is usually sent in field 0.
4125 # define TV_CC_FID_MASK (1 << 27)
4126 # define TV_CC_FID_SHIFT 27
4127 /* Sets the horizontal position of the CC data. Usually 135. */
4128 # define TV_CC_HOFF_MASK 0x03ff0000
4129 # define TV_CC_HOFF_SHIFT 16
4130 /* Sets the vertical position of the CC data. Usually 21 */
4131 # define TV_CC_LINE_MASK 0x0000003f
4132 # define TV_CC_LINE_SHIFT 0
4134 #define TV_CC_DATA 0x68094
4135 # define TV_CC_RDY (1 << 31)
4136 /* Second word of CC data to be transmitted. */
4137 # define TV_CC_DATA_2_MASK 0x007f0000
4138 # define TV_CC_DATA_2_SHIFT 16
4139 /* First word of CC data to be transmitted. */
4140 # define TV_CC_DATA_1_MASK 0x0000007f
4141 # define TV_CC_DATA_1_SHIFT 0
4143 #define TV_H_LUMA(i) (0x68100 + (i) * 4) /* 60 registers */
4144 #define TV_H_CHROMA(i) (0x68200 + (i) * 4) /* 60 registers */
4145 #define TV_V_LUMA(i) (0x68300 + (i) * 4) /* 43 registers */
4146 #define TV_V_CHROMA(i) (0x68400 + (i) * 4) /* 43 registers */
4149 #define DP_A 0x64000 /* eDP */
4150 #define DP_B 0x64100
4151 #define DP_C 0x64200
4152 #define DP_D 0x64300
4154 #define VLV_DP_B (VLV_DISPLAY_BASE + DP_B)
4155 #define VLV_DP_C (VLV_DISPLAY_BASE + DP_C)
4156 #define CHV_DP_D (VLV_DISPLAY_BASE + DP_D)
4158 #define DP_PORT_EN (1 << 31)
4159 #define DP_PIPEB_SELECT (1 << 30)
4160 #define DP_PIPE_MASK (1 << 30)
4161 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4162 #define DP_PIPE_MASK_CHV (3 << 16)
4164 /* Link training mode - select a suitable mode for each stage */
4165 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
4166 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
4167 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4168 #define DP_LINK_TRAIN_OFF (3 << 28)
4169 #define DP_LINK_TRAIN_MASK (3 << 28)
4170 #define DP_LINK_TRAIN_SHIFT 28
4171 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4172 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
4174 /* CPT Link training mode */
4175 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4176 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4177 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4178 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4179 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4180 #define DP_LINK_TRAIN_SHIFT_CPT 8
4182 /* Signal voltages. These are mostly controlled by the other end */
4183 #define DP_VOLTAGE_0_4 (0 << 25)
4184 #define DP_VOLTAGE_0_6 (1 << 25)
4185 #define DP_VOLTAGE_0_8 (2 << 25)
4186 #define DP_VOLTAGE_1_2 (3 << 25)
4187 #define DP_VOLTAGE_MASK (7 << 25)
4188 #define DP_VOLTAGE_SHIFT 25
4190 /* Signal pre-emphasis levels, like voltages, the other end tells us what
4193 #define DP_PRE_EMPHASIS_0 (0 << 22)
4194 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
4195 #define DP_PRE_EMPHASIS_6 (2 << 22)
4196 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
4197 #define DP_PRE_EMPHASIS_MASK (7 << 22)
4198 #define DP_PRE_EMPHASIS_SHIFT 22
4200 /* How many wires to use. I guess 3 was too hard */
4201 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
4202 #define DP_PORT_WIDTH_MASK (7 << 19)
4203 #define DP_PORT_WIDTH_SHIFT 19
4205 /* Mystic DPCD version 1.1 special mode */
4206 #define DP_ENHANCED_FRAMING (1 << 18)
4209 #define DP_PLL_FREQ_270MHZ (0 << 16)
4210 #define DP_PLL_FREQ_160MHZ (1 << 16)
4211 #define DP_PLL_FREQ_MASK (3 << 16)
4213 /* locked once port is enabled */
4214 #define DP_PORT_REVERSAL (1 << 15)
4217 #define DP_PLL_ENABLE (1 << 14)
4219 /* sends the clock on lane 15 of the PEG for debug */
4220 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4222 #define DP_SCRAMBLING_DISABLE (1 << 12)
4223 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
4225 /* limit RGB values to avoid confusing TVs */
4226 #define DP_COLOR_RANGE_16_235 (1 << 8)
4228 /* Turn on the audio link */
4229 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4231 /* vs and hs sync polarity */
4232 #define DP_SYNC_VS_HIGH (1 << 4)
4233 #define DP_SYNC_HS_HIGH (1 << 3)
4236 #define DP_DETECTED (1 << 2)
4238 /* The aux channel provides a way to talk to the
4239 * signal sink for DDC etc. Max packet size supported
4240 * is 20 bytes in each direction, hence the 5 fixed
4243 #define DPA_AUX_CH_CTL 0x64010
4244 #define DPA_AUX_CH_DATA1 0x64014
4245 #define DPA_AUX_CH_DATA2 0x64018
4246 #define DPA_AUX_CH_DATA3 0x6401c
4247 #define DPA_AUX_CH_DATA4 0x64020
4248 #define DPA_AUX_CH_DATA5 0x64024
4250 #define DPB_AUX_CH_CTL 0x64110
4251 #define DPB_AUX_CH_DATA1 0x64114
4252 #define DPB_AUX_CH_DATA2 0x64118
4253 #define DPB_AUX_CH_DATA3 0x6411c
4254 #define DPB_AUX_CH_DATA4 0x64120
4255 #define DPB_AUX_CH_DATA5 0x64124
4257 #define DPC_AUX_CH_CTL 0x64210
4258 #define DPC_AUX_CH_DATA1 0x64214
4259 #define DPC_AUX_CH_DATA2 0x64218
4260 #define DPC_AUX_CH_DATA3 0x6421c
4261 #define DPC_AUX_CH_DATA4 0x64220
4262 #define DPC_AUX_CH_DATA5 0x64224
4264 #define DPD_AUX_CH_CTL 0x64310
4265 #define DPD_AUX_CH_DATA1 0x64314
4266 #define DPD_AUX_CH_DATA2 0x64318
4267 #define DPD_AUX_CH_DATA3 0x6431c
4268 #define DPD_AUX_CH_DATA4 0x64320
4269 #define DPD_AUX_CH_DATA5 0x64324
4271 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4272 #define DP_AUX_CH_CTL_DONE (1 << 30)
4273 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4274 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4275 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4276 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4277 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4278 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4279 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4280 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4281 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4282 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4283 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4284 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4285 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4286 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4287 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4288 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4289 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4290 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4291 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
4292 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4293 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4294 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
4295 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
4296 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
4297 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
4300 * Computing GMCH M and N values for the Display Port link
4302 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4304 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4306 * The GMCH value is used internally
4308 * bytes_per_pixel is the number of bytes coming out of the plane,
4309 * which is after the LUTs, so we want the bytes for our color format.
4310 * For our current usage, this is always 3, one byte for R, G and B.
4312 #define _PIPEA_DATA_M_G4X 0x70050
4313 #define _PIPEB_DATA_M_G4X 0x71050
4315 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
4316 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
4317 #define TU_SIZE_SHIFT 25
4318 #define TU_SIZE_MASK (0x3f << 25)
4320 #define DATA_LINK_M_N_MASK (0xffffff)
4321 #define DATA_LINK_N_MAX (0x800000)
4323 #define _PIPEA_DATA_N_G4X 0x70054
4324 #define _PIPEB_DATA_N_G4X 0x71054
4325 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
4328 * Computing Link M and N values for the Display Port link
4330 * Link M / N = pixel_clock / ls_clk
4332 * (the DP spec calls pixel_clock the 'strm_clk')
4334 * The Link value is transmitted in the Main Stream
4335 * Attributes and VB-ID.
4338 #define _PIPEA_LINK_M_G4X 0x70060
4339 #define _PIPEB_LINK_M_G4X 0x71060
4340 #define PIPEA_DP_LINK_M_MASK (0xffffff)
4342 #define _PIPEA_LINK_N_G4X 0x70064
4343 #define _PIPEB_LINK_N_G4X 0x71064
4344 #define PIPEA_DP_LINK_N_MASK (0xffffff)
4346 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4347 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4348 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4349 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4351 /* Display & cursor control */
4354 #define _PIPEADSL 0x70000
4355 #define DSL_LINEMASK_GEN2 0x00000fff
4356 #define DSL_LINEMASK_GEN3 0x00001fff
4357 #define _PIPEACONF 0x70008
4358 #define PIPECONF_ENABLE (1<<31)
4359 #define PIPECONF_DISABLE 0
4360 #define PIPECONF_DOUBLE_WIDE (1<<30)
4361 #define I965_PIPECONF_ACTIVE (1<<30)
4362 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
4363 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
4364 #define PIPECONF_SINGLE_WIDE 0
4365 #define PIPECONF_PIPE_UNLOCKED 0
4366 #define PIPECONF_PIPE_LOCKED (1<<25)
4367 #define PIPECONF_PALETTE 0
4368 #define PIPECONF_GAMMA (1<<24)
4369 #define PIPECONF_FORCE_BORDER (1<<25)
4370 #define PIPECONF_INTERLACE_MASK (7 << 21)
4371 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
4372 /* Note that pre-gen3 does not support interlaced display directly. Panel
4373 * fitting must be disabled on pre-ilk for interlaced. */
4374 #define PIPECONF_PROGRESSIVE (0 << 21)
4375 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4376 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4377 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4378 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4379 /* Ironlake and later have a complete new set of values for interlaced. PFIT
4380 * means panel fitter required, PF means progressive fetch, DBL means power
4381 * saving pixel doubling. */
4382 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4383 #define PIPECONF_INTERLACED_ILK (3 << 21)
4384 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4385 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
4386 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
4387 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
4388 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
4389 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
4390 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
4391 #define PIPECONF_BPC_MASK (0x7 << 5)
4392 #define PIPECONF_8BPC (0<<5)
4393 #define PIPECONF_10BPC (1<<5)
4394 #define PIPECONF_6BPC (2<<5)
4395 #define PIPECONF_12BPC (3<<5)
4396 #define PIPECONF_DITHER_EN (1<<4)
4397 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4398 #define PIPECONF_DITHER_TYPE_SP (0<<2)
4399 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4400 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4401 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
4402 #define _PIPEASTAT 0x70024
4403 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
4404 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
4405 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4406 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
4407 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
4408 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
4409 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
4410 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4411 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4412 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4413 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
4414 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
4415 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4416 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4417 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
4418 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
4419 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
4420 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4421 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
4422 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
4423 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
4424 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
4425 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
4426 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4427 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
4428 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4429 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
4430 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
4431 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
4432 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
4433 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4434 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4435 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4436 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
4437 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
4438 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
4439 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4440 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
4441 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
4442 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
4443 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4444 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
4445 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
4446 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
4447 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
4448 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4450 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4451 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4453 #define PIPE_A_OFFSET 0x70000
4454 #define PIPE_B_OFFSET 0x71000
4455 #define PIPE_C_OFFSET 0x72000
4456 #define CHV_PIPE_C_OFFSET 0x74000
4458 * There's actually no pipe EDP. Some pipe registers have
4459 * simply shifted from the pipe to the transcoder, while
4460 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4461 * to access such registers in transcoder EDP.
4463 #define PIPE_EDP_OFFSET 0x7f000
4465 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4466 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4467 dev_priv->info.display_mmio_offset)
4469 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
4470 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
4471 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
4472 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
4473 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
4475 #define _PIPE_MISC_A 0x70030
4476 #define _PIPE_MISC_B 0x71030
4477 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
4478 #define PIPEMISC_DITHER_8_BPC (0<<5)
4479 #define PIPEMISC_DITHER_10_BPC (1<<5)
4480 #define PIPEMISC_DITHER_6_BPC (2<<5)
4481 #define PIPEMISC_DITHER_12_BPC (3<<5)
4482 #define PIPEMISC_DITHER_ENABLE (1<<4)
4483 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4484 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
4485 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
4487 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
4488 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
4489 #define PIPEB_HLINE_INT_EN (1<<28)
4490 #define PIPEB_VBLANK_INT_EN (1<<27)
4491 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
4492 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4493 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
4494 #define PIPE_PSR_INT_EN (1<<22)
4495 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
4496 #define PIPEA_HLINE_INT_EN (1<<20)
4497 #define PIPEA_VBLANK_INT_EN (1<<19)
4498 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4499 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
4500 #define PLANEA_FLIPDONE_INT_EN (1<<16)
4501 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4502 #define PIPEC_HLINE_INT_EN (1<<12)
4503 #define PIPEC_VBLANK_INT_EN (1<<11)
4504 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
4505 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
4506 #define PLANEC_FLIPDONE_INT_EN (1<<8)
4508 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4509 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4510 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4511 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
4512 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
4513 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
4514 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
4515 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
4516 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4517 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
4518 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4519 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4520 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
4521 #define DPINVGTT_EN_MASK 0xff0000
4522 #define DPINVGTT_EN_MASK_CHV 0xfff0000
4523 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
4524 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
4525 #define PLANEC_INVALID_GTT_STATUS (1<<9)
4526 #define CURSORC_INVALID_GTT_STATUS (1<<8)
4527 #define CURSORB_INVALID_GTT_STATUS (1<<7)
4528 #define CURSORA_INVALID_GTT_STATUS (1<<6)
4529 #define SPRITED_INVALID_GTT_STATUS (1<<5)
4530 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
4531 #define PLANEB_INVALID_GTT_STATUS (1<<3)
4532 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
4533 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
4534 #define PLANEA_INVALID_GTT_STATUS (1<<0)
4535 #define DPINVGTT_STATUS_MASK 0xff
4536 #define DPINVGTT_STATUS_MASK_CHV 0xfff
4538 #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
4539 #define DSPARB_CSTART_MASK (0x7f << 7)
4540 #define DSPARB_CSTART_SHIFT 7
4541 #define DSPARB_BSTART_MASK (0x7f)
4542 #define DSPARB_BSTART_SHIFT 0
4543 #define DSPARB_BEND_SHIFT 9 /* on 855 */
4544 #define DSPARB_AEND_SHIFT 0
4545 #define DSPARB_SPRITEA_SHIFT_VLV 0
4546 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4547 #define DSPARB_SPRITEB_SHIFT_VLV 8
4548 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4549 #define DSPARB_SPRITEC_SHIFT_VLV 16
4550 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4551 #define DSPARB_SPRITED_SHIFT_VLV 24
4552 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
4553 #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4554 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4555 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4556 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4557 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4558 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4559 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4560 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
4561 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4562 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4563 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4564 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4565 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
4566 #define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */
4567 #define DSPARB_SPRITEE_SHIFT_VLV 0
4568 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4569 #define DSPARB_SPRITEF_SHIFT_VLV 8
4570 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
4572 /* pnv/gen4/g4x/vlv/chv */
4573 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
4574 #define DSPFW_SR_SHIFT 23
4575 #define DSPFW_SR_MASK (0x1ff<<23)
4576 #define DSPFW_CURSORB_SHIFT 16
4577 #define DSPFW_CURSORB_MASK (0x3f<<16)
4578 #define DSPFW_PLANEB_SHIFT 8
4579 #define DSPFW_PLANEB_MASK (0x7f<<8)
4580 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4581 #define DSPFW_PLANEA_SHIFT 0
4582 #define DSPFW_PLANEA_MASK (0x7f<<0)
4583 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4584 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
4585 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4586 #define DSPFW_FBC_SR_SHIFT 28
4587 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4588 #define DSPFW_FBC_HPLL_SR_SHIFT 24
4589 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4590 #define DSPFW_SPRITEB_SHIFT (16)
4591 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4592 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4593 #define DSPFW_CURSORA_SHIFT 8
4594 #define DSPFW_CURSORA_MASK (0x3f<<8)
4595 #define DSPFW_PLANEC_OLD_SHIFT 0
4596 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
4597 #define DSPFW_SPRITEA_SHIFT 0
4598 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4599 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4600 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
4601 #define DSPFW_HPLL_SR_EN (1<<31)
4602 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
4603 #define DSPFW_CURSOR_SR_SHIFT 24
4604 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4605 #define DSPFW_HPLL_CURSOR_SHIFT 16
4606 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
4607 #define DSPFW_HPLL_SR_SHIFT 0
4608 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4611 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4612 #define DSPFW_SPRITEB_WM1_SHIFT 16
4613 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4614 #define DSPFW_CURSORA_WM1_SHIFT 8
4615 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4616 #define DSPFW_SPRITEA_WM1_SHIFT 0
4617 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4618 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4619 #define DSPFW_PLANEB_WM1_SHIFT 24
4620 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4621 #define DSPFW_PLANEA_WM1_SHIFT 16
4622 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4623 #define DSPFW_CURSORB_WM1_SHIFT 8
4624 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4625 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
4626 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4627 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4628 #define DSPFW_SR_WM1_SHIFT 0
4629 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
4630 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4631 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4632 #define DSPFW_SPRITED_WM1_SHIFT 24
4633 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4634 #define DSPFW_SPRITED_SHIFT 16
4635 #define DSPFW_SPRITED_MASK_VLV (0xff<<16)
4636 #define DSPFW_SPRITEC_WM1_SHIFT 8
4637 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4638 #define DSPFW_SPRITEC_SHIFT 0
4639 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
4640 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4641 #define DSPFW_SPRITEF_WM1_SHIFT 24
4642 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4643 #define DSPFW_SPRITEF_SHIFT 16
4644 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
4645 #define DSPFW_SPRITEE_WM1_SHIFT 8
4646 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4647 #define DSPFW_SPRITEE_SHIFT 0
4648 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
4649 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4650 #define DSPFW_PLANEC_WM1_SHIFT 24
4651 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4652 #define DSPFW_PLANEC_SHIFT 16
4653 #define DSPFW_PLANEC_MASK_VLV (0xff<<16)
4654 #define DSPFW_CURSORC_WM1_SHIFT 8
4655 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4656 #define DSPFW_CURSORC_SHIFT 0
4657 #define DSPFW_CURSORC_MASK (0x3f<<0)
4659 /* vlv/chv high order bits */
4660 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4661 #define DSPFW_SR_HI_SHIFT 24
4662 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4663 #define DSPFW_SPRITEF_HI_SHIFT 23
4664 #define DSPFW_SPRITEF_HI_MASK (1<<23)
4665 #define DSPFW_SPRITEE_HI_SHIFT 22
4666 #define DSPFW_SPRITEE_HI_MASK (1<<22)
4667 #define DSPFW_PLANEC_HI_SHIFT 21
4668 #define DSPFW_PLANEC_HI_MASK (1<<21)
4669 #define DSPFW_SPRITED_HI_SHIFT 20
4670 #define DSPFW_SPRITED_HI_MASK (1<<20)
4671 #define DSPFW_SPRITEC_HI_SHIFT 16
4672 #define DSPFW_SPRITEC_HI_MASK (1<<16)
4673 #define DSPFW_PLANEB_HI_SHIFT 12
4674 #define DSPFW_PLANEB_HI_MASK (1<<12)
4675 #define DSPFW_SPRITEB_HI_SHIFT 8
4676 #define DSPFW_SPRITEB_HI_MASK (1<<8)
4677 #define DSPFW_SPRITEA_HI_SHIFT 4
4678 #define DSPFW_SPRITEA_HI_MASK (1<<4)
4679 #define DSPFW_PLANEA_HI_SHIFT 0
4680 #define DSPFW_PLANEA_HI_MASK (1<<0)
4681 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4682 #define DSPFW_SR_WM1_HI_SHIFT 24
4683 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4684 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4685 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4686 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4687 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4688 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
4689 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4690 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
4691 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4692 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4693 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4694 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
4695 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4696 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4697 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4698 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4699 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4700 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
4701 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4703 /* drain latency register values*/
4704 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4705 #define DDL_CURSOR_SHIFT 24
4706 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4707 #define DDL_PLANE_SHIFT 0
4708 #define DDL_PRECISION_HIGH (1<<7)
4709 #define DDL_PRECISION_LOW (0<<7)
4710 #define DRAIN_LATENCY_MASK 0x7f
4712 #define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
4713 #define CBR_PND_DEADLINE_DISABLE (1<<31)
4714 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
4716 /* FIFO watermark sizes etc */
4717 #define G4X_FIFO_LINE_SIZE 64
4718 #define I915_FIFO_LINE_SIZE 64
4719 #define I830_FIFO_LINE_SIZE 32
4721 #define VALLEYVIEW_FIFO_SIZE 255
4722 #define G4X_FIFO_SIZE 127
4723 #define I965_FIFO_SIZE 512
4724 #define I945_FIFO_SIZE 127
4725 #define I915_FIFO_SIZE 95
4726 #define I855GM_FIFO_SIZE 127 /* In cachelines */
4727 #define I830_FIFO_SIZE 95
4729 #define VALLEYVIEW_MAX_WM 0xff
4730 #define G4X_MAX_WM 0x3f
4731 #define I915_MAX_WM 0x3f
4733 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4734 #define PINEVIEW_FIFO_LINE_SIZE 64
4735 #define PINEVIEW_MAX_WM 0x1ff
4736 #define PINEVIEW_DFT_WM 0x3f
4737 #define PINEVIEW_DFT_HPLLOFF_WM 0
4738 #define PINEVIEW_GUARD_WM 10
4739 #define PINEVIEW_CURSOR_FIFO 64
4740 #define PINEVIEW_CURSOR_MAX_WM 0x3f
4741 #define PINEVIEW_CURSOR_DFT_WM 0
4742 #define PINEVIEW_CURSOR_GUARD_WM 5
4744 #define VALLEYVIEW_CURSOR_MAX_WM 64
4745 #define I965_CURSOR_FIFO 64
4746 #define I965_CURSOR_MAX_WM 32
4747 #define I965_CURSOR_DFT_WM 8
4749 /* Watermark register definitions for SKL */
4750 #define CUR_WM_A_0 0x70140
4751 #define CUR_WM_B_0 0x71140
4752 #define PLANE_WM_1_A_0 0x70240
4753 #define PLANE_WM_1_B_0 0x71240
4754 #define PLANE_WM_2_A_0 0x70340
4755 #define PLANE_WM_2_B_0 0x71340
4756 #define PLANE_WM_TRANS_1_A_0 0x70268
4757 #define PLANE_WM_TRANS_1_B_0 0x71268
4758 #define PLANE_WM_TRANS_2_A_0 0x70368
4759 #define PLANE_WM_TRANS_2_B_0 0x71368
4760 #define CUR_WM_TRANS_A_0 0x70168
4761 #define CUR_WM_TRANS_B_0 0x71168
4762 #define PLANE_WM_EN (1 << 31)
4763 #define PLANE_WM_LINES_SHIFT 14
4764 #define PLANE_WM_LINES_MASK 0x1f
4765 #define PLANE_WM_BLOCKS_MASK 0x3ff
4767 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4768 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4769 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4771 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4772 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4773 #define _PLANE_WM_BASE(pipe, plane) \
4774 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4775 #define PLANE_WM(pipe, plane, level) \
4776 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4777 #define _PLANE_WM_TRANS_1(pipe) \
4778 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4779 #define _PLANE_WM_TRANS_2(pipe) \
4780 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4781 #define PLANE_WM_TRANS(pipe, plane) \
4782 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4784 /* define the Watermark register on Ironlake */
4785 #define WM0_PIPEA_ILK 0x45100
4786 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
4787 #define WM0_PIPE_PLANE_SHIFT 16
4788 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
4789 #define WM0_PIPE_SPRITE_SHIFT 8
4790 #define WM0_PIPE_CURSOR_MASK (0xff)
4792 #define WM0_PIPEB_ILK 0x45104
4793 #define WM0_PIPEC_IVB 0x45200
4794 #define WM1_LP_ILK 0x45108
4795 #define WM1_LP_SR_EN (1<<31)
4796 #define WM1_LP_LATENCY_SHIFT 24
4797 #define WM1_LP_LATENCY_MASK (0x7f<<24)
4798 #define WM1_LP_FBC_MASK (0xf<<20)
4799 #define WM1_LP_FBC_SHIFT 20
4800 #define WM1_LP_FBC_SHIFT_BDW 19
4801 #define WM1_LP_SR_MASK (0x7ff<<8)
4802 #define WM1_LP_SR_SHIFT 8
4803 #define WM1_LP_CURSOR_MASK (0xff)
4804 #define WM2_LP_ILK 0x4510c
4805 #define WM2_LP_EN (1<<31)
4806 #define WM3_LP_ILK 0x45110
4807 #define WM3_LP_EN (1<<31)
4808 #define WM1S_LP_ILK 0x45120
4809 #define WM2S_LP_IVB 0x45124
4810 #define WM3S_LP_IVB 0x45128
4811 #define WM1S_LP_EN (1<<31)
4813 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4814 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4815 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4817 /* Memory latency timer register */
4818 #define MLTR_ILK 0x11222
4819 #define MLTR_WM1_SHIFT 0
4820 #define MLTR_WM2_SHIFT 8
4821 /* the unit of memory self-refresh latency time is 0.5us */
4822 #define ILK_SRLT_MASK 0x3f
4825 /* the address where we get all kinds of latency value */
4826 #define SSKPD 0x5d10
4827 #define SSKPD_WM_MASK 0x3f
4828 #define SSKPD_WM0_SHIFT 0
4829 #define SSKPD_WM1_SHIFT 8
4830 #define SSKPD_WM2_SHIFT 16
4831 #define SSKPD_WM3_SHIFT 24
4834 * The two pipe frame counter registers are not synchronized, so
4835 * reading a stable value is somewhat tricky. The following code
4839 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4840 * PIPE_FRAME_HIGH_SHIFT;
4841 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4842 * PIPE_FRAME_LOW_SHIFT);
4843 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4844 * PIPE_FRAME_HIGH_SHIFT);
4845 * } while (high1 != high2);
4846 * frame = (high1 << 8) | low1;
4848 #define _PIPEAFRAMEHIGH 0x70040
4849 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4850 #define PIPE_FRAME_HIGH_SHIFT 0
4851 #define _PIPEAFRAMEPIXEL 0x70044
4852 #define PIPE_FRAME_LOW_MASK 0xff000000
4853 #define PIPE_FRAME_LOW_SHIFT 24
4854 #define PIPE_PIXEL_MASK 0x00ffffff
4855 #define PIPE_PIXEL_SHIFT 0
4856 /* GM45+ just has to be different */
4857 #define _PIPEA_FRMCOUNT_G4X 0x70040
4858 #define _PIPEA_FLIPCOUNT_G4X 0x70044
4859 #define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4860 #define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4862 /* Cursor A & B regs */
4863 #define _CURACNTR 0x70080
4864 /* Old style CUR*CNTR flags (desktop 8xx) */
4865 #define CURSOR_ENABLE 0x80000000
4866 #define CURSOR_GAMMA_ENABLE 0x40000000
4867 #define CURSOR_STRIDE_SHIFT 28
4868 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4869 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
4870 #define CURSOR_FORMAT_SHIFT 24
4871 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4872 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4873 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4874 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4875 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4876 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4877 /* New style CUR*CNTR flags */
4878 #define CURSOR_MODE 0x27
4879 #define CURSOR_MODE_DISABLE 0x00
4880 #define CURSOR_MODE_128_32B_AX 0x02
4881 #define CURSOR_MODE_256_32B_AX 0x03
4882 #define CURSOR_MODE_64_32B_AX 0x07
4883 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4884 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4885 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4886 #define MCURSOR_PIPE_SELECT (1 << 28)
4887 #define MCURSOR_PIPE_A 0x00
4888 #define MCURSOR_PIPE_B (1 << 28)
4889 #define MCURSOR_GAMMA_ENABLE (1 << 26)
4890 #define CURSOR_ROTATE_180 (1<<15)
4891 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4892 #define _CURABASE 0x70084
4893 #define _CURAPOS 0x70088
4894 #define CURSOR_POS_MASK 0x007FF
4895 #define CURSOR_POS_SIGN 0x8000
4896 #define CURSOR_X_SHIFT 0
4897 #define CURSOR_Y_SHIFT 16
4898 #define CURSIZE 0x700a0
4899 #define _CURBCNTR 0x700c0
4900 #define _CURBBASE 0x700c4
4901 #define _CURBPOS 0x700c8
4903 #define _CURBCNTR_IVB 0x71080
4904 #define _CURBBASE_IVB 0x71084
4905 #define _CURBPOS_IVB 0x71088
4907 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4908 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4909 dev_priv->info.display_mmio_offset)
4911 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4912 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4913 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4915 #define CURSOR_A_OFFSET 0x70080
4916 #define CURSOR_B_OFFSET 0x700c0
4917 #define CHV_CURSOR_C_OFFSET 0x700e0
4918 #define IVB_CURSOR_B_OFFSET 0x71080
4919 #define IVB_CURSOR_C_OFFSET 0x72080
4921 /* Display A control */
4922 #define _DSPACNTR 0x70180
4923 #define DISPLAY_PLANE_ENABLE (1<<31)
4924 #define DISPLAY_PLANE_DISABLE 0
4925 #define DISPPLANE_GAMMA_ENABLE (1<<30)
4926 #define DISPPLANE_GAMMA_DISABLE 0
4927 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
4928 #define DISPPLANE_YUV422 (0x0<<26)
4929 #define DISPPLANE_8BPP (0x2<<26)
4930 #define DISPPLANE_BGRA555 (0x3<<26)
4931 #define DISPPLANE_BGRX555 (0x4<<26)
4932 #define DISPPLANE_BGRX565 (0x5<<26)
4933 #define DISPPLANE_BGRX888 (0x6<<26)
4934 #define DISPPLANE_BGRA888 (0x7<<26)
4935 #define DISPPLANE_RGBX101010 (0x8<<26)
4936 #define DISPPLANE_RGBA101010 (0x9<<26)
4937 #define DISPPLANE_BGRX101010 (0xa<<26)
4938 #define DISPPLANE_RGBX161616 (0xc<<26)
4939 #define DISPPLANE_RGBX888 (0xe<<26)
4940 #define DISPPLANE_RGBA888 (0xf<<26)
4941 #define DISPPLANE_STEREO_ENABLE (1<<25)
4942 #define DISPPLANE_STEREO_DISABLE 0
4943 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
4944 #define DISPPLANE_SEL_PIPE_SHIFT 24
4945 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
4946 #define DISPPLANE_SEL_PIPE_A 0
4947 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
4948 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4949 #define DISPPLANE_SRC_KEY_DISABLE 0
4950 #define DISPPLANE_LINE_DOUBLE (1<<20)
4951 #define DISPPLANE_NO_LINE_DOUBLE 0
4952 #define DISPPLANE_STEREO_POLARITY_FIRST 0
4953 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
4954 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4955 #define DISPPLANE_ROTATE_180 (1<<15)
4956 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
4957 #define DISPPLANE_TILED (1<<10)
4958 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
4959 #define _DSPAADDR 0x70184
4960 #define _DSPASTRIDE 0x70188
4961 #define _DSPAPOS 0x7018C /* reserved */
4962 #define _DSPASIZE 0x70190
4963 #define _DSPASURF 0x7019C /* 965+ only */
4964 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4965 #define _DSPAOFFSET 0x701A4 /* HSW */
4966 #define _DSPASURFLIVE 0x701AC
4968 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4969 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4970 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4971 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4972 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4973 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4974 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4975 #define DSPLINOFF(plane) DSPADDR(plane)
4976 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4977 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4979 /* CHV pipe B blender and primary plane */
4980 #define _CHV_BLEND_A 0x60a00
4981 #define CHV_BLEND_LEGACY (0<<30)
4982 #define CHV_BLEND_ANDROID (1<<30)
4983 #define CHV_BLEND_MPO (2<<30)
4984 #define CHV_BLEND_MASK (3<<30)
4985 #define _CHV_CANVAS_A 0x60a04
4986 #define _PRIMPOS_A 0x60a08
4987 #define _PRIMSIZE_A 0x60a0c
4988 #define _PRIMCNSTALPHA_A 0x60a10
4989 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
4991 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4992 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4993 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4994 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4995 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4997 /* Display/Sprite base address macros */
4998 #define DISP_BASEADDR_MASK (0xfffff000)
4999 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
5000 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
5013 #define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5014 #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5015 #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5018 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
5019 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
5020 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
5021 #define _PIPEBFRAMEHIGH 0x71040
5022 #define _PIPEBFRAMEPIXEL 0x71044
5023 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
5024 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
5027 /* Display B control */
5028 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
5029 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
5030 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
5031 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
5032 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
5033 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
5034 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
5035 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
5036 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
5037 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
5038 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
5039 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
5040 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
5042 /* Sprite A control */
5043 #define _DVSACNTR 0x72180
5044 #define DVS_ENABLE (1<<31)
5045 #define DVS_GAMMA_ENABLE (1<<30)
5046 #define DVS_PIXFORMAT_MASK (3<<25)
5047 #define DVS_FORMAT_YUV422 (0<<25)
5048 #define DVS_FORMAT_RGBX101010 (1<<25)
5049 #define DVS_FORMAT_RGBX888 (2<<25)
5050 #define DVS_FORMAT_RGBX161616 (3<<25)
5051 #define DVS_PIPE_CSC_ENABLE (1<<24)
5052 #define DVS_SOURCE_KEY (1<<22)
5053 #define DVS_RGB_ORDER_XBGR (1<<20)
5054 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
5055 #define DVS_YUV_ORDER_YUYV (0<<16)
5056 #define DVS_YUV_ORDER_UYVY (1<<16)
5057 #define DVS_YUV_ORDER_YVYU (2<<16)
5058 #define DVS_YUV_ORDER_VYUY (3<<16)
5059 #define DVS_ROTATE_180 (1<<15)
5060 #define DVS_DEST_KEY (1<<2)
5061 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
5062 #define DVS_TILED (1<<10)
5063 #define _DVSALINOFF 0x72184
5064 #define _DVSASTRIDE 0x72188
5065 #define _DVSAPOS 0x7218c
5066 #define _DVSASIZE 0x72190
5067 #define _DVSAKEYVAL 0x72194
5068 #define _DVSAKEYMSK 0x72198
5069 #define _DVSASURF 0x7219c
5070 #define _DVSAKEYMAXVAL 0x721a0
5071 #define _DVSATILEOFF 0x721a4
5072 #define _DVSASURFLIVE 0x721ac
5073 #define _DVSASCALE 0x72204
5074 #define DVS_SCALE_ENABLE (1<<31)
5075 #define DVS_FILTER_MASK (3<<29)
5076 #define DVS_FILTER_MEDIUM (0<<29)
5077 #define DVS_FILTER_ENHANCING (1<<29)
5078 #define DVS_FILTER_SOFTENING (2<<29)
5079 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5080 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5081 #define _DVSAGAMC 0x72300
5083 #define _DVSBCNTR 0x73180
5084 #define _DVSBLINOFF 0x73184
5085 #define _DVSBSTRIDE 0x73188
5086 #define _DVSBPOS 0x7318c
5087 #define _DVSBSIZE 0x73190
5088 #define _DVSBKEYVAL 0x73194
5089 #define _DVSBKEYMSK 0x73198
5090 #define _DVSBSURF 0x7319c
5091 #define _DVSBKEYMAXVAL 0x731a0
5092 #define _DVSBTILEOFF 0x731a4
5093 #define _DVSBSURFLIVE 0x731ac
5094 #define _DVSBSCALE 0x73204
5095 #define _DVSBGAMC 0x73300
5097 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5098 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5099 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5100 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
5101 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
5102 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5103 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5104 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5105 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5106 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5107 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5108 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5110 #define _SPRA_CTL 0x70280
5111 #define SPRITE_ENABLE (1<<31)
5112 #define SPRITE_GAMMA_ENABLE (1<<30)
5113 #define SPRITE_PIXFORMAT_MASK (7<<25)
5114 #define SPRITE_FORMAT_YUV422 (0<<25)
5115 #define SPRITE_FORMAT_RGBX101010 (1<<25)
5116 #define SPRITE_FORMAT_RGBX888 (2<<25)
5117 #define SPRITE_FORMAT_RGBX161616 (3<<25)
5118 #define SPRITE_FORMAT_YUV444 (4<<25)
5119 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
5120 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
5121 #define SPRITE_SOURCE_KEY (1<<22)
5122 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5123 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5124 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5125 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5126 #define SPRITE_YUV_ORDER_YUYV (0<<16)
5127 #define SPRITE_YUV_ORDER_UYVY (1<<16)
5128 #define SPRITE_YUV_ORDER_YVYU (2<<16)
5129 #define SPRITE_YUV_ORDER_VYUY (3<<16)
5130 #define SPRITE_ROTATE_180 (1<<15)
5131 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5132 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
5133 #define SPRITE_TILED (1<<10)
5134 #define SPRITE_DEST_KEY (1<<2)
5135 #define _SPRA_LINOFF 0x70284
5136 #define _SPRA_STRIDE 0x70288
5137 #define _SPRA_POS 0x7028c
5138 #define _SPRA_SIZE 0x70290
5139 #define _SPRA_KEYVAL 0x70294
5140 #define _SPRA_KEYMSK 0x70298
5141 #define _SPRA_SURF 0x7029c
5142 #define _SPRA_KEYMAX 0x702a0
5143 #define _SPRA_TILEOFF 0x702a4
5144 #define _SPRA_OFFSET 0x702a4
5145 #define _SPRA_SURFLIVE 0x702ac
5146 #define _SPRA_SCALE 0x70304
5147 #define SPRITE_SCALE_ENABLE (1<<31)
5148 #define SPRITE_FILTER_MASK (3<<29)
5149 #define SPRITE_FILTER_MEDIUM (0<<29)
5150 #define SPRITE_FILTER_ENHANCING (1<<29)
5151 #define SPRITE_FILTER_SOFTENING (2<<29)
5152 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5153 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5154 #define _SPRA_GAMC 0x70400
5156 #define _SPRB_CTL 0x71280
5157 #define _SPRB_LINOFF 0x71284
5158 #define _SPRB_STRIDE 0x71288
5159 #define _SPRB_POS 0x7128c
5160 #define _SPRB_SIZE 0x71290
5161 #define _SPRB_KEYVAL 0x71294
5162 #define _SPRB_KEYMSK 0x71298
5163 #define _SPRB_SURF 0x7129c
5164 #define _SPRB_KEYMAX 0x712a0
5165 #define _SPRB_TILEOFF 0x712a4
5166 #define _SPRB_OFFSET 0x712a4
5167 #define _SPRB_SURFLIVE 0x712ac
5168 #define _SPRB_SCALE 0x71304
5169 #define _SPRB_GAMC 0x71400
5171 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5172 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5173 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5174 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
5175 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5176 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5177 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5178 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5179 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5180 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5181 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5182 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5183 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5184 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5186 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5187 #define SP_ENABLE (1<<31)
5188 #define SP_GAMMA_ENABLE (1<<30)
5189 #define SP_PIXFORMAT_MASK (0xf<<26)
5190 #define SP_FORMAT_YUV422 (0<<26)
5191 #define SP_FORMAT_BGR565 (5<<26)
5192 #define SP_FORMAT_BGRX8888 (6<<26)
5193 #define SP_FORMAT_BGRA8888 (7<<26)
5194 #define SP_FORMAT_RGBX1010102 (8<<26)
5195 #define SP_FORMAT_RGBA1010102 (9<<26)
5196 #define SP_FORMAT_RGBX8888 (0xe<<26)
5197 #define SP_FORMAT_RGBA8888 (0xf<<26)
5198 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
5199 #define SP_SOURCE_KEY (1<<22)
5200 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
5201 #define SP_YUV_ORDER_YUYV (0<<16)
5202 #define SP_YUV_ORDER_UYVY (1<<16)
5203 #define SP_YUV_ORDER_YVYU (2<<16)
5204 #define SP_YUV_ORDER_VYUY (3<<16)
5205 #define SP_ROTATE_180 (1<<15)
5206 #define SP_TILED (1<<10)
5207 #define SP_MIRROR (1<<8) /* CHV pipe B */
5208 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5209 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5210 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5211 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5212 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5213 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5214 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5215 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5216 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5217 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
5218 #define SP_CONST_ALPHA_ENABLE (1<<31)
5219 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
5221 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5222 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5223 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5224 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5225 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5226 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5227 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5228 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5229 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5230 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5231 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5232 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5234 #define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5235 #define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5236 #define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5237 #define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5238 #define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5239 #define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5240 #define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5241 #define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5242 #define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5243 #define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5244 #define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5245 #define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
5248 * CHV pipe B sprite CSC
5250 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5251 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5252 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5254 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5255 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5256 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5257 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5258 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5260 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5261 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5262 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5263 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5264 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5265 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5266 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5268 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5269 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5270 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5271 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5272 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5274 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5275 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5276 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5277 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5278 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5280 /* Skylake plane registers */
5282 #define _PLANE_CTL_1_A 0x70180
5283 #define _PLANE_CTL_2_A 0x70280
5284 #define _PLANE_CTL_3_A 0x70380
5285 #define PLANE_CTL_ENABLE (1 << 31)
5286 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5287 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
5288 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5289 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5290 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5291 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5292 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5293 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5294 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5295 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5296 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
5297 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5298 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5299 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
5300 #define PLANE_CTL_ORDER_BGRX (0 << 20)
5301 #define PLANE_CTL_ORDER_RGBX (1 << 20)
5302 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5303 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5304 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5305 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5306 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5307 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5308 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5309 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5310 #define PLANE_CTL_TILED_MASK (0x7 << 10)
5311 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5312 #define PLANE_CTL_TILED_X ( 1 << 10)
5313 #define PLANE_CTL_TILED_Y ( 4 << 10)
5314 #define PLANE_CTL_TILED_YF ( 5 << 10)
5315 #define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5316 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5317 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5318 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
5319 #define PLANE_CTL_ROTATE_MASK 0x3
5320 #define PLANE_CTL_ROTATE_0 0x0
5321 #define PLANE_CTL_ROTATE_90 0x1
5322 #define PLANE_CTL_ROTATE_180 0x2
5323 #define PLANE_CTL_ROTATE_270 0x3
5324 #define _PLANE_STRIDE_1_A 0x70188
5325 #define _PLANE_STRIDE_2_A 0x70288
5326 #define _PLANE_STRIDE_3_A 0x70388
5327 #define _PLANE_POS_1_A 0x7018c
5328 #define _PLANE_POS_2_A 0x7028c
5329 #define _PLANE_POS_3_A 0x7038c
5330 #define _PLANE_SIZE_1_A 0x70190
5331 #define _PLANE_SIZE_2_A 0x70290
5332 #define _PLANE_SIZE_3_A 0x70390
5333 #define _PLANE_SURF_1_A 0x7019c
5334 #define _PLANE_SURF_2_A 0x7029c
5335 #define _PLANE_SURF_3_A 0x7039c
5336 #define _PLANE_OFFSET_1_A 0x701a4
5337 #define _PLANE_OFFSET_2_A 0x702a4
5338 #define _PLANE_OFFSET_3_A 0x703a4
5339 #define _PLANE_KEYVAL_1_A 0x70194
5340 #define _PLANE_KEYVAL_2_A 0x70294
5341 #define _PLANE_KEYMSK_1_A 0x70198
5342 #define _PLANE_KEYMSK_2_A 0x70298
5343 #define _PLANE_KEYMAX_1_A 0x701a0
5344 #define _PLANE_KEYMAX_2_A 0x702a0
5345 #define _PLANE_BUF_CFG_1_A 0x7027c
5346 #define _PLANE_BUF_CFG_2_A 0x7037c
5347 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
5348 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
5350 #define _PLANE_CTL_1_B 0x71180
5351 #define _PLANE_CTL_2_B 0x71280
5352 #define _PLANE_CTL_3_B 0x71380
5353 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5354 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5355 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5356 #define PLANE_CTL(pipe, plane) \
5357 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5359 #define _PLANE_STRIDE_1_B 0x71188
5360 #define _PLANE_STRIDE_2_B 0x71288
5361 #define _PLANE_STRIDE_3_B 0x71388
5362 #define _PLANE_STRIDE_1(pipe) \
5363 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5364 #define _PLANE_STRIDE_2(pipe) \
5365 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5366 #define _PLANE_STRIDE_3(pipe) \
5367 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5368 #define PLANE_STRIDE(pipe, plane) \
5369 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5371 #define _PLANE_POS_1_B 0x7118c
5372 #define _PLANE_POS_2_B 0x7128c
5373 #define _PLANE_POS_3_B 0x7138c
5374 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5375 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5376 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5377 #define PLANE_POS(pipe, plane) \
5378 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5380 #define _PLANE_SIZE_1_B 0x71190
5381 #define _PLANE_SIZE_2_B 0x71290
5382 #define _PLANE_SIZE_3_B 0x71390
5383 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5384 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5385 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5386 #define PLANE_SIZE(pipe, plane) \
5387 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5389 #define _PLANE_SURF_1_B 0x7119c
5390 #define _PLANE_SURF_2_B 0x7129c
5391 #define _PLANE_SURF_3_B 0x7139c
5392 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5393 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5394 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5395 #define PLANE_SURF(pipe, plane) \
5396 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5398 #define _PLANE_OFFSET_1_B 0x711a4
5399 #define _PLANE_OFFSET_2_B 0x712a4
5400 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5401 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5402 #define PLANE_OFFSET(pipe, plane) \
5403 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5405 #define _PLANE_KEYVAL_1_B 0x71194
5406 #define _PLANE_KEYVAL_2_B 0x71294
5407 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5408 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5409 #define PLANE_KEYVAL(pipe, plane) \
5410 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5412 #define _PLANE_KEYMSK_1_B 0x71198
5413 #define _PLANE_KEYMSK_2_B 0x71298
5414 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5415 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5416 #define PLANE_KEYMSK(pipe, plane) \
5417 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5419 #define _PLANE_KEYMAX_1_B 0x711a0
5420 #define _PLANE_KEYMAX_2_B 0x712a0
5421 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5422 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5423 #define PLANE_KEYMAX(pipe, plane) \
5424 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5426 #define _PLANE_BUF_CFG_1_B 0x7127c
5427 #define _PLANE_BUF_CFG_2_B 0x7137c
5428 #define _PLANE_BUF_CFG_1(pipe) \
5429 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5430 #define _PLANE_BUF_CFG_2(pipe) \
5431 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5432 #define PLANE_BUF_CFG(pipe, plane) \
5433 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5435 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
5436 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
5437 #define _PLANE_NV12_BUF_CFG_1(pipe) \
5438 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5439 #define _PLANE_NV12_BUF_CFG_2(pipe) \
5440 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5441 #define PLANE_NV12_BUF_CFG(pipe, plane) \
5442 _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5444 /* SKL new cursor registers */
5445 #define _CUR_BUF_CFG_A 0x7017c
5446 #define _CUR_BUF_CFG_B 0x7117c
5447 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5450 #define VGACNTRL 0x71400
5451 # define VGA_DISP_DISABLE (1 << 31)
5452 # define VGA_2X_MODE (1 << 30)
5453 # define VGA_PIPE_B_SELECT (1 << 29)
5455 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
5459 #define CPU_VGACNTRL 0x41000
5461 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
5462 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5463 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5464 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5465 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5466 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5467 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5468 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5469 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5470 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5471 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5473 /* refresh rate hardware control */
5474 #define RR_HW_CTL 0x45300
5475 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5476 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5478 #define FDI_PLL_BIOS_0 0x46000
5479 #define FDI_PLL_FB_CLOCK_MASK 0xff
5480 #define FDI_PLL_BIOS_1 0x46004
5481 #define FDI_PLL_BIOS_2 0x46008
5482 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
5483 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
5484 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
5486 #define PCH_3DCGDIS0 0x46020
5487 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5488 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5490 #define PCH_3DCGDIS1 0x46024
5491 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5493 #define FDI_PLL_FREQ_CTL 0x46030
5494 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5495 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5496 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5499 #define _PIPEA_DATA_M1 0x60030
5500 #define PIPE_DATA_M1_OFFSET 0
5501 #define _PIPEA_DATA_N1 0x60034
5502 #define PIPE_DATA_N1_OFFSET 0
5504 #define _PIPEA_DATA_M2 0x60038
5505 #define PIPE_DATA_M2_OFFSET 0
5506 #define _PIPEA_DATA_N2 0x6003c
5507 #define PIPE_DATA_N2_OFFSET 0
5509 #define _PIPEA_LINK_M1 0x60040
5510 #define PIPE_LINK_M1_OFFSET 0
5511 #define _PIPEA_LINK_N1 0x60044
5512 #define PIPE_LINK_N1_OFFSET 0
5514 #define _PIPEA_LINK_M2 0x60048
5515 #define PIPE_LINK_M2_OFFSET 0
5516 #define _PIPEA_LINK_N2 0x6004c
5517 #define PIPE_LINK_N2_OFFSET 0
5519 /* PIPEB timing regs are same start from 0x61000 */
5521 #define _PIPEB_DATA_M1 0x61030
5522 #define _PIPEB_DATA_N1 0x61034
5523 #define _PIPEB_DATA_M2 0x61038
5524 #define _PIPEB_DATA_N2 0x6103c
5525 #define _PIPEB_LINK_M1 0x61040
5526 #define _PIPEB_LINK_N1 0x61044
5527 #define _PIPEB_LINK_M2 0x61048
5528 #define _PIPEB_LINK_N2 0x6104c
5530 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
5531 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
5532 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
5533 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
5534 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
5535 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
5536 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
5537 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
5539 /* CPU panel fitter */
5540 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5541 #define _PFA_CTL_1 0x68080
5542 #define _PFB_CTL_1 0x68880
5543 #define PF_ENABLE (1<<31)
5544 #define PF_PIPE_SEL_MASK_IVB (3<<29)
5545 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
5546 #define PF_FILTER_MASK (3<<23)
5547 #define PF_FILTER_PROGRAMMED (0<<23)
5548 #define PF_FILTER_MED_3x3 (1<<23)
5549 #define PF_FILTER_EDGE_ENHANCE (2<<23)
5550 #define PF_FILTER_EDGE_SOFTEN (3<<23)
5551 #define _PFA_WIN_SZ 0x68074
5552 #define _PFB_WIN_SZ 0x68874
5553 #define _PFA_WIN_POS 0x68070
5554 #define _PFB_WIN_POS 0x68870
5555 #define _PFA_VSCALE 0x68084
5556 #define _PFB_VSCALE 0x68884
5557 #define _PFA_HSCALE 0x68090
5558 #define _PFB_HSCALE 0x68890
5560 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5561 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5562 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5563 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5564 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5566 #define _PSA_CTL 0x68180
5567 #define _PSB_CTL 0x68980
5568 #define PS_ENABLE (1<<31)
5569 #define _PSA_WIN_SZ 0x68174
5570 #define _PSB_WIN_SZ 0x68974
5571 #define _PSA_WIN_POS 0x68170
5572 #define _PSB_WIN_POS 0x68970
5574 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
5575 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5576 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5581 #define _PS_1A_CTRL 0x68180
5582 #define _PS_2A_CTRL 0x68280
5583 #define _PS_1B_CTRL 0x68980
5584 #define _PS_2B_CTRL 0x68A80
5585 #define _PS_1C_CTRL 0x69180
5586 #define PS_SCALER_EN (1 << 31)
5587 #define PS_SCALER_MODE_MASK (3 << 28)
5588 #define PS_SCALER_MODE_DYN (0 << 28)
5589 #define PS_SCALER_MODE_HQ (1 << 28)
5590 #define PS_PLANE_SEL_MASK (7 << 25)
5591 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5592 #define PS_FILTER_MASK (3 << 23)
5593 #define PS_FILTER_MEDIUM (0 << 23)
5594 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5595 #define PS_FILTER_BILINEAR (3 << 23)
5596 #define PS_VERT3TAP (1 << 21)
5597 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5598 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5599 #define PS_PWRUP_PROGRESS (1 << 17)
5600 #define PS_V_FILTER_BYPASS (1 << 8)
5601 #define PS_VADAPT_EN (1 << 7)
5602 #define PS_VADAPT_MODE_MASK (3 << 5)
5603 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5604 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5605 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5607 #define _PS_PWR_GATE_1A 0x68160
5608 #define _PS_PWR_GATE_2A 0x68260
5609 #define _PS_PWR_GATE_1B 0x68960
5610 #define _PS_PWR_GATE_2B 0x68A60
5611 #define _PS_PWR_GATE_1C 0x69160
5612 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5613 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5614 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5615 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5616 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5617 #define PS_PWR_GATE_SLPEN_8 0
5618 #define PS_PWR_GATE_SLPEN_16 1
5619 #define PS_PWR_GATE_SLPEN_24 2
5620 #define PS_PWR_GATE_SLPEN_32 3
5622 #define _PS_WIN_POS_1A 0x68170
5623 #define _PS_WIN_POS_2A 0x68270
5624 #define _PS_WIN_POS_1B 0x68970
5625 #define _PS_WIN_POS_2B 0x68A70
5626 #define _PS_WIN_POS_1C 0x69170
5628 #define _PS_WIN_SZ_1A 0x68174
5629 #define _PS_WIN_SZ_2A 0x68274
5630 #define _PS_WIN_SZ_1B 0x68974
5631 #define _PS_WIN_SZ_2B 0x68A74
5632 #define _PS_WIN_SZ_1C 0x69174
5634 #define _PS_VSCALE_1A 0x68184
5635 #define _PS_VSCALE_2A 0x68284
5636 #define _PS_VSCALE_1B 0x68984
5637 #define _PS_VSCALE_2B 0x68A84
5638 #define _PS_VSCALE_1C 0x69184
5640 #define _PS_HSCALE_1A 0x68190
5641 #define _PS_HSCALE_2A 0x68290
5642 #define _PS_HSCALE_1B 0x68990
5643 #define _PS_HSCALE_2B 0x68A90
5644 #define _PS_HSCALE_1C 0x69190
5646 #define _PS_VPHASE_1A 0x68188
5647 #define _PS_VPHASE_2A 0x68288
5648 #define _PS_VPHASE_1B 0x68988
5649 #define _PS_VPHASE_2B 0x68A88
5650 #define _PS_VPHASE_1C 0x69188
5652 #define _PS_HPHASE_1A 0x68194
5653 #define _PS_HPHASE_2A 0x68294
5654 #define _PS_HPHASE_1B 0x68994
5655 #define _PS_HPHASE_2B 0x68A94
5656 #define _PS_HPHASE_1C 0x69194
5658 #define _PS_ECC_STAT_1A 0x681D0
5659 #define _PS_ECC_STAT_2A 0x682D0
5660 #define _PS_ECC_STAT_1B 0x689D0
5661 #define _PS_ECC_STAT_2B 0x68AD0
5662 #define _PS_ECC_STAT_1C 0x691D0
5664 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5665 #define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \
5666 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5667 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5668 #define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \
5669 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5670 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5671 #define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \
5672 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5673 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5674 #define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \
5675 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5676 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5677 #define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \
5678 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5679 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5680 #define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \
5681 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5682 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5683 #define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \
5684 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5685 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5686 #define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \
5687 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5688 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5689 #define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \
5690 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5691 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
5693 /* legacy palette */
5694 #define _LGC_PALETTE_A 0x4a000
5695 #define _LGC_PALETTE_B 0x4a800
5696 #define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5698 #define _GAMMA_MODE_A 0x4a480
5699 #define _GAMMA_MODE_B 0x4ac80
5700 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5701 #define GAMMA_MODE_MODE_MASK (3 << 0)
5702 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5703 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5704 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5705 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
5708 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5709 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5710 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5711 #define DE_PLANEB_FLIP_DONE (1 << 27)
5712 #define DE_PLANEA_FLIP_DONE (1 << 26)
5713 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5714 #define DE_PCU_EVENT (1 << 25)
5715 #define DE_GTT_FAULT (1 << 24)
5716 #define DE_POISON (1 << 23)
5717 #define DE_PERFORM_COUNTER (1 << 22)
5718 #define DE_PCH_EVENT (1 << 21)
5719 #define DE_AUX_CHANNEL_A (1 << 20)
5720 #define DE_DP_A_HOTPLUG (1 << 19)
5721 #define DE_GSE (1 << 18)
5722 #define DE_PIPEB_VBLANK (1 << 15)
5723 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5724 #define DE_PIPEB_ODD_FIELD (1 << 13)
5725 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5726 #define DE_PIPEB_VSYNC (1 << 11)
5727 #define DE_PIPEB_CRC_DONE (1 << 10)
5728 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5729 #define DE_PIPEA_VBLANK (1 << 7)
5730 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
5731 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5732 #define DE_PIPEA_ODD_FIELD (1 << 5)
5733 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5734 #define DE_PIPEA_VSYNC (1 << 3)
5735 #define DE_PIPEA_CRC_DONE (1 << 2)
5736 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
5737 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5738 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
5740 /* More Ivybridge lolz */
5741 #define DE_ERR_INT_IVB (1<<30)
5742 #define DE_GSE_IVB (1<<29)
5743 #define DE_PCH_EVENT_IVB (1<<28)
5744 #define DE_DP_A_HOTPLUG_IVB (1<<27)
5745 #define DE_AUX_CHANNEL_A_IVB (1<<26)
5746 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5747 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5748 #define DE_PIPEC_VBLANK_IVB (1<<10)
5749 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
5750 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
5751 #define DE_PIPEB_VBLANK_IVB (1<<5)
5752 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5753 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
5754 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
5755 #define DE_PIPEA_VBLANK_IVB (1<<0)
5756 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5758 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5759 #define MASTER_INTERRUPT_ENABLE (1<<31)
5761 #define DEISR 0x44000
5762 #define DEIMR 0x44004
5763 #define DEIIR 0x44008
5764 #define DEIER 0x4400c
5766 #define GTISR 0x44010
5767 #define GTIMR 0x44014
5768 #define GTIIR 0x44018
5769 #define GTIER 0x4401c
5771 #define GEN8_MASTER_IRQ 0x44200
5772 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
5773 #define GEN8_PCU_IRQ (1<<30)
5774 #define GEN8_DE_PCH_IRQ (1<<23)
5775 #define GEN8_DE_MISC_IRQ (1<<22)
5776 #define GEN8_DE_PORT_IRQ (1<<20)
5777 #define GEN8_DE_PIPE_C_IRQ (1<<18)
5778 #define GEN8_DE_PIPE_B_IRQ (1<<17)
5779 #define GEN8_DE_PIPE_A_IRQ (1<<16)
5780 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
5781 #define GEN8_GT_VECS_IRQ (1<<6)
5782 #define GEN8_GT_PM_IRQ (1<<4)
5783 #define GEN8_GT_VCS2_IRQ (1<<3)
5784 #define GEN8_GT_VCS1_IRQ (1<<2)
5785 #define GEN8_GT_BCS_IRQ (1<<1)
5786 #define GEN8_GT_RCS_IRQ (1<<0)
5788 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5789 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5790 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5791 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5793 #define GEN8_RCS_IRQ_SHIFT 0
5794 #define GEN8_BCS_IRQ_SHIFT 16
5795 #define GEN8_VCS1_IRQ_SHIFT 0
5796 #define GEN8_VCS2_IRQ_SHIFT 16
5797 #define GEN8_VECS_IRQ_SHIFT 0
5798 #define GEN8_WD_IRQ_SHIFT 16
5800 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5801 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5802 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5803 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
5804 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5805 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5806 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5807 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5808 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5809 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5810 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5811 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5812 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5813 #define GEN8_PIPE_VSYNC (1 << 1)
5814 #define GEN8_PIPE_VBLANK (1 << 0)
5815 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5816 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
5817 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5818 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5819 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5820 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
5821 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5822 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5823 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5824 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
5825 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5826 (GEN8_PIPE_CURSOR_FAULT | \
5827 GEN8_PIPE_SPRITE_FAULT | \
5828 GEN8_PIPE_PRIMARY_FAULT)
5829 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5830 (GEN9_PIPE_CURSOR_FAULT | \
5831 GEN9_PIPE_PLANE4_FAULT | \
5832 GEN9_PIPE_PLANE3_FAULT | \
5833 GEN9_PIPE_PLANE2_FAULT | \
5834 GEN9_PIPE_PLANE1_FAULT)
5836 #define GEN8_DE_PORT_ISR 0x44440
5837 #define GEN8_DE_PORT_IMR 0x44444
5838 #define GEN8_DE_PORT_IIR 0x44448
5839 #define GEN8_DE_PORT_IER 0x4444c
5840 #define GEN9_AUX_CHANNEL_D (1 << 27)
5841 #define GEN9_AUX_CHANNEL_C (1 << 26)
5842 #define GEN9_AUX_CHANNEL_B (1 << 25)
5843 #define BXT_DE_PORT_HP_DDIC (1 << 5)
5844 #define BXT_DE_PORT_HP_DDIB (1 << 4)
5845 #define BXT_DE_PORT_HP_DDIA (1 << 3)
5846 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
5847 BXT_DE_PORT_HP_DDIB | \
5848 BXT_DE_PORT_HP_DDIC)
5849 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
5850 #define BXT_DE_PORT_GMBUS (1 << 1)
5851 #define GEN8_AUX_CHANNEL_A (1 << 0)
5853 #define GEN8_DE_MISC_ISR 0x44460
5854 #define GEN8_DE_MISC_IMR 0x44464
5855 #define GEN8_DE_MISC_IIR 0x44468
5856 #define GEN8_DE_MISC_IER 0x4446c
5857 #define GEN8_DE_MISC_GSE (1 << 27)
5859 #define GEN8_PCU_ISR 0x444e0
5860 #define GEN8_PCU_IMR 0x444e4
5861 #define GEN8_PCU_IIR 0x444e8
5862 #define GEN8_PCU_IER 0x444ec
5864 #define ILK_DISPLAY_CHICKEN2 0x42004
5865 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5866 #define ILK_ELPIN_409_SELECT (1 << 25)
5867 #define ILK_DPARB_GATE (1<<22)
5868 #define ILK_VSDPFD_FULL (1<<21)
5869 #define FUSE_STRAP 0x42014
5870 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5871 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5872 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5873 #define ILK_HDCP_DISABLE (1 << 25)
5874 #define ILK_eDP_A_DISABLE (1 << 24)
5875 #define HSW_CDCLK_LIMIT (1 << 24)
5876 #define ILK_DESKTOP (1 << 23)
5878 #define ILK_DSPCLK_GATE_D 0x42020
5879 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5880 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5881 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5882 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5883 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5885 #define IVB_CHICKEN3 0x4200c
5886 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5887 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5889 #define CHICKEN_PAR1_1 0x42080
5890 #define DPA_MASK_VBLANK_SRD (1 << 15)
5891 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5893 #define _CHICKEN_PIPESL_1_A 0x420b0
5894 #define _CHICKEN_PIPESL_1_B 0x420b4
5895 #define HSW_FBCQ_DIS (1 << 22)
5896 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5897 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5899 #define DISP_ARB_CTL 0x45000
5900 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5901 #define DISP_FBC_WM_DIS (1<<15)
5902 #define DISP_ARB_CTL2 0x45004
5903 #define DISP_DATA_PARTITION_5_6 (1<<6)
5904 #define DBUF_CTL 0x45008
5905 #define DBUF_POWER_REQUEST (1<<31)
5906 #define DBUF_POWER_STATE (1<<30)
5907 #define GEN7_MSG_CTL 0x45010
5908 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
5909 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
5910 #define HSW_NDE_RSTWRN_OPT 0x46408
5911 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
5913 #define SKL_DFSM 0x51000
5914 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5915 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5916 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5917 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5918 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5920 #define FF_SLICE_CS_CHICKEN2 0x20e4
5921 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
5924 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5925 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
5926 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
5927 #define COMMON_SLICE_CHICKEN2 0x7014
5928 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
5930 #define HIZ_CHICKEN 0x7018
5931 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
5932 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
5934 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308
5935 #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
5937 #define GEN7_L3SQCREG1 0xB010
5938 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5940 #define GEN8_L3SQCREG1 0xB100
5941 #define BDW_WA_L3SQCREG1_DEFAULT 0x784000
5943 #define GEN7_L3CNTLREG1 0xB01C
5944 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
5945 #define GEN7_L3AGDIS (1<<19)
5946 #define GEN7_L3CNTLREG2 0xB020
5947 #define GEN7_L3CNTLREG3 0xB024
5949 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5950 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5952 #define GEN7_L3SQCREG4 0xb034
5953 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5955 #define GEN8_L3SQCREG4 0xb118
5956 #define GEN8_LQSC_RO_PERF_DIS (1<<27)
5957 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
5960 #define HDC_CHICKEN0 0x7300
5961 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
5962 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
5963 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5964 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
5965 #define HDC_FORCE_NON_COHERENT (1<<4)
5966 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
5969 #define SLICE_ECO_CHICKEN0 0x7308
5970 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
5972 /* WaCatErrorRejectionIssue */
5973 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5974 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5976 #define HSW_SCRATCH1 0xb038
5977 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5979 #define BDW_SCRATCH1 0xb11c
5980 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
5984 /* south display engine interrupt: IBX */
5985 #define SDE_AUDIO_POWER_D (1 << 27)
5986 #define SDE_AUDIO_POWER_C (1 << 26)
5987 #define SDE_AUDIO_POWER_B (1 << 25)
5988 #define SDE_AUDIO_POWER_SHIFT (25)
5989 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5990 #define SDE_GMBUS (1 << 24)
5991 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5992 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5993 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5994 #define SDE_AUDIO_TRANSB (1 << 21)
5995 #define SDE_AUDIO_TRANSA (1 << 20)
5996 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5997 #define SDE_POISON (1 << 19)
5999 #define SDE_FDI_RXB (1 << 17)
6000 #define SDE_FDI_RXA (1 << 16)
6001 #define SDE_FDI_MASK (3 << 16)
6002 #define SDE_AUXD (1 << 15)
6003 #define SDE_AUXC (1 << 14)
6004 #define SDE_AUXB (1 << 13)
6005 #define SDE_AUX_MASK (7 << 13)
6007 #define SDE_CRT_HOTPLUG (1 << 11)
6008 #define SDE_PORTD_HOTPLUG (1 << 10)
6009 #define SDE_PORTC_HOTPLUG (1 << 9)
6010 #define SDE_PORTB_HOTPLUG (1 << 8)
6011 #define SDE_SDVOB_HOTPLUG (1 << 6)
6012 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
6013 SDE_SDVOB_HOTPLUG | \
6014 SDE_PORTB_HOTPLUG | \
6015 SDE_PORTC_HOTPLUG | \
6017 #define SDE_TRANSB_CRC_DONE (1 << 5)
6018 #define SDE_TRANSB_CRC_ERR (1 << 4)
6019 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
6020 #define SDE_TRANSA_CRC_DONE (1 << 2)
6021 #define SDE_TRANSA_CRC_ERR (1 << 1)
6022 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
6023 #define SDE_TRANS_MASK (0x3f)
6025 /* south display engine interrupt: CPT/PPT */
6026 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
6027 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
6028 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
6029 #define SDE_AUDIO_POWER_SHIFT_CPT 29
6030 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
6031 #define SDE_AUXD_CPT (1 << 27)
6032 #define SDE_AUXC_CPT (1 << 26)
6033 #define SDE_AUXB_CPT (1 << 25)
6034 #define SDE_AUX_MASK_CPT (7 << 25)
6035 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
6036 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
6037 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
6038 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
6039 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
6040 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
6041 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
6042 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
6043 SDE_SDVOB_HOTPLUG_CPT | \
6044 SDE_PORTD_HOTPLUG_CPT | \
6045 SDE_PORTC_HOTPLUG_CPT | \
6046 SDE_PORTB_HOTPLUG_CPT)
6047 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
6048 SDE_PORTD_HOTPLUG_CPT | \
6049 SDE_PORTC_HOTPLUG_CPT | \
6050 SDE_PORTB_HOTPLUG_CPT | \
6051 SDE_PORTA_HOTPLUG_SPT)
6052 #define SDE_GMBUS_CPT (1 << 17)
6053 #define SDE_ERROR_CPT (1 << 16)
6054 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
6055 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
6056 #define SDE_FDI_RXC_CPT (1 << 8)
6057 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
6058 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
6059 #define SDE_FDI_RXB_CPT (1 << 4)
6060 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
6061 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
6062 #define SDE_FDI_RXA_CPT (1 << 0)
6063 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
6064 SDE_AUDIO_CP_REQ_B_CPT | \
6065 SDE_AUDIO_CP_REQ_A_CPT)
6066 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
6067 SDE_AUDIO_CP_CHG_B_CPT | \
6068 SDE_AUDIO_CP_CHG_A_CPT)
6069 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
6073 #define SDEISR 0xc4000
6074 #define SDEIMR 0xc4004
6075 #define SDEIIR 0xc4008
6076 #define SDEIER 0xc400c
6078 #define SERR_INT 0xc4040
6079 #define SERR_INT_POISON (1<<31)
6080 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
6081 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
6082 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
6083 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
6085 /* digital port hotplug */
6086 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
6087 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
6088 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
6089 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
6090 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
6091 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
6092 #define PORTD_HOTPLUG_ENABLE (1 << 20)
6093 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
6094 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
6095 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
6096 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
6097 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
6098 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
6099 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
6100 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
6101 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
6102 #define PORTC_HOTPLUG_ENABLE (1 << 12)
6103 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
6104 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
6105 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
6106 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
6107 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
6108 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
6109 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6110 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6111 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
6112 #define PORTB_HOTPLUG_ENABLE (1 << 4)
6113 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
6114 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
6115 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
6116 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
6117 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
6118 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
6119 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6120 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6121 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
6123 #define PCH_PORT_HOTPLUG2 0xc403C /* SHOTPLUG_CTL2 SPT+ */
6124 #define PORTE_HOTPLUG_ENABLE (1 << 4)
6125 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
6126 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
6127 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
6128 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
6130 #define PCH_GPIOA 0xc5010
6131 #define PCH_GPIOB 0xc5014
6132 #define PCH_GPIOC 0xc5018
6133 #define PCH_GPIOD 0xc501c
6134 #define PCH_GPIOE 0xc5020
6135 #define PCH_GPIOF 0xc5024
6137 #define PCH_GMBUS0 0xc5100
6138 #define PCH_GMBUS1 0xc5104
6139 #define PCH_GMBUS2 0xc5108
6140 #define PCH_GMBUS3 0xc510c
6141 #define PCH_GMBUS4 0xc5110
6142 #define PCH_GMBUS5 0xc5120
6144 #define _PCH_DPLL_A 0xc6014
6145 #define _PCH_DPLL_B 0xc6018
6146 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6148 #define _PCH_FPA0 0xc6040
6149 #define FP_CB_TUNE (0x3<<22)
6150 #define _PCH_FPA1 0xc6044
6151 #define _PCH_FPB0 0xc6048
6152 #define _PCH_FPB1 0xc604c
6153 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6154 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6156 #define PCH_DPLL_TEST 0xc606c
6158 #define PCH_DREF_CONTROL 0xC6200
6159 #define DREF_CONTROL_MASK 0x7fc3
6160 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6161 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6162 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6163 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6164 #define DREF_SSC_SOURCE_DISABLE (0<<11)
6165 #define DREF_SSC_SOURCE_ENABLE (2<<11)
6166 #define DREF_SSC_SOURCE_MASK (3<<11)
6167 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6168 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6169 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
6170 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
6171 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6172 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
6173 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
6174 #define DREF_SSC4_DOWNSPREAD (0<<6)
6175 #define DREF_SSC4_CENTERSPREAD (1<<6)
6176 #define DREF_SSC1_DISABLE (0<<1)
6177 #define DREF_SSC1_ENABLE (1<<1)
6178 #define DREF_SSC4_DISABLE (0)
6179 #define DREF_SSC4_ENABLE (1)
6181 #define PCH_RAWCLK_FREQ 0xc6204
6182 #define FDL_TP1_TIMER_SHIFT 12
6183 #define FDL_TP1_TIMER_MASK (3<<12)
6184 #define FDL_TP2_TIMER_SHIFT 10
6185 #define FDL_TP2_TIMER_MASK (3<<10)
6186 #define RAWCLK_FREQ_MASK 0x3ff
6188 #define PCH_DPLL_TMR_CFG 0xc6208
6190 #define PCH_SSC4_PARMS 0xc6210
6191 #define PCH_SSC4_AUX_PARMS 0xc6214
6193 #define PCH_DPLL_SEL 0xc7000
6194 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6195 #define TRANS_DPLLA_SEL(pipe) 0
6196 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
6200 #define _PCH_TRANS_HTOTAL_A 0xe0000
6201 #define TRANS_HTOTAL_SHIFT 16
6202 #define TRANS_HACTIVE_SHIFT 0
6203 #define _PCH_TRANS_HBLANK_A 0xe0004
6204 #define TRANS_HBLANK_END_SHIFT 16
6205 #define TRANS_HBLANK_START_SHIFT 0
6206 #define _PCH_TRANS_HSYNC_A 0xe0008
6207 #define TRANS_HSYNC_END_SHIFT 16
6208 #define TRANS_HSYNC_START_SHIFT 0
6209 #define _PCH_TRANS_VTOTAL_A 0xe000c
6210 #define TRANS_VTOTAL_SHIFT 16
6211 #define TRANS_VACTIVE_SHIFT 0
6212 #define _PCH_TRANS_VBLANK_A 0xe0010
6213 #define TRANS_VBLANK_END_SHIFT 16
6214 #define TRANS_VBLANK_START_SHIFT 0
6215 #define _PCH_TRANS_VSYNC_A 0xe0014
6216 #define TRANS_VSYNC_END_SHIFT 16
6217 #define TRANS_VSYNC_START_SHIFT 0
6218 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6220 #define _PCH_TRANSA_DATA_M1 0xe0030
6221 #define _PCH_TRANSA_DATA_N1 0xe0034
6222 #define _PCH_TRANSA_DATA_M2 0xe0038
6223 #define _PCH_TRANSA_DATA_N2 0xe003c
6224 #define _PCH_TRANSA_LINK_M1 0xe0040
6225 #define _PCH_TRANSA_LINK_N1 0xe0044
6226 #define _PCH_TRANSA_LINK_M2 0xe0048
6227 #define _PCH_TRANSA_LINK_N2 0xe004c
6229 /* Per-transcoder DIP controls (PCH) */
6230 #define _VIDEO_DIP_CTL_A 0xe0200
6231 #define _VIDEO_DIP_DATA_A 0xe0208
6232 #define _VIDEO_DIP_GCP_A 0xe0210
6233 #define GCP_COLOR_INDICATION (1 << 2)
6234 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6235 #define GCP_AV_MUTE (1 << 0)
6237 #define _VIDEO_DIP_CTL_B 0xe1200
6238 #define _VIDEO_DIP_DATA_B 0xe1208
6239 #define _VIDEO_DIP_GCP_B 0xe1210
6241 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6242 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6243 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6245 /* Per-transcoder DIP controls (VLV) */
6246 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6247 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6248 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6250 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6251 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6252 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6254 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6255 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6256 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6258 #define VLV_TVIDEO_DIP_CTL(pipe) \
6259 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
6260 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
6261 #define VLV_TVIDEO_DIP_DATA(pipe) \
6262 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
6263 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
6264 #define VLV_TVIDEO_DIP_GCP(pipe) \
6265 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6266 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6268 /* Haswell DIP controls */
6269 #define HSW_VIDEO_DIP_CTL_A 0x60200
6270 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6271 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
6272 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6273 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6274 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6275 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6276 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
6277 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6278 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6279 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6280 #define HSW_VIDEO_DIP_GCP_A 0x60210
6282 #define HSW_VIDEO_DIP_CTL_B 0x61200
6283 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6284 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
6285 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6286 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6287 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6288 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6289 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
6290 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6291 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6292 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6293 #define HSW_VIDEO_DIP_GCP_B 0x61210
6295 #define HSW_TVIDEO_DIP_CTL(trans) \
6296 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
6297 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
6298 (_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
6299 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
6300 (_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
6301 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
6302 (_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
6303 #define HSW_TVIDEO_DIP_GCP(trans) \
6304 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
6305 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
6306 (_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
6308 #define HSW_STEREO_3D_CTL_A 0x70020
6309 #define S3D_ENABLE (1<<31)
6310 #define HSW_STEREO_3D_CTL_B 0x71020
6312 #define HSW_STEREO_3D_CTL(trans) \
6313 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
6315 #define _PCH_TRANS_HTOTAL_B 0xe1000
6316 #define _PCH_TRANS_HBLANK_B 0xe1004
6317 #define _PCH_TRANS_HSYNC_B 0xe1008
6318 #define _PCH_TRANS_VTOTAL_B 0xe100c
6319 #define _PCH_TRANS_VBLANK_B 0xe1010
6320 #define _PCH_TRANS_VSYNC_B 0xe1014
6321 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6323 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6324 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6325 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6326 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6327 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6328 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6329 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
6330 _PCH_TRANS_VSYNCSHIFT_B)
6332 #define _PCH_TRANSB_DATA_M1 0xe1030
6333 #define _PCH_TRANSB_DATA_N1 0xe1034
6334 #define _PCH_TRANSB_DATA_M2 0xe1038
6335 #define _PCH_TRANSB_DATA_N2 0xe103c
6336 #define _PCH_TRANSB_LINK_M1 0xe1040
6337 #define _PCH_TRANSB_LINK_N1 0xe1044
6338 #define _PCH_TRANSB_LINK_M2 0xe1048
6339 #define _PCH_TRANSB_LINK_N2 0xe104c
6341 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6342 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6343 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6344 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6345 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6346 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6347 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6348 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6350 #define _PCH_TRANSACONF 0xf0008
6351 #define _PCH_TRANSBCONF 0xf1008
6352 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6353 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
6354 #define TRANS_DISABLE (0<<31)
6355 #define TRANS_ENABLE (1<<31)
6356 #define TRANS_STATE_MASK (1<<30)
6357 #define TRANS_STATE_DISABLE (0<<30)
6358 #define TRANS_STATE_ENABLE (1<<30)
6359 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
6360 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
6361 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
6362 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
6363 #define TRANS_INTERLACE_MASK (7<<21)
6364 #define TRANS_PROGRESSIVE (0<<21)
6365 #define TRANS_INTERLACED (3<<21)
6366 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
6367 #define TRANS_8BPC (0<<5)
6368 #define TRANS_10BPC (1<<5)
6369 #define TRANS_6BPC (2<<5)
6370 #define TRANS_12BPC (3<<5)
6372 #define _TRANSA_CHICKEN1 0xf0060
6373 #define _TRANSB_CHICKEN1 0xf1060
6374 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6375 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
6376 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
6377 #define _TRANSA_CHICKEN2 0xf0064
6378 #define _TRANSB_CHICKEN2 0xf1064
6379 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6380 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6381 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6382 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6383 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6384 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
6386 #define SOUTH_CHICKEN1 0xc2000
6387 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
6388 #define FDIA_PHASE_SYNC_SHIFT_EN 18
6389 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6390 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6391 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
6392 #define SPT_PWM_GRANULARITY (1<<0)
6393 #define SOUTH_CHICKEN2 0xc2004
6394 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6395 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6396 #define LPT_PWM_GRANULARITY (1<<5)
6397 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
6399 #define _FDI_RXA_CHICKEN 0xc200c
6400 #define _FDI_RXB_CHICKEN 0xc2010
6401 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6402 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
6403 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6405 #define SOUTH_DSPCLK_GATE_D 0xc2020
6406 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6407 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6408 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6409 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
6412 #define _FDI_TXA_CTL 0x60100
6413 #define _FDI_TXB_CTL 0x61100
6414 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6415 #define FDI_TX_DISABLE (0<<31)
6416 #define FDI_TX_ENABLE (1<<31)
6417 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6418 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6419 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6420 #define FDI_LINK_TRAIN_NONE (3<<28)
6421 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6422 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6423 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6424 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6425 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6426 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6427 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6428 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
6429 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6430 SNB has different settings. */
6431 /* SNB A-stepping */
6432 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6433 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6434 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6435 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6436 /* SNB B-stepping */
6437 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6438 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6439 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6440 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6441 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
6442 #define FDI_DP_PORT_WIDTH_SHIFT 19
6443 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6444 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6445 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
6446 /* Ironlake: hardwired to 1 */
6447 #define FDI_TX_PLL_ENABLE (1<<14)
6449 /* Ivybridge has different bits for lolz */
6450 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6451 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6452 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6453 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6455 /* both Tx and Rx */
6456 #define FDI_COMPOSITE_SYNC (1<<11)
6457 #define FDI_LINK_TRAIN_AUTO (1<<10)
6458 #define FDI_SCRAMBLING_ENABLE (0<<7)
6459 #define FDI_SCRAMBLING_DISABLE (1<<7)
6461 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6462 #define _FDI_RXA_CTL 0xf000c
6463 #define _FDI_RXB_CTL 0xf100c
6464 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6465 #define FDI_RX_ENABLE (1<<31)
6466 /* train, dp width same as FDI_TX */
6467 #define FDI_FS_ERRC_ENABLE (1<<27)
6468 #define FDI_FE_ERRC_ENABLE (1<<26)
6469 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
6470 #define FDI_8BPC (0<<16)
6471 #define FDI_10BPC (1<<16)
6472 #define FDI_6BPC (2<<16)
6473 #define FDI_12BPC (3<<16)
6474 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
6475 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6476 #define FDI_RX_PLL_ENABLE (1<<13)
6477 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6478 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6479 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6480 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6481 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
6482 #define FDI_PCDCLK (1<<4)
6484 #define FDI_AUTO_TRAINING (1<<10)
6485 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6486 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6487 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6488 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6489 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
6491 #define _FDI_RXA_MISC 0xf0010
6492 #define _FDI_RXB_MISC 0xf1010
6493 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6494 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6495 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6496 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6497 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
6498 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
6499 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
6500 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6502 #define _FDI_RXA_TUSIZE1 0xf0030
6503 #define _FDI_RXA_TUSIZE2 0xf0038
6504 #define _FDI_RXB_TUSIZE1 0xf1030
6505 #define _FDI_RXB_TUSIZE2 0xf1038
6506 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6507 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6509 /* FDI_RX interrupt register format */
6510 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
6511 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6512 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6513 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6514 #define FDI_RX_FS_CODE_ERR (1<<6)
6515 #define FDI_RX_FE_CODE_ERR (1<<5)
6516 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6517 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
6518 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6519 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6520 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6522 #define _FDI_RXA_IIR 0xf0014
6523 #define _FDI_RXA_IMR 0xf0018
6524 #define _FDI_RXB_IIR 0xf1014
6525 #define _FDI_RXB_IMR 0xf1018
6526 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6527 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6529 #define FDI_PLL_CTL_1 0xfe000
6530 #define FDI_PLL_CTL_2 0xfe004
6532 #define PCH_LVDS 0xe1180
6533 #define LVDS_DETECTED (1 << 1)
6535 /* vlv has 2 sets of panel control regs. */
6536 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6537 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6538 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
6539 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
6540 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6541 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
6543 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6544 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6545 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6546 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6547 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
6549 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
6550 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
6551 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
6552 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
6553 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
6554 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
6555 #define VLV_PIPE_PP_DIVISOR(pipe) \
6556 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
6558 #define PCH_PP_STATUS 0xc7200
6559 #define PCH_PP_CONTROL 0xc7204
6560 #define PANEL_UNLOCK_REGS (0xabcd << 16)
6561 #define PANEL_UNLOCK_MASK (0xffff << 16)
6562 #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
6563 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
6564 #define EDP_FORCE_VDD (1 << 3)
6565 #define EDP_BLC_ENABLE (1 << 2)
6566 #define PANEL_POWER_RESET (1 << 1)
6567 #define PANEL_POWER_OFF (0 << 0)
6568 #define PANEL_POWER_ON (1 << 0)
6569 #define PCH_PP_ON_DELAYS 0xc7208
6570 #define PANEL_PORT_SELECT_MASK (3 << 30)
6571 #define PANEL_PORT_SELECT_LVDS (0 << 30)
6572 #define PANEL_PORT_SELECT_DPA (1 << 30)
6573 #define PANEL_PORT_SELECT_DPC (2 << 30)
6574 #define PANEL_PORT_SELECT_DPD (3 << 30)
6575 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
6576 #define PANEL_POWER_UP_DELAY_SHIFT 16
6577 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6578 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
6580 #define PCH_PP_OFF_DELAYS 0xc720c
6581 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6582 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
6583 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6584 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6586 #define PCH_PP_DIVISOR 0xc7210
6587 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6588 #define PP_REFERENCE_DIVIDER_SHIFT 8
6589 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6590 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
6592 /* BXT PPS changes - 2nd set of PPS registers */
6593 #define _BXT_PP_STATUS2 0xc7300
6594 #define _BXT_PP_CONTROL2 0xc7304
6595 #define _BXT_PP_ON_DELAYS2 0xc7308
6596 #define _BXT_PP_OFF_DELAYS2 0xc730c
6598 #define BXT_PP_STATUS(n) _PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
6599 #define BXT_PP_CONTROL(n) _PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6600 #define BXT_PP_ON_DELAYS(n) _PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6601 #define BXT_PP_OFF_DELAYS(n) _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
6603 #define PCH_DP_B 0xe4100
6604 #define PCH_DPB_AUX_CH_CTL 0xe4110
6605 #define PCH_DPB_AUX_CH_DATA1 0xe4114
6606 #define PCH_DPB_AUX_CH_DATA2 0xe4118
6607 #define PCH_DPB_AUX_CH_DATA3 0xe411c
6608 #define PCH_DPB_AUX_CH_DATA4 0xe4120
6609 #define PCH_DPB_AUX_CH_DATA5 0xe4124
6611 #define PCH_DP_C 0xe4200
6612 #define PCH_DPC_AUX_CH_CTL 0xe4210
6613 #define PCH_DPC_AUX_CH_DATA1 0xe4214
6614 #define PCH_DPC_AUX_CH_DATA2 0xe4218
6615 #define PCH_DPC_AUX_CH_DATA3 0xe421c
6616 #define PCH_DPC_AUX_CH_DATA4 0xe4220
6617 #define PCH_DPC_AUX_CH_DATA5 0xe4224
6619 #define PCH_DP_D 0xe4300
6620 #define PCH_DPD_AUX_CH_CTL 0xe4310
6621 #define PCH_DPD_AUX_CH_DATA1 0xe4314
6622 #define PCH_DPD_AUX_CH_DATA2 0xe4318
6623 #define PCH_DPD_AUX_CH_DATA3 0xe431c
6624 #define PCH_DPD_AUX_CH_DATA4 0xe4320
6625 #define PCH_DPD_AUX_CH_DATA5 0xe4324
6628 #define PORT_TRANS_A_SEL_CPT 0
6629 #define PORT_TRANS_B_SEL_CPT (1<<29)
6630 #define PORT_TRANS_C_SEL_CPT (2<<29)
6631 #define PORT_TRANS_SEL_MASK (3<<29)
6632 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
6633 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6634 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
6635 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6636 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
6638 #define TRANS_DP_CTL_A 0xe0300
6639 #define TRANS_DP_CTL_B 0xe1300
6640 #define TRANS_DP_CTL_C 0xe2300
6641 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
6642 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
6643 #define TRANS_DP_PORT_SEL_B (0<<29)
6644 #define TRANS_DP_PORT_SEL_C (1<<29)
6645 #define TRANS_DP_PORT_SEL_D (2<<29)
6646 #define TRANS_DP_PORT_SEL_NONE (3<<29)
6647 #define TRANS_DP_PORT_SEL_MASK (3<<29)
6648 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
6649 #define TRANS_DP_AUDIO_ONLY (1<<26)
6650 #define TRANS_DP_ENH_FRAMING (1<<18)
6651 #define TRANS_DP_8BPC (0<<9)
6652 #define TRANS_DP_10BPC (1<<9)
6653 #define TRANS_DP_6BPC (2<<9)
6654 #define TRANS_DP_12BPC (3<<9)
6655 #define TRANS_DP_BPC_MASK (3<<9)
6656 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6657 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
6658 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6659 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
6660 #define TRANS_DP_SYNC_MASK (3<<3)
6662 /* SNB eDP training params */
6663 /* SNB A-stepping */
6664 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6665 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6666 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6667 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6668 /* SNB B-stepping */
6669 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6670 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6671 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6672 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6673 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
6674 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6677 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6678 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6679 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6680 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6681 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6682 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
6683 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
6686 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6687 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6688 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6689 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6690 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6692 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6694 #define VLV_PMWGICZ 0x1300a4
6696 #define FORCEWAKE 0xA18C
6697 #define FORCEWAKE_VLV 0x1300b0
6698 #define FORCEWAKE_ACK_VLV 0x1300b4
6699 #define FORCEWAKE_MEDIA_VLV 0x1300b8
6700 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
6701 #define FORCEWAKE_ACK_HSW 0x130044
6702 #define FORCEWAKE_ACK 0x130090
6703 #define VLV_GTLC_WAKE_CTRL 0x130090
6704 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6705 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6706 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6708 #define VLV_GTLC_PW_STATUS 0x130094
6709 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6710 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6711 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6712 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
6713 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
6714 #define FORCEWAKE_MEDIA_GEN9 0xa270
6715 #define FORCEWAKE_RENDER_GEN9 0xa278
6716 #define FORCEWAKE_BLITTER_GEN9 0xa188
6717 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
6718 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
6719 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
6720 #define FORCEWAKE_KERNEL 0x1
6721 #define FORCEWAKE_USER 0x2
6722 #define FORCEWAKE_MT_ACK 0x130040
6723 #define ECOBUS 0xa180
6724 #define FORCEWAKE_MT_ENABLE (1<<5)
6725 #define VLV_SPAREG2H 0xA194
6727 #define GTFIFODBG 0x120000
6728 #define GT_FIFO_SBDROPERR (1<<6)
6729 #define GT_FIFO_BLOBDROPERR (1<<5)
6730 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
6731 #define GT_FIFO_DROPERR (1<<3)
6732 #define GT_FIFO_OVFERR (1<<2)
6733 #define GT_FIFO_IAWRERR (1<<1)
6734 #define GT_FIFO_IARDERR (1<<0)
6736 #define GTFIFOCTL 0x120008
6737 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
6738 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
6739 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6740 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
6742 #define HSW_IDICR 0x9008
6743 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6744 #define HSW_EDRAM_PRESENT 0x120010
6745 #define EDRAM_ENABLED 0x1
6747 #define GEN6_UCGCTL1 0x9400
6748 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6749 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6750 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
6752 #define GEN6_UCGCTL2 0x9404
6753 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
6754 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6755 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
6756 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
6757 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
6758 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
6760 #define GEN6_UCGCTL3 0x9408
6762 #define GEN7_UCGCTL4 0x940c
6763 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6765 #define GEN6_RCGCTL1 0x9410
6766 #define GEN6_RCGCTL2 0x9414
6767 #define GEN6_RSTCTL 0x9420
6769 #define GEN8_UCGCTL6 0x9430
6770 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
6771 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6772 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6774 #define GEN6_GFXPAUSE 0xA000
6775 #define GEN6_RPNSWREQ 0xA008
6776 #define GEN6_TURBO_DISABLE (1<<31)
6777 #define GEN6_FREQUENCY(x) ((x)<<25)
6778 #define HSW_FREQUENCY(x) ((x)<<24)
6779 #define GEN9_FREQUENCY(x) ((x)<<23)
6780 #define GEN6_OFFSET(x) ((x)<<19)
6781 #define GEN6_AGGRESSIVE_TURBO (0<<15)
6782 #define GEN6_RC_VIDEO_FREQ 0xA00C
6783 #define GEN6_RC_CONTROL 0xA090
6784 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6785 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6786 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
6787 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
6788 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
6789 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
6790 #define GEN7_RC_CTL_TO_MODE (1<<28)
6791 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6792 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
6793 #define GEN6_RP_DOWN_TIMEOUT 0xA010
6794 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
6795 #define GEN6_RPSTAT1 0xA01C
6796 #define GEN6_CAGF_SHIFT 8
6797 #define HSW_CAGF_SHIFT 7
6798 #define GEN9_CAGF_SHIFT 23
6799 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
6800 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
6801 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
6802 #define GEN6_RP_CONTROL 0xA024
6803 #define GEN6_RP_MEDIA_TURBO (1<<11)
6804 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6805 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6806 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6807 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
6808 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
6809 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
6810 #define GEN6_RP_ENABLE (1<<7)
6811 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6812 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6813 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
6814 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
6815 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
6816 #define GEN6_RP_UP_THRESHOLD 0xA02C
6817 #define GEN6_RP_DOWN_THRESHOLD 0xA030
6818 #define GEN6_RP_CUR_UP_EI 0xA050
6819 #define GEN6_CURICONT_MASK 0xffffff
6820 #define GEN6_RP_CUR_UP 0xA054
6821 #define GEN6_CURBSYTAVG_MASK 0xffffff
6822 #define GEN6_RP_PREV_UP 0xA058
6823 #define GEN6_RP_CUR_DOWN_EI 0xA05C
6824 #define GEN6_CURIAVG_MASK 0xffffff
6825 #define GEN6_RP_CUR_DOWN 0xA060
6826 #define GEN6_RP_PREV_DOWN 0xA064
6827 #define GEN6_RP_UP_EI 0xA068
6828 #define GEN6_RP_DOWN_EI 0xA06C
6829 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
6830 #define GEN6_RPDEUHWTC 0xA080
6831 #define GEN6_RPDEUC 0xA084
6832 #define GEN6_RPDEUCSW 0xA088
6833 #define GEN6_RC_STATE 0xA094
6834 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
6835 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
6836 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
6837 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
6838 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
6839 #define GEN6_RC_SLEEP 0xA0B0
6840 #define GEN6_RCUBMABDTMR 0xA0B0
6841 #define GEN6_RC1e_THRESHOLD 0xA0B4
6842 #define GEN6_RC6_THRESHOLD 0xA0B8
6843 #define GEN6_RC6p_THRESHOLD 0xA0BC
6844 #define VLV_RCEDATA 0xA0BC
6845 #define GEN6_RC6pp_THRESHOLD 0xA0C0
6846 #define GEN6_PMINTRMSK 0xA168
6847 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6848 #define VLV_PWRDWNUPCTL 0xA294
6849 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
6850 #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
6851 #define GEN9_PG_ENABLE 0xA210
6852 #define GEN9_RENDER_PG_ENABLE (1<<0)
6853 #define GEN9_MEDIA_PG_ENABLE (1<<1)
6855 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6856 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6857 #define PIXEL_OVERLAP_CNT_SHIFT 30
6859 #define GEN6_PMISR 0x44020
6860 #define GEN6_PMIMR 0x44024 /* rps_lock */
6861 #define GEN6_PMIIR 0x44028
6862 #define GEN6_PMIER 0x4402C
6863 #define GEN6_PM_MBOX_EVENT (1<<25)
6864 #define GEN6_PM_THERMAL_EVENT (1<<24)
6865 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6866 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6867 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6868 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6869 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
6870 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
6871 GEN6_PM_RP_DOWN_THRESHOLD | \
6872 GEN6_PM_RP_DOWN_TIMEOUT)
6874 #define GEN7_GT_SCRATCH(i) (0x4F100 + (i) * 4)
6875 #define GEN7_GT_SCRATCH_REG_NUM 8
6877 #define VLV_GTLC_SURVIVABILITY_REG 0x130098
6878 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
6879 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6881 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
6882 #define VLV_COUNTER_CONTROL 0x138104
6883 #define VLV_COUNT_RANGE_HIGH (1<<15)
6884 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6885 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
6886 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6887 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
6888 #define GEN6_GT_GFX_RC6 0x138108
6889 #define VLV_GT_RENDER_RC6 0x138108
6890 #define VLV_GT_MEDIA_RC6 0x13810C
6892 #define GEN6_GT_GFX_RC6p 0x13810C
6893 #define GEN6_GT_GFX_RC6pp 0x138110
6894 #define VLV_RENDER_C0_COUNT 0x138118
6895 #define VLV_MEDIA_C0_COUNT 0x13811C
6897 #define GEN6_PCODE_MAILBOX 0x138124
6898 #define GEN6_PCODE_READY (1<<31)
6899 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6900 #define GEN6_PCODE_READ_RC6VIDS 0x5
6901 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6902 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6903 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
6904 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6905 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6906 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6907 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6908 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
6909 #define SKL_PCODE_CDCLK_CONTROL 0x7
6910 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
6911 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
6912 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6913 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6914 #define GEN6_READ_OC_PARAMS 0xc
6915 #define GEN6_PCODE_READ_D_COMP 0x10
6916 #define GEN6_PCODE_WRITE_D_COMP 0x11
6917 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
6918 #define DISPLAY_IPS_CONTROL 0x19
6919 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6920 #define GEN6_PCODE_DATA 0x138128
6921 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6922 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6923 #define GEN6_PCODE_DATA1 0x13812C
6925 #define GEN6_GT_CORE_STATUS 0x138060
6926 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
6927 #define GEN6_RCn_MASK 7
6933 #define GEN8_GT_SLICE_INFO 0x138064
6934 #define GEN8_LSLICESTAT_MASK 0x7
6936 #define CHV_POWER_SS0_SIG1 0xa720
6937 #define CHV_POWER_SS1_SIG1 0xa728
6938 #define CHV_SS_PG_ENABLE (1<<1)
6939 #define CHV_EU08_PG_ENABLE (1<<9)
6940 #define CHV_EU19_PG_ENABLE (1<<17)
6941 #define CHV_EU210_PG_ENABLE (1<<25)
6943 #define CHV_POWER_SS0_SIG2 0xa724
6944 #define CHV_POWER_SS1_SIG2 0xa72c
6945 #define CHV_EU311_PG_ENABLE (1<<1)
6947 #define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)
6948 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
6949 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
6951 #define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)
6952 #define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)
6953 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
6954 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
6955 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
6956 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
6957 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
6958 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
6959 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
6960 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
6962 #define GEN7_MISCCPCTL (0x9424)
6963 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6964 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
6965 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
6966 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
6968 #define GEN8_GARBCNTL 0xB004
6969 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
6972 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
6973 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
6974 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6975 #define GEN7_PARITY_ERROR_VALID (1<<13)
6976 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6977 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6978 #define GEN7_PARITY_ERROR_ROW(reg) \
6979 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6980 #define GEN7_PARITY_ERROR_BANK(reg) \
6981 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6982 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6983 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6984 #define GEN7_L3CDERRST1_ENABLE (1<<7)
6986 #define GEN7_L3LOG_BASE 0xB070
6987 #define HSW_L3LOG_BASE_SLICE1 0xB270
6988 #define GEN7_L3LOG_SIZE 0x80
6990 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6991 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6992 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
6993 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
6994 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
6995 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6997 #define GEN9_HALF_SLICE_CHICKEN5 0xe188
6998 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
6999 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
7001 #define GEN8_ROW_CHICKEN 0xe4f0
7002 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
7003 #define STALL_DOP_GATING_DISABLE (1<<5)
7005 #define GEN7_ROW_CHICKEN2 0xe4f4
7006 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
7007 #define DOP_CLOCK_GATING_DISABLE (1<<0)
7009 #define HSW_ROW_CHICKEN3 0xe49c
7010 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
7012 #define HALF_SLICE_CHICKEN2 0xe180
7013 #define GEN8_ST_PO_DISABLE (1<<13)
7015 #define HALF_SLICE_CHICKEN3 0xe184
7016 #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
7017 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
7018 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
7019 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
7021 #define GEN9_HALF_SLICE_CHICKEN7 0xe194
7022 #define GEN9_ENABLE_YV12_BUGFIX (1<<4)
7025 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
7026 #define INTEL_AUDIO_DEVCL 0x808629FB
7027 #define INTEL_AUDIO_DEVBLC 0x80862801
7028 #define INTEL_AUDIO_DEVCTG 0x80862802
7030 #define G4X_AUD_CNTL_ST 0x620B4
7031 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
7032 #define G4X_ELDV_DEVCTG (1 << 14)
7033 #define G4X_ELD_ADDR_MASK (0xf << 5)
7034 #define G4X_ELD_ACK (1 << 4)
7035 #define G4X_HDMIW_HDMIEDID 0x6210C
7037 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
7038 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
7039 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7040 _IBX_HDMIW_HDMIEDID_A, \
7041 _IBX_HDMIW_HDMIEDID_B)
7042 #define _IBX_AUD_CNTL_ST_A 0xE20B4
7043 #define _IBX_AUD_CNTL_ST_B 0xE21B4
7044 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7045 _IBX_AUD_CNTL_ST_A, \
7047 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
7048 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
7049 #define IBX_ELD_ACK (1 << 4)
7050 #define IBX_AUD_CNTL_ST2 0xE20C0
7051 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
7052 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
7054 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
7055 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
7056 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7057 _CPT_HDMIW_HDMIEDID_A, \
7058 _CPT_HDMIW_HDMIEDID_B)
7059 #define _CPT_AUD_CNTL_ST_A 0xE50B4
7060 #define _CPT_AUD_CNTL_ST_B 0xE51B4
7061 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7062 _CPT_AUD_CNTL_ST_A, \
7064 #define CPT_AUD_CNTRL_ST2 0xE50C0
7066 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7067 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
7068 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7069 _VLV_HDMIW_HDMIEDID_A, \
7070 _VLV_HDMIW_HDMIEDID_B)
7071 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7072 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
7073 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7074 _VLV_AUD_CNTL_ST_A, \
7076 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
7078 /* These are the 4 32-bit write offset registers for each stream
7079 * output buffer. It determines the offset from the
7080 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7082 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
7084 #define _IBX_AUD_CONFIG_A 0xe2000
7085 #define _IBX_AUD_CONFIG_B 0xe2100
7086 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
7087 _IBX_AUD_CONFIG_A, \
7089 #define _CPT_AUD_CONFIG_A 0xe5000
7090 #define _CPT_AUD_CONFIG_B 0xe5100
7091 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
7092 _CPT_AUD_CONFIG_A, \
7094 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7095 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
7096 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
7097 _VLV_AUD_CONFIG_A, \
7100 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
7101 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
7102 #define AUD_CONFIG_UPPER_N_SHIFT 20
7103 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
7104 #define AUD_CONFIG_LOWER_N_SHIFT 4
7105 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
7106 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
7107 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
7108 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
7109 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
7110 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
7111 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
7112 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
7113 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
7114 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
7115 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
7116 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
7117 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
7118 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
7121 #define _HSW_AUD_CONFIG_A 0x65000
7122 #define _HSW_AUD_CONFIG_B 0x65100
7123 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
7124 _HSW_AUD_CONFIG_A, \
7127 #define _HSW_AUD_MISC_CTRL_A 0x65010
7128 #define _HSW_AUD_MISC_CTRL_B 0x65110
7129 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
7130 _HSW_AUD_MISC_CTRL_A, \
7131 _HSW_AUD_MISC_CTRL_B)
7133 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7134 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7135 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
7136 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
7137 _HSW_AUD_DIP_ELD_CTRL_ST_B)
7139 /* Audio Digital Converter */
7140 #define _HSW_AUD_DIG_CNVT_1 0x65080
7141 #define _HSW_AUD_DIG_CNVT_2 0x65180
7142 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
7143 _HSW_AUD_DIG_CNVT_1, \
7144 _HSW_AUD_DIG_CNVT_2)
7145 #define DIP_PORT_SEL_MASK 0x3
7147 #define _HSW_AUD_EDID_DATA_A 0x65050
7148 #define _HSW_AUD_EDID_DATA_B 0x65150
7149 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
7150 _HSW_AUD_EDID_DATA_A, \
7151 _HSW_AUD_EDID_DATA_B)
7153 #define HSW_AUD_PIPE_CONV_CFG 0x6507c
7154 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
7155 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7156 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7157 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7158 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
7160 #define HSW_AUD_CHICKENBIT 0x65f10
7161 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7163 /* HSW Power Wells */
7164 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
7165 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
7166 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
7167 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
7168 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7169 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
7170 #define HSW_PWR_WELL_CTL5 0x45410
7171 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7172 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
7173 #define HSW_PWR_WELL_FORCE_ON (1<<19)
7174 #define HSW_PWR_WELL_CTL6 0x45414
7176 /* SKL Fuse Status */
7177 #define SKL_FUSE_STATUS 0x42000
7178 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7179 #define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7180 #define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7181 #define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7183 /* Per-pipe DDI Function Control */
7184 #define TRANS_DDI_FUNC_CTL_A 0x60400
7185 #define TRANS_DDI_FUNC_CTL_B 0x61400
7186 #define TRANS_DDI_FUNC_CTL_C 0x62400
7187 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
7188 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
7190 #define TRANS_DDI_FUNC_ENABLE (1<<31)
7191 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
7192 #define TRANS_DDI_PORT_MASK (7<<28)
7193 #define TRANS_DDI_PORT_SHIFT 28
7194 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7195 #define TRANS_DDI_PORT_NONE (0<<28)
7196 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7197 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7198 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7199 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7200 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7201 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7202 #define TRANS_DDI_BPC_MASK (7<<20)
7203 #define TRANS_DDI_BPC_8 (0<<20)
7204 #define TRANS_DDI_BPC_10 (1<<20)
7205 #define TRANS_DDI_BPC_6 (2<<20)
7206 #define TRANS_DDI_BPC_12 (3<<20)
7207 #define TRANS_DDI_PVSYNC (1<<17)
7208 #define TRANS_DDI_PHSYNC (1<<16)
7209 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7210 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7211 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7212 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7213 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
7214 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
7215 #define TRANS_DDI_BFI_ENABLE (1<<4)
7217 /* DisplayPort Transport Control */
7218 #define DP_TP_CTL_A 0x64040
7219 #define DP_TP_CTL_B 0x64140
7220 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
7221 #define DP_TP_CTL_ENABLE (1<<31)
7222 #define DP_TP_CTL_MODE_SST (0<<27)
7223 #define DP_TP_CTL_MODE_MST (1<<27)
7224 #define DP_TP_CTL_FORCE_ACT (1<<25)
7225 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
7226 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
7227 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7228 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7229 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
7230 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7231 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
7232 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
7233 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
7235 /* DisplayPort Transport Status */
7236 #define DP_TP_STATUS_A 0x64044
7237 #define DP_TP_STATUS_B 0x64144
7238 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
7239 #define DP_TP_STATUS_IDLE_DONE (1<<25)
7240 #define DP_TP_STATUS_ACT_SENT (1<<24)
7241 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7242 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7243 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7244 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7245 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
7247 /* DDI Buffer Control */
7248 #define DDI_BUF_CTL_A 0x64000
7249 #define DDI_BUF_CTL_B 0x64100
7250 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
7251 #define DDI_BUF_CTL_ENABLE (1<<31)
7252 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
7253 #define DDI_BUF_EMP_MASK (0xf<<24)
7254 #define DDI_BUF_PORT_REVERSAL (1<<16)
7255 #define DDI_BUF_IS_IDLE (1<<7)
7256 #define DDI_A_4_LANES (1<<4)
7257 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
7258 #define DDI_PORT_WIDTH_MASK (7 << 1)
7259 #define DDI_PORT_WIDTH_SHIFT 1
7260 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
7262 /* DDI Buffer Translations */
7263 #define DDI_BUF_TRANS_A 0x64E00
7264 #define DDI_BUF_TRANS_B 0x64E60
7265 #define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)
7266 #define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)
7268 /* Sideband Interface (SBI) is programmed indirectly, via
7269 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7270 * which contains the payload */
7271 #define SBI_ADDR 0xC6000
7272 #define SBI_DATA 0xC6004
7273 #define SBI_CTL_STAT 0xC6008
7274 #define SBI_CTL_DEST_ICLK (0x0<<16)
7275 #define SBI_CTL_DEST_MPHY (0x1<<16)
7276 #define SBI_CTL_OP_IORD (0x2<<8)
7277 #define SBI_CTL_OP_IOWR (0x3<<8)
7278 #define SBI_CTL_OP_CRRD (0x6<<8)
7279 #define SBI_CTL_OP_CRWR (0x7<<8)
7280 #define SBI_RESPONSE_FAIL (0x1<<1)
7281 #define SBI_RESPONSE_SUCCESS (0x0<<1)
7282 #define SBI_BUSY (0x1<<0)
7283 #define SBI_READY (0x0<<0)
7286 #define SBI_SSCDIVINTPHASE6 0x0600
7287 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
7288 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
7289 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
7290 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
7291 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
7292 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
7293 #define SBI_SSCCTL 0x020c
7294 #define SBI_SSCCTL6 0x060C
7295 #define SBI_SSCCTL_PATHALT (1<<3)
7296 #define SBI_SSCCTL_DISABLE (1<<0)
7297 #define SBI_SSCAUXDIV6 0x0610
7298 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
7299 #define SBI_DBUFF0 0x2a00
7300 #define SBI_GEN0 0x1f00
7301 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
7303 /* LPT PIXCLK_GATE */
7304 #define PIXCLK_GATE 0xC6020
7305 #define PIXCLK_GATE_UNGATE (1<<0)
7306 #define PIXCLK_GATE_GATE (0<<0)
7309 #define SPLL_CTL 0x46020
7310 #define SPLL_PLL_ENABLE (1<<31)
7311 #define SPLL_PLL_SSC (1<<28)
7312 #define SPLL_PLL_NON_SSC (2<<28)
7313 #define SPLL_PLL_LCPLL (3<<28)
7314 #define SPLL_PLL_REF_MASK (3<<28)
7315 #define SPLL_PLL_FREQ_810MHz (0<<26)
7316 #define SPLL_PLL_FREQ_1350MHz (1<<26)
7317 #define SPLL_PLL_FREQ_2700MHz (2<<26)
7318 #define SPLL_PLL_FREQ_MASK (3<<26)
7321 #define WRPLL_CTL1 0x46040
7322 #define WRPLL_CTL2 0x46060
7323 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
7324 #define WRPLL_PLL_ENABLE (1<<31)
7325 #define WRPLL_PLL_SSC (1<<28)
7326 #define WRPLL_PLL_NON_SSC (2<<28)
7327 #define WRPLL_PLL_LCPLL (3<<28)
7328 #define WRPLL_PLL_REF_MASK (3<<28)
7329 /* WRPLL divider programming */
7330 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
7331 #define WRPLL_DIVIDER_REF_MASK (0xff)
7332 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
7333 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7334 #define WRPLL_DIVIDER_POST_SHIFT 8
7335 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
7336 #define WRPLL_DIVIDER_FB_SHIFT 16
7337 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
7339 /* Port clock selection */
7340 #define PORT_CLK_SEL_A 0x46100
7341 #define PORT_CLK_SEL_B 0x46104
7342 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
7343 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7344 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7345 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
7346 #define PORT_CLK_SEL_SPLL (3<<29)
7347 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
7348 #define PORT_CLK_SEL_WRPLL1 (4<<29)
7349 #define PORT_CLK_SEL_WRPLL2 (5<<29)
7350 #define PORT_CLK_SEL_NONE (7<<29)
7351 #define PORT_CLK_SEL_MASK (7<<29)
7353 /* Transcoder clock selection */
7354 #define TRANS_CLK_SEL_A 0x46140
7355 #define TRANS_CLK_SEL_B 0x46144
7356 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
7357 /* For each transcoder, we need to select the corresponding port clock */
7358 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
7359 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
7361 #define CDCLK_FREQ 0x46200
7363 #define TRANSA_MSA_MISC 0x60410
7364 #define TRANSB_MSA_MISC 0x61410
7365 #define TRANSC_MSA_MISC 0x62410
7366 #define TRANS_EDP_MSA_MISC 0x6f410
7367 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
7369 #define TRANS_MSA_SYNC_CLK (1<<0)
7370 #define TRANS_MSA_6_BPC (0<<5)
7371 #define TRANS_MSA_8_BPC (1<<5)
7372 #define TRANS_MSA_10_BPC (2<<5)
7373 #define TRANS_MSA_12_BPC (3<<5)
7374 #define TRANS_MSA_16_BPC (4<<5)
7377 #define LCPLL_CTL 0x130040
7378 #define LCPLL_PLL_DISABLE (1<<31)
7379 #define LCPLL_PLL_LOCK (1<<30)
7380 #define LCPLL_CLK_FREQ_MASK (3<<26)
7381 #define LCPLL_CLK_FREQ_450 (0<<26)
7382 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7383 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7384 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
7385 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
7386 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
7387 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
7388 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
7389 #define LCPLL_CD_SOURCE_FCLK (1<<21)
7390 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7397 #define CDCLK_CTL 0x46000
7398 #define CDCLK_FREQ_SEL_MASK (3<<26)
7399 #define CDCLK_FREQ_450_432 (0<<26)
7400 #define CDCLK_FREQ_540 (1<<26)
7401 #define CDCLK_FREQ_337_308 (2<<26)
7402 #define CDCLK_FREQ_675_617 (3<<26)
7403 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7405 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7406 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7407 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7408 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7409 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
7410 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7413 #define LCPLL1_CTL 0x46010
7414 #define LCPLL2_CTL 0x46014
7415 #define LCPLL_PLL_ENABLE (1<<31)
7418 #define DPLL_CTRL1 0x6C058
7419 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7420 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
7421 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7422 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7423 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
7424 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
7425 #define DPLL_CTRL1_LINK_RATE_2700 0
7426 #define DPLL_CTRL1_LINK_RATE_1350 1
7427 #define DPLL_CTRL1_LINK_RATE_810 2
7428 #define DPLL_CTRL1_LINK_RATE_1620 3
7429 #define DPLL_CTRL1_LINK_RATE_1080 4
7430 #define DPLL_CTRL1_LINK_RATE_2160 5
7433 #define DPLL_CTRL2 0x6C05C
7434 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
7435 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
7436 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
7437 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
7438 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7441 #define DPLL_STATUS 0x6C060
7442 #define DPLL_LOCK(id) (1<<((id)*8))
7445 #define DPLL1_CFGCR1 0x6C040
7446 #define DPLL2_CFGCR1 0x6C048
7447 #define DPLL3_CFGCR1 0x6C050
7448 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7449 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7450 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
7451 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7453 #define DPLL1_CFGCR2 0x6C044
7454 #define DPLL2_CFGCR2 0x6C04C
7455 #define DPLL3_CFGCR2 0x6C054
7456 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7457 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
7458 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
7459 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
7460 #define DPLL_CFGCR2_KDIV(x) ((x)<<5)
7461 #define DPLL_CFGCR2_KDIV_5 (0<<5)
7462 #define DPLL_CFGCR2_KDIV_2 (1<<5)
7463 #define DPLL_CFGCR2_KDIV_3 (2<<5)
7464 #define DPLL_CFGCR2_KDIV_1 (3<<5)
7465 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
7466 #define DPLL_CFGCR2_PDIV(x) ((x)<<2)
7467 #define DPLL_CFGCR2_PDIV_1 (0<<2)
7468 #define DPLL_CFGCR2_PDIV_2 (1<<2)
7469 #define DPLL_CFGCR2_PDIV_3 (2<<2)
7470 #define DPLL_CFGCR2_PDIV_7 (4<<2)
7471 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7473 #define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
7474 #define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
7476 /* BXT display engine PLL */
7477 #define BXT_DE_PLL_CTL 0x6d000
7478 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7479 #define BXT_DE_PLL_RATIO_MASK 0xff
7481 #define BXT_DE_PLL_ENABLE 0x46070
7482 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7483 #define BXT_DE_PLL_LOCK (1 << 30)
7486 #define DC_STATE_EN 0x45504
7487 #define DC_STATE_EN_UPTO_DC5 (1<<0)
7488 #define DC_STATE_EN_DC9 (1<<3)
7489 #define DC_STATE_EN_UPTO_DC6 (2<<0)
7490 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7492 #define DC_STATE_DEBUG 0x45520
7493 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7495 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7496 * since on HSW we can't write to it using I915_WRITE. */
7497 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7498 #define D_COMP_BDW 0x138144
7499 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7500 #define D_COMP_COMP_FORCE (1<<8)
7501 #define D_COMP_COMP_DISABLE (1<<0)
7503 /* Pipe WM_LINETIME - watermark line time */
7504 #define PIPE_WM_LINETIME_A 0x45270
7505 #define PIPE_WM_LINETIME_B 0x45274
7506 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
7508 #define PIPE_WM_LINETIME_MASK (0x1ff)
7509 #define PIPE_WM_LINETIME_TIME(x) ((x))
7510 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
7511 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
7514 #define SFUSE_STRAP 0xc2014
7515 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
7516 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
7517 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7518 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7519 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
7521 #define WM_MISC 0x45260
7522 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7524 #define WM_DBG 0x45280
7525 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7526 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7527 #define WM_DBG_DISALLOW_SPRITE (1<<2)
7530 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7531 #define _PIPE_A_CSC_COEFF_BY 0x49014
7532 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7533 #define _PIPE_A_CSC_COEFF_BU 0x4901c
7534 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7535 #define _PIPE_A_CSC_COEFF_BV 0x49024
7536 #define _PIPE_A_CSC_MODE 0x49028
7537 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7538 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7539 #define CSC_MODE_YUV_TO_RGB (1 << 0)
7540 #define _PIPE_A_CSC_PREOFF_HI 0x49030
7541 #define _PIPE_A_CSC_PREOFF_ME 0x49034
7542 #define _PIPE_A_CSC_PREOFF_LO 0x49038
7543 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
7544 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
7545 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
7547 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7548 #define _PIPE_B_CSC_COEFF_BY 0x49114
7549 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7550 #define _PIPE_B_CSC_COEFF_BU 0x4911c
7551 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7552 #define _PIPE_B_CSC_COEFF_BV 0x49124
7553 #define _PIPE_B_CSC_MODE 0x49128
7554 #define _PIPE_B_CSC_PREOFF_HI 0x49130
7555 #define _PIPE_B_CSC_PREOFF_ME 0x49134
7556 #define _PIPE_B_CSC_PREOFF_LO 0x49138
7557 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
7558 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
7559 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
7561 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7562 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7563 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7564 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7565 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7566 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7567 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7568 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7569 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7570 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7571 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7572 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7573 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7575 /* MIPI DSI registers */
7577 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
7579 /* BXT MIPI clock controls */
7580 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
7582 #define BXT_MIPI_CLOCK_CTL 0x46090
7583 #define BXT_MIPI1_DIV_SHIFT 26
7584 #define BXT_MIPI2_DIV_SHIFT 10
7585 #define BXT_MIPI_DIV_SHIFT(port) \
7586 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7587 BXT_MIPI2_DIV_SHIFT)
7588 /* Var clock divider to generate TX source. Result must be < 39.5 M */
7589 #define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
7590 #define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
7591 #define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
7592 _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
7593 BXT_MIPI2_ESCLK_VAR_DIV_MASK)
7595 #define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
7596 (val << BXT_MIPI_DIV_SHIFT(port))
7597 /* TX control divider to select actual TX clock output from (8x/var) */
7598 #define BXT_MIPI1_TX_ESCLK_SHIFT 21
7599 #define BXT_MIPI2_TX_ESCLK_SHIFT 5
7600 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
7601 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7602 BXT_MIPI2_TX_ESCLK_SHIFT)
7603 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
7604 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
7605 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
7606 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
7607 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7608 #define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
7609 (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7610 #define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
7611 (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7612 #define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
7613 (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7614 /* RX control divider to select actual RX clock output from 8x*/
7615 #define BXT_MIPI1_RX_ESCLK_SHIFT 19
7616 #define BXT_MIPI2_RX_ESCLK_SHIFT 3
7617 #define BXT_MIPI_RX_ESCLK_SHIFT(port) \
7618 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
7619 BXT_MIPI2_RX_ESCLK_SHIFT)
7620 #define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
7621 #define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
7622 #define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
7623 (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7624 #define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
7625 (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7626 #define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
7627 (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7628 #define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
7629 (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7630 /* BXT-A WA: Always prog DPHY dividers to 00 */
7631 #define BXT_MIPI1_DPHY_DIV_SHIFT 16
7632 #define BXT_MIPI2_DPHY_DIV_SHIFT 0
7633 #define BXT_MIPI_DPHY_DIV_SHIFT(port) \
7634 _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
7635 BXT_MIPI2_DPHY_DIV_SHIFT)
7636 #define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
7637 #define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
7638 #define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
7639 (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
7641 /* BXT MIPI mode configure */
7642 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
7643 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
7644 #define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \
7645 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7647 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
7648 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
7649 #define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \
7650 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7652 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
7653 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
7654 #define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
7655 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7657 #define BXT_DSI_PLL_CTL 0x161000
7658 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
7659 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7660 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7661 #define BXT_DSIC_16X_BY2 (1 << 10)
7662 #define BXT_DSIC_16X_BY3 (2 << 10)
7663 #define BXT_DSIC_16X_BY4 (3 << 10)
7664 #define BXT_DSIA_16X_BY2 (1 << 8)
7665 #define BXT_DSIA_16X_BY3 (2 << 8)
7666 #define BXT_DSIA_16X_BY4 (3 << 8)
7667 #define BXT_DSI_FREQ_SEL_SHIFT 8
7668 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
7670 #define BXT_DSI_PLL_RATIO_MAX 0x7D
7671 #define BXT_DSI_PLL_RATIO_MIN 0x22
7672 #define BXT_DSI_PLL_RATIO_MASK 0xFF
7673 #define BXT_REF_CLOCK_KHZ 19500
7675 #define BXT_DSI_PLL_ENABLE 0x46080
7676 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
7677 #define BXT_DSI_PLL_LOCKED (1 << 30)
7679 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
7680 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7681 #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7683 /* BXT port control */
7684 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
7685 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
7686 #define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
7687 _BXT_MIPIC_PORT_CTRL)
7689 #define DPI_ENABLE (1 << 31) /* A + C */
7690 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7691 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
7692 #define DUAL_LINK_MODE_SHIFT 26
7693 #define DUAL_LINK_MODE_MASK (1 << 26)
7694 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7695 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
7696 #define DITHERING_ENABLE (1 << 25) /* A + C */
7697 #define FLOPPED_HSTX (1 << 23)
7698 #define DE_INVERT (1 << 19) /* XXX */
7699 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7700 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7701 #define AFE_LATCHOUT (1 << 17)
7702 #define LP_OUTPUT_HOLD (1 << 16)
7703 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7704 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7705 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7706 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
7708 #define CSB_MASK (3 << 9)
7709 #define CSB_20MHZ (0 << 9)
7710 #define CSB_10MHZ (1 << 9)
7711 #define CSB_40MHZ (2 << 9)
7712 #define BANDGAP_MASK (1 << 8)
7713 #define BANDGAP_PNW_CIRCUIT (0 << 8)
7714 #define BANDGAP_LNC_CIRCUIT (1 << 8)
7715 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7716 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
7717 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
7718 #define TEARING_EFFECT_SHIFT 2 /* A + C */
7719 #define TEARING_EFFECT_MASK (3 << 2)
7720 #define TEARING_EFFECT_OFF (0 << 2)
7721 #define TEARING_EFFECT_DSI (1 << 2)
7722 #define TEARING_EFFECT_GPIO (2 << 2)
7723 #define LANE_CONFIGURATION_SHIFT 0
7724 #define LANE_CONFIGURATION_MASK (3 << 0)
7725 #define LANE_CONFIGURATION_4LANE (0 << 0)
7726 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
7727 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
7729 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
7730 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
7731 #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \
7732 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
7733 #define TEARING_EFFECT_DELAY_SHIFT 0
7734 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
7736 /* XXX: all bits reserved */
7737 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
7739 /* MIPI DSI Controller and D-PHY registers */
7741 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
7742 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
7743 #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \
7744 _MIPIC_DEVICE_READY)
7745 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
7746 #define ULPS_STATE_MASK (3 << 1)
7747 #define ULPS_STATE_ENTER (2 << 1)
7748 #define ULPS_STATE_EXIT (1 << 1)
7749 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
7750 #define DEVICE_READY (1 << 0)
7752 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
7753 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
7754 #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \
7756 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
7757 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
7758 #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \
7760 #define TEARING_EFFECT (1 << 31)
7761 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
7762 #define GEN_READ_DATA_AVAIL (1 << 29)
7763 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
7764 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
7765 #define RX_PROT_VIOLATION (1 << 26)
7766 #define RX_INVALID_TX_LENGTH (1 << 25)
7767 #define ACK_WITH_NO_ERROR (1 << 24)
7768 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
7769 #define LP_RX_TIMEOUT (1 << 22)
7770 #define HS_TX_TIMEOUT (1 << 21)
7771 #define DPI_FIFO_UNDERRUN (1 << 20)
7772 #define LOW_CONTENTION (1 << 19)
7773 #define HIGH_CONTENTION (1 << 18)
7774 #define TXDSI_VC_ID_INVALID (1 << 17)
7775 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
7776 #define TXCHECKSUM_ERROR (1 << 15)
7777 #define TXECC_MULTIBIT_ERROR (1 << 14)
7778 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
7779 #define TXFALSE_CONTROL_ERROR (1 << 12)
7780 #define RXDSI_VC_ID_INVALID (1 << 11)
7781 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
7782 #define RXCHECKSUM_ERROR (1 << 9)
7783 #define RXECC_MULTIBIT_ERROR (1 << 8)
7784 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
7785 #define RXFALSE_CONTROL_ERROR (1 << 6)
7786 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
7787 #define RX_LP_TX_SYNC_ERROR (1 << 4)
7788 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
7789 #define RXEOT_SYNC_ERROR (1 << 2)
7790 #define RXSOT_SYNC_ERROR (1 << 1)
7791 #define RXSOT_ERROR (1 << 0)
7793 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
7794 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7795 #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
7796 _MIPIC_DSI_FUNC_PRG)
7797 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
7798 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
7799 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
7800 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
7801 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
7802 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
7803 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
7804 #define VID_MODE_FORMAT_MASK (0xf << 7)
7805 #define VID_MODE_NOT_SUPPORTED (0 << 7)
7806 #define VID_MODE_FORMAT_RGB565 (1 << 7)
7807 #define VID_MODE_FORMAT_RGB666 (2 << 7)
7808 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
7809 #define VID_MODE_FORMAT_RGB888 (4 << 7)
7810 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
7811 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
7812 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
7813 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
7814 #define DATA_LANES_PRG_REG_SHIFT 0
7815 #define DATA_LANES_PRG_REG_MASK (7 << 0)
7817 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
7818 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7819 #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
7820 _MIPIC_HS_TX_TIMEOUT)
7821 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
7823 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
7824 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7825 #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
7826 _MIPIC_LP_RX_TIMEOUT)
7827 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
7829 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
7830 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7831 #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \
7832 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
7833 #define TURN_AROUND_TIMEOUT_MASK 0x3f
7835 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
7836 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7837 #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \
7838 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
7839 #define DEVICE_RESET_TIMER_MASK 0xffff
7841 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
7842 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7843 #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
7844 _MIPIC_DPI_RESOLUTION)
7845 #define VERTICAL_ADDRESS_SHIFT 16
7846 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
7847 #define HORIZONTAL_ADDRESS_SHIFT 0
7848 #define HORIZONTAL_ADDRESS_MASK 0xffff
7850 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
7851 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7852 #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \
7853 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
7854 #define DBI_FIFO_EMPTY_HALF (0 << 0)
7855 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
7856 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
7858 /* regs below are bits 15:0 */
7859 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
7860 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7861 #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7862 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
7864 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
7865 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7866 #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \
7869 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
7870 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7871 #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \
7874 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
7875 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7876 #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \
7877 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
7879 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
7880 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7881 #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7882 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
7884 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
7885 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7886 #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \
7889 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
7890 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7891 #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \
7894 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
7895 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7896 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \
7897 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
7899 /* regs above are bits 15:0 */
7901 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
7902 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7903 #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
7905 #define DPI_LP_MODE (1 << 6)
7906 #define BACKLIGHT_OFF (1 << 5)
7907 #define BACKLIGHT_ON (1 << 4)
7908 #define COLOR_MODE_OFF (1 << 3)
7909 #define COLOR_MODE_ON (1 << 2)
7910 #define TURN_ON (1 << 1)
7911 #define SHUTDOWN (1 << 0)
7913 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
7914 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7915 #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \
7917 #define COMMAND_BYTE_SHIFT 0
7918 #define COMMAND_BYTE_MASK (0x3f << 0)
7920 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
7921 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7922 #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \
7924 #define MASTER_INIT_TIMER_SHIFT 0
7925 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
7927 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
7928 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7929 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \
7930 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
7931 #define MAX_RETURN_PKT_SIZE_SHIFT 0
7932 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
7934 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
7935 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7936 #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \
7937 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
7938 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
7939 #define DISABLE_VIDEO_BTA (1 << 3)
7940 #define IP_TG_CONFIG (1 << 2)
7941 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
7942 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
7943 #define VIDEO_MODE_BURST (3 << 0)
7945 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
7946 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7947 #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
7949 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
7950 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
7951 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
7952 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
7953 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7954 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
7955 #define CLOCKSTOP (1 << 1)
7956 #define EOT_DISABLE (1 << 0)
7958 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
7959 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7960 #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
7962 #define LP_BYTECLK_SHIFT 0
7963 #define LP_BYTECLK_MASK (0xffff << 0)
7966 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
7967 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7968 #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
7972 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
7973 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7974 #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
7977 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
7978 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7979 #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
7981 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
7982 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7983 #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
7985 #define LONG_PACKET_WORD_COUNT_SHIFT 8
7986 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
7987 #define SHORT_PACKET_PARAM_SHIFT 8
7988 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
7989 #define VIRTUAL_CHANNEL_SHIFT 6
7990 #define VIRTUAL_CHANNEL_MASK (3 << 6)
7991 #define DATA_TYPE_SHIFT 0
7992 #define DATA_TYPE_MASK (0x3f << 0)
7993 /* data type values, see include/video/mipi_display.h */
7995 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
7996 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
7997 #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
7998 _MIPIC_GEN_FIFO_STAT)
7999 #define DPI_FIFO_EMPTY (1 << 28)
8000 #define DBI_FIFO_EMPTY (1 << 27)
8001 #define LP_CTRL_FIFO_EMPTY (1 << 26)
8002 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
8003 #define LP_CTRL_FIFO_FULL (1 << 24)
8004 #define HS_CTRL_FIFO_EMPTY (1 << 18)
8005 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
8006 #define HS_CTRL_FIFO_FULL (1 << 16)
8007 #define LP_DATA_FIFO_EMPTY (1 << 10)
8008 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
8009 #define LP_DATA_FIFO_FULL (1 << 8)
8010 #define HS_DATA_FIFO_EMPTY (1 << 2)
8011 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
8012 #define HS_DATA_FIFO_FULL (1 << 0)
8014 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
8015 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
8016 #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \
8017 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
8018 #define DBI_HS_LP_MODE_MASK (1 << 0)
8019 #define DBI_LP_MODE (1 << 0)
8020 #define DBI_HS_MODE (0 << 0)
8022 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
8023 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
8024 #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
8026 #define EXIT_ZERO_COUNT_SHIFT 24
8027 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
8028 #define TRAIL_COUNT_SHIFT 16
8029 #define TRAIL_COUNT_MASK (0x1f << 16)
8030 #define CLK_ZERO_COUNT_SHIFT 8
8031 #define CLK_ZERO_COUNT_MASK (0xff << 8)
8032 #define PREPARE_COUNT_SHIFT 0
8033 #define PREPARE_COUNT_MASK (0x3f << 0)
8036 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
8037 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
8038 #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
8041 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
8043 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
8045 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \
8046 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
8047 #define LP_HS_SSW_CNT_SHIFT 16
8048 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
8049 #define HS_LP_PWR_SW_CNT_SHIFT 0
8050 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
8052 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
8053 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
8054 #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \
8055 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
8056 #define STOP_STATE_STALL_COUNTER_SHIFT 0
8057 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
8059 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
8060 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
8061 #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \
8062 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
8063 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
8064 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
8065 #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
8066 _MIPIC_INTR_EN_REG_1)
8067 #define RX_CONTENTION_DETECTED (1 << 0)
8069 /* XXX: only pipe A ?!? */
8070 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
8071 #define DBI_TYPEC_ENABLE (1 << 31)
8072 #define DBI_TYPEC_WIP (1 << 30)
8073 #define DBI_TYPEC_OPTION_SHIFT 28
8074 #define DBI_TYPEC_OPTION_MASK (3 << 28)
8075 #define DBI_TYPEC_FREQ_SHIFT 24
8076 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
8077 #define DBI_TYPEC_OVERRIDE (1 << 8)
8078 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
8079 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
8082 /* MIPI adapter registers */
8084 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
8085 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
8086 #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \
8088 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
8089 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
8090 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
8091 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
8092 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
8093 #define READ_REQUEST_PRIORITY_SHIFT 3
8094 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
8095 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
8096 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
8097 #define RGB_FLIP_TO_BGR (1 << 2)
8099 #define BXT_PIPE_SELECT_MASK (7 << 7)
8100 #define BXT_PIPE_SELECT_C (2 << 7)
8101 #define BXT_PIPE_SELECT_B (1 << 7)
8102 #define BXT_PIPE_SELECT_A (0 << 7)
8104 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
8105 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
8106 #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
8107 _MIPIC_DATA_ADDRESS)
8108 #define DATA_MEM_ADDRESS_SHIFT 5
8109 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
8110 #define DATA_VALID (1 << 0)
8112 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
8113 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
8114 #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
8116 #define DATA_LENGTH_SHIFT 0
8117 #define DATA_LENGTH_MASK (0xfffff << 0)
8119 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
8120 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
8121 #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \
8122 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
8123 #define COMMAND_MEM_ADDRESS_SHIFT 5
8124 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
8125 #define AUTO_PWG_ENABLE (1 << 2)
8126 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
8127 #define COMMAND_VALID (1 << 0)
8129 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
8130 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
8131 #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
8132 _MIPIC_COMMAND_LENGTH)
8133 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
8134 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
8136 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
8137 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
8138 #define MIPI_READ_DATA_RETURN(port, n) \
8139 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
8140 + 4 * (n)) /* n: 0...7 */
8142 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
8143 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
8144 #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \
8145 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
8146 #define READ_DATA_VALID(n) (1 << (n))
8148 /* For UMS only (deprecated): */
8149 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8150 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
8152 /* MOCS (Memory Object Control State) registers */
8153 #define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */
8155 #define GEN9_GFX_MOCS_0 0xc800 /* Graphics MOCS base register*/
8156 #define GEN9_MFX0_MOCS_0 0xc900 /* Media 0 MOCS base register*/
8157 #define GEN9_MFX1_MOCS_0 0xca00 /* Media 1 MOCS base register*/
8158 #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/
8159 #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
8161 #endif /* _I915_REG_H_ */
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