kernel/drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
 143 {
 144         u32 val = I915_READ(reg);
 145
 146         if (val == 0)
 147                 return;
 148
 149         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 150              reg, val);
 151         I915_WRITE(reg, 0xffffffff);
 152         POSTING_READ(reg);
 153         I915_WRITE(reg, 0xffffffff);
 154         POSTING_READ(reg);
 155 }
 156
 157 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 158         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 159         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 160         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 161         POSTING_READ(GEN8_##type##_IMR(which)); \
 162 } while (0)
 163
 164 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 165         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 166         I915_WRITE(type##IER, (ier_val)); \
 167         I915_WRITE(type##IMR, (imr_val)); \
 168         POSTING_READ(type##IMR); \
 169 } while (0)
 170
 171 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 172
 173 /* For display hotplug interrupt */
 174 static inline void
 175 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 176                                      uint32_t mask,
 177                                      uint32_t bits)
 178 {
 179         uint32_t val;
 180
 181         assert_spin_locked(&dev_priv->irq_lock);
 182         WARN_ON(bits & ~mask);
 183
 184         val = I915_READ(PORT_HOTPLUG_EN);
 185         val &= ~mask;
 186         val |= bits;
 187         I915_WRITE(PORT_HOTPLUG_EN, val);
 188 }
 189
 190 /**
 191  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 192  * @dev_priv: driver private
 193  * @mask: bits to update
 194  * @bits: bits to enable
 195  * NOTE: the HPD enable bits are modified both inside and outside
 196  * of an interrupt context. To avoid that read-modify-write cycles
 197  * interfer, these bits are protected by a spinlock. Since this
 198  * function is usually not called from a context where the lock is
 199  * held already, this function acquires the lock itself. A non-locking
 200  * version is also available.
 201  */
 202 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 203                                    uint32_t mask,
 204                                    uint32_t bits)
 205 {
 206         spin_lock_irq(&dev_priv->irq_lock);
 207         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 208         spin_unlock_irq(&dev_priv->irq_lock);
 209 }
 210
 211 /**
 212  * ilk_update_display_irq - update DEIMR
 213  * @dev_priv: driver private
 214  * @interrupt_mask: mask of interrupt bits to update
 215  * @enabled_irq_mask: mask of interrupt bits to enable
 216  */
 217 static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 218                                    uint32_t interrupt_mask,
 219                                    uint32_t enabled_irq_mask)
 220 {
 221         uint32_t new_val;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 226
 227         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 228                 return;
 229
 230         new_val = dev_priv->irq_mask;
 231         new_val &= ~interrupt_mask;
 232         new_val |= (~enabled_irq_mask & interrupt_mask);
 233
 234         if (new_val != dev_priv->irq_mask) {
 235                 dev_priv->irq_mask = new_val;
 236                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 237                 POSTING_READ(DEIMR);
 238         }
 239 }
 240
 241 void
 242 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 243 {
 244         ilk_update_display_irq(dev_priv, mask, mask);
 245 }
 246
 247 void
 248 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 249 {
 250         ilk_update_display_irq(dev_priv, mask, 0);
 251 }
 252
 253 /**
 254  * ilk_update_gt_irq - update GTIMR
 255  * @dev_priv: driver private
 256  * @interrupt_mask: mask of interrupt bits to update
 257  * @enabled_irq_mask: mask of interrupt bits to enable
 258  */
 259 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 260                               uint32_t interrupt_mask,
 261                               uint32_t enabled_irq_mask)
 262 {
 263         assert_spin_locked(&dev_priv->irq_lock);
 264
 265         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 266
 267         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 268                 return;
 269
 270         dev_priv->gt_irq_mask &= ~interrupt_mask;
 271         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 272         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 273         POSTING_READ(GTIMR);
 274 }
 275
 276 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 277 {
 278         ilk_update_gt_irq(dev_priv, mask, mask);
 279 }
 280
 281 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 282 {
 283         ilk_update_gt_irq(dev_priv, mask, 0);
 284 }
 285
 286 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 289 }
 290
 291 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
 292 {
 293         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 294 }
 295
 296 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
 297 {
 298         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 299 }
 300
 301 /**
 302   * snb_update_pm_irq - update GEN6_PMIMR
 303   * @dev_priv: driver private
 304   * @interrupt_mask: mask of interrupt bits to update
 305   * @enabled_irq_mask: mask of interrupt bits to enable
 306   */
 307 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 308                               uint32_t interrupt_mask,
 309                               uint32_t enabled_irq_mask)
 310 {
 311         uint32_t new_val;
 312
 313         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 314
 315         assert_spin_locked(&dev_priv->irq_lock);
 316
 317         new_val = dev_priv->pm_irq_mask;
 318         new_val &= ~interrupt_mask;
 319         new_val |= (~enabled_irq_mask & interrupt_mask);
 320
 321         if (new_val != dev_priv->pm_irq_mask) {
 322                 dev_priv->pm_irq_mask = new_val;
 323                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 324                 POSTING_READ(gen6_pm_imr(dev_priv));
 325         }
 326 }
 327
 328 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 329 {
 330         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 331                 return;
 332
 333         snb_update_pm_irq(dev_priv, mask, mask);
 334 }
 335
 336 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 337                                   uint32_t mask)
 338 {
 339         snb_update_pm_irq(dev_priv, mask, 0);
 340 }
 341
 342 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 343 {
 344         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 345                 return;
 346
 347         __gen6_disable_pm_irq(dev_priv, mask);
 348 }
 349
 350 void gen6_reset_rps_interrupts(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353         uint32_t reg = gen6_pm_iir(dev_priv);
 354
 355         spin_lock_irq(&dev_priv->irq_lock);
 356         I915_WRITE(reg, dev_priv->pm_rps_events);
 357         I915_WRITE(reg, dev_priv->pm_rps_events);
 358         POSTING_READ(reg);
 359         dev_priv->rps.pm_iir = 0;
 360         spin_unlock_irq(&dev_priv->irq_lock);
 361 }
 362
 363 void gen6_enable_rps_interrupts(struct drm_device *dev)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366
 367         spin_lock_irq(&dev_priv->irq_lock);
 368
 369         WARN_ON(dev_priv->rps.pm_iir);
 370         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 371         dev_priv->rps.interrupts_enabled = true;
 372         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 373                                 dev_priv->pm_rps_events);
 374         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 375
 376         spin_unlock_irq(&dev_priv->irq_lock);
 377 }
 378
 379 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 380 {
 381         /*
 382          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 383          * if GEN6_PM_UP_EI_EXPIRED is masked.
 384          *
 385          * TODO: verify if this can be reproduced on VLV,CHV.
 386          */
 387         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 388                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 389
 390         if (INTEL_INFO(dev_priv)->gen >= 8)
 391                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 392
 393         return mask;
 394 }
 395
 396 void gen6_disable_rps_interrupts(struct drm_device *dev)
 397 {
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399
 400         spin_lock_irq(&dev_priv->irq_lock);
 401         dev_priv->rps.interrupts_enabled = false;
 402         spin_unlock_irq(&dev_priv->irq_lock);
 403
 404         cancel_work_sync(&dev_priv->rps.work);
 405
 406         spin_lock_irq(&dev_priv->irq_lock);
 407
 408         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 409
 410         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 411         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 412                                 ~dev_priv->pm_rps_events);
 413
 414         spin_unlock_irq(&dev_priv->irq_lock);
 415
 416         synchronize_irq(dev->irq);
 417 }
 418
 419 /**
 420   * bdw_update_port_irq - update DE port interrupt
 421   * @dev_priv: driver private
 422   * @interrupt_mask: mask of interrupt bits to update
 423   * @enabled_irq_mask: mask of interrupt bits to enable
 424   */
 425 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 426                                 uint32_t interrupt_mask,
 427                                 uint32_t enabled_irq_mask)
 428 {
 429         uint32_t new_val;
 430         uint32_t old_val;
 431
 432         assert_spin_locked(&dev_priv->irq_lock);
 433
 434         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 435
 436         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 437                 return;
 438
 439         old_val = I915_READ(GEN8_DE_PORT_IMR);
 440
 441         new_val = old_val;
 442         new_val &= ~interrupt_mask;
 443         new_val |= (~enabled_irq_mask & interrupt_mask);
 444
 445         if (new_val != old_val) {
 446                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 447                 POSTING_READ(GEN8_DE_PORT_IMR);
 448         }
 449 }
 450
 451 /**
 452  * ibx_display_interrupt_update - update SDEIMR
 453  * @dev_priv: driver private
 454  * @interrupt_mask: mask of interrupt bits to update
 455  * @enabled_irq_mask: mask of interrupt bits to enable
 456  */
 457 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 458                                   uint32_t interrupt_mask,
 459                                   uint32_t enabled_irq_mask)
 460 {
 461         uint32_t sdeimr = I915_READ(SDEIMR);
 462         sdeimr &= ~interrupt_mask;
 463         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 464
 465         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 466
 467         assert_spin_locked(&dev_priv->irq_lock);
 468
 469         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 470                 return;
 471
 472         I915_WRITE(SDEIMR, sdeimr);
 473         POSTING_READ(SDEIMR);
 474 }
 475
 476 static void
 477 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 478                        u32 enable_mask, u32 status_mask)
 479 {
 480         u32 reg = PIPESTAT(pipe);
 481         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 482
 483         assert_spin_locked(&dev_priv->irq_lock);
 484         WARN_ON(!intel_irqs_enabled(dev_priv));
 485
 486         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 487                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 488                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 489                       pipe_name(pipe), enable_mask, status_mask))
 490                 return;
 491
 492         if ((pipestat & enable_mask) == enable_mask)
 493                 return;
 494
 495         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 496
 497         /* Enable the interrupt, clear any pending status */
 498         pipestat |= enable_mask | status_mask;
 499         I915_WRITE(reg, pipestat);
 500         POSTING_READ(reg);
 501 }
 502
 503 static void
 504 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 505                         u32 enable_mask, u32 status_mask)
 506 {
 507         u32 reg = PIPESTAT(pipe);
 508         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 509
 510         assert_spin_locked(&dev_priv->irq_lock);
 511         WARN_ON(!intel_irqs_enabled(dev_priv));
 512
 513         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 514                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 515                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 516                       pipe_name(pipe), enable_mask, status_mask))
 517                 return;
 518
 519         if ((pipestat & enable_mask) == 0)
 520                 return;
 521
 522         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 523
 524         pipestat &= ~enable_mask;
 525         I915_WRITE(reg, pipestat);
 526         POSTING_READ(reg);
 527 }
 528
 529 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 530 {
 531         u32 enable_mask = status_mask << 16;
 532
 533         /*
 534          * On pipe A we don't support the PSR interrupt yet,
 535          * on pipe B and C the same bit MBZ.
 536          */
 537         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 538                 return 0;
 539         /*
 540          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 541          * A the same bit is for perf counters which we don't use either.
 542          */
 543         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 544                 return 0;
 545
 546         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 547                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 548                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 549         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 550                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 551         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 552                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 553
 554         return enable_mask;
 555 }
 556
 557 void
 558 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 559                      u32 status_mask)
 560 {
 561         u32 enable_mask;
 562
 563         if (IS_VALLEYVIEW(dev_priv->dev))
 564                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 565                                                            status_mask);
 566         else
 567                 enable_mask = status_mask << 16;
 568         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 569 }
 570
 571 void
 572 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 573                       u32 status_mask)
 574 {
 575         u32 enable_mask;
 576
 577         if (IS_VALLEYVIEW(dev_priv->dev))
 578                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 579                                                            status_mask);
 580         else
 581                 enable_mask = status_mask << 16;
 582         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 583 }
 584
 585 /**
 586  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 587  * @dev: drm device
 588  */
 589 static void i915_enable_asle_pipestat(struct drm_device *dev)
 590 {
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592
 593         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 594                 return;
 595
 596         spin_lock_irq(&dev_priv->irq_lock);
 597
 598         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 599         if (INTEL_INFO(dev)->gen >= 4)
 600                 i915_enable_pipestat(dev_priv, PIPE_A,
 601                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 602
 603         spin_unlock_irq(&dev_priv->irq_lock);
 604 }
 605
 606 /*
 607  * This timing diagram depicts the video signal in and
 608  * around the vertical blanking period.
 609  *
 610  * Assumptions about the fictitious mode used in this example:
 611  *  vblank_start >= 3
 612  *  vsync_start = vblank_start + 1
 613  *  vsync_end = vblank_start + 2
 614  *  vtotal = vblank_start + 3
 615  *
 616  *           start of vblank:
 617  *           latch double buffered registers
 618  *           increment frame counter (ctg+)
 619  *           generate start of vblank interrupt (gen4+)
 620  *           |
 621  *           |          frame start:
 622  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 623  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 624  *           |          |
 625  *           |          |  start of vsync:
 626  *           |          |  generate vsync interrupt
 627  *           |          |  |
 628  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 629  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 630  * ----va---> <-----------------vb--------------------> <--------va-------------
 631  *       |          |       <----vs----->                     |
 632  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 633  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 634  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 635  *       |          |                                         |
 636  *       last visible pixel                                   first visible pixel
 637  *                  |                                         increment frame counter (gen3/4)
 638  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 639  *
 640  * x  = horizontal active
 641  * _  = horizontal blanking
 642  * hs = horizontal sync
 643  * va = vertical active
 644  * vb = vertical blanking
 645  * vs = vertical sync
 646  * vbs = vblank_start (number)
 647  *
 648  * Summary:
 649  * - most events happen at the start of horizontal sync
 650  * - frame start happens at the start of horizontal blank, 1-4 lines
 651  *   (depending on PIPECONF settings) after the start of vblank
 652  * - gen3/4 pixel and frame counter are synchronized with the start
 653  *   of horizontal active on the first line of vertical active
 654  */
 655
 656 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 657 {
 658         /* Gen2 doesn't have a hardware frame counter */
 659         return 0;
 660 }
 661
 662 /* Called from drm generic code, passed a 'crtc', which
 663  * we use as a pipe index
 664  */
 665 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 666 {
 667         struct drm_i915_private *dev_priv = dev->dev_private;
 668         unsigned long high_frame;
 669         unsigned long low_frame;
 670         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 671         struct intel_crtc *intel_crtc =
 672                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 673         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 674
 675         htotal = mode->crtc_htotal;
 676         hsync_start = mode->crtc_hsync_start;
 677         vbl_start = mode->crtc_vblank_start;
 678         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 679                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 680
 681         /* Convert to pixel count */
 682         vbl_start *= htotal;
 683
 684         /* Start of vblank event occurs at start of hsync */
 685         vbl_start -= htotal - hsync_start;
 686
 687         high_frame = PIPEFRAME(pipe);
 688         low_frame = PIPEFRAMEPIXEL(pipe);
 689
 690         /*
 691          * High & low register fields aren't synchronized, so make sure
 692          * we get a low value that's stable across two reads of the high
 693          * register.
 694          */
 695         do {
 696                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 697                 low   = I915_READ(low_frame);
 698                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 699         } while (high1 != high2);
 700
 701         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 702         pixel = low & PIPE_PIXEL_MASK;
 703         low >>= PIPE_FRAME_LOW_SHIFT;
 704
 705         /*
 706          * The frame counter increments at beginning of active.
 707          * Cook up a vblank counter by also checking the pixel
 708          * counter against vblank start.
 709          */
 710         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 711 }
 712
 713 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 714 {
 715         struct drm_i915_private *dev_priv = dev->dev_private;
 716
 717         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 718 }
 719
 720 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 721 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 722
 723 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 724 {
 725         struct drm_device *dev = crtc->base.dev;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         const struct drm_display_mode *mode = &crtc->base.hwmode;
 728         enum pipe pipe = crtc->pipe;
 729         int position, vtotal;
 730
 731         vtotal = mode->crtc_vtotal;
 732         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 733                 vtotal /= 2;
 734
 735         if (IS_GEN2(dev))
 736                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 737         else
 738                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 739
 740         /*
 741          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 742          * read it just before the start of vblank.  So try it again
 743          * so we don't accidentally end up spanning a vblank frame
 744          * increment, causing the pipe_update_end() code to squak at us.
 745          *
 746          * The nature of this problem means we can't simply check the ISR
 747          * bit and return the vblank start value; nor can we use the scanline
 748          * debug register in the transcoder as it appears to have the same
 749          * problem.  We may need to extend this to include other platforms,
 750          * but so far testing only shows the problem on HSW.
 751          */
 752         if (HAS_DDI(dev) && !position) {
 753                 int i, temp;
 754
 755                 for (i = 0; i < 100; i++) {
 756                         udelay(1);
 757                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 758                                 DSL_LINEMASK_GEN3;
 759                         if (temp != position) {
 760                                 position = temp;
 761                                 break;
 762                         }
 763                 }
 764         }
 765
 766         /*
 767          * See update_scanline_offset() for the details on the
 768          * scanline_offset adjustment.
 769          */
 770         return (position + crtc->scanline_offset) % vtotal;
 771 }
 772
 773 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 774                                     unsigned int flags, int *vpos, int *hpos,
 775                                     ktime_t *stime, ktime_t *etime,
 776                                     const struct drm_display_mode *mode)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 781         int position;
 782         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 783         bool in_vbl = true;
 784         int ret = 0;
 785         unsigned long irqflags;
 786
 787         if (WARN_ON(!mode->crtc_clock)) {
 788                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 789                                  "pipe %c\n", pipe_name(pipe));
 790                 return 0;
 791         }
 792
 793         htotal = mode->crtc_htotal;
 794         hsync_start = mode->crtc_hsync_start;
 795         vtotal = mode->crtc_vtotal;
 796         vbl_start = mode->crtc_vblank_start;
 797         vbl_end = mode->crtc_vblank_end;
 798
 799         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 800                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 801                 vbl_end /= 2;
 802                 vtotal /= 2;
 803         }
 804
 805         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 806
 807         /*
 808          * Lock uncore.lock, as we will do multiple timing critical raw
 809          * register reads, potentially with preemption disabled, so the
 810          * following code must not block on uncore.lock.
 811          */
 812         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 813
 814         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 815         preempt_disable_rt();
 816
 817         /* Get optional system timestamp before query. */
 818         if (stime)
 819                 *stime = ktime_get();
 820
 821         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 822                 /* No obvious pixelcount register. Only query vertical
 823                  * scanout position from Display scan line register.
 824                  */
 825                 position = __intel_get_crtc_scanline(intel_crtc);
 826         } else {
 827                 /* Have access to pixelcount since start of frame.
 828                  * We can split this into vertical and horizontal
 829                  * scanout position.
 830                  */
 831                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 832
 833                 /* convert to pixel counts */
 834                 vbl_start *= htotal;
 835                 vbl_end *= htotal;
 836                 vtotal *= htotal;
 837
 838                 /*
 839                  * In interlaced modes, the pixel counter counts all pixels,
 840                  * so one field will have htotal more pixels. In order to avoid
 841                  * the reported position from jumping backwards when the pixel
 842                  * counter is beyond the length of the shorter field, just
 843                  * clamp the position the length of the shorter field. This
 844                  * matches how the scanline counter based position works since
 845                  * the scanline counter doesn't count the two half lines.
 846                  */
 847                 if (position >= vtotal)
 848                         position = vtotal - 1;
 849
 850                 /*
 851                  * Start of vblank interrupt is triggered at start of hsync,
 852                  * just prior to the first active line of vblank. However we
 853                  * consider lines to start at the leading edge of horizontal
 854                  * active. So, should we get here before we've crossed into
 855                  * the horizontal active of the first line in vblank, we would
 856                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 857                  * always add htotal-hsync_start to the current pixel position.
 858                  */
 859                 position = (position + htotal - hsync_start) % vtotal;
 860         }
 861
 862         /* Get optional system timestamp after query. */
 863         if (etime)
 864                 *etime = ktime_get();
 865
 866         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 867         preempt_enable_rt();
 868
 869         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 870
 871         in_vbl = position >= vbl_start && position < vbl_end;
 872
 873         /*
 874          * While in vblank, position will be negative
 875          * counting up towards 0 at vbl_end. And outside
 876          * vblank, position will be positive counting
 877          * up since vbl_end.
 878          */
 879         if (position >= vbl_start)
 880                 position -= vbl_end;
 881         else
 882                 position += vtotal - vbl_end;
 883
 884         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 885                 *vpos = position;
 886                 *hpos = 0;
 887         } else {
 888                 *vpos = position / htotal;
 889                 *hpos = position - (*vpos * htotal);
 890         }
 891
 892         /* In vblank? */
 893         if (in_vbl)
 894                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 895
 896         return ret;
 897 }
 898
 899 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 900 {
 901         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 902         unsigned long irqflags;
 903         int position;
 904
 905         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 906         position = __intel_get_crtc_scanline(crtc);
 907         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 908
 909         return position;
 910 }
 911
 912 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 913                               int *max_error,
 914                               struct timeval *vblank_time,
 915                               unsigned flags)
 916 {
 917         struct drm_crtc *crtc;
 918
 919         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 920                 DRM_ERROR("Invalid crtc %u\n", pipe);
 921                 return -EINVAL;
 922         }
 923
 924         /* Get drm_crtc to timestamp: */
 925         crtc = intel_get_crtc_for_pipe(dev, pipe);
 926         if (crtc == NULL) {
 927                 DRM_ERROR("Invalid crtc %u\n", pipe);
 928                 return -EINVAL;
 929         }
 930
 931         if (!crtc->hwmode.crtc_clock) {
 932                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 933                 return -EBUSY;
 934         }
 935
 936         /* Helper routine in DRM core does all the work: */
 937         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 938                                                      vblank_time, flags,
 939                                                      &crtc->hwmode);
 940 }
 941
 942 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 943 {
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         u32 busy_up, busy_down, max_avg, min_avg;
 946         u8 new_delay;
 947
 948         spin_lock(&mchdev_lock);
 949
 950         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 951
 952         new_delay = dev_priv->ips.cur_delay;
 953
 954         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 955         busy_up = I915_READ(RCPREVBSYTUPAVG);
 956         busy_down = I915_READ(RCPREVBSYTDNAVG);
 957         max_avg = I915_READ(RCBMAXAVG);
 958         min_avg = I915_READ(RCBMINAVG);
 959
 960         /* Handle RCS change request from hw */
 961         if (busy_up > max_avg) {
 962                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 963                         new_delay = dev_priv->ips.cur_delay - 1;
 964                 if (new_delay < dev_priv->ips.max_delay)
 965                         new_delay = dev_priv->ips.max_delay;
 966         } else if (busy_down < min_avg) {
 967                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 968                         new_delay = dev_priv->ips.cur_delay + 1;
 969                 if (new_delay > dev_priv->ips.min_delay)
 970                         new_delay = dev_priv->ips.min_delay;
 971         }
 972
 973         if (ironlake_set_drps(dev, new_delay))
 974                 dev_priv->ips.cur_delay = new_delay;
 975
 976         spin_unlock(&mchdev_lock);
 977
 978         return;
 979 }
 980
 981 static void notify_ring(struct intel_engine_cs *ring)
 982 {
 983         if (!intel_ring_initialized(ring))
 984                 return;
 985
 986         trace_i915_gem_request_notify(ring);
 987
 988         wake_up_all(&ring->irq_queue);
 989 }
 990
 991 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 992                         struct intel_rps_ei *ei)
 993 {
 994         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 995         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 996         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 997 }
 998
 999 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1000                          const struct intel_rps_ei *old,
1001                          const struct intel_rps_ei *now,
1002                          int threshold)
1003 {
1004         u64 time, c0;
1005         unsigned int mul = 100;
1006
1007         if (old->cz_clock == 0)
1008                 return false;
1009
1010         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1011                 mul <<= 8;
1012
1013         time = now->cz_clock - old->cz_clock;
1014         time *= threshold * dev_priv->czclk_freq;
1015
1016         /* Workload can be split between render + media, e.g. SwapBuffers
1017          * being blitted in X after being rendered in mesa. To account for
1018          * this we need to combine both engines into our activity counter.
1019          */
1020         c0 = now->render_c0 - old->render_c0;
1021         c0 += now->media_c0 - old->media_c0;
1022         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1023
1024         return c0 >= time;
1025 }
1026
1027 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1028 {
1029         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1030         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1031 }
1032
1033 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1034 {
1035         struct intel_rps_ei now;
1036         u32 events = 0;
1037
1038         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1039                 return 0;
1040
1041         vlv_c0_read(dev_priv, &now);
1042         if (now.cz_clock == 0)
1043                 return 0;
1044
1045         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1046                 if (!vlv_c0_above(dev_priv,
1047                                   &dev_priv->rps.down_ei, &now,
1048                                   dev_priv->rps.down_threshold))
1049                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1050                 dev_priv->rps.down_ei = now;
1051         }
1052
1053         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1054                 if (vlv_c0_above(dev_priv,
1055                                  &dev_priv->rps.up_ei, &now,
1056                                  dev_priv->rps.up_threshold))
1057                         events |= GEN6_PM_RP_UP_THRESHOLD;
1058                 dev_priv->rps.up_ei = now;
1059         }
1060
1061         return events;
1062 }
1063
1064 static bool any_waiters(struct drm_i915_private *dev_priv)
1065 {
1066         struct intel_engine_cs *ring;
1067         int i;
1068
1069         for_each_ring(ring, dev_priv, i)
1070                 if (ring->irq_refcount)
1071                         return true;
1072
1073         return false;
1074 }
1075
1076 static void gen6_pm_rps_work(struct work_struct *work)
1077 {
1078         struct drm_i915_private *dev_priv =
1079                 container_of(work, struct drm_i915_private, rps.work);
1080         bool client_boost;
1081         int new_delay, adj, min, max;
1082         u32 pm_iir;
1083
1084         spin_lock_irq(&dev_priv->irq_lock);
1085         /* Speed up work cancelation during disabling rps interrupts. */
1086         if (!dev_priv->rps.interrupts_enabled) {
1087                 spin_unlock_irq(&dev_priv->irq_lock);
1088                 return;
1089         }
1090         pm_iir = dev_priv->rps.pm_iir;
1091         dev_priv->rps.pm_iir = 0;
1092         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1093         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1094         client_boost = dev_priv->rps.client_boost;
1095         dev_priv->rps.client_boost = false;
1096         spin_unlock_irq(&dev_priv->irq_lock);
1097
1098         /* Make sure we didn't queue anything we're not going to process. */
1099         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1100
1101         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1102                 return;
1103
1104         mutex_lock(&dev_priv->rps.hw_lock);
1105
1106         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1107
1108         adj = dev_priv->rps.last_adj;
1109         new_delay = dev_priv->rps.cur_freq;
1110         min = dev_priv->rps.min_freq_softlimit;
1111         max = dev_priv->rps.max_freq_softlimit;
1112
1113         if (client_boost) {
1114                 new_delay = dev_priv->rps.max_freq_softlimit;
1115                 adj = 0;
1116         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1117                 if (adj > 0)
1118                         adj *= 2;
1119                 else /* CHV needs even encode values */
1120                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1121                 /*
1122                  * For better performance, jump directly
1123                  * to RPe if we're below it.
1124                  */
1125                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1126                         new_delay = dev_priv->rps.efficient_freq;
1127                         adj = 0;
1128                 }
1129         } else if (any_waiters(dev_priv)) {
1130                 adj = 0;
1131         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1132                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1133                         new_delay = dev_priv->rps.efficient_freq;
1134                 else
1135                         new_delay = dev_priv->rps.min_freq_softlimit;
1136                 adj = 0;
1137         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1138                 if (adj < 0)
1139                         adj *= 2;
1140                 else /* CHV needs even encode values */
1141                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1142         } else { /* unknown event */
1143                 adj = 0;
1144         }
1145
1146         dev_priv->rps.last_adj = adj;
1147
1148         /* sysfs frequency interfaces may have snuck in while servicing the
1149          * interrupt
1150          */
1151         new_delay += adj;
1152         new_delay = clamp_t(int, new_delay, min, max);
1153
1154         intel_set_rps(dev_priv->dev, new_delay);
1155
1156         mutex_unlock(&dev_priv->rps.hw_lock);
1157 }
1158
1159
1160 /**
1161  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1162  * occurred.
1163  * @work: workqueue struct
1164  *
1165  * Doesn't actually do anything except notify userspace. As a consequence of
1166  * this event, userspace should try to remap the bad rows since statistically
1167  * it is likely the same row is more likely to go bad again.
1168  */
1169 static void ivybridge_parity_work(struct work_struct *work)
1170 {
1171         struct drm_i915_private *dev_priv =
1172                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1173         u32 error_status, row, bank, subbank;
1174         char *parity_event[6];
1175         uint32_t misccpctl;
1176         uint8_t slice = 0;
1177
1178         /* We must turn off DOP level clock gating to access the L3 registers.
1179          * In order to prevent a get/put style interface, acquire struct mutex
1180          * any time we access those registers.
1181          */
1182         mutex_lock(&dev_priv->dev->struct_mutex);
1183
1184         /* If we've screwed up tracking, just let the interrupt fire again */
1185         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1186                 goto out;
1187
1188         misccpctl = I915_READ(GEN7_MISCCPCTL);
1189         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1190         POSTING_READ(GEN7_MISCCPCTL);
1191
1192         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1193                 u32 reg;
1194
1195                 slice--;
1196                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1197                         break;
1198
1199                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1200
1201                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1202
1203                 error_status = I915_READ(reg);
1204                 row = GEN7_PARITY_ERROR_ROW(error_status);
1205                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1206                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1207
1208                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1209                 POSTING_READ(reg);
1210
1211                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1212                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1213                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1214                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1215                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1216                 parity_event[5] = NULL;
1217
1218                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1219                                    KOBJ_CHANGE, parity_event);
1220
1221                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1222                           slice, row, bank, subbank);
1223
1224                 kfree(parity_event[4]);
1225                 kfree(parity_event[3]);
1226                 kfree(parity_event[2]);
1227                 kfree(parity_event[1]);
1228         }
1229
1230         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1231
1232 out:
1233         WARN_ON(dev_priv->l3_parity.which_slice);
1234         spin_lock_irq(&dev_priv->irq_lock);
1235         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1236         spin_unlock_irq(&dev_priv->irq_lock);
1237
1238         mutex_unlock(&dev_priv->dev->struct_mutex);
1239 }
1240
1241 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1242 {
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244
1245         if (!HAS_L3_DPF(dev))
1246                 return;
1247
1248         spin_lock(&dev_priv->irq_lock);
1249         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1250         spin_unlock(&dev_priv->irq_lock);
1251
1252         iir &= GT_PARITY_ERROR(dev);
1253         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1254                 dev_priv->l3_parity.which_slice |= 1 << 1;
1255
1256         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1257                 dev_priv->l3_parity.which_slice |= 1 << 0;
1258
1259         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1260 }
1261
1262 static void ilk_gt_irq_handler(struct drm_device *dev,
1263                                struct drm_i915_private *dev_priv,
1264                                u32 gt_iir)
1265 {
1266         if (gt_iir &
1267             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1268                 notify_ring(&dev_priv->ring[RCS]);
1269         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1270                 notify_ring(&dev_priv->ring[VCS]);
1271 }
1272
1273 static void snb_gt_irq_handler(struct drm_device *dev,
1274                                struct drm_i915_private *dev_priv,
1275                                u32 gt_iir)
1276 {
1277
1278         if (gt_iir &
1279             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1280                 notify_ring(&dev_priv->ring[RCS]);
1281         if (gt_iir & GT_BSD_USER_INTERRUPT)
1282                 notify_ring(&dev_priv->ring[VCS]);
1283         if (gt_iir & GT_BLT_USER_INTERRUPT)
1284                 notify_ring(&dev_priv->ring[BCS]);
1285
1286         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1287                       GT_BSD_CS_ERROR_INTERRUPT |
1288                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1289                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1290
1291         if (gt_iir & GT_PARITY_ERROR(dev))
1292                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1293 }
1294
1295 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1296                                        u32 master_ctl)
1297 {
1298         irqreturn_t ret = IRQ_NONE;
1299
1300         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1301                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1302                 if (tmp) {
1303                         I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1304                         ret = IRQ_HANDLED;
1305
1306                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1307                                 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1308                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1309                                 notify_ring(&dev_priv->ring[RCS]);
1310
1311                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1312                                 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1313                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1314                                 notify_ring(&dev_priv->ring[BCS]);
1315                 } else
1316                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1317         }
1318
1319         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1320                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1321                 if (tmp) {
1322                         I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1323                         ret = IRQ_HANDLED;
1324
1325                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1326                                 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1327                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1328                                 notify_ring(&dev_priv->ring[VCS]);
1329
1330                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1331                                 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1332                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1333                                 notify_ring(&dev_priv->ring[VCS2]);
1334                 } else
1335                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1336         }
1337
1338         if (master_ctl & GEN8_GT_VECS_IRQ) {
1339                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1340                 if (tmp) {
1341                         I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1342                         ret = IRQ_HANDLED;
1343
1344                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1345                                 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1346                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1347                                 notify_ring(&dev_priv->ring[VECS]);
1348                 } else
1349                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1350         }
1351
1352         if (master_ctl & GEN8_GT_PM_IRQ) {
1353                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1354                 if (tmp & dev_priv->pm_rps_events) {
1355                         I915_WRITE_FW(GEN8_GT_IIR(2),
1356                                       tmp & dev_priv->pm_rps_events);
1357                         ret = IRQ_HANDLED;
1358                         gen6_rps_irq_handler(dev_priv, tmp);
1359                 } else
1360                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1361         }
1362
1363         return ret;
1364 }
1365
1366 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1367 {
1368         switch (port) {
1369         case PORT_A:
1370                 return val & PORTA_HOTPLUG_LONG_DETECT;
1371         case PORT_B:
1372                 return val & PORTB_HOTPLUG_LONG_DETECT;
1373         case PORT_C:
1374                 return val & PORTC_HOTPLUG_LONG_DETECT;
1375         default:
1376                 return false;
1377         }
1378 }
1379
1380 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1381 {
1382         switch (port) {
1383         case PORT_E:
1384                 return val & PORTE_HOTPLUG_LONG_DETECT;
1385         default:
1386                 return false;
1387         }
1388 }
1389
1390 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1391 {
1392         switch (port) {
1393         case PORT_A:
1394                 return val & PORTA_HOTPLUG_LONG_DETECT;
1395         case PORT_B:
1396                 return val & PORTB_HOTPLUG_LONG_DETECT;
1397         case PORT_C:
1398                 return val & PORTC_HOTPLUG_LONG_DETECT;
1399         case PORT_D:
1400                 return val & PORTD_HOTPLUG_LONG_DETECT;
1401         default:
1402                 return false;
1403         }
1404 }
1405
1406 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1407 {
1408         switch (port) {
1409         case PORT_A:
1410                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1411         default:
1412                 return false;
1413         }
1414 }
1415
1416 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1417 {
1418         switch (port) {
1419         case PORT_B:
1420                 return val & PORTB_HOTPLUG_LONG_DETECT;
1421         case PORT_C:
1422                 return val & PORTC_HOTPLUG_LONG_DETECT;
1423         case PORT_D:
1424                 return val & PORTD_HOTPLUG_LONG_DETECT;
1425         default:
1426                 return false;
1427         }
1428 }
1429
1430 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1431 {
1432         switch (port) {
1433         case PORT_B:
1434                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1435         case PORT_C:
1436                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1437         case PORT_D:
1438                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1439         default:
1440                 return false;
1441         }
1442 }
1443
1444 /*
1445  * Get a bit mask of pins that have triggered, and which ones may be long.
1446  * This can be called multiple times with the same masks to accumulate
1447  * hotplug detection results from several registers.
1448  *
1449  * Note that the caller is expected to zero out the masks initially.
1450  */
1451 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1452                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1453                              const u32 hpd[HPD_NUM_PINS],
1454                              bool long_pulse_detect(enum port port, u32 val))
1455 {
1456         enum port port;
1457         int i;
1458
1459         for_each_hpd_pin(i) {
1460                 if ((hpd[i] & hotplug_trigger) == 0)
1461                         continue;
1462
1463                 *pin_mask |= BIT(i);
1464
1465                 if (!intel_hpd_pin_to_port(i, &port))
1466                         continue;
1467
1468                 if (long_pulse_detect(port, dig_hotplug_reg))
1469                         *long_mask |= BIT(i);
1470         }
1471
1472         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1473                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1474
1475 }
1476
1477 static void gmbus_irq_handler(struct drm_device *dev)
1478 {
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480
1481         wake_up_all(&dev_priv->gmbus_wait_queue);
1482 }
1483
1484 static void dp_aux_irq_handler(struct drm_device *dev)
1485 {
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487
1488         wake_up_all(&dev_priv->gmbus_wait_queue);
1489 }
1490
1491 #if defined(CONFIG_DEBUG_FS)
1492 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1493                                          uint32_t crc0, uint32_t crc1,
1494                                          uint32_t crc2, uint32_t crc3,
1495                                          uint32_t crc4)
1496 {
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1499         struct intel_pipe_crc_entry *entry;
1500         int head, tail;
1501
1502         spin_lock(&pipe_crc->lock);
1503
1504         if (!pipe_crc->entries) {
1505                 spin_unlock(&pipe_crc->lock);
1506                 DRM_DEBUG_KMS("spurious interrupt\n");
1507                 return;
1508         }
1509
1510         head = pipe_crc->head;
1511         tail = pipe_crc->tail;
1512
1513         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1514                 spin_unlock(&pipe_crc->lock);
1515                 DRM_ERROR("CRC buffer overflowing\n");
1516                 return;
1517         }
1518
1519         entry = &pipe_crc->entries[head];
1520
1521         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1522         entry->crc[0] = crc0;
1523         entry->crc[1] = crc1;
1524         entry->crc[2] = crc2;
1525         entry->crc[3] = crc3;
1526         entry->crc[4] = crc4;
1527
1528         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1529         pipe_crc->head = head;
1530
1531         spin_unlock(&pipe_crc->lock);
1532
1533         wake_up_interruptible(&pipe_crc->wq);
1534 }
1535 #else
1536 static inline void
1537 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1538                              uint32_t crc0, uint32_t crc1,
1539                              uint32_t crc2, uint32_t crc3,
1540                              uint32_t crc4) {}
1541 #endif
1542
1543
1544 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548         display_pipe_crc_irq_handler(dev, pipe,
1549                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1550                                      0, 0, 0, 0);
1551 }
1552
1553 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1554 {
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556
1557         display_pipe_crc_irq_handler(dev, pipe,
1558                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1559                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1560                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1561                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1562                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1563 }
1564
1565 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1566 {
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         uint32_t res1, res2;
1569
1570         if (INTEL_INFO(dev)->gen >= 3)
1571                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1572         else
1573                 res1 = 0;
1574
1575         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1576                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1577         else
1578                 res2 = 0;
1579
1580         display_pipe_crc_irq_handler(dev, pipe,
1581                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1582                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1583                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1584                                      res1, res2);
1585 }
1586
1587 /* The RPS events need forcewake, so we add them to a work queue and mask their
1588  * IMR bits until the work is done. Other interrupts can be processed without
1589  * the work queue. */
1590 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1591 {
1592         if (pm_iir & dev_priv->pm_rps_events) {
1593                 spin_lock(&dev_priv->irq_lock);
1594                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1595                 if (dev_priv->rps.interrupts_enabled) {
1596                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1597                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1598                 }
1599                 spin_unlock(&dev_priv->irq_lock);
1600         }
1601
1602         if (INTEL_INFO(dev_priv)->gen >= 8)
1603                 return;
1604
1605         if (HAS_VEBOX(dev_priv->dev)) {
1606                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1607                         notify_ring(&dev_priv->ring[VECS]);
1608
1609                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1610                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1611         }
1612 }
1613
1614 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1615 {
1616         if (!drm_handle_vblank(dev, pipe))
1617                 return false;
1618
1619         return true;
1620 }
1621
1622 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1623 {
1624         struct drm_i915_private *dev_priv = dev->dev_private;
1625         u32 pipe_stats[I915_MAX_PIPES] = { };
1626         int pipe;
1627
1628         spin_lock(&dev_priv->irq_lock);
1629         for_each_pipe(dev_priv, pipe) {
1630                 int reg;
1631                 u32 mask, iir_bit = 0;
1632
1633                 /*
1634                  * PIPESTAT bits get signalled even when the interrupt is
1635                  * disabled with the mask bits, and some of the status bits do
1636                  * not generate interrupts at all (like the underrun bit). Hence
1637                  * we need to be careful that we only handle what we want to
1638                  * handle.
1639                  */
1640
1641                 /* fifo underruns are filterered in the underrun handler. */
1642                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1643
1644                 switch (pipe) {
1645                 case PIPE_A:
1646                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1647                         break;
1648                 case PIPE_B:
1649                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1650                         break;
1651                 case PIPE_C:
1652                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1653                         break;
1654                 }
1655                 if (iir & iir_bit)
1656                         mask |= dev_priv->pipestat_irq_mask[pipe];
1657
1658                 if (!mask)
1659                         continue;
1660
1661                 reg = PIPESTAT(pipe);
1662                 mask |= PIPESTAT_INT_ENABLE_MASK;
1663                 pipe_stats[pipe] = I915_READ(reg) & mask;
1664
1665                 /*
1666                  * Clear the PIPE*STAT regs before the IIR
1667                  */
1668                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1669                                         PIPESTAT_INT_STATUS_MASK))
1670                         I915_WRITE(reg, pipe_stats[pipe]);
1671         }
1672         spin_unlock(&dev_priv->irq_lock);
1673
1674         for_each_pipe(dev_priv, pipe) {
1675                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1676                     intel_pipe_handle_vblank(dev, pipe))
1677                         intel_check_page_flip(dev, pipe);
1678
1679                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1680                         intel_prepare_page_flip(dev, pipe);
1681                         intel_finish_page_flip(dev, pipe);
1682                 }
1683
1684                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1685                         i9xx_pipe_crc_irq_handler(dev, pipe);
1686
1687                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1688                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1689         }
1690
1691         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1692                 gmbus_irq_handler(dev);
1693 }
1694
1695 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1696 {
1697         struct drm_i915_private *dev_priv = dev->dev_private;
1698         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1699         u32 pin_mask = 0, long_mask = 0;
1700
1701         if (!hotplug_status)
1702                 return;
1703
1704         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1705         /*
1706          * Make sure hotplug status is cleared before we clear IIR, or else we
1707          * may miss hotplug events.
1708          */
1709         POSTING_READ(PORT_HOTPLUG_STAT);
1710
1711         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1712                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1713
1714                 if (hotplug_trigger) {
1715                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1716                                            hotplug_trigger, hpd_status_g4x,
1717                                            i9xx_port_hotplug_long_detect);
1718
1719                         intel_hpd_irq_handler(dev, pin_mask, long_mask);
1720                 }
1721
1722                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1723                         dp_aux_irq_handler(dev);
1724         } else {
1725                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1726
1727                 if (hotplug_trigger) {
1728                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1729                                            hotplug_trigger, hpd_status_i915,
1730                                            i9xx_port_hotplug_long_detect);
1731                         intel_hpd_irq_handler(dev, pin_mask, long_mask);
1732                 }
1733         }
1734 }
1735
1736 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1737 {
1738         struct drm_device *dev = arg;
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         u32 iir, gt_iir, pm_iir;
1741         irqreturn_t ret = IRQ_NONE;
1742
1743         if (!intel_irqs_enabled(dev_priv))
1744                 return IRQ_NONE;
1745
1746         while (true) {
1747                 /* Find, clear, then process each source of interrupt */
1748
1749                 gt_iir = I915_READ(GTIIR);
1750                 if (gt_iir)
1751                         I915_WRITE(GTIIR, gt_iir);
1752
1753                 pm_iir = I915_READ(GEN6_PMIIR);
1754                 if (pm_iir)
1755                         I915_WRITE(GEN6_PMIIR, pm_iir);
1756
1757                 iir = I915_READ(VLV_IIR);
1758                 if (iir) {
1759                         /* Consume port before clearing IIR or we'll miss events */
1760                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1761                                 i9xx_hpd_irq_handler(dev);
1762                         I915_WRITE(VLV_IIR, iir);
1763                 }
1764
1765                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1766                         goto out;
1767
1768                 ret = IRQ_HANDLED;
1769
1770                 if (gt_iir)
1771                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1772                 if (pm_iir)
1773                         gen6_rps_irq_handler(dev_priv, pm_iir);
1774                 /* Call regardless, as some status bits might not be
1775                  * signalled in iir */
1776                 valleyview_pipestat_irq_handler(dev, iir);
1777         }
1778
1779 out:
1780         return ret;
1781 }
1782
1783 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1784 {
1785         struct drm_device *dev = arg;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         u32 master_ctl, iir;
1788         irqreturn_t ret = IRQ_NONE;
1789
1790         if (!intel_irqs_enabled(dev_priv))
1791                 return IRQ_NONE;
1792
1793         for (;;) {
1794                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1795                 iir = I915_READ(VLV_IIR);
1796
1797                 if (master_ctl == 0 && iir == 0)
1798                         break;
1799
1800                 ret = IRQ_HANDLED;
1801
1802                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1803
1804                 /* Find, clear, then process each source of interrupt */
1805
1806                 if (iir) {
1807                         /* Consume port before clearing IIR or we'll miss events */
1808                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1809                                 i9xx_hpd_irq_handler(dev);
1810                         I915_WRITE(VLV_IIR, iir);
1811                 }
1812
1813                 gen8_gt_irq_handler(dev_priv, master_ctl);
1814
1815                 /* Call regardless, as some status bits might not be
1816                  * signalled in iir */
1817                 valleyview_pipestat_irq_handler(dev, iir);
1818
1819                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1820                 POSTING_READ(GEN8_MASTER_IRQ);
1821         }
1822
1823         return ret;
1824 }
1825
1826 static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1827                                 const u32 hpd[HPD_NUM_PINS])
1828 {
1829         struct drm_i915_private *dev_priv = to_i915(dev);
1830         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1831
1832         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1833         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1834
1835         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1836                            dig_hotplug_reg, hpd,
1837                            pch_port_hotplug_long_detect);
1838
1839         intel_hpd_irq_handler(dev, pin_mask, long_mask);
1840 }
1841
1842 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1843 {
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         int pipe;
1846         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1847
1848         if (hotplug_trigger)
1849                 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1850
1851         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1852                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1853                                SDE_AUDIO_POWER_SHIFT);
1854                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1855                                  port_name(port));
1856         }
1857
1858         if (pch_iir & SDE_AUX_MASK)
1859                 dp_aux_irq_handler(dev);
1860
1861         if (pch_iir & SDE_GMBUS)
1862                 gmbus_irq_handler(dev);
1863
1864         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1865                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1866
1867         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1868                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1869
1870         if (pch_iir & SDE_POISON)
1871                 DRM_ERROR("PCH poison interrupt\n");
1872
1873         if (pch_iir & SDE_FDI_MASK)
1874                 for_each_pipe(dev_priv, pipe)
1875                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1876                                          pipe_name(pipe),
1877                                          I915_READ(FDI_RX_IIR(pipe)));
1878
1879         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1880                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1881
1882         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1883                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1884
1885         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1886                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1887
1888         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1889                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1890 }
1891
1892 static void ivb_err_int_handler(struct drm_device *dev)
1893 {
1894         struct drm_i915_private *dev_priv = dev->dev_private;
1895         u32 err_int = I915_READ(GEN7_ERR_INT);
1896         enum pipe pipe;
1897
1898         if (err_int & ERR_INT_POISON)
1899                 DRM_ERROR("Poison interrupt\n");
1900
1901         for_each_pipe(dev_priv, pipe) {
1902                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1903                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1904
1905                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1906                         if (IS_IVYBRIDGE(dev))
1907                                 ivb_pipe_crc_irq_handler(dev, pipe);
1908                         else
1909                                 hsw_pipe_crc_irq_handler(dev, pipe);
1910                 }
1911         }
1912
1913         I915_WRITE(GEN7_ERR_INT, err_int);
1914 }
1915
1916 static void cpt_serr_int_handler(struct drm_device *dev)
1917 {
1918         struct drm_i915_private *dev_priv = dev->dev_private;
1919         u32 serr_int = I915_READ(SERR_INT);
1920
1921         if (serr_int & SERR_INT_POISON)
1922                 DRM_ERROR("PCH poison interrupt\n");
1923
1924         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1925                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1926
1927         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1928                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1929
1930         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1931                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1932
1933         I915_WRITE(SERR_INT, serr_int);
1934 }
1935
1936 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1937 {
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         int pipe;
1940         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1941
1942         if (hotplug_trigger)
1943                 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1944
1945         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1946                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1947                                SDE_AUDIO_POWER_SHIFT_CPT);
1948                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1949                                  port_name(port));
1950         }
1951
1952         if (pch_iir & SDE_AUX_MASK_CPT)
1953                 dp_aux_irq_handler(dev);
1954
1955         if (pch_iir & SDE_GMBUS_CPT)
1956                 gmbus_irq_handler(dev);
1957
1958         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1959                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1960
1961         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1962                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1963
1964         if (pch_iir & SDE_FDI_MASK_CPT)
1965                 for_each_pipe(dev_priv, pipe)
1966                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1967                                          pipe_name(pipe),
1968                                          I915_READ(FDI_RX_IIR(pipe)));
1969
1970         if (pch_iir & SDE_ERROR_CPT)
1971                 cpt_serr_int_handler(dev);
1972 }
1973
1974 static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
1975 {
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1978                 ~SDE_PORTE_HOTPLUG_SPT;
1979         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1980         u32 pin_mask = 0, long_mask = 0;
1981
1982         if (hotplug_trigger) {
1983                 u32 dig_hotplug_reg;
1984
1985                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1986                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1987
1988                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1989                                    dig_hotplug_reg, hpd_spt,
1990                                    spt_port_hotplug_long_detect);
1991         }
1992
1993         if (hotplug2_trigger) {
1994                 u32 dig_hotplug_reg;
1995
1996                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1997                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1998
1999                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2000                                    dig_hotplug_reg, hpd_spt,
2001                                    spt_port_hotplug2_long_detect);
2002         }
2003
2004         if (pin_mask)
2005                 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2006
2007         if (pch_iir & SDE_GMBUS_CPT)
2008                 gmbus_irq_handler(dev);
2009 }
2010
2011 static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2012                                 const u32 hpd[HPD_NUM_PINS])
2013 {
2014         struct drm_i915_private *dev_priv = to_i915(dev);
2015         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2016
2017         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2018         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2019
2020         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2021                            dig_hotplug_reg, hpd,
2022                            ilk_port_hotplug_long_detect);
2023
2024         intel_hpd_irq_handler(dev, pin_mask, long_mask);
2025 }
2026
2027 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2028 {
2029         struct drm_i915_private *dev_priv = dev->dev_private;
2030         enum pipe pipe;
2031         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2032
2033         if (hotplug_trigger)
2034                 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
2035
2036         if (de_iir & DE_AUX_CHANNEL_A)
2037                 dp_aux_irq_handler(dev);
2038
2039         if (de_iir & DE_GSE)
2040                 intel_opregion_asle_intr(dev);
2041
2042         if (de_iir & DE_POISON)
2043                 DRM_ERROR("Poison interrupt\n");
2044
2045         for_each_pipe(dev_priv, pipe) {
2046                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2047                     intel_pipe_handle_vblank(dev, pipe))
2048                         intel_check_page_flip(dev, pipe);
2049
2050                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2051                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2052
2053                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2054                         i9xx_pipe_crc_irq_handler(dev, pipe);
2055
2056                 /* plane/pipes map 1:1 on ilk+ */
2057                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2058                         intel_prepare_page_flip(dev, pipe);
2059                         intel_finish_page_flip_plane(dev, pipe);
2060                 }
2061         }
2062
2063         /* check event from PCH */
2064         if (de_iir & DE_PCH_EVENT) {
2065                 u32 pch_iir = I915_READ(SDEIIR);
2066
2067                 if (HAS_PCH_CPT(dev))
2068                         cpt_irq_handler(dev, pch_iir);
2069                 else
2070                         ibx_irq_handler(dev, pch_iir);
2071
2072                 /* should clear PCH hotplug event before clear CPU irq */
2073                 I915_WRITE(SDEIIR, pch_iir);
2074         }
2075
2076         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2077                 ironlake_rps_change_irq_handler(dev);
2078 }
2079
2080 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2081 {
2082         struct drm_i915_private *dev_priv = dev->dev_private;
2083         enum pipe pipe;
2084         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2085
2086         if (hotplug_trigger)
2087                 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2088
2089         if (de_iir & DE_ERR_INT_IVB)
2090                 ivb_err_int_handler(dev);
2091
2092         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2093                 dp_aux_irq_handler(dev);
2094
2095         if (de_iir & DE_GSE_IVB)
2096                 intel_opregion_asle_intr(dev);
2097
2098         for_each_pipe(dev_priv, pipe) {
2099                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2100                     intel_pipe_handle_vblank(dev, pipe))
2101                         intel_check_page_flip(dev, pipe);
2102
2103                 /* plane/pipes map 1:1 on ilk+ */
2104                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2105                         intel_prepare_page_flip(dev, pipe);
2106                         intel_finish_page_flip_plane(dev, pipe);
2107                 }
2108         }
2109
2110         /* check event from PCH */
2111         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2112                 u32 pch_iir = I915_READ(SDEIIR);
2113
2114                 cpt_irq_handler(dev, pch_iir);
2115
2116                 /* clear PCH hotplug event before clear CPU irq */
2117                 I915_WRITE(SDEIIR, pch_iir);
2118         }
2119 }
2120
2121 /*
2122  * To handle irqs with the minimum potential races with fresh interrupts, we:
2123  * 1 - Disable Master Interrupt Control.
2124  * 2 - Find the source(s) of the interrupt.
2125  * 3 - Clear the Interrupt Identity bits (IIR).
2126  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2127  * 5 - Re-enable Master Interrupt Control.
2128  */
2129 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2130 {
2131         struct drm_device *dev = arg;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2134         irqreturn_t ret = IRQ_NONE;
2135
2136         if (!intel_irqs_enabled(dev_priv))
2137                 return IRQ_NONE;
2138
2139         /* We get interrupts on unclaimed registers, so check for this before we
2140          * do any I915_{READ,WRITE}. */
2141         intel_uncore_check_errors(dev);
2142
2143         /* disable master interrupt before clearing iir  */
2144         de_ier = I915_READ(DEIER);
2145         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2146         POSTING_READ(DEIER);
2147
2148         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2149          * interrupts will will be stored on its back queue, and then we'll be
2150          * able to process them after we restore SDEIER (as soon as we restore
2151          * it, we'll get an interrupt if SDEIIR still has something to process
2152          * due to its back queue). */
2153         if (!HAS_PCH_NOP(dev)) {
2154                 sde_ier = I915_READ(SDEIER);
2155                 I915_WRITE(SDEIER, 0);
2156                 POSTING_READ(SDEIER);
2157         }
2158
2159         /* Find, clear, then process each source of interrupt */
2160
2161         gt_iir = I915_READ(GTIIR);
2162         if (gt_iir) {
2163                 I915_WRITE(GTIIR, gt_iir);
2164                 ret = IRQ_HANDLED;
2165                 if (INTEL_INFO(dev)->gen >= 6)
2166                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2167                 else
2168                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2169         }
2170
2171         de_iir = I915_READ(DEIIR);
2172         if (de_iir) {
2173                 I915_WRITE(DEIIR, de_iir);
2174                 ret = IRQ_HANDLED;
2175                 if (INTEL_INFO(dev)->gen >= 7)
2176                         ivb_display_irq_handler(dev, de_iir);
2177                 else
2178                         ilk_display_irq_handler(dev, de_iir);
2179         }
2180
2181         if (INTEL_INFO(dev)->gen >= 6) {
2182                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2183                 if (pm_iir) {
2184                         I915_WRITE(GEN6_PMIIR, pm_iir);
2185                         ret = IRQ_HANDLED;
2186                         gen6_rps_irq_handler(dev_priv, pm_iir);
2187                 }
2188         }
2189
2190         I915_WRITE(DEIER, de_ier);
2191         POSTING_READ(DEIER);
2192         if (!HAS_PCH_NOP(dev)) {
2193                 I915_WRITE(SDEIER, sde_ier);
2194                 POSTING_READ(SDEIER);
2195         }
2196
2197         return ret;
2198 }
2199
2200 static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2201                                 const u32 hpd[HPD_NUM_PINS])
2202 {
2203         struct drm_i915_private *dev_priv = to_i915(dev);
2204         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2205
2206         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2207         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2208
2209         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2210                            dig_hotplug_reg, hpd,
2211                            bxt_port_hotplug_long_detect);
2212
2213         intel_hpd_irq_handler(dev, pin_mask, long_mask);
2214 }
2215
2216 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2217 {
2218         struct drm_device *dev = arg;
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220         u32 master_ctl;
2221         irqreturn_t ret = IRQ_NONE;
2222         uint32_t tmp = 0;
2223         enum pipe pipe;
2224         u32 aux_mask = GEN8_AUX_CHANNEL_A;
2225
2226         if (!intel_irqs_enabled(dev_priv))
2227                 return IRQ_NONE;
2228
2229         if (INTEL_INFO(dev_priv)->gen >= 9)
2230                 aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2231                         GEN9_AUX_CHANNEL_D;
2232
2233         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2234         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2235         if (!master_ctl)
2236                 return IRQ_NONE;
2237
2238         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2239
2240         /* Find, clear, then process each source of interrupt */
2241
2242         ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2243
2244         if (master_ctl & GEN8_DE_MISC_IRQ) {
2245                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2246                 if (tmp) {
2247                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2248                         ret = IRQ_HANDLED;
2249                         if (tmp & GEN8_DE_MISC_GSE)
2250                                 intel_opregion_asle_intr(dev);
2251                         else
2252                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2253                 }
2254                 else
2255                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2256         }
2257
2258         if (master_ctl & GEN8_DE_PORT_IRQ) {
2259                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2260                 if (tmp) {
2261                         bool found = false;
2262                         u32 hotplug_trigger = 0;
2263
2264                         if (IS_BROXTON(dev_priv))
2265                                 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
2266                         else if (IS_BROADWELL(dev_priv))
2267                                 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
2268
2269                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2270                         ret = IRQ_HANDLED;
2271
2272                         if (tmp & aux_mask) {
2273                                 dp_aux_irq_handler(dev);
2274                                 found = true;
2275                         }
2276
2277                         if (hotplug_trigger) {
2278                                 if (IS_BROXTON(dev))
2279                                         bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
2280                                 else
2281                                         ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
2282                                 found = true;
2283                         }
2284
2285                         if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2286                                 gmbus_irq_handler(dev);
2287                                 found = true;
2288                         }
2289
2290                         if (!found)
2291                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2292                 }
2293                 else
2294                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2295         }
2296
2297         for_each_pipe(dev_priv, pipe) {
2298                 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2299
2300                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2301                         continue;
2302
2303                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2304                 if (pipe_iir) {
2305                         ret = IRQ_HANDLED;
2306                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2307
2308                         if (pipe_iir & GEN8_PIPE_VBLANK &&
2309                             intel_pipe_handle_vblank(dev, pipe))
2310                                 intel_check_page_flip(dev, pipe);
2311
2312                         if (INTEL_INFO(dev_priv)->gen >= 9)
2313                                 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2314                         else
2315                                 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2316
2317                         if (flip_done) {
2318                                 intel_prepare_page_flip(dev, pipe);
2319                                 intel_finish_page_flip_plane(dev, pipe);
2320                         }
2321
2322                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2323                                 hsw_pipe_crc_irq_handler(dev, pipe);
2324
2325                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2326                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2327                                                                     pipe);
2328
2329
2330                         if (INTEL_INFO(dev_priv)->gen >= 9)
2331                                 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2332                         else
2333                                 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2334
2335                         if (fault_errors)
2336                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2337                                           pipe_name(pipe),
2338                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2339                 } else
2340                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2341         }
2342
2343         if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2344             master_ctl & GEN8_DE_PCH_IRQ) {
2345                 /*
2346                  * FIXME(BDW): Assume for now that the new interrupt handling
2347                  * scheme also closed the SDE interrupt handling race we've seen
2348                  * on older pch-split platforms. But this needs testing.
2349                  */
2350                 u32 pch_iir = I915_READ(SDEIIR);
2351                 if (pch_iir) {
2352                         I915_WRITE(SDEIIR, pch_iir);
2353                         ret = IRQ_HANDLED;
2354
2355                         if (HAS_PCH_SPT(dev_priv))
2356                                 spt_irq_handler(dev, pch_iir);
2357                         else
2358                                 cpt_irq_handler(dev, pch_iir);
2359                 } else {
2360                         /*
2361                          * Like on previous PCH there seems to be something
2362                          * fishy going on with forwarding PCH interrupts.
2363                          */
2364                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2365                 }
2366         }
2367
2368         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2369         POSTING_READ_FW(GEN8_MASTER_IRQ);
2370
2371         return ret;
2372 }
2373
2374 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2375                                bool reset_completed)
2376 {
2377         struct intel_engine_cs *ring;
2378         int i;
2379
2380         /*
2381          * Notify all waiters for GPU completion events that reset state has
2382          * been changed, and that they need to restart their wait after
2383          * checking for potential errors (and bail out to drop locks if there is
2384          * a gpu reset pending so that i915_error_work_func can acquire them).
2385          */
2386
2387         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2388         for_each_ring(ring, dev_priv, i)
2389                 wake_up_all(&ring->irq_queue);
2390
2391         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2392         wake_up_all(&dev_priv->pending_flip_queue);
2393
2394         /*
2395          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2396          * reset state is cleared.
2397          */
2398         if (reset_completed)
2399                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2400 }
2401
2402 /**
2403  * i915_reset_and_wakeup - do process context error handling work
2404  * @dev: drm device
2405  *
2406  * Fire an error uevent so userspace can see that a hang or error
2407  * was detected.
2408  */
2409 static void i915_reset_and_wakeup(struct drm_device *dev)
2410 {
2411         struct drm_i915_private *dev_priv = to_i915(dev);
2412         struct i915_gpu_error *error = &dev_priv->gpu_error;
2413         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2414         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2415         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2416         int ret;
2417
2418         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2419
2420         /*
2421          * Note that there's only one work item which does gpu resets, so we
2422          * need not worry about concurrent gpu resets potentially incrementing
2423          * error->reset_counter twice. We only need to take care of another
2424          * racing irq/hangcheck declaring the gpu dead for a second time. A
2425          * quick check for that is good enough: schedule_work ensures the
2426          * correct ordering between hang detection and this work item, and since
2427          * the reset in-progress bit is only ever set by code outside of this
2428          * work we don't need to worry about any other races.
2429          */
2430         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2431                 DRM_DEBUG_DRIVER("resetting chip\n");
2432                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2433                                    reset_event);
2434
2435                 /*
2436                  * In most cases it's guaranteed that we get here with an RPM
2437                  * reference held, for example because there is a pending GPU
2438                  * request that won't finish until the reset is done. This
2439                  * isn't the case at least when we get here by doing a
2440                  * simulated reset via debugs, so get an RPM reference.
2441                  */
2442                 intel_runtime_pm_get(dev_priv);
2443
2444                 intel_prepare_reset(dev);
2445
2446                 /*
2447                  * All state reset _must_ be completed before we update the
2448                  * reset counter, for otherwise waiters might miss the reset
2449                  * pending state and not properly drop locks, resulting in
2450                  * deadlocks with the reset work.
2451                  */
2452                 ret = i915_reset(dev);
2453
2454                 intel_finish_reset(dev);
2455
2456                 intel_runtime_pm_put(dev_priv);
2457
2458                 if (ret == 0) {
2459                         /*
2460                          * After all the gem state is reset, increment the reset
2461                          * counter and wake up everyone waiting for the reset to
2462                          * complete.
2463                          *
2464                          * Since unlock operations are a one-sided barrier only,
2465                          * we need to insert a barrier here to order any seqno
2466                          * updates before
2467                          * the counter increment.
2468                          */
2469                         smp_mb__before_atomic();
2470                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2471
2472                         kobject_uevent_env(&dev->primary->kdev->kobj,
2473                                            KOBJ_CHANGE, reset_done_event);
2474                 } else {
2475                         atomic_or(I915_WEDGED, &error->reset_counter);
2476                 }
2477
2478                 /*
2479                  * Note: The wake_up also serves as a memory barrier so that
2480                  * waiters see the update value of the reset counter atomic_t.
2481                  */
2482                 i915_error_wake_up(dev_priv, true);
2483         }
2484 }
2485
2486 static void i915_report_and_clear_eir(struct drm_device *dev)
2487 {
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         uint32_t instdone[I915_NUM_INSTDONE_REG];
2490         u32 eir = I915_READ(EIR);
2491         int pipe, i;
2492
2493         if (!eir)
2494                 return;
2495
2496         pr_err("render error detected, EIR: 0x%08x\n", eir);
2497
2498         i915_get_extra_instdone(dev, instdone);
2499
2500         if (IS_G4X(dev)) {
2501                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2502                         u32 ipeir = I915_READ(IPEIR_I965);
2503
2504                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2505                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2506                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2507                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2508                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2509                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2510                         I915_WRITE(IPEIR_I965, ipeir);
2511                         POSTING_READ(IPEIR_I965);
2512                 }
2513                 if (eir & GM45_ERROR_PAGE_TABLE) {
2514                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2515                         pr_err("page table error\n");
2516                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2517                         I915_WRITE(PGTBL_ER, pgtbl_err);
2518                         POSTING_READ(PGTBL_ER);
2519                 }
2520         }
2521
2522         if (!IS_GEN2(dev)) {
2523                 if (eir & I915_ERROR_PAGE_TABLE) {
2524                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2525                         pr_err("page table error\n");
2526                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2527                         I915_WRITE(PGTBL_ER, pgtbl_err);
2528                         POSTING_READ(PGTBL_ER);
2529                 }
2530         }
2531
2532         if (eir & I915_ERROR_MEMORY_REFRESH) {
2533                 pr_err("memory refresh error:\n");
2534                 for_each_pipe(dev_priv, pipe)
2535                         pr_err("pipe %c stat: 0x%08x\n",
2536                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2537                 /* pipestat has already been acked */
2538         }
2539         if (eir & I915_ERROR_INSTRUCTION) {
2540                 pr_err("instruction error\n");
2541                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2542                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2543                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2544                 if (INTEL_INFO(dev)->gen < 4) {
2545                         u32 ipeir = I915_READ(IPEIR);
2546
2547                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2548                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2549                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2550                         I915_WRITE(IPEIR, ipeir);
2551                         POSTING_READ(IPEIR);
2552                 } else {
2553                         u32 ipeir = I915_READ(IPEIR_I965);
2554
2555                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2556                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2557                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2558                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2559                         I915_WRITE(IPEIR_I965, ipeir);
2560                         POSTING_READ(IPEIR_I965);
2561                 }
2562         }
2563
2564         I915_WRITE(EIR, eir);
2565         POSTING_READ(EIR);
2566         eir = I915_READ(EIR);
2567         if (eir) {
2568                 /*
2569                  * some errors might have become stuck,
2570                  * mask them.
2571                  */
2572                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2573                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2574                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2575         }
2576 }
2577
2578 /**
2579  * i915_handle_error - handle a gpu error
2580  * @dev: drm device
2581  *
2582  * Do some basic checking of register state at error time and
2583  * dump it to the syslog.  Also call i915_capture_error_state() to make
2584  * sure we get a record and make it available in debugfs.  Fire a uevent
2585  * so userspace knows something bad happened (should trigger collection
2586  * of a ring dump etc.).
2587  */
2588 void i915_handle_error(struct drm_device *dev, bool wedged,
2589                        const char *fmt, ...)
2590 {
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         va_list args;
2593         char error_msg[80];
2594
2595         va_start(args, fmt);
2596         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2597         va_end(args);
2598
2599         i915_capture_error_state(dev, wedged, error_msg);
2600         i915_report_and_clear_eir(dev);
2601
2602         if (wedged) {
2603                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2604                                 &dev_priv->gpu_error.reset_counter);
2605
2606                 /*
2607                  * Wakeup waiting processes so that the reset function
2608                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2609                  * various locks. By bumping the reset counter first, the woken
2610                  * processes will see a reset in progress and back off,
2611                  * releasing their locks and then wait for the reset completion.
2612                  * We must do this for _all_ gpu waiters that might hold locks
2613                  * that the reset work needs to acquire.
2614                  *
2615                  * Note: The wake_up serves as the required memory barrier to
2616                  * ensure that the waiters see the updated value of the reset
2617                  * counter atomic_t.
2618                  */
2619                 i915_error_wake_up(dev_priv, false);
2620         }
2621
2622         i915_reset_and_wakeup(dev);
2623 }
2624
2625 /* Called from drm generic code, passed 'crtc' which
2626  * we use as a pipe index
2627  */
2628 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2629 {
2630         struct drm_i915_private *dev_priv = dev->dev_private;
2631         unsigned long irqflags;
2632
2633         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2634         if (INTEL_INFO(dev)->gen >= 4)
2635                 i915_enable_pipestat(dev_priv, pipe,
2636                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2637         else
2638                 i915_enable_pipestat(dev_priv, pipe,
2639                                      PIPE_VBLANK_INTERRUPT_STATUS);
2640         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2641
2642         return 0;
2643 }
2644
2645 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2646 {
2647         struct drm_i915_private *dev_priv = dev->dev_private;
2648         unsigned long irqflags;
2649         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2650                                                      DE_PIPE_VBLANK(pipe);
2651
2652         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2653         ironlake_enable_display_irq(dev_priv, bit);
2654         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2655
2656         return 0;
2657 }
2658
2659 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2660 {
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         unsigned long irqflags;
2663
2664         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2665         i915_enable_pipestat(dev_priv, pipe,
2666                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2667         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2668
2669         return 0;
2670 }
2671
2672 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2673 {
2674         struct drm_i915_private *dev_priv = dev->dev_private;
2675         unsigned long irqflags;
2676
2677         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2678         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2679         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2680         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2681         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2682         return 0;
2683 }
2684
2685 /* Called from drm generic code, passed 'crtc' which
2686  * we use as a pipe index
2687  */
2688 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2689 {
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         unsigned long irqflags;
2692
2693         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2694         i915_disable_pipestat(dev_priv, pipe,
2695                               PIPE_VBLANK_INTERRUPT_STATUS |
2696                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2697         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2698 }
2699
2700 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2701 {
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         unsigned long irqflags;
2704         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2705                                                      DE_PIPE_VBLANK(pipe);
2706
2707         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2708         ironlake_disable_display_irq(dev_priv, bit);
2709         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2710 }
2711
2712 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2713 {
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         unsigned long irqflags;
2716
2717         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2718         i915_disable_pipestat(dev_priv, pipe,
2719                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2720         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2721 }
2722
2723 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2724 {
2725         struct drm_i915_private *dev_priv = dev->dev_private;
2726         unsigned long irqflags;
2727
2728         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2729         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2730         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2731         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2732         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2733 }
2734
2735 static bool
2736 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2737 {
2738         return (list_empty(&ring->request_list) ||
2739                 i915_seqno_passed(seqno, ring->last_submitted_seqno));
2740 }
2741
2742 static bool
2743 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2744 {
2745         if (INTEL_INFO(dev)->gen >= 8) {
2746                 return (ipehr >> 23) == 0x1c;
2747         } else {
2748                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2749                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2750                                  MI_SEMAPHORE_REGISTER);
2751         }
2752 }
2753
2754 static struct intel_engine_cs *
2755 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2756 {
2757         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2758         struct intel_engine_cs *signaller;
2759         int i;
2760
2761         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2762                 for_each_ring(signaller, dev_priv, i) {
2763                         if (ring == signaller)
2764                                 continue;
2765
2766                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
2767                                 return signaller;
2768                 }
2769         } else {
2770                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2771
2772                 for_each_ring(signaller, dev_priv, i) {
2773                         if(ring == signaller)
2774                                 continue;
2775
2776                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2777                                 return signaller;
2778                 }
2779         }
2780
2781         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2782                   ring->id, ipehr, offset);
2783
2784         return NULL;
2785 }
2786
2787 static struct intel_engine_cs *
2788 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2789 {
2790         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2791         u32 cmd, ipehr, head;
2792         u64 offset = 0;
2793         int i, backwards;
2794
2795         /*
2796          * This function does not support execlist mode - any attempt to
2797          * proceed further into this function will result in a kernel panic
2798          * when dereferencing ring->buffer, which is not set up in execlist
2799          * mode.
2800          *
2801          * The correct way of doing it would be to derive the currently
2802          * executing ring buffer from the current context, which is derived
2803          * from the currently running request. Unfortunately, to get the
2804          * current request we would have to grab the struct_mutex before doing
2805          * anything else, which would be ill-advised since some other thread
2806          * might have grabbed it already and managed to hang itself, causing
2807          * the hang checker to deadlock.
2808          *
2809          * Therefore, this function does not support execlist mode in its
2810          * current form. Just return NULL and move on.
2811          */
2812         if (ring->buffer == NULL)
2813                 return NULL;
2814
2815         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2816         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2817                 return NULL;
2818
2819         /*
2820          * HEAD is likely pointing to the dword after the actual command,
2821          * so scan backwards until we find the MBOX. But limit it to just 3
2822          * or 4 dwords depending on the semaphore wait command size.
2823          * Note that we don't care about ACTHD here since that might
2824          * point at at batch, and semaphores are always emitted into the
2825          * ringbuffer itself.
2826          */
2827         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2828         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2829
2830         for (i = backwards; i; --i) {
2831                 /*
2832                  * Be paranoid and presume the hw has gone off into the wild -
2833                  * our ring is smaller than what the hardware (and hence
2834                  * HEAD_ADDR) allows. Also handles wrap-around.
2835                  */
2836                 head &= ring->buffer->size - 1;
2837
2838                 /* This here seems to blow up */
2839                 cmd = ioread32(ring->buffer->virtual_start + head);
2840                 if (cmd == ipehr)
2841                         break;
2842
2843                 head -= 4;
2844         }
2845
2846         if (!i)
2847                 return NULL;
2848
2849         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2850         if (INTEL_INFO(ring->dev)->gen >= 8) {
2851                 offset = ioread32(ring->buffer->virtual_start + head + 12);
2852                 offset <<= 32;
2853                 offset = ioread32(ring->buffer->virtual_start + head + 8);
2854         }
2855         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2856 }
2857
2858 static int semaphore_passed(struct intel_engine_cs *ring)
2859 {
2860         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2861         struct intel_engine_cs *signaller;
2862         u32 seqno;
2863
2864         ring->hangcheck.deadlock++;
2865
2866         signaller = semaphore_waits_for(ring, &seqno);
2867         if (signaller == NULL)
2868                 return -1;
2869
2870         /* Prevent pathological recursion due to driver bugs */
2871         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2872                 return -1;
2873
2874         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2875                 return 1;
2876
2877         /* cursory check for an unkickable deadlock */
2878         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2879             semaphore_passed(signaller) < 0)
2880                 return -1;
2881
2882         return 0;
2883 }
2884
2885 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2886 {
2887         struct intel_engine_cs *ring;
2888         int i;
2889
2890         for_each_ring(ring, dev_priv, i)
2891                 ring->hangcheck.deadlock = 0;
2892 }
2893
2894 static enum intel_ring_hangcheck_action
2895 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2896 {
2897         struct drm_device *dev = ring->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         u32 tmp;
2900
2901         if (acthd != ring->hangcheck.acthd) {
2902                 if (acthd > ring->hangcheck.max_acthd) {
2903                         ring->hangcheck.max_acthd = acthd;
2904                         return HANGCHECK_ACTIVE;
2905                 }
2906
2907                 return HANGCHECK_ACTIVE_LOOP;
2908         }
2909
2910         if (IS_GEN2(dev))
2911                 return HANGCHECK_HUNG;
2912
2913         /* Is the chip hanging on a WAIT_FOR_EVENT?
2914          * If so we can simply poke the RB_WAIT bit
2915          * and break the hang. This should work on
2916          * all but the second generation chipsets.
2917          */
2918         tmp = I915_READ_CTL(ring);
2919         if (tmp & RING_WAIT) {
2920                 i915_handle_error(dev, false,
2921                                   "Kicking stuck wait on %s",
2922                                   ring->name);
2923                 I915_WRITE_CTL(ring, tmp);
2924                 return HANGCHECK_KICK;
2925         }
2926
2927         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2928                 switch (semaphore_passed(ring)) {
2929                 default:
2930                         return HANGCHECK_HUNG;
2931                 case 1:
2932                         i915_handle_error(dev, false,
2933                                           "Kicking stuck semaphore on %s",
2934                                           ring->name);
2935                         I915_WRITE_CTL(ring, tmp);
2936                         return HANGCHECK_KICK;
2937                 case 0:
2938                         return HANGCHECK_WAIT;
2939                 }
2940         }
2941
2942         return HANGCHECK_HUNG;
2943 }
2944
2945 /*
2946  * This is called when the chip hasn't reported back with completed
2947  * batchbuffers in a long time. We keep track per ring seqno progress and
2948  * if there are no progress, hangcheck score for that ring is increased.
2949  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2950  * we kick the ring. If we see no progress on three subsequent calls
2951  * we assume chip is wedged and try to fix it by resetting the chip.
2952  */
2953 static void i915_hangcheck_elapsed(struct work_struct *work)
2954 {
2955         struct drm_i915_private *dev_priv =
2956                 container_of(work, typeof(*dev_priv),
2957                              gpu_error.hangcheck_work.work);
2958         struct drm_device *dev = dev_priv->dev;
2959         struct intel_engine_cs *ring;
2960         int i;
2961         int busy_count = 0, rings_hung = 0;
2962         bool stuck[I915_NUM_RINGS] = { 0 };
2963 #define BUSY 1
2964 #define KICK 5
2965 #define HUNG 20
2966
2967         if (!i915.enable_hangcheck)
2968                 return;
2969
2970         for_each_ring(ring, dev_priv, i) {
2971                 u64 acthd;
2972                 u32 seqno;
2973                 bool busy = true;
2974
2975                 semaphore_clear_deadlocks(dev_priv);
2976
2977                 seqno = ring->get_seqno(ring, false);
2978                 acthd = intel_ring_get_active_head(ring);
2979
2980                 if (ring->hangcheck.seqno == seqno) {
2981                         if (ring_idle(ring, seqno)) {
2982                                 ring->hangcheck.action = HANGCHECK_IDLE;
2983
2984                                 if (waitqueue_active(&ring->irq_queue)) {
2985                                         /* Issue a wake-up to catch stuck h/w. */
2986                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2987                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2988                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2989                                                                   ring->name);
2990                                                 else
2991                                                         DRM_INFO("Fake missed irq on %s\n",
2992                                                                  ring->name);
2993                                                 wake_up_all(&ring->irq_queue);
2994                                         }
2995                                         /* Safeguard against driver failure */
2996                                         ring->hangcheck.score += BUSY;
2997                                 } else
2998                                         busy = false;
2999                         } else {
3000                                 /* We always increment the hangcheck score
3001                                  * if the ring is busy and still processing
3002                                  * the same request, so that no single request
3003                                  * can run indefinitely (such as a chain of
3004                                  * batches). The only time we do not increment
3005                                  * the hangcheck score on this ring, if this
3006                                  * ring is in a legitimate wait for another
3007                                  * ring. In that case the waiting ring is a
3008                                  * victim and we want to be sure we catch the
3009                                  * right culprit. Then every time we do kick
3010                                  * the ring, add a small increment to the
3011                                  * score so that we can catch a batch that is
3012                                  * being repeatedly kicked and so responsible
3013                                  * for stalling the machine.
3014                                  */
3015                                 ring->hangcheck.action = ring_stuck(ring,
3016                                                                     acthd);
3017
3018                                 switch (ring->hangcheck.action) {
3019                                 case HANGCHECK_IDLE:
3020                                 case HANGCHECK_WAIT:
3021                                 case HANGCHECK_ACTIVE:
3022                                         break;
3023                                 case HANGCHECK_ACTIVE_LOOP:
3024                                         ring->hangcheck.score += BUSY;
3025                                         break;
3026                                 case HANGCHECK_KICK:
3027                                         ring->hangcheck.score += KICK;
3028                                         break;
3029                                 case HANGCHECK_HUNG:
3030                                         ring->hangcheck.score += HUNG;
3031                                         stuck[i] = true;
3032                                         break;
3033                                 }
3034                         }
3035                 } else {
3036                         ring->hangcheck.action = HANGCHECK_ACTIVE;
3037
3038                         /* Gradually reduce the count so that we catch DoS
3039                          * attempts across multiple batches.
3040                          */
3041                         if (ring->hangcheck.score > 0)
3042                                 ring->hangcheck.score--;
3043
3044                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3045                 }
3046
3047                 ring->hangcheck.seqno = seqno;
3048                 ring->hangcheck.acthd = acthd;
3049                 busy_count += busy;
3050         }
3051
3052         for_each_ring(ring, dev_priv, i) {
3053                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3054                         DRM_INFO("%s on %s\n",
3055                                  stuck[i] ? "stuck" : "no progress",
3056                                  ring->name);
3057                         rings_hung++;
3058                 }
3059         }
3060
3061         if (rings_hung)
3062                 return i915_handle_error(dev, true, "Ring hung");
3063
3064         if (busy_count)
3065                 /* Reset timer case chip hangs without another request
3066                  * being added */
3067                 i915_queue_hangcheck(dev);
3068 }
3069
3070 void i915_queue_hangcheck(struct drm_device *dev)
3071 {
3072         struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3073
3074         if (!i915.enable_hangcheck)
3075                 return;
3076
3077         /* Don't continually defer the hangcheck so that it is always run at
3078          * least once after work has been scheduled on any ring. Otherwise,
3079          * we will ignore a hung ring if a second ring is kept busy.
3080          */
3081
3082         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3083                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3084 }
3085
3086 static void ibx_irq_reset(struct drm_device *dev)
3087 {
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089
3090         if (HAS_PCH_NOP(dev))
3091                 return;
3092
3093         GEN5_IRQ_RESET(SDE);
3094
3095         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3096                 I915_WRITE(SERR_INT, 0xffffffff);
3097 }
3098
3099 /*
3100  * SDEIER is also touched by the interrupt handler to work around missed PCH
3101  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3102  * instead we unconditionally enable all PCH interrupt sources here, but then
3103  * only unmask them as needed with SDEIMR.
3104  *
3105  * This function needs to be called before interrupts are enabled.
3106  */
3107 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3108 {
3109         struct drm_i915_private *dev_priv = dev->dev_private;
3110
3111         if (HAS_PCH_NOP(dev))
3112                 return;
3113
3114         WARN_ON(I915_READ(SDEIER) != 0);
3115         I915_WRITE(SDEIER, 0xffffffff);
3116         POSTING_READ(SDEIER);
3117 }
3118
3119 static void gen5_gt_irq_reset(struct drm_device *dev)
3120 {
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122
3123         GEN5_IRQ_RESET(GT);
3124         if (INTEL_INFO(dev)->gen >= 6)
3125                 GEN5_IRQ_RESET(GEN6_PM);
3126 }
3127
3128 /* drm_dma.h hooks
3129 */
3130 static void ironlake_irq_reset(struct drm_device *dev)
3131 {
3132         struct drm_i915_private *dev_priv = dev->dev_private;
3133
3134         I915_WRITE(HWSTAM, 0xffffffff);
3135
3136         GEN5_IRQ_RESET(DE);
3137         if (IS_GEN7(dev))
3138                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3139
3140         gen5_gt_irq_reset(dev);
3141
3142         ibx_irq_reset(dev);
3143 }
3144
3145 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3146 {
3147         enum pipe pipe;
3148
3149         i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
3150         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3151
3152         for_each_pipe(dev_priv, pipe)
3153                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3154
3155         GEN5_IRQ_RESET(VLV_);
3156 }
3157
3158 static void valleyview_irq_preinstall(struct drm_device *dev)
3159 {
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161
3162         /* VLV magic */
3163         I915_WRITE(VLV_IMR, 0);
3164         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3165         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3166         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3167
3168         gen5_gt_irq_reset(dev);
3169
3170         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3171
3172         vlv_display_irq_reset(dev_priv);
3173 }
3174
3175 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3176 {
3177         GEN8_IRQ_RESET_NDX(GT, 0);
3178         GEN8_IRQ_RESET_NDX(GT, 1);
3179         GEN8_IRQ_RESET_NDX(GT, 2);
3180         GEN8_IRQ_RESET_NDX(GT, 3);
3181 }
3182
3183 static void gen8_irq_reset(struct drm_device *dev)
3184 {
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         int pipe;
3187
3188         I915_WRITE(GEN8_MASTER_IRQ, 0);
3189         POSTING_READ(GEN8_MASTER_IRQ);
3190
3191         gen8_gt_irq_reset(dev_priv);
3192
3193         for_each_pipe(dev_priv, pipe)
3194                 if (intel_display_power_is_enabled(dev_priv,
3195                                                    POWER_DOMAIN_PIPE(pipe)))
3196                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3197
3198         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3199         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3200         GEN5_IRQ_RESET(GEN8_PCU_);
3201
3202         if (HAS_PCH_SPLIT(dev))
3203                 ibx_irq_reset(dev);
3204 }
3205
3206 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3207                                      unsigned int pipe_mask)
3208 {
3209         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3210
3211         spin_lock_irq(&dev_priv->irq_lock);
3212         if (pipe_mask & 1 << PIPE_A)
3213                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3214                                   dev_priv->de_irq_mask[PIPE_A],
3215                                   ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3216         if (pipe_mask & 1 << PIPE_B)
3217                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3218                                   dev_priv->de_irq_mask[PIPE_B],
3219                                   ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3220         if (pipe_mask & 1 << PIPE_C)
3221                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3222                                   dev_priv->de_irq_mask[PIPE_C],
3223                                   ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3224         spin_unlock_irq(&dev_priv->irq_lock);
3225 }
3226
3227 static void cherryview_irq_preinstall(struct drm_device *dev)
3228 {
3229         struct drm_i915_private *dev_priv = dev->dev_private;
3230
3231         I915_WRITE(GEN8_MASTER_IRQ, 0);
3232         POSTING_READ(GEN8_MASTER_IRQ);
3233
3234         gen8_gt_irq_reset(dev_priv);
3235
3236         GEN5_IRQ_RESET(GEN8_PCU_);
3237
3238         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3239
3240         vlv_display_irq_reset(dev_priv);
3241 }
3242
3243 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3244                                   const u32 hpd[HPD_NUM_PINS])
3245 {
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247         struct intel_encoder *encoder;
3248         u32 enabled_irqs = 0;
3249
3250         for_each_intel_encoder(dev, encoder)
3251                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3252                         enabled_irqs |= hpd[encoder->hpd_pin];
3253
3254         return enabled_irqs;
3255 }
3256
3257 static void ibx_hpd_irq_setup(struct drm_device *dev)
3258 {
3259         struct drm_i915_private *dev_priv = dev->dev_private;
3260         u32 hotplug_irqs, hotplug, enabled_irqs;
3261
3262         if (HAS_PCH_IBX(dev)) {
3263                 hotplug_irqs = SDE_HOTPLUG_MASK;
3264                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3265         } else {
3266                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3267                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3268         }
3269
3270         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3271
3272         /*
3273          * Enable digital hotplug on the PCH, and configure the DP short pulse
3274          * duration to 2ms (which is the minimum in the Display Port spec).
3275          * The pulse duration bits are reserved on LPT+.
3276          */
3277         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3278         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3279         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3280         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3281         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3282         /*
3283          * When CPU and PCH are on the same package, port A
3284          * HPD must be enabled in both north and south.
3285          */
3286         if (HAS_PCH_LPT_LP(dev))
3287                 hotplug |= PORTA_HOTPLUG_ENABLE;
3288         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3289 }
3290
3291 static void spt_hpd_irq_setup(struct drm_device *dev)
3292 {
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         u32 hotplug_irqs, hotplug, enabled_irqs;
3295
3296         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3297         enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3298
3299         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3300
3301         /* Enable digital hotplug on the PCH */
3302         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3303         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3304                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3305         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3306
3307         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3308         hotplug |= PORTE_HOTPLUG_ENABLE;
3309         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3310 }
3311
3312 static void ilk_hpd_irq_setup(struct drm_device *dev)
3313 {
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315         u32 hotplug_irqs, hotplug, enabled_irqs;
3316
3317         if (INTEL_INFO(dev)->gen >= 8) {
3318                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3319                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3320
3321                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3322         } else if (INTEL_INFO(dev)->gen >= 7) {
3323                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3324                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3325
3326                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3327         } else {
3328                 hotplug_irqs = DE_DP_A_HOTPLUG;
3329                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3330
3331                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3332         }
3333
3334         /*
3335          * Enable digital hotplug on the CPU, and configure the DP short pulse
3336          * duration to 2ms (which is the minimum in the Display Port spec)
3337          * The pulse duration bits are reserved on HSW+.
3338          */
3339         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3340         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3341         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3342         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3343
3344         ibx_hpd_irq_setup(dev);
3345 }
3346
3347 static void bxt_hpd_irq_setup(struct drm_device *dev)
3348 {
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         u32 hotplug_irqs, hotplug, enabled_irqs;
3351
3352         enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3353         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3354
3355         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3356
3357         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3358         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3359                 PORTA_HOTPLUG_ENABLE;
3360         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3361 }
3362
3363 static void ibx_irq_postinstall(struct drm_device *dev)
3364 {
3365         struct drm_i915_private *dev_priv = dev->dev_private;
3366         u32 mask;
3367
3368         if (HAS_PCH_NOP(dev))
3369                 return;
3370
3371         if (HAS_PCH_IBX(dev))
3372                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3373         else
3374                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3375
3376         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3377         I915_WRITE(SDEIMR, ~mask);
3378 }
3379
3380 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3381 {
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         u32 pm_irqs, gt_irqs;
3384
3385         pm_irqs = gt_irqs = 0;
3386
3387         dev_priv->gt_irq_mask = ~0;
3388         if (HAS_L3_DPF(dev)) {
3389                 /* L3 parity interrupt is always unmasked. */
3390                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3391                 gt_irqs |= GT_PARITY_ERROR(dev);
3392         }
3393
3394         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3395         if (IS_GEN5(dev)) {
3396                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3397                            ILK_BSD_USER_INTERRUPT;
3398         } else {
3399                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3400         }
3401
3402         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3403
3404         if (INTEL_INFO(dev)->gen >= 6) {
3405                 /*
3406                  * RPS interrupts will get enabled/disabled on demand when RPS
3407                  * itself is enabled/disabled.
3408                  */
3409                 if (HAS_VEBOX(dev))
3410                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3411
3412                 dev_priv->pm_irq_mask = 0xffffffff;
3413                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3414         }
3415 }
3416
3417 static int ironlake_irq_postinstall(struct drm_device *dev)
3418 {
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         u32 display_mask, extra_mask;
3421
3422         if (INTEL_INFO(dev)->gen >= 7) {
3423                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3424                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3425                                 DE_PLANEB_FLIP_DONE_IVB |
3426                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3427                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3428                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3429                               DE_DP_A_HOTPLUG_IVB);
3430         } else {
3431                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3432                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3433                                 DE_AUX_CHANNEL_A |
3434                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3435                                 DE_POISON);
3436                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3437                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3438                               DE_DP_A_HOTPLUG);
3439         }
3440
3441         dev_priv->irq_mask = ~display_mask;
3442
3443         I915_WRITE(HWSTAM, 0xeffe);
3444
3445         ibx_irq_pre_postinstall(dev);
3446
3447         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3448
3449         gen5_gt_irq_postinstall(dev);
3450
3451         ibx_irq_postinstall(dev);
3452
3453         if (IS_IRONLAKE_M(dev)) {
3454                 /* Enable PCU event interrupts
3455                  *
3456                  * spinlocking not required here for correctness since interrupt
3457                  * setup is guaranteed to run in single-threaded context. But we
3458                  * need it to make the assert_spin_locked happy. */
3459                 spin_lock_irq(&dev_priv->irq_lock);
3460                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3461                 spin_unlock_irq(&dev_priv->irq_lock);
3462         }
3463
3464         return 0;
3465 }
3466
3467 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3468 {
3469         u32 pipestat_mask;
3470         u32 iir_mask;
3471         enum pipe pipe;
3472
3473         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3474                         PIPE_FIFO_UNDERRUN_STATUS;
3475
3476         for_each_pipe(dev_priv, pipe)
3477                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3478         POSTING_READ(PIPESTAT(PIPE_A));
3479
3480         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3481                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3482
3483         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3484         for_each_pipe(dev_priv, pipe)
3485                       i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3486
3487         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3488                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3489                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3490         if (IS_CHERRYVIEW(dev_priv))
3491                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3492         dev_priv->irq_mask &= ~iir_mask;
3493
3494         I915_WRITE(VLV_IIR, iir_mask);
3495         I915_WRITE(VLV_IIR, iir_mask);
3496         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3497         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3498         POSTING_READ(VLV_IMR);
3499 }
3500
3501 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3502 {
3503         u32 pipestat_mask;
3504         u32 iir_mask;
3505         enum pipe pipe;
3506
3507         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3508                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3509                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3510         if (IS_CHERRYVIEW(dev_priv))
3511                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3512
3513         dev_priv->irq_mask |= iir_mask;
3514         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3515         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3516         I915_WRITE(VLV_IIR, iir_mask);
3517         I915_WRITE(VLV_IIR, iir_mask);
3518         POSTING_READ(VLV_IIR);
3519
3520         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3521                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3522
3523         i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3524         for_each_pipe(dev_priv, pipe)
3525                 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3526
3527         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3528                         PIPE_FIFO_UNDERRUN_STATUS;
3529
3530         for_each_pipe(dev_priv, pipe)
3531                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3532         POSTING_READ(PIPESTAT(PIPE_A));
3533 }
3534
3535 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3536 {
3537         assert_spin_locked(&dev_priv->irq_lock);
3538
3539         if (dev_priv->display_irqs_enabled)
3540                 return;
3541
3542         dev_priv->display_irqs_enabled = true;
3543
3544         if (intel_irqs_enabled(dev_priv))
3545                 valleyview_display_irqs_install(dev_priv);
3546 }
3547
3548 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3549 {
3550         assert_spin_locked(&dev_priv->irq_lock);
3551
3552         if (!dev_priv->display_irqs_enabled)
3553                 return;
3554
3555         dev_priv->display_irqs_enabled = false;
3556
3557         if (intel_irqs_enabled(dev_priv))
3558                 valleyview_display_irqs_uninstall(dev_priv);
3559 }
3560
3561 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3562 {
3563         dev_priv->irq_mask = ~0;
3564
3565         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3566         POSTING_READ(PORT_HOTPLUG_EN);
3567
3568         I915_WRITE(VLV_IIR, 0xffffffff);
3569         I915_WRITE(VLV_IIR, 0xffffffff);
3570         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3571         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3572         POSTING_READ(VLV_IMR);
3573
3574         /* Interrupt setup is already guaranteed to be single-threaded, this is
3575          * just to make the assert_spin_locked check happy. */
3576         spin_lock_irq(&dev_priv->irq_lock);
3577         if (dev_priv->display_irqs_enabled)
3578                 valleyview_display_irqs_install(dev_priv);
3579         spin_unlock_irq(&dev_priv->irq_lock);
3580 }
3581
3582 static int valleyview_irq_postinstall(struct drm_device *dev)
3583 {
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586         vlv_display_irq_postinstall(dev_priv);
3587
3588         gen5_gt_irq_postinstall(dev);
3589
3590         /* ack & enable invalid PTE error interrupts */
3591 #if 0 /* FIXME: add support to irq handler for checking these bits */
3592         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3593         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3594 #endif
3595
3596         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3597
3598         return 0;
3599 }
3600
3601 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3602 {
3603         /* These are interrupts we'll toggle with the ring mask register */
3604         uint32_t gt_interrupts[] = {
3605                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3606                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3607                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3608                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3609                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3610                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3611                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3612                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3613                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3614                 0,
3615                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3616                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3617                 };
3618
3619         dev_priv->pm_irq_mask = 0xffffffff;
3620         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3621         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3622         /*
3623          * RPS interrupts will get enabled/disabled on demand when RPS itself
3624          * is enabled/disabled.
3625          */
3626         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3627         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3628 }
3629
3630 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3631 {
3632         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3633         uint32_t de_pipe_enables;
3634         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3635         u32 de_port_enables;
3636         enum pipe pipe;
3637
3638         if (INTEL_INFO(dev_priv)->gen >= 9) {
3639                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3640                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3641                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3642                                   GEN9_AUX_CHANNEL_D;
3643                 if (IS_BROXTON(dev_priv))
3644                         de_port_masked |= BXT_DE_PORT_GMBUS;
3645         } else {
3646                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3647                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3648         }
3649
3650         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3651                                            GEN8_PIPE_FIFO_UNDERRUN;
3652
3653         de_port_enables = de_port_masked;
3654         if (IS_BROXTON(dev_priv))
3655                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3656         else if (IS_BROADWELL(dev_priv))
3657                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3658
3659         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3660         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3661         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3662
3663         for_each_pipe(dev_priv, pipe)
3664                 if (intel_display_power_is_enabled(dev_priv,
3665                                 POWER_DOMAIN_PIPE(pipe)))
3666                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3667                                           dev_priv->de_irq_mask[pipe],
3668                                           de_pipe_enables);
3669
3670         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3671 }
3672
3673 static int gen8_irq_postinstall(struct drm_device *dev)
3674 {
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676
3677         if (HAS_PCH_SPLIT(dev))
3678                 ibx_irq_pre_postinstall(dev);
3679
3680         gen8_gt_irq_postinstall(dev_priv);
3681         gen8_de_irq_postinstall(dev_priv);
3682
3683         if (HAS_PCH_SPLIT(dev))
3684                 ibx_irq_postinstall(dev);
3685
3686         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3687         POSTING_READ(GEN8_MASTER_IRQ);
3688
3689         return 0;
3690 }
3691
3692 static int cherryview_irq_postinstall(struct drm_device *dev)
3693 {
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695
3696         vlv_display_irq_postinstall(dev_priv);
3697
3698         gen8_gt_irq_postinstall(dev_priv);
3699
3700         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3701         POSTING_READ(GEN8_MASTER_IRQ);
3702
3703         return 0;
3704 }
3705
3706 static void gen8_irq_uninstall(struct drm_device *dev)
3707 {
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         if (!dev_priv)
3711                 return;
3712
3713         gen8_irq_reset(dev);
3714 }
3715
3716 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3717 {
3718         /* Interrupt setup is already guaranteed to be single-threaded, this is
3719          * just to make the assert_spin_locked check happy. */
3720         spin_lock_irq(&dev_priv->irq_lock);
3721         if (dev_priv->display_irqs_enabled)
3722                 valleyview_display_irqs_uninstall(dev_priv);
3723         spin_unlock_irq(&dev_priv->irq_lock);
3724
3725         vlv_display_irq_reset(dev_priv);
3726
3727         dev_priv->irq_mask = ~0;
3728 }
3729
3730 static void valleyview_irq_uninstall(struct drm_device *dev)
3731 {
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733
3734         if (!dev_priv)
3735                 return;
3736
3737         I915_WRITE(VLV_MASTER_IER, 0);
3738
3739         gen5_gt_irq_reset(dev);
3740
3741         I915_WRITE(HWSTAM, 0xffffffff);
3742
3743         vlv_display_irq_uninstall(dev_priv);
3744 }
3745
3746 static void cherryview_irq_uninstall(struct drm_device *dev)
3747 {
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749
3750         if (!dev_priv)
3751                 return;
3752
3753         I915_WRITE(GEN8_MASTER_IRQ, 0);
3754         POSTING_READ(GEN8_MASTER_IRQ);
3755
3756         gen8_gt_irq_reset(dev_priv);
3757
3758         GEN5_IRQ_RESET(GEN8_PCU_);
3759
3760         vlv_display_irq_uninstall(dev_priv);
3761 }
3762
3763 static void ironlake_irq_uninstall(struct drm_device *dev)
3764 {
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766
3767         if (!dev_priv)
3768                 return;
3769
3770         ironlake_irq_reset(dev);
3771 }
3772
3773 static void i8xx_irq_preinstall(struct drm_device * dev)
3774 {
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         int pipe;
3777
3778         for_each_pipe(dev_priv, pipe)
3779                 I915_WRITE(PIPESTAT(pipe), 0);
3780         I915_WRITE16(IMR, 0xffff);
3781         I915_WRITE16(IER, 0x0);
3782         POSTING_READ16(IER);
3783 }
3784
3785 static int i8xx_irq_postinstall(struct drm_device *dev)
3786 {
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788
3789         I915_WRITE16(EMR,
3790                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3791
3792         /* Unmask the interrupts that we always want on. */
3793         dev_priv->irq_mask =
3794                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3795                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3796                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3797                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3798         I915_WRITE16(IMR, dev_priv->irq_mask);
3799
3800         I915_WRITE16(IER,
3801                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3802                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3803                      I915_USER_INTERRUPT);
3804         POSTING_READ16(IER);
3805
3806         /* Interrupt setup is already guaranteed to be single-threaded, this is
3807          * just to make the assert_spin_locked check happy. */
3808         spin_lock_irq(&dev_priv->irq_lock);
3809         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3810         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3811         spin_unlock_irq(&dev_priv->irq_lock);
3812
3813         return 0;
3814 }
3815
3816 /*
3817  * Returns true when a page flip has completed.
3818  */
3819 static bool i8xx_handle_vblank(struct drm_device *dev,
3820                                int plane, int pipe, u32 iir)
3821 {
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3824
3825         if (!intel_pipe_handle_vblank(dev, pipe))
3826                 return false;
3827
3828         if ((iir & flip_pending) == 0)
3829                 goto check_page_flip;
3830
3831         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3832          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3833          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3834          * the flip is completed (no longer pending). Since this doesn't raise
3835          * an interrupt per se, we watch for the change at vblank.
3836          */
3837         if (I915_READ16(ISR) & flip_pending)
3838                 goto check_page_flip;
3839
3840         intel_prepare_page_flip(dev, plane);
3841         intel_finish_page_flip(dev, pipe);
3842         return true;
3843
3844 check_page_flip:
3845         intel_check_page_flip(dev, pipe);
3846         return false;
3847 }
3848
3849 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3850 {
3851         struct drm_device *dev = arg;
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         u16 iir, new_iir;
3854         u32 pipe_stats[2];
3855         int pipe;
3856         u16 flip_mask =
3857                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3858                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3859
3860         if (!intel_irqs_enabled(dev_priv))
3861                 return IRQ_NONE;
3862
3863         iir = I915_READ16(IIR);
3864         if (iir == 0)
3865                 return IRQ_NONE;
3866
3867         while (iir & ~flip_mask) {
3868                 /* Can't rely on pipestat interrupt bit in iir as it might
3869                  * have been cleared after the pipestat interrupt was received.
3870                  * It doesn't set the bit in iir again, but it still produces
3871                  * interrupts (for non-MSI).
3872                  */
3873                 spin_lock(&dev_priv->irq_lock);
3874                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3875                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3876
3877                 for_each_pipe(dev_priv, pipe) {
3878                         int reg = PIPESTAT(pipe);
3879                         pipe_stats[pipe] = I915_READ(reg);
3880
3881                         /*
3882                          * Clear the PIPE*STAT regs before the IIR
3883                          */
3884                         if (pipe_stats[pipe] & 0x8000ffff)
3885                                 I915_WRITE(reg, pipe_stats[pipe]);
3886                 }
3887                 spin_unlock(&dev_priv->irq_lock);
3888
3889                 I915_WRITE16(IIR, iir & ~flip_mask);
3890                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3891
3892                 if (iir & I915_USER_INTERRUPT)
3893                         notify_ring(&dev_priv->ring[RCS]);
3894
3895                 for_each_pipe(dev_priv, pipe) {
3896                         int plane = pipe;
3897                         if (HAS_FBC(dev))
3898                                 plane = !plane;
3899
3900                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3901                             i8xx_handle_vblank(dev, plane, pipe, iir))
3902                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3903
3904                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3905                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3906
3907                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3908                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3909                                                                     pipe);
3910                 }
3911
3912                 iir = new_iir;
3913         }
3914
3915         return IRQ_HANDLED;
3916 }
3917
3918 static void i8xx_irq_uninstall(struct drm_device * dev)
3919 {
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         int pipe;
3922
3923         for_each_pipe(dev_priv, pipe) {
3924                 /* Clear enable bits; then clear status bits */
3925                 I915_WRITE(PIPESTAT(pipe), 0);
3926                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3927         }
3928         I915_WRITE16(IMR, 0xffff);
3929         I915_WRITE16(IER, 0x0);
3930         I915_WRITE16(IIR, I915_READ16(IIR));
3931 }
3932
3933 static void i915_irq_preinstall(struct drm_device * dev)
3934 {
3935         struct drm_i915_private *dev_priv = dev->dev_private;
3936         int pipe;
3937
3938         if (I915_HAS_HOTPLUG(dev)) {
3939                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3940                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3941         }
3942
3943         I915_WRITE16(HWSTAM, 0xeffe);
3944         for_each_pipe(dev_priv, pipe)
3945                 I915_WRITE(PIPESTAT(pipe), 0);
3946         I915_WRITE(IMR, 0xffffffff);
3947         I915_WRITE(IER, 0x0);
3948         POSTING_READ(IER);
3949 }
3950
3951 static int i915_irq_postinstall(struct drm_device *dev)
3952 {
3953         struct drm_i915_private *dev_priv = dev->dev_private;
3954         u32 enable_mask;
3955
3956         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3957
3958         /* Unmask the interrupts that we always want on. */
3959         dev_priv->irq_mask =
3960                 ~(I915_ASLE_INTERRUPT |
3961                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3962                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3963                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3964                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3965
3966         enable_mask =
3967                 I915_ASLE_INTERRUPT |
3968                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3969                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3970                 I915_USER_INTERRUPT;
3971
3972         if (I915_HAS_HOTPLUG(dev)) {
3973                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3974                 POSTING_READ(PORT_HOTPLUG_EN);
3975
3976                 /* Enable in IER... */
3977                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3978                 /* and unmask in IMR */
3979                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3980         }
3981
3982         I915_WRITE(IMR, dev_priv->irq_mask);
3983         I915_WRITE(IER, enable_mask);
3984         POSTING_READ(IER);
3985
3986         i915_enable_asle_pipestat(dev);
3987
3988         /* Interrupt setup is already guaranteed to be single-threaded, this is
3989          * just to make the assert_spin_locked check happy. */
3990         spin_lock_irq(&dev_priv->irq_lock);
3991         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3992         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3993         spin_unlock_irq(&dev_priv->irq_lock);
3994
3995         return 0;
3996 }
3997
3998 /*
3999  * Returns true when a page flip has completed.
4000  */
4001 static bool i915_handle_vblank(struct drm_device *dev,
4002                                int plane, int pipe, u32 iir)
4003 {
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4006
4007         if (!intel_pipe_handle_vblank(dev, pipe))
4008                 return false;
4009
4010         if ((iir & flip_pending) == 0)
4011                 goto check_page_flip;
4012
4013         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4014          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4015          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4016          * the flip is completed (no longer pending). Since this doesn't raise
4017          * an interrupt per se, we watch for the change at vblank.
4018          */
4019         if (I915_READ(ISR) & flip_pending)
4020                 goto check_page_flip;
4021
4022         intel_prepare_page_flip(dev, plane);
4023         intel_finish_page_flip(dev, pipe);
4024         return true;
4025
4026 check_page_flip:
4027         intel_check_page_flip(dev, pipe);
4028         return false;
4029 }
4030
4031 static irqreturn_t i915_irq_handler(int irq, void *arg)
4032 {
4033         struct drm_device *dev = arg;
4034         struct drm_i915_private *dev_priv = dev->dev_private;
4035         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4036         u32 flip_mask =
4037                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4038                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4039         int pipe, ret = IRQ_NONE;
4040
4041         if (!intel_irqs_enabled(dev_priv))
4042                 return IRQ_NONE;
4043
4044         iir = I915_READ(IIR);
4045         do {
4046                 bool irq_received = (iir & ~flip_mask) != 0;
4047                 bool blc_event = false;
4048
4049                 /* Can't rely on pipestat interrupt bit in iir as it might
4050                  * have been cleared after the pipestat interrupt was received.
4051                  * It doesn't set the bit in iir again, but it still produces
4052                  * interrupts (for non-MSI).
4053                  */
4054                 spin_lock(&dev_priv->irq_lock);
4055                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4056                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4057
4058                 for_each_pipe(dev_priv, pipe) {
4059                         int reg = PIPESTAT(pipe);
4060                         pipe_stats[pipe] = I915_READ(reg);
4061
4062                         /* Clear the PIPE*STAT regs before the IIR */
4063                         if (pipe_stats[pipe] & 0x8000ffff) {
4064                                 I915_WRITE(reg, pipe_stats[pipe]);
4065                                 irq_received = true;
4066                         }
4067                 }
4068                 spin_unlock(&dev_priv->irq_lock);
4069
4070                 if (!irq_received)
4071                         break;
4072
4073                 /* Consume port.  Then clear IIR or we'll miss events */
4074                 if (I915_HAS_HOTPLUG(dev) &&
4075                     iir & I915_DISPLAY_PORT_INTERRUPT)
4076                         i9xx_hpd_irq_handler(dev);
4077
4078                 I915_WRITE(IIR, iir & ~flip_mask);
4079                 new_iir = I915_READ(IIR); /* Flush posted writes */
4080
4081                 if (iir & I915_USER_INTERRUPT)
4082                         notify_ring(&dev_priv->ring[RCS]);
4083
4084                 for_each_pipe(dev_priv, pipe) {
4085                         int plane = pipe;
4086                         if (HAS_FBC(dev))
4087                                 plane = !plane;
4088
4089                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4090                             i915_handle_vblank(dev, plane, pipe, iir))
4091                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4092
4093                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4094                                 blc_event = true;
4095
4096                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4097                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4098
4099                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4100                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4101                                                                     pipe);
4102                 }
4103
4104                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4105                         intel_opregion_asle_intr(dev);
4106
4107                 /* With MSI, interrupts are only generated when iir
4108                  * transitions from zero to nonzero.  If another bit got
4109                  * set while we were handling the existing iir bits, then
4110                  * we would never get another interrupt.
4111                  *
4112                  * This is fine on non-MSI as well, as if we hit this path
4113                  * we avoid exiting the interrupt handler only to generate
4114                  * another one.
4115                  *
4116                  * Note that for MSI this could cause a stray interrupt report
4117                  * if an interrupt landed in the time between writing IIR and
4118                  * the posting read.  This should be rare enough to never
4119                  * trigger the 99% of 100,000 interrupts test for disabling
4120                  * stray interrupts.
4121                  */
4122                 ret = IRQ_HANDLED;
4123                 iir = new_iir;
4124         } while (iir & ~flip_mask);
4125
4126         return ret;
4127 }
4128
4129 static void i915_irq_uninstall(struct drm_device * dev)
4130 {
4131         struct drm_i915_private *dev_priv = dev->dev_private;
4132         int pipe;
4133
4134         if (I915_HAS_HOTPLUG(dev)) {
4135                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4136                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4137         }
4138
4139         I915_WRITE16(HWSTAM, 0xffff);
4140         for_each_pipe(dev_priv, pipe) {
4141                 /* Clear enable bits; then clear status bits */
4142                 I915_WRITE(PIPESTAT(pipe), 0);
4143                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4144         }
4145         I915_WRITE(IMR, 0xffffffff);
4146         I915_WRITE(IER, 0x0);
4147
4148         I915_WRITE(IIR, I915_READ(IIR));
4149 }
4150
4151 static void i965_irq_preinstall(struct drm_device * dev)
4152 {
4153         struct drm_i915_private *dev_priv = dev->dev_private;
4154         int pipe;
4155
4156         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4157         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4158
4159         I915_WRITE(HWSTAM, 0xeffe);
4160         for_each_pipe(dev_priv, pipe)
4161                 I915_WRITE(PIPESTAT(pipe), 0);
4162         I915_WRITE(IMR, 0xffffffff);
4163         I915_WRITE(IER, 0x0);
4164         POSTING_READ(IER);
4165 }
4166
4167 static int i965_irq_postinstall(struct drm_device *dev)
4168 {
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         u32 enable_mask;
4171         u32 error_mask;
4172
4173         /* Unmask the interrupts that we always want on. */
4174         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4175                                I915_DISPLAY_PORT_INTERRUPT |
4176                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4177                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4178                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4179                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4180                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4181
4182         enable_mask = ~dev_priv->irq_mask;
4183         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4184                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4185         enable_mask |= I915_USER_INTERRUPT;
4186
4187         if (IS_G4X(dev))
4188                 enable_mask |= I915_BSD_USER_INTERRUPT;
4189
4190         /* Interrupt setup is already guaranteed to be single-threaded, this is
4191          * just to make the assert_spin_locked check happy. */
4192         spin_lock_irq(&dev_priv->irq_lock);
4193         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4194         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4195         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4196         spin_unlock_irq(&dev_priv->irq_lock);
4197
4198         /*
4199          * Enable some error detection, note the instruction error mask
4200          * bit is reserved, so we leave it masked.
4201          */
4202         if (IS_G4X(dev)) {
4203                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4204                                GM45_ERROR_MEM_PRIV |
4205                                GM45_ERROR_CP_PRIV |
4206                                I915_ERROR_MEMORY_REFRESH);
4207         } else {
4208                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4209                                I915_ERROR_MEMORY_REFRESH);
4210         }
4211         I915_WRITE(EMR, error_mask);
4212
4213         I915_WRITE(IMR, dev_priv->irq_mask);
4214         I915_WRITE(IER, enable_mask);
4215         POSTING_READ(IER);
4216
4217         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4218         POSTING_READ(PORT_HOTPLUG_EN);
4219
4220         i915_enable_asle_pipestat(dev);
4221
4222         return 0;
4223 }
4224
4225 static void i915_hpd_irq_setup(struct drm_device *dev)
4226 {
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         u32 hotplug_en;
4229
4230         assert_spin_locked(&dev_priv->irq_lock);
4231
4232         /* Note HDMI and DP share hotplug bits */
4233         /* enable bits are the same for all generations */
4234         hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4235         /* Programming the CRT detection parameters tends
4236            to generate a spurious hotplug event about three
4237            seconds later.  So just do it once.
4238         */
4239         if (IS_G4X(dev))
4240                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4241         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4242
4243         /* Ignore TV since it's buggy */
4244         i915_hotplug_interrupt_update_locked(dev_priv,
4245                                              HOTPLUG_INT_EN_MASK |
4246                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4247                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4248                                              hotplug_en);
4249 }
4250
4251 static irqreturn_t i965_irq_handler(int irq, void *arg)
4252 {
4253         struct drm_device *dev = arg;
4254         struct drm_i915_private *dev_priv = dev->dev_private;
4255         u32 iir, new_iir;
4256         u32 pipe_stats[I915_MAX_PIPES];
4257         int ret = IRQ_NONE, pipe;
4258         u32 flip_mask =
4259                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4260                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4261
4262         if (!intel_irqs_enabled(dev_priv))
4263                 return IRQ_NONE;
4264
4265         iir = I915_READ(IIR);
4266
4267         for (;;) {
4268                 bool irq_received = (iir & ~flip_mask) != 0;
4269                 bool blc_event = false;
4270
4271                 /* Can't rely on pipestat interrupt bit in iir as it might
4272                  * have been cleared after the pipestat interrupt was received.
4273                  * It doesn't set the bit in iir again, but it still produces
4274                  * interrupts (for non-MSI).
4275                  */
4276                 spin_lock(&dev_priv->irq_lock);
4277                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4278                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4279
4280                 for_each_pipe(dev_priv, pipe) {
4281                         int reg = PIPESTAT(pipe);
4282                         pipe_stats[pipe] = I915_READ(reg);
4283
4284                         /*
4285                          * Clear the PIPE*STAT regs before the IIR
4286                          */
4287                         if (pipe_stats[pipe] & 0x8000ffff) {
4288                                 I915_WRITE(reg, pipe_stats[pipe]);
4289                                 irq_received = true;
4290                         }
4291                 }
4292                 spin_unlock(&dev_priv->irq_lock);
4293
4294                 if (!irq_received)
4295                         break;
4296
4297                 ret = IRQ_HANDLED;
4298
4299                 /* Consume port.  Then clear IIR or we'll miss events */
4300                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4301                         i9xx_hpd_irq_handler(dev);
4302
4303                 I915_WRITE(IIR, iir & ~flip_mask);
4304                 new_iir = I915_READ(IIR); /* Flush posted writes */
4305
4306                 if (iir & I915_USER_INTERRUPT)
4307                         notify_ring(&dev_priv->ring[RCS]);
4308                 if (iir & I915_BSD_USER_INTERRUPT)
4309                         notify_ring(&dev_priv->ring[VCS]);
4310
4311                 for_each_pipe(dev_priv, pipe) {
4312                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4313                             i915_handle_vblank(dev, pipe, pipe, iir))
4314                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4315
4316                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4317                                 blc_event = true;
4318
4319                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4320                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4321
4322                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4323                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4324                 }
4325
4326                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4327                         intel_opregion_asle_intr(dev);
4328
4329                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4330                         gmbus_irq_handler(dev);
4331
4332                 /* With MSI, interrupts are only generated when iir
4333                  * transitions from zero to nonzero.  If another bit got
4334                  * set while we were handling the existing iir bits, then
4335                  * we would never get another interrupt.
4336                  *
4337                  * This is fine on non-MSI as well, as if we hit this path
4338                  * we avoid exiting the interrupt handler only to generate
4339                  * another one.
4340                  *
4341                  * Note that for MSI this could cause a stray interrupt report
4342                  * if an interrupt landed in the time between writing IIR and
4343                  * the posting read.  This should be rare enough to never
4344                  * trigger the 99% of 100,000 interrupts test for disabling
4345                  * stray interrupts.
4346                  */
4347                 iir = new_iir;
4348         }
4349
4350         return ret;
4351 }
4352
4353 static void i965_irq_uninstall(struct drm_device * dev)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         int pipe;
4357
4358         if (!dev_priv)
4359                 return;
4360
4361         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4362         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4363
4364         I915_WRITE(HWSTAM, 0xffffffff);
4365         for_each_pipe(dev_priv, pipe)
4366                 I915_WRITE(PIPESTAT(pipe), 0);
4367         I915_WRITE(IMR, 0xffffffff);
4368         I915_WRITE(IER, 0x0);
4369
4370         for_each_pipe(dev_priv, pipe)
4371                 I915_WRITE(PIPESTAT(pipe),
4372                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4373         I915_WRITE(IIR, I915_READ(IIR));
4374 }
4375
4376 /**
4377  * intel_irq_init - initializes irq support
4378  * @dev_priv: i915 device instance
4379  *
4380  * This function initializes all the irq support including work items, timers
4381  * and all the vtables. It does not setup the interrupt itself though.
4382  */
4383 void intel_irq_init(struct drm_i915_private *dev_priv)
4384 {
4385         struct drm_device *dev = dev_priv->dev;
4386
4387         intel_hpd_init_work(dev_priv);
4388
4389         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4390         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4391
4392         /* Let's track the enabled rps events */
4393         if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4394                 /* WaGsvRC0ResidencyMethod:vlv */
4395                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4396         else
4397                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4398
4399         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4400                           i915_hangcheck_elapsed);
4401
4402         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4403
4404         if (IS_GEN2(dev_priv)) {
4405                 dev->max_vblank_count = 0;
4406                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4407         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4408                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4409                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4410         } else {
4411                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4412                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4413         }
4414
4415         /*
4416          * Opt out of the vblank disable timer on everything except gen2.
4417          * Gen2 doesn't have a hardware frame counter and so depends on
4418          * vblank interrupts to produce sane vblank seuquence numbers.
4419          */
4420         if (!IS_GEN2(dev_priv))
4421                 dev->vblank_disable_immediate = true;
4422
4423         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4424         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4425
4426         if (IS_CHERRYVIEW(dev_priv)) {
4427                 dev->driver->irq_handler = cherryview_irq_handler;
4428                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4429                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4430                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4431                 dev->driver->enable_vblank = valleyview_enable_vblank;
4432                 dev->driver->disable_vblank = valleyview_disable_vblank;
4433                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4434         } else if (IS_VALLEYVIEW(dev_priv)) {
4435                 dev->driver->irq_handler = valleyview_irq_handler;
4436                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4437                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4438                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4439                 dev->driver->enable_vblank = valleyview_enable_vblank;
4440                 dev->driver->disable_vblank = valleyview_disable_vblank;
4441                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4442         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4443                 dev->driver->irq_handler = gen8_irq_handler;
4444                 dev->driver->irq_preinstall = gen8_irq_reset;
4445                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4446                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4447                 dev->driver->enable_vblank = gen8_enable_vblank;
4448                 dev->driver->disable_vblank = gen8_disable_vblank;
4449                 if (IS_BROXTON(dev))
4450                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4451                 else if (HAS_PCH_SPT(dev))
4452                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4453                 else
4454                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4455         } else if (HAS_PCH_SPLIT(dev)) {
4456                 dev->driver->irq_handler = ironlake_irq_handler;
4457                 dev->driver->irq_preinstall = ironlake_irq_reset;
4458                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4459                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4460                 dev->driver->enable_vblank = ironlake_enable_vblank;
4461                 dev->driver->disable_vblank = ironlake_disable_vblank;
4462                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4463         } else {
4464                 if (INTEL_INFO(dev_priv)->gen == 2) {
4465                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4466                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4467                         dev->driver->irq_handler = i8xx_irq_handler;
4468                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4469                 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4470                         dev->driver->irq_preinstall = i915_irq_preinstall;
4471                         dev->driver->irq_postinstall = i915_irq_postinstall;
4472                         dev->driver->irq_uninstall = i915_irq_uninstall;
4473                         dev->driver->irq_handler = i915_irq_handler;
4474                 } else {
4475                         dev->driver->irq_preinstall = i965_irq_preinstall;
4476                         dev->driver->irq_postinstall = i965_irq_postinstall;
4477                         dev->driver->irq_uninstall = i965_irq_uninstall;
4478                         dev->driver->irq_handler = i965_irq_handler;
4479                 }
4480                 if (I915_HAS_HOTPLUG(dev_priv))
4481                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4482                 dev->driver->enable_vblank = i915_enable_vblank;
4483                 dev->driver->disable_vblank = i915_disable_vblank;
4484         }
4485 }
4486
4487 /**
4488  * intel_irq_install - enables the hardware interrupt
4489  * @dev_priv: i915 device instance
4490  *
4491  * This function enables the hardware interrupt handling, but leaves the hotplug
4492  * handling still disabled. It is called after intel_irq_init().
4493  *
4494  * In the driver load and resume code we need working interrupts in a few places
4495  * but don't want to deal with the hassle of concurrent probe and hotplug
4496  * workers. Hence the split into this two-stage approach.
4497  */
4498 int intel_irq_install(struct drm_i915_private *dev_priv)
4499 {
4500         /*
4501          * We enable some interrupt sources in our postinstall hooks, so mark
4502          * interrupts as enabled _before_ actually enabling them to avoid
4503          * special cases in our ordering checks.
4504          */
4505         dev_priv->pm.irqs_enabled = true;
4506
4507         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4508 }
4509
4510 /**
4511  * intel_irq_uninstall - finilizes all irq handling
4512  * @dev_priv: i915 device instance
4513  *
4514  * This stops interrupt and hotplug handling and unregisters and frees all
4515  * resources acquired in the init functions.
4516  */
4517 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4518 {
4519         drm_irq_uninstall(dev_priv->dev);
4520         intel_hpd_cancel_work(dev_priv);
4521         dev_priv->pm.irqs_enabled = false;
4522 }
4523
4524 /**
4525  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4526  * @dev_priv: i915 device instance
4527  *
4528  * This function is used to disable interrupts at runtime, both in the runtime
4529  * pm and the system suspend/resume code.
4530  */
4531 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4532 {
4533         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4534         dev_priv->pm.irqs_enabled = false;
4535         synchronize_irq(dev_priv->dev->irq);
4536 }
4537
4538 /**
4539  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4540  * @dev_priv: i915 device instance
4541  *
4542  * This function is used to enable interrupts at runtime, both in the runtime
4543  * pm and the system suspend/resume code.
4544  */
4545 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4546 {
4547         dev_priv->pm.irqs_enabled = true;
4548         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4549         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4550 }