2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device *dev)
103 return GEN6_CONTEXT_ALIGN;
105 return GEN7_CONTEXT_ALIGN;
108 static int get_context_size(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
114 switch (INTEL_INFO(dev)->gen) {
116 reg = I915_READ(CXT_SIZE);
117 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
120 reg = I915_READ(GEN7_CXT_SIZE);
122 ret = HSW_CXT_TOTAL_SIZE;
124 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
127 ret = GEN8_CXT_TOTAL_SIZE;
136 static void i915_gem_context_clean(struct intel_context *ctx)
138 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
139 struct i915_vma *vma, *next;
144 list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
146 if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
151 void i915_gem_context_free(struct kref *ctx_ref)
153 struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
155 trace_i915_context_free(ctx);
157 if (i915.enable_execlists)
158 intel_lr_context_free(ctx);
161 * This context is going away and we need to remove all VMAs still
162 * around. This is to handle imported shared objects for which
163 * destructor did not run when their handles were closed.
165 i915_gem_context_clean(ctx);
167 i915_ppgtt_put(ctx->ppgtt);
169 if (ctx->legacy_hw_ctx.rcs_state)
170 drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
171 list_del(&ctx->link);
175 struct drm_i915_gem_object *
176 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
178 struct drm_i915_gem_object *obj;
181 obj = i915_gem_alloc_object(dev, size);
183 return ERR_PTR(-ENOMEM);
186 * Try to make the context utilize L3 as well as LLC.
188 * On VLV we don't have L3 controls in the PTEs so we
189 * shouldn't touch the cache level, especially as that
190 * would make the object snooped which might have a
191 * negative performance impact.
193 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
194 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
195 /* Failure shouldn't ever happen this early */
197 drm_gem_object_unreference(&obj->base);
205 static struct intel_context *
206 __create_hw_context(struct drm_device *dev,
207 struct drm_i915_file_private *file_priv)
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 struct intel_context *ctx;
213 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
215 return ERR_PTR(-ENOMEM);
217 kref_init(&ctx->ref);
218 list_add_tail(&ctx->link, &dev_priv->context_list);
219 ctx->i915 = dev_priv;
221 if (dev_priv->hw_context_size) {
222 struct drm_i915_gem_object *obj =
223 i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
228 ctx->legacy_hw_ctx.rcs_state = obj;
231 /* Default context will never have a file_priv */
232 if (file_priv != NULL) {
233 ret = idr_alloc(&file_priv->context_idr, ctx,
234 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
238 ret = DEFAULT_CONTEXT_HANDLE;
240 ctx->file_priv = file_priv;
241 ctx->user_handle = ret;
242 /* NB: Mark all slices as needing a remap so that when the context first
243 * loads it will restore whatever remap state already exists. If there
244 * is no remap info, it will be a NOP. */
245 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
247 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
252 i915_gem_context_unreference(ctx);
257 * The default context needs to exist per ring that uses contexts. It stores the
258 * context state of the GPU for applications that don't utilize HW contexts, as
259 * well as an idle case.
261 static struct intel_context *
262 i915_gem_create_context(struct drm_device *dev,
263 struct drm_i915_file_private *file_priv)
265 const bool is_global_default_ctx = file_priv == NULL;
266 struct intel_context *ctx;
269 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
271 ctx = __create_hw_context(dev, file_priv);
275 if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
276 /* We may need to do things with the shrinker which
277 * require us to immediately switch back to the default
278 * context. This can cause a problem as pinning the
279 * default context also requires GTT space which may not
280 * be available. To avoid this we always pin the default
283 ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
284 get_context_alignment(dev), 0);
286 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
291 if (USES_FULL_PPGTT(dev)) {
292 struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
294 if (IS_ERR_OR_NULL(ppgtt)) {
295 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
297 ret = PTR_ERR(ppgtt);
304 trace_i915_context_create(ctx);
309 if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
310 i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
312 idr_remove(&file_priv->context_idr, ctx->user_handle);
313 i915_gem_context_unreference(ctx);
317 void i915_gem_context_reset(struct drm_device *dev)
319 struct drm_i915_private *dev_priv = dev->dev_private;
322 if (i915.enable_execlists) {
323 struct intel_context *ctx;
325 list_for_each_entry(ctx, &dev_priv->context_list, link) {
326 intel_lr_context_reset(dev, ctx);
332 for (i = 0; i < I915_NUM_RINGS; i++) {
333 struct intel_engine_cs *ring = &dev_priv->ring[i];
334 struct intel_context *lctx = ring->last_context;
337 if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
338 i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
340 i915_gem_context_unreference(lctx);
341 ring->last_context = NULL;
344 /* Force the GPU state to be reinitialised on enabling */
345 if (ring->default_context)
346 ring->default_context->legacy_hw_ctx.initialized = false;
350 int i915_gem_context_init(struct drm_device *dev)
352 struct drm_i915_private *dev_priv = dev->dev_private;
353 struct intel_context *ctx;
356 /* Init should only be called once per module load. Eventually the
357 * restriction on the context_disabled check can be loosened. */
358 if (WARN_ON(dev_priv->ring[RCS].default_context))
361 if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
362 if (!i915.enable_execlists) {
363 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
368 if (i915.enable_execlists) {
369 /* NB: intentionally left blank. We will allocate our own
370 * backing objects as we need them, thank you very much */
371 dev_priv->hw_context_size = 0;
372 } else if (HAS_HW_CONTEXTS(dev)) {
373 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
374 if (dev_priv->hw_context_size > (1<<20)) {
375 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
376 dev_priv->hw_context_size);
377 dev_priv->hw_context_size = 0;
381 ctx = i915_gem_create_context(dev, NULL);
383 DRM_ERROR("Failed to create default global context (error %ld)\n",
388 for (i = 0; i < I915_NUM_RINGS; i++) {
389 struct intel_engine_cs *ring = &dev_priv->ring[i];
391 /* NB: RCS will hold a ref for all rings */
392 ring->default_context = ctx;
395 DRM_DEBUG_DRIVER("%s context support initialized\n",
396 i915.enable_execlists ? "LR" :
397 dev_priv->hw_context_size ? "HW" : "fake");
401 void i915_gem_context_fini(struct drm_device *dev)
403 struct drm_i915_private *dev_priv = dev->dev_private;
404 struct intel_context *dctx = dev_priv->ring[RCS].default_context;
407 if (dctx->legacy_hw_ctx.rcs_state) {
408 /* The only known way to stop the gpu from accessing the hw context is
409 * to reset it. Do this as the very last operation to avoid confusing
410 * other code, leading to spurious errors. */
411 intel_gpu_reset(dev);
413 /* When default context is created and switched to, base object refcount
414 * will be 2 (+1 from object creation and +1 from do_switch()).
415 * i915_gem_context_fini() will be called after gpu_idle() has switched
416 * to default context. So we need to unreference the base object once
417 * to offset the do_switch part, so that i915_gem_context_unreference()
418 * can then free the base object correctly. */
419 WARN_ON(!dev_priv->ring[RCS].last_context);
420 if (dev_priv->ring[RCS].last_context == dctx) {
421 /* Fake switch to NULL context */
422 WARN_ON(dctx->legacy_hw_ctx.rcs_state->active);
423 i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
424 i915_gem_context_unreference(dctx);
425 dev_priv->ring[RCS].last_context = NULL;
428 i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
431 for (i = 0; i < I915_NUM_RINGS; i++) {
432 struct intel_engine_cs *ring = &dev_priv->ring[i];
434 if (ring->last_context)
435 i915_gem_context_unreference(ring->last_context);
437 ring->default_context = NULL;
438 ring->last_context = NULL;
441 i915_gem_context_unreference(dctx);
444 int i915_gem_context_enable(struct drm_i915_gem_request *req)
446 struct intel_engine_cs *ring = req->ring;
449 if (i915.enable_execlists) {
450 if (ring->init_context == NULL)
453 ret = ring->init_context(req);
455 ret = i915_switch_context(req);
458 DRM_ERROR("ring init context: %d\n", ret);
465 static int context_idr_cleanup(int id, void *p, void *data)
467 struct intel_context *ctx = p;
469 i915_gem_context_unreference(ctx);
473 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
475 struct drm_i915_file_private *file_priv = file->driver_priv;
476 struct intel_context *ctx;
478 idr_init(&file_priv->context_idr);
480 mutex_lock(&dev->struct_mutex);
481 ctx = i915_gem_create_context(dev, file_priv);
482 mutex_unlock(&dev->struct_mutex);
485 idr_destroy(&file_priv->context_idr);
492 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
494 struct drm_i915_file_private *file_priv = file->driver_priv;
496 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
497 idr_destroy(&file_priv->context_idr);
500 struct intel_context *
501 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
503 struct intel_context *ctx;
505 ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
507 return ERR_PTR(-ENOENT);
513 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
515 struct intel_engine_cs *ring = req->ring;
516 u32 flags = hw_flags | MI_MM_SPACE_GTT;
517 const int num_rings =
518 /* Use an extended w/a on ivb+ if signalling from other rings */
519 i915_semaphore_is_enabled(ring->dev) ?
520 hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
524 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
525 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
526 * explicitly, so we rely on the value at ring init, stored in
527 * itlb_before_ctx_switch.
529 if (IS_GEN6(ring->dev)) {
530 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
535 /* These flags are for resource streamer on HSW+ */
536 if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
537 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
538 else if (INTEL_INFO(ring->dev)->gen < 8)
539 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
543 if (INTEL_INFO(ring->dev)->gen >= 7)
544 len += 2 + (num_rings ? 4*num_rings + 2 : 0);
546 ret = intel_ring_begin(req, len);
550 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
551 if (INTEL_INFO(ring->dev)->gen >= 7) {
552 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
554 struct intel_engine_cs *signaller;
556 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
557 for_each_ring(signaller, to_i915(ring->dev), i) {
558 if (signaller == ring)
561 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
562 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
567 intel_ring_emit(ring, MI_NOOP);
568 intel_ring_emit(ring, MI_SET_CONTEXT);
569 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) |
572 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
573 * WaMiSetContext_Hang:snb,ivb,vlv
575 intel_ring_emit(ring, MI_NOOP);
577 if (INTEL_INFO(ring->dev)->gen >= 7) {
579 struct intel_engine_cs *signaller;
581 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
582 for_each_ring(signaller, to_i915(ring->dev), i) {
583 if (signaller == ring)
586 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
587 intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
590 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
593 intel_ring_advance(ring);
598 static inline bool should_skip_switch(struct intel_engine_cs *ring,
599 struct intel_context *from,
600 struct intel_context *to)
605 if (to->ppgtt && from == to &&
606 !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings))
613 needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to)
615 struct drm_i915_private *dev_priv = ring->dev->dev_private;
620 if (INTEL_INFO(ring->dev)->gen < 8)
623 if (ring != &dev_priv->ring[RCS])
630 needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
633 struct drm_i915_private *dev_priv = ring->dev->dev_private;
638 if (!IS_GEN8(ring->dev))
641 if (ring != &dev_priv->ring[RCS])
644 if (hw_flags & MI_RESTORE_INHIBIT)
650 static int do_switch(struct drm_i915_gem_request *req)
652 struct intel_context *to = req->ctx;
653 struct intel_engine_cs *ring = req->ring;
654 struct drm_i915_private *dev_priv = ring->dev->dev_private;
655 struct intel_context *from = ring->last_context;
657 bool uninitialized = false;
660 if (from != NULL && ring == &dev_priv->ring[RCS]) {
661 BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
662 BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
665 if (should_skip_switch(ring, from, to))
668 /* Trying to pin first makes error handling easier. */
669 if (ring == &dev_priv->ring[RCS]) {
670 ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
671 get_context_alignment(ring->dev), 0);
677 * Pin can switch back to the default context if we end up calling into
678 * evict_everything - as a last ditch gtt defrag effort that also
679 * switches to the default context. Hence we need to reload from here.
681 from = ring->last_context;
683 if (needs_pd_load_pre(ring, to)) {
684 /* Older GENs and non render rings still want the load first,
685 * "PP_DCLV followed by PP_DIR_BASE register through Load
686 * Register Immediate commands in Ring Buffer before submitting
688 trace_switch_mm(ring, to);
689 ret = to->ppgtt->switch_mm(to->ppgtt, req);
693 /* Doing a PD load always reloads the page dirs */
694 to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
697 if (ring != &dev_priv->ring[RCS]) {
699 i915_gem_context_unreference(from);
704 * Clear this page out of any CPU caches for coherent swap-in/out. Note
705 * that thanks to write = false in this call and us not setting any gpu
706 * write domains when putting a context object onto the active list
707 * (when switching away from it), this won't block.
709 * XXX: We need a real interface to do this instead of trickery.
711 ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
715 if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
716 hw_flags |= MI_RESTORE_INHIBIT;
717 /* NB: If we inhibit the restore, the context is not allowed to
718 * die because future work may end up depending on valid address
719 * space. This means we must enforce that a page table load
720 * occur when this occurs. */
721 } else if (to->ppgtt &&
722 (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
723 hw_flags |= MI_FORCE_RESTORE;
724 to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
727 /* We should never emit switch_mm more than once */
728 WARN_ON(needs_pd_load_pre(ring, to) &&
729 needs_pd_load_post(ring, to, hw_flags));
731 ret = mi_set_context(req, hw_flags);
735 /* GEN8 does *not* require an explicit reload if the PDPs have been
736 * setup, and we do not wish to move them.
738 if (needs_pd_load_post(ring, to, hw_flags)) {
739 trace_switch_mm(ring, to);
740 ret = to->ppgtt->switch_mm(to->ppgtt, req);
741 /* The hardware context switch is emitted, but we haven't
742 * actually changed the state - so it's probably safe to bail
743 * here. Still, let the user know something dangerous has
747 DRM_ERROR("Failed to change address space on context switch\n");
752 for (i = 0; i < MAX_L3_SLICES; i++) {
753 if (!(to->remap_slice & (1<<i)))
756 ret = i915_gem_l3_remap(req, i);
757 /* If it failed, try again next round */
759 DRM_DEBUG_DRIVER("L3 remapping failed\n");
761 to->remap_slice &= ~(1<<i);
764 /* The backing object for the context is done after switching to the
765 * *next* context. Therefore we cannot retire the previous context until
766 * the next context has already started running. In fact, the below code
767 * is a bit suboptimal because the retiring can occur simply after the
768 * MI_SET_CONTEXT instead of when the next seqno has completed.
771 from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
772 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
773 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
774 * whole damn pipeline, we don't need to explicitly mark the
775 * object dirty. The only exception is that the context must be
776 * correct in case the object gets swapped out. Ideally we'd be
777 * able to defer doing this until we know the object would be
778 * swapped, but there is no way to do that yet.
780 from->legacy_hw_ctx.rcs_state->dirty = 1;
782 /* obj is kept alive until the next request by its active ref */
783 i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
784 i915_gem_context_unreference(from);
787 uninitialized = !to->legacy_hw_ctx.initialized;
788 to->legacy_hw_ctx.initialized = true;
791 i915_gem_context_reference(to);
792 ring->last_context = to;
795 if (ring->init_context) {
796 ret = ring->init_context(req);
798 DRM_ERROR("ring init context: %d\n", ret);
806 i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
811 * i915_switch_context() - perform a GPU context switch.
812 * @req: request for which we'll execute the context switch
814 * The context life cycle is simple. The context refcount is incremented and
815 * decremented by 1 and create and destroy. If the context is in use by the GPU,
816 * it will have a refcount > 1. This allows us to destroy the context abstract
817 * object while letting the normal object tracking destroy the backing BO.
819 * This function should not be used in execlists mode. Instead the context is
820 * switched by writing to the ELSP and requests keep a reference to their
823 int i915_switch_context(struct drm_i915_gem_request *req)
825 struct intel_engine_cs *ring = req->ring;
826 struct drm_i915_private *dev_priv = ring->dev->dev_private;
828 WARN_ON(i915.enable_execlists);
829 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
831 if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
832 if (req->ctx != ring->last_context) {
833 i915_gem_context_reference(req->ctx);
834 if (ring->last_context)
835 i915_gem_context_unreference(ring->last_context);
836 ring->last_context = req->ctx;
841 return do_switch(req);
844 static bool contexts_enabled(struct drm_device *dev)
846 return i915.enable_execlists || to_i915(dev)->hw_context_size;
849 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
850 struct drm_file *file)
852 struct drm_i915_gem_context_create *args = data;
853 struct drm_i915_file_private *file_priv = file->driver_priv;
854 struct intel_context *ctx;
857 if (!contexts_enabled(dev))
860 ret = i915_mutex_lock_interruptible(dev);
864 ctx = i915_gem_create_context(dev, file_priv);
865 mutex_unlock(&dev->struct_mutex);
869 args->ctx_id = ctx->user_handle;
870 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
875 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file)
878 struct drm_i915_gem_context_destroy *args = data;
879 struct drm_i915_file_private *file_priv = file->driver_priv;
880 struct intel_context *ctx;
883 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
886 ret = i915_mutex_lock_interruptible(dev);
890 ctx = i915_gem_context_get(file_priv, args->ctx_id);
892 mutex_unlock(&dev->struct_mutex);
896 idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
897 i915_gem_context_unreference(ctx);
898 mutex_unlock(&dev->struct_mutex);
900 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
904 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
905 struct drm_file *file)
907 struct drm_i915_file_private *file_priv = file->driver_priv;
908 struct drm_i915_gem_context_param *args = data;
909 struct intel_context *ctx;
912 ret = i915_mutex_lock_interruptible(dev);
916 ctx = i915_gem_context_get(file_priv, args->ctx_id);
918 mutex_unlock(&dev->struct_mutex);
923 switch (args->param) {
924 case I915_CONTEXT_PARAM_BAN_PERIOD:
925 args->value = ctx->hang_stats.ban_period_seconds;
927 case I915_CONTEXT_PARAM_NO_ZEROMAP:
928 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
934 mutex_unlock(&dev->struct_mutex);
939 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
940 struct drm_file *file)
942 struct drm_i915_file_private *file_priv = file->driver_priv;
943 struct drm_i915_gem_context_param *args = data;
944 struct intel_context *ctx;
947 ret = i915_mutex_lock_interruptible(dev);
951 ctx = i915_gem_context_get(file_priv, args->ctx_id);
953 mutex_unlock(&dev->struct_mutex);
957 switch (args->param) {
958 case I915_CONTEXT_PARAM_BAN_PERIOD:
961 else if (args->value < ctx->hang_stats.ban_period_seconds &&
962 !capable(CAP_SYS_ADMIN))
965 ctx->hang_stats.ban_period_seconds = args->value;
967 case I915_CONTEXT_PARAM_NO_ZEROMAP:
971 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
972 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
979 mutex_unlock(&dev->struct_mutex);