kernel/drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fbdev.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35 #include "exynos_drm_iommu.h"
  36
  37 /*
  38  * FIMD stands for Fully Interactive Mobile Display and
  39  * as a display controller, it transfers contents drawn on memory
  40  * to a LCD Panel through Display Interfaces such as RGB or
  41  * CPU Interface.
  42  */
  43
  44 #define FIMD_DEFAULT_FRAMERATE 60
  45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  46
  47 /* position control register for hardware window 0, 2 ~ 4.*/
  48 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  49 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  50 /*
  51  * size control register for hardware windows 0 and alpha control register
  52  * for hardware windows 1 ~ 4
  53  */
  54 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  55 /* size control register for hardware windows 1 ~ 2. */
  56 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  57
  58 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  59 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  60
  61 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  62 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  63 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  64
  65 /* color key control register for hardware window 1 ~ 4. */
  66 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  67 /* color key value register for hardware window 1 ~ 4. */
  68 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  69
  70 /* I80 / RGB trigger control register */
  71 #define TRIGCON                         0x1A4
  72 #define TRGMODE_I80_RGB_ENABLE_I80      (1 << 0)
  73 #define SWTRGCMD_I80_RGB_ENABLE         (1 << 1)
  74
  75 /* display mode change control register except exynos4 */
  76 #define VIDOUT_CON                      0x000
  77 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  78
  79 /* I80 interface control for main LDI register */
  80 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  81 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  82 #define LCD_CS_SETUP(x)                 ((x) << 16)
  83 #define LCD_WR_SETUP(x)                 ((x) << 12)
  84 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  85 #define LCD_WR_HOLD(x)                  ((x) << 4)
  86 #define I80IFEN_ENABLE                  (1 << 0)
  87
  88 /* FIMD has totally five hardware windows. */
  89 #define WINDOWS_NR      5
  90
  91 struct fimd_driver_data {
  92         unsigned int timing_base;
  93         unsigned int lcdblk_offset;
  94         unsigned int lcdblk_vt_shift;
  95         unsigned int lcdblk_bypass_shift;
  96
  97         unsigned int has_shadowcon:1;
  98         unsigned int has_clksel:1;
  99         unsigned int has_limited_fmt:1;
 100         unsigned int has_vidoutcon:1;
 101         unsigned int has_vtsel:1;
 102 };
 103
 104 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 105         .timing_base = 0x0,
 106         .has_clksel = 1,
 107         .has_limited_fmt = 1,
 108 };
 109
 110 static struct fimd_driver_data exynos3_fimd_driver_data = {
 111         .timing_base = 0x20000,
 112         .lcdblk_offset = 0x210,
 113         .lcdblk_bypass_shift = 1,
 114         .has_shadowcon = 1,
 115         .has_vidoutcon = 1,
 116 };
 117
 118 static struct fimd_driver_data exynos4_fimd_driver_data = {
 119         .timing_base = 0x0,
 120         .lcdblk_offset = 0x210,
 121         .lcdblk_vt_shift = 10,
 122         .lcdblk_bypass_shift = 1,
 123         .has_shadowcon = 1,
 124         .has_vtsel = 1,
 125 };
 126
 127 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 128         .timing_base = 0x20000,
 129         .lcdblk_offset = 0x210,
 130         .lcdblk_vt_shift = 10,
 131         .lcdblk_bypass_shift = 1,
 132         .has_shadowcon = 1,
 133         .has_vidoutcon = 1,
 134         .has_vtsel = 1,
 135 };
 136
 137 static struct fimd_driver_data exynos5_fimd_driver_data = {
 138         .timing_base = 0x20000,
 139         .lcdblk_offset = 0x214,
 140         .lcdblk_vt_shift = 24,
 141         .lcdblk_bypass_shift = 15,
 142         .has_shadowcon = 1,
 143         .has_vidoutcon = 1,
 144         .has_vtsel = 1,
 145 };
 146
 147 struct fimd_context {
 148         struct device                   *dev;
 149         struct drm_device               *drm_dev;
 150         struct exynos_drm_crtc          *crtc;
 151         struct exynos_drm_plane         planes[WINDOWS_NR];
 152         struct clk                      *bus_clk;
 153         struct clk                      *lcd_clk;
 154         void __iomem                    *regs;
 155         struct regmap                   *sysreg;
 156         unsigned int                    default_win;
 157         unsigned long                   irq_flags;
 158         u32                             vidcon0;
 159         u32                             vidcon1;
 160         u32                             vidout_con;
 161         u32                             i80ifcon;
 162         bool                            i80_if;
 163         bool                            suspended;
 164         int                             pipe;
 165         wait_queue_head_t               wait_vsync_queue;
 166         atomic_t                        wait_vsync_event;
 167         atomic_t                        win_updated;
 168         atomic_t                        triggering;
 169
 170         struct exynos_drm_panel_info panel;
 171         struct fimd_driver_data *driver_data;
 172         struct exynos_drm_display *display;
 173 };
 174
 175 static const struct of_device_id fimd_driver_dt_match[] = {
 176         { .compatible = "samsung,s3c6400-fimd",
 177           .data = &s3c64xx_fimd_driver_data },
 178         { .compatible = "samsung,exynos3250-fimd",
 179           .data = &exynos3_fimd_driver_data },
 180         { .compatible = "samsung,exynos4210-fimd",
 181           .data = &exynos4_fimd_driver_data },
 182         { .compatible = "samsung,exynos4415-fimd",
 183           .data = &exynos4415_fimd_driver_data },
 184         { .compatible = "samsung,exynos5250-fimd",
 185           .data = &exynos5_fimd_driver_data },
 186         {},
 187 };
 188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 189
 190 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 191         struct platform_device *pdev)
 192 {
 193         const struct of_device_id *of_id =
 194                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 195
 196         return (struct fimd_driver_data *)of_id->data;
 197 }
 198
 199 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 200 {
 201         struct fimd_context *ctx = crtc->ctx;
 202
 203         if (ctx->suspended)
 204                 return;
 205
 206         atomic_set(&ctx->wait_vsync_event, 1);
 207
 208         /*
 209          * wait for FIMD to signal VSYNC interrupt or return after
 210          * timeout which is set to 50ms (refresh rate of 20).
 211          */
 212         if (!wait_event_timeout(ctx->wait_vsync_queue,
 213                                 !atomic_read(&ctx->wait_vsync_event),
 214                                 HZ/20))
 215                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 216 }
 217
 218 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 219                                         bool enable)
 220 {
 221         u32 val = readl(ctx->regs + WINCON(win));
 222
 223         if (enable)
 224                 val |= WINCONx_ENWIN;
 225         else
 226                 val &= ~WINCONx_ENWIN;
 227
 228         writel(val, ctx->regs + WINCON(win));
 229 }
 230
 231 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 232                                                 unsigned int win,
 233                                                 bool enable)
 234 {
 235         u32 val = readl(ctx->regs + SHADOWCON);
 236
 237         if (enable)
 238                 val |= SHADOWCON_CHx_ENABLE(win);
 239         else
 240                 val &= ~SHADOWCON_CHx_ENABLE(win);
 241
 242         writel(val, ctx->regs + SHADOWCON);
 243 }
 244
 245 static void fimd_clear_channel(struct fimd_context *ctx)
 246 {
 247         unsigned int win, ch_enabled = 0;
 248
 249         DRM_DEBUG_KMS("%s\n", __FILE__);
 250
 251         /* Check if any channel is enabled. */
 252         for (win = 0; win < WINDOWS_NR; win++) {
 253                 u32 val = readl(ctx->regs + WINCON(win));
 254
 255                 if (val & WINCONx_ENWIN) {
 256                         fimd_enable_video_output(ctx, win, false);
 257
 258                         if (ctx->driver_data->has_shadowcon)
 259                                 fimd_enable_shadow_channel_path(ctx, win,
 260                                                                 false);
 261
 262                         ch_enabled = 1;
 263                 }
 264         }
 265
 266         /* Wait for vsync, as disable channel takes effect at next vsync */
 267         if (ch_enabled) {
 268                 unsigned int state = ctx->suspended;
 269
 270                 ctx->suspended = 0;
 271                 fimd_wait_for_vblank(ctx->crtc);
 272                 ctx->suspended = state;
 273         }
 274 }
 275
 276 static int fimd_iommu_attach_devices(struct fimd_context *ctx,
 277                         struct drm_device *drm_dev)
 278 {
 279
 280         /* attach this sub driver to iommu mapping if supported. */
 281         if (is_drm_iommu_supported(ctx->drm_dev)) {
 282                 int ret;
 283
 284                 /*
 285                  * If any channel is already active, iommu will throw
 286                  * a PAGE FAULT when enabled. So clear any channel if enabled.
 287                  */
 288                 fimd_clear_channel(ctx);
 289                 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
 290                 if (ret) {
 291                         DRM_ERROR("drm_iommu_attach failed.\n");
 292                         return ret;
 293                 }
 294
 295         }
 296
 297         return 0;
 298 }
 299
 300 static void fimd_iommu_detach_devices(struct fimd_context *ctx)
 301 {
 302         /* detach this sub driver from iommu mapping if supported. */
 303         if (is_drm_iommu_supported(ctx->drm_dev))
 304                 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 305 }
 306
 307 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 308                 const struct drm_display_mode *mode)
 309 {
 310         unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
 311         u32 clkdiv;
 312
 313         if (ctx->i80_if) {
 314                 /*
 315                  * The frame done interrupt should be occurred prior to the
 316                  * next TE signal.
 317                  */
 318                 ideal_clk *= 2;
 319         }
 320
 321         /* Find the clock divider value that gets us closest to ideal_clk */
 322         clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
 323
 324         return (clkdiv < 0x100) ? clkdiv : 0xff;
 325 }
 326
 327 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
 328                 const struct drm_display_mode *mode,
 329                 struct drm_display_mode *adjusted_mode)
 330 {
 331         if (adjusted_mode->vrefresh == 0)
 332                 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
 333
 334         return true;
 335 }
 336
 337 static void fimd_commit(struct exynos_drm_crtc *crtc)
 338 {
 339         struct fimd_context *ctx = crtc->ctx;
 340         struct drm_display_mode *mode = &crtc->base.mode;
 341         struct fimd_driver_data *driver_data = ctx->driver_data;
 342         void *timing_base = ctx->regs + driver_data->timing_base;
 343         u32 val, clkdiv;
 344
 345         if (ctx->suspended)
 346                 return;
 347
 348         /* nothing to do if we haven't set the mode yet */
 349         if (mode->htotal == 0 || mode->vtotal == 0)
 350                 return;
 351
 352         if (ctx->i80_if) {
 353                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 354                 writel(val, timing_base + I80IFCONFAx(0));
 355
 356                 /* disable auto frame rate */
 357                 writel(0, timing_base + I80IFCONFBx(0));
 358
 359                 /* set video type selection to I80 interface */
 360                 if (driver_data->has_vtsel && ctx->sysreg &&
 361                                 regmap_update_bits(ctx->sysreg,
 362                                         driver_data->lcdblk_offset,
 363                                         0x3 << driver_data->lcdblk_vt_shift,
 364                                         0x1 << driver_data->lcdblk_vt_shift)) {
 365                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 366                         return;
 367                 }
 368         } else {
 369                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 370                 u32 vidcon1;
 371
 372                 /* setup polarity values */
 373                 vidcon1 = ctx->vidcon1;
 374                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 375                         vidcon1 |= VIDCON1_INV_VSYNC;
 376                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 377                         vidcon1 |= VIDCON1_INV_HSYNC;
 378                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 379
 380                 /* setup vertical timing values. */
 381                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 382                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 383                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 384
 385                 val = VIDTCON0_VBPD(vbpd - 1) |
 386                         VIDTCON0_VFPD(vfpd - 1) |
 387                         VIDTCON0_VSPW(vsync_len - 1);
 388                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 389
 390                 /* setup horizontal timing values.  */
 391                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 392                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 393                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 394
 395                 val = VIDTCON1_HBPD(hbpd - 1) |
 396                         VIDTCON1_HFPD(hfpd - 1) |
 397                         VIDTCON1_HSPW(hsync_len - 1);
 398                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 399         }
 400
 401         if (driver_data->has_vidoutcon)
 402                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 403
 404         /* set bypass selection */
 405         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 406                                 driver_data->lcdblk_offset,
 407                                 0x1 << driver_data->lcdblk_bypass_shift,
 408                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 409                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 410                 return;
 411         }
 412
 413         /* setup horizontal and vertical display size. */
 414         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 415                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 416                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 417                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 418         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 419
 420         /*
 421          * fields of register with prefix '_F' would be updated
 422          * at vsync(same as dma start)
 423          */
 424         val = ctx->vidcon0;
 425         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 426
 427         if (ctx->driver_data->has_clksel)
 428                 val |= VIDCON0_CLKSEL_LCD;
 429
 430         clkdiv = fimd_calc_clkdiv(ctx, mode);
 431         if (clkdiv > 1)
 432                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 433
 434         writel(val, ctx->regs + VIDCON0);
 435 }
 436
 437 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 438 {
 439         struct fimd_context *ctx = crtc->ctx;
 440         u32 val;
 441
 442         if (ctx->suspended)
 443                 return -EPERM;
 444
 445         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 446                 val = readl(ctx->regs + VIDINTCON0);
 447
 448                 val |= VIDINTCON0_INT_ENABLE;
 449
 450                 if (ctx->i80_if) {
 451                         val |= VIDINTCON0_INT_I80IFDONE;
 452                         val |= VIDINTCON0_INT_SYSMAINCON;
 453                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 454                 } else {
 455                         val |= VIDINTCON0_INT_FRAME;
 456
 457                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 458                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 459                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 460                         val |= VIDINTCON0_FRAMESEL1_NONE;
 461                 }
 462
 463                 writel(val, ctx->regs + VIDINTCON0);
 464         }
 465
 466         return 0;
 467 }
 468
 469 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 470 {
 471         struct fimd_context *ctx = crtc->ctx;
 472         u32 val;
 473
 474         if (ctx->suspended)
 475                 return;
 476
 477         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 478                 val = readl(ctx->regs + VIDINTCON0);
 479
 480                 val &= ~VIDINTCON0_INT_ENABLE;
 481
 482                 if (ctx->i80_if) {
 483                         val &= ~VIDINTCON0_INT_I80IFDONE;
 484                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 485                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 486                 } else
 487                         val &= ~VIDINTCON0_INT_FRAME;
 488
 489                 writel(val, ctx->regs + VIDINTCON0);
 490         }
 491 }
 492
 493 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
 494 {
 495         struct exynos_drm_plane *plane = &ctx->planes[win];
 496         unsigned long val;
 497
 498         val = WINCONx_ENWIN;
 499
 500         /*
 501          * In case of s3c64xx, window 0 doesn't support alpha channel.
 502          * So the request format is ARGB8888 then change it to XRGB8888.
 503          */
 504         if (ctx->driver_data->has_limited_fmt && !win) {
 505                 if (plane->pixel_format == DRM_FORMAT_ARGB8888)
 506                         plane->pixel_format = DRM_FORMAT_XRGB8888;
 507         }
 508
 509         switch (plane->pixel_format) {
 510         case DRM_FORMAT_C8:
 511                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 512                 val |= WINCONx_BURSTLEN_8WORD;
 513                 val |= WINCONx_BYTSWP;
 514                 break;
 515         case DRM_FORMAT_XRGB1555:
 516                 val |= WINCON0_BPPMODE_16BPP_1555;
 517                 val |= WINCONx_HAWSWP;
 518                 val |= WINCONx_BURSTLEN_16WORD;
 519                 break;
 520         case DRM_FORMAT_RGB565:
 521                 val |= WINCON0_BPPMODE_16BPP_565;
 522                 val |= WINCONx_HAWSWP;
 523                 val |= WINCONx_BURSTLEN_16WORD;
 524                 break;
 525         case DRM_FORMAT_XRGB8888:
 526                 val |= WINCON0_BPPMODE_24BPP_888;
 527                 val |= WINCONx_WSWP;
 528                 val |= WINCONx_BURSTLEN_16WORD;
 529                 break;
 530         case DRM_FORMAT_ARGB8888:
 531                 val |= WINCON1_BPPMODE_25BPP_A1888
 532                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 533                 val |= WINCONx_WSWP;
 534                 val |= WINCONx_BURSTLEN_16WORD;
 535                 break;
 536         default:
 537                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 538
 539                 val |= WINCON0_BPPMODE_24BPP_888;
 540                 val |= WINCONx_WSWP;
 541                 val |= WINCONx_BURSTLEN_16WORD;
 542                 break;
 543         }
 544
 545         DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
 546
 547         /*
 548          * In case of exynos, setting dma-burst to 16Word causes permanent
 549          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 550          * switching which is based on plane size is not recommended as
 551          * plane size varies alot towards the end of the screen and rapid
 552          * movement causes unstable DMA which results into iommu crash/tear.
 553          */
 554
 555         if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 556                 val &= ~WINCONx_BURSTLEN_MASK;
 557                 val |= WINCONx_BURSTLEN_4WORD;
 558         }
 559
 560         writel(val, ctx->regs + WINCON(win));
 561
 562         /* hardware window 0 doesn't support alpha channel. */
 563         if (win != 0) {
 564                 /* OSD alpha */
 565                 val = VIDISD14C_ALPHA0_R(0xf) |
 566                         VIDISD14C_ALPHA0_G(0xf) |
 567                         VIDISD14C_ALPHA0_B(0xf) |
 568                         VIDISD14C_ALPHA1_R(0xf) |
 569                         VIDISD14C_ALPHA1_G(0xf) |
 570                         VIDISD14C_ALPHA1_B(0xf);
 571
 572                 writel(val, ctx->regs + VIDOSD_C(win));
 573
 574                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 575                         VIDW_ALPHA_G(0xf);
 576                 writel(val, ctx->regs + VIDWnALPHA0(win));
 577                 writel(val, ctx->regs + VIDWnALPHA1(win));
 578         }
 579 }
 580
 581 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 582 {
 583         unsigned int keycon0 = 0, keycon1 = 0;
 584
 585         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 586                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 587
 588         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 589
 590         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 591         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 592 }
 593
 594 /**
 595  * shadow_protect_win() - disable updating values from shadow registers at vsync
 596  *
 597  * @win: window to protect registers for
 598  * @protect: 1 to protect (disable updates)
 599  */
 600 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 601                                     unsigned int win, bool protect)
 602 {
 603         u32 reg, bits, val;
 604
 605         if (ctx->driver_data->has_shadowcon) {
 606                 reg = SHADOWCON;
 607                 bits = SHADOWCON_WINx_PROTECT(win);
 608         } else {
 609                 reg = PRTCON;
 610                 bits = PRTCON_PROTECT;
 611         }
 612
 613         val = readl(ctx->regs + reg);
 614         if (protect)
 615                 val |= bits;
 616         else
 617                 val &= ~bits;
 618         writel(val, ctx->regs + reg);
 619 }
 620
 621 static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
 622 {
 623         struct fimd_context *ctx = crtc->ctx;
 624         struct exynos_drm_plane *plane;
 625         dma_addr_t dma_addr;
 626         unsigned long val, size, offset;
 627         unsigned int last_x, last_y, buf_offsize, line_size;
 628
 629         if (ctx->suspended)
 630                 return;
 631
 632         if (win < 0 || win >= WINDOWS_NR)
 633                 return;
 634
 635         plane = &ctx->planes[win];
 636
 637         /* If suspended, enable this on resume */
 638         if (ctx->suspended) {
 639                 plane->resume = true;
 640                 return;
 641         }
 642
 643         /*
 644          * SHADOWCON/PRTCON register is used for enabling timing.
 645          *
 646          * for example, once only width value of a register is set,
 647          * if the dma is started then fimd hardware could malfunction so
 648          * with protect window setting, the register fields with prefix '_F'
 649          * wouldn't be updated at vsync also but updated once unprotect window
 650          * is set.
 651          */
 652
 653         /* protect windows */
 654         fimd_shadow_protect_win(ctx, win, true);
 655
 656
 657         offset = plane->src_x * (plane->bpp >> 3);
 658         offset += plane->src_y * plane->pitch;
 659
 660         /* buffer start address */
 661         dma_addr = plane->dma_addr[0] + offset;
 662         val = (unsigned long)dma_addr;
 663         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 664
 665         /* buffer end address */
 666         size = plane->pitch * plane->crtc_height;
 667         val = (unsigned long)(dma_addr + size);
 668         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 669
 670         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 671                         (unsigned long)dma_addr, val, size);
 672         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 673                         plane->crtc_width, plane->crtc_height);
 674
 675         /* buffer size */
 676         buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
 677         line_size = plane->crtc_width * (plane->bpp >> 3);
 678         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 679                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 680                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 681                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 682         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 683
 684         /* OSD position */
 685         val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
 686                 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
 687                 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
 688                 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
 689         writel(val, ctx->regs + VIDOSD_A(win));
 690
 691         last_x = plane->crtc_x + plane->crtc_width;
 692         if (last_x)
 693                 last_x--;
 694         last_y = plane->crtc_y + plane->crtc_height;
 695         if (last_y)
 696                 last_y--;
 697
 698         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 699                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 700
 701         writel(val, ctx->regs + VIDOSD_B(win));
 702
 703         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 704                         plane->crtc_x, plane->crtc_y, last_x, last_y);
 705
 706         /* OSD size */
 707         if (win != 3 && win != 4) {
 708                 u32 offset = VIDOSD_D(win);
 709                 if (win == 0)
 710                         offset = VIDOSD_C(win);
 711                 val = plane->crtc_width * plane->crtc_height;
 712                 writel(val, ctx->regs + offset);
 713
 714                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 715         }
 716
 717         fimd_win_set_pixfmt(ctx, win);
 718
 719         /* hardware window 0 doesn't support color key. */
 720         if (win != 0)
 721                 fimd_win_set_colkey(ctx, win);
 722
 723         fimd_enable_video_output(ctx, win, true);
 724
 725         if (ctx->driver_data->has_shadowcon)
 726                 fimd_enable_shadow_channel_path(ctx, win, true);
 727
 728         /* Enable DMA channel and unprotect windows */
 729         fimd_shadow_protect_win(ctx, win, false);
 730
 731         plane->enabled = true;
 732
 733         if (ctx->i80_if)
 734                 atomic_set(&ctx->win_updated, 1);
 735 }
 736
 737 static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
 738 {
 739         struct fimd_context *ctx = crtc->ctx;
 740         struct exynos_drm_plane *plane;
 741
 742         if (win < 0 || win >= WINDOWS_NR)
 743                 return;
 744
 745         plane = &ctx->planes[win];
 746
 747         if (ctx->suspended) {
 748                 /* do not resume this window*/
 749                 plane->resume = false;
 750                 return;
 751         }
 752
 753         /* protect windows */
 754         fimd_shadow_protect_win(ctx, win, true);
 755
 756         fimd_enable_video_output(ctx, win, false);
 757
 758         if (ctx->driver_data->has_shadowcon)
 759                 fimd_enable_shadow_channel_path(ctx, win, false);
 760
 761         /* unprotect windows */
 762         fimd_shadow_protect_win(ctx, win, false);
 763
 764         plane->enabled = false;
 765 }
 766
 767 static void fimd_window_suspend(struct fimd_context *ctx)
 768 {
 769         struct exynos_drm_plane *plane;
 770         int i;
 771
 772         for (i = 0; i < WINDOWS_NR; i++) {
 773                 plane = &ctx->planes[i];
 774                 plane->resume = plane->enabled;
 775                 if (plane->enabled)
 776                         fimd_win_disable(ctx->crtc, i);
 777         }
 778 }
 779
 780 static void fimd_window_resume(struct fimd_context *ctx)
 781 {
 782         struct exynos_drm_plane *plane;
 783         int i;
 784
 785         for (i = 0; i < WINDOWS_NR; i++) {
 786                 plane = &ctx->planes[i];
 787                 plane->enabled = plane->resume;
 788                 plane->resume = false;
 789         }
 790 }
 791
 792 static void fimd_apply(struct fimd_context *ctx)
 793 {
 794         struct exynos_drm_plane *plane;
 795         int i;
 796
 797         for (i = 0; i < WINDOWS_NR; i++) {
 798                 plane = &ctx->planes[i];
 799                 if (plane->enabled)
 800                         fimd_win_commit(ctx->crtc, i);
 801                 else
 802                         fimd_win_disable(ctx->crtc, i);
 803         }
 804
 805         fimd_commit(ctx->crtc);
 806 }
 807
 808 static int fimd_poweron(struct fimd_context *ctx)
 809 {
 810         int ret;
 811
 812         if (!ctx->suspended)
 813                 return 0;
 814
 815         ctx->suspended = false;
 816
 817         pm_runtime_get_sync(ctx->dev);
 818
 819         ret = clk_prepare_enable(ctx->bus_clk);
 820         if (ret < 0) {
 821                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
 822                 goto bus_clk_err;
 823         }
 824
 825         ret = clk_prepare_enable(ctx->lcd_clk);
 826         if  (ret < 0) {
 827                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
 828                 goto lcd_clk_err;
 829         }
 830
 831         /* if vblank was enabled status, enable it again. */
 832         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 833                 ret = fimd_enable_vblank(ctx->crtc);
 834                 if (ret) {
 835                         DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
 836                         goto enable_vblank_err;
 837                 }
 838         }
 839
 840         fimd_window_resume(ctx);
 841
 842         fimd_apply(ctx);
 843
 844         return 0;
 845
 846 enable_vblank_err:
 847         clk_disable_unprepare(ctx->lcd_clk);
 848 lcd_clk_err:
 849         clk_disable_unprepare(ctx->bus_clk);
 850 bus_clk_err:
 851         ctx->suspended = true;
 852         return ret;
 853 }
 854
 855 static int fimd_poweroff(struct fimd_context *ctx)
 856 {
 857         if (ctx->suspended)
 858                 return 0;
 859
 860         /*
 861          * We need to make sure that all windows are disabled before we
 862          * suspend that connector. Otherwise we might try to scan from
 863          * a destroyed buffer later.
 864          */
 865         fimd_window_suspend(ctx);
 866
 867         clk_disable_unprepare(ctx->lcd_clk);
 868         clk_disable_unprepare(ctx->bus_clk);
 869
 870         pm_runtime_put_sync(ctx->dev);
 871
 872         ctx->suspended = true;
 873         return 0;
 874 }
 875
 876 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
 877 {
 878         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 879
 880         switch (mode) {
 881         case DRM_MODE_DPMS_ON:
 882                 fimd_poweron(crtc->ctx);
 883                 break;
 884         case DRM_MODE_DPMS_STANDBY:
 885         case DRM_MODE_DPMS_SUSPEND:
 886         case DRM_MODE_DPMS_OFF:
 887                 fimd_poweroff(crtc->ctx);
 888                 break;
 889         default:
 890                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 891                 break;
 892         }
 893 }
 894
 895 static void fimd_trigger(struct device *dev)
 896 {
 897         struct fimd_context *ctx = dev_get_drvdata(dev);
 898         struct fimd_driver_data *driver_data = ctx->driver_data;
 899         void *timing_base = ctx->regs + driver_data->timing_base;
 900         u32 reg;
 901
 902          /*
 903           * Skips triggering if in triggering state, because multiple triggering
 904           * requests can cause panel reset.
 905           */
 906         if (atomic_read(&ctx->triggering))
 907                 return;
 908
 909         /* Enters triggering mode */
 910         atomic_set(&ctx->triggering, 1);
 911
 912         reg = readl(timing_base + TRIGCON);
 913         reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
 914         writel(reg, timing_base + TRIGCON);
 915
 916         /*
 917          * Exits triggering mode if vblank is not enabled yet, because when the
 918          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 919          */
 920         if (!test_bit(0, &ctx->irq_flags))
 921                 atomic_set(&ctx->triggering, 0);
 922 }
 923
 924 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 925 {
 926         struct fimd_context *ctx = crtc->ctx;
 927
 928         /* Checks the crtc is detached already from encoder */
 929         if (ctx->pipe < 0 || !ctx->drm_dev)
 930                 return;
 931
 932         /*
 933          * If there is a page flip request, triggers and handles the page flip
 934          * event so that current fb can be updated into panel GRAM.
 935          */
 936         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 937                 fimd_trigger(ctx->dev);
 938
 939         /* Wakes up vsync event queue */
 940         if (atomic_read(&ctx->wait_vsync_event)) {
 941                 atomic_set(&ctx->wait_vsync_event, 0);
 942                 wake_up(&ctx->wait_vsync_queue);
 943         }
 944
 945         if (test_bit(0, &ctx->irq_flags))
 946                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
 947 }
 948
 949 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
 950 {
 951         struct fimd_context *ctx = crtc->ctx;
 952         u32 val;
 953
 954         /*
 955          * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
 956          * clock. On these SoCs the bootloader may enable it but any
 957          * power domain off/on will reset it to disable state.
 958          */
 959         if (ctx->driver_data != &exynos5_fimd_driver_data)
 960                 return;
 961
 962         val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 963         writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
 964 }
 965
 966 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 967         .dpms = fimd_dpms,
 968         .mode_fixup = fimd_mode_fixup,
 969         .commit = fimd_commit,
 970         .enable_vblank = fimd_enable_vblank,
 971         .disable_vblank = fimd_disable_vblank,
 972         .wait_for_vblank = fimd_wait_for_vblank,
 973         .win_commit = fimd_win_commit,
 974         .win_disable = fimd_win_disable,
 975         .te_handler = fimd_te_handler,
 976         .clock_enable = fimd_dp_clock_enable,
 977 };
 978
 979 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 980 {
 981         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 982         u32 val, clear_bit;
 983
 984         val = readl(ctx->regs + VIDINTCON1);
 985
 986         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 987         if (val & clear_bit)
 988                 writel(clear_bit, ctx->regs + VIDINTCON1);
 989
 990         /* check the crtc is detached already from encoder */
 991         if (ctx->pipe < 0 || !ctx->drm_dev)
 992                 goto out;
 993
 994         if (ctx->i80_if) {
 995                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
 996
 997                 /* Exits triggering mode */
 998                 atomic_set(&ctx->triggering, 0);
 999         } else {
1000                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1001                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1002
1003                 /* set wait vsync event to zero and wake up queue. */
1004                 if (atomic_read(&ctx->wait_vsync_event)) {
1005                         atomic_set(&ctx->wait_vsync_event, 0);
1006                         wake_up(&ctx->wait_vsync_queue);
1007                 }
1008         }
1009
1010 out:
1011         return IRQ_HANDLED;
1012 }
1013
1014 static int fimd_bind(struct device *dev, struct device *master, void *data)
1015 {
1016         struct fimd_context *ctx = dev_get_drvdata(dev);
1017         struct drm_device *drm_dev = data;
1018         struct exynos_drm_private *priv = drm_dev->dev_private;
1019         struct exynos_drm_plane *exynos_plane;
1020         enum drm_plane_type type;
1021         unsigned int zpos;
1022         int ret;
1023
1024         ctx->drm_dev = drm_dev;
1025         ctx->pipe = priv->pipe++;
1026
1027         for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
1028                 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
1029                                                 DRM_PLANE_TYPE_OVERLAY;
1030                 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1031                                         1 << ctx->pipe, type, zpos);
1032                 if (ret)
1033                         return ret;
1034         }
1035
1036         exynos_plane = &ctx->planes[ctx->default_win];
1037         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1038                                            ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1039                                            &fimd_crtc_ops, ctx);
1040         if (IS_ERR(ctx->crtc))
1041                 return PTR_ERR(ctx->crtc);
1042
1043         if (ctx->display)
1044                 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1045
1046         return fimd_iommu_attach_devices(ctx, drm_dev);
1047 }
1048
1049 static void fimd_unbind(struct device *dev, struct device *master,
1050                         void *data)
1051 {
1052         struct fimd_context *ctx = dev_get_drvdata(dev);
1053
1054         fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1055
1056         fimd_iommu_detach_devices(ctx);
1057
1058         if (ctx->display)
1059                 exynos_dpi_remove(ctx->display);
1060 }
1061
1062 static const struct component_ops fimd_component_ops = {
1063         .bind   = fimd_bind,
1064         .unbind = fimd_unbind,
1065 };
1066
1067 static int fimd_probe(struct platform_device *pdev)
1068 {
1069         struct device *dev = &pdev->dev;
1070         struct fimd_context *ctx;
1071         struct device_node *i80_if_timings;
1072         struct resource *res;
1073         int ret;
1074
1075         if (!dev->of_node)
1076                 return -ENODEV;
1077
1078         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1079         if (!ctx)
1080                 return -ENOMEM;
1081
1082         ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1083                                        EXYNOS_DISPLAY_TYPE_LCD);
1084         if (ret)
1085                 return ret;
1086
1087         ctx->dev = dev;
1088         ctx->suspended = true;
1089         ctx->driver_data = drm_fimd_get_driver_data(pdev);
1090
1091         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1092                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1093         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1094                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1095
1096         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1097         if (i80_if_timings) {
1098                 u32 val;
1099
1100                 ctx->i80_if = true;
1101
1102                 if (ctx->driver_data->has_vidoutcon)
1103                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1104                 else
1105                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1106                 /*
1107                  * The user manual describes that this "DSI_EN" bit is required
1108                  * to enable I80 24-bit data interface.
1109                  */
1110                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1111
1112                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1113                         val = 0;
1114                 ctx->i80ifcon = LCD_CS_SETUP(val);
1115                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1116                         val = 0;
1117                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1118                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1119                         val = 1;
1120                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1121                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1122                         val = 0;
1123                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1124         }
1125         of_node_put(i80_if_timings);
1126
1127         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1128                                                         "samsung,sysreg");
1129         if (IS_ERR(ctx->sysreg)) {
1130                 dev_warn(dev, "failed to get system register.\n");
1131                 ctx->sysreg = NULL;
1132         }
1133
1134         ctx->bus_clk = devm_clk_get(dev, "fimd");
1135         if (IS_ERR(ctx->bus_clk)) {
1136                 dev_err(dev, "failed to get bus clock\n");
1137                 ret = PTR_ERR(ctx->bus_clk);
1138                 goto err_del_component;
1139         }
1140
1141         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1142         if (IS_ERR(ctx->lcd_clk)) {
1143                 dev_err(dev, "failed to get lcd clock\n");
1144                 ret = PTR_ERR(ctx->lcd_clk);
1145                 goto err_del_component;
1146         }
1147
1148         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1149
1150         ctx->regs = devm_ioremap_resource(dev, res);
1151         if (IS_ERR(ctx->regs)) {
1152                 ret = PTR_ERR(ctx->regs);
1153                 goto err_del_component;
1154         }
1155
1156         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1157                                            ctx->i80_if ? "lcd_sys" : "vsync");
1158         if (!res) {
1159                 dev_err(dev, "irq request failed.\n");
1160                 ret = -ENXIO;
1161                 goto err_del_component;
1162         }
1163
1164         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1165                                                         0, "drm_fimd", ctx);
1166         if (ret) {
1167                 dev_err(dev, "irq request failed.\n");
1168                 goto err_del_component;
1169         }
1170
1171         init_waitqueue_head(&ctx->wait_vsync_queue);
1172         atomic_set(&ctx->wait_vsync_event, 0);
1173
1174         platform_set_drvdata(pdev, ctx);
1175
1176         ctx->display = exynos_dpi_probe(dev);
1177         if (IS_ERR(ctx->display)) {
1178                 ret = PTR_ERR(ctx->display);
1179                 goto err_del_component;
1180         }
1181
1182         pm_runtime_enable(dev);
1183
1184         ret = component_add(dev, &fimd_component_ops);
1185         if (ret)
1186                 goto err_disable_pm_runtime;
1187
1188         return ret;
1189
1190 err_disable_pm_runtime:
1191         pm_runtime_disable(dev);
1192
1193 err_del_component:
1194         exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1195         return ret;
1196 }
1197
1198 static int fimd_remove(struct platform_device *pdev)
1199 {
1200         pm_runtime_disable(&pdev->dev);
1201
1202         component_del(&pdev->dev, &fimd_component_ops);
1203         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1204
1205         return 0;
1206 }
1207
1208 struct platform_driver fimd_driver = {
1209         .probe          = fimd_probe,
1210         .remove         = fimd_remove,
1211         .driver         = {
1212                 .name   = "exynos4-fb",
1213                 .owner  = THIS_MODULE,
1214                 .of_match_table = fimd_driver_dt_match,
1215         },
1216 };