2 * Header file for Samsung DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef _EXYNOS_DP_CORE_H
14 #define _EXYNOS_DP_CORE_H
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_dp_helper.h>
18 #include <drm/exynos_drm.h>
20 #include "exynos_drm_drv.h"
22 #define DP_TIMEOUT_LOOP_COUNT 100
27 LINK_RATE_1_62GBPS = 0x06,
28 LINK_RATE_2_70GBPS = 0x0a
31 enum link_lane_count_type {
37 enum link_training_state {
45 enum voltage_swing_level {
52 enum pre_emphasis_level {
80 enum color_coefficient {
95 enum clock_recovery_m_value_type {
100 enum video_timing_recognition_type {
101 VIDEO_TIMING_FROM_CAPTURE,
102 VIDEO_TIMING_FROM_REGISTER
105 enum analog_power_block {
116 DP_IRQ_TYPE_HP_CABLE_IN,
117 DP_IRQ_TYPE_HP_CABLE_OUT,
118 DP_IRQ_TYPE_HP_CHANGE,
125 bool h_sync_polarity;
126 bool v_sync_polarity;
129 enum color_space color_space;
130 enum dynamic_range dynamic_range;
131 enum color_coefficient ycbcr_coeff;
132 enum color_depth color_depth;
134 enum link_rate_type link_rate;
135 enum link_lane_count_type lane_count;
146 enum link_training_state lt_state;
149 struct exynos_dp_device {
150 struct drm_encoder encoder;
152 struct drm_device *drm_dev;
153 struct drm_connector connector;
154 struct drm_panel *panel;
155 struct drm_bridge *bridge;
158 void __iomem *reg_base;
160 struct video_info *video_info;
161 struct link_train link_train;
162 struct work_struct hotplug_work;
167 struct exynos_drm_panel_info priv;
170 /* exynos_dp_reg.c */
171 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
172 void exynos_dp_stop_video(struct exynos_dp_device *dp);
173 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
174 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
175 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
176 void exynos_dp_reset(struct exynos_dp_device *dp);
177 void exynos_dp_swreset(struct exynos_dp_device *dp);
178 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
179 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
180 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
181 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
182 enum analog_power_block block,
184 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
185 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
186 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
187 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
188 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
189 void exynos_dp_init_aux(struct exynos_dp_device *dp);
190 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
191 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
192 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
193 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
194 unsigned int reg_addr,
196 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
197 unsigned int reg_addr,
198 unsigned char *data);
199 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
200 unsigned int reg_addr,
202 unsigned char data[]);
203 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
204 unsigned int reg_addr,
206 unsigned char data[]);
207 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
208 unsigned int device_addr,
209 unsigned int reg_addr);
210 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
211 unsigned int device_addr,
212 unsigned int reg_addr,
214 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
215 unsigned int device_addr,
216 unsigned int reg_addr,
218 unsigned char edid[]);
219 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
220 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
221 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
222 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
223 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
224 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
225 enum pattern_set pattern);
226 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
227 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
228 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
229 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
230 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
232 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
234 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
236 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
238 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
239 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
240 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
241 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
242 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
243 void exynos_dp_init_video(struct exynos_dp_device *dp);
245 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
246 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
247 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
248 enum clock_recovery_m_value_type type,
251 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
252 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
253 void exynos_dp_start_video(struct exynos_dp_device *dp);
254 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
255 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
256 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
257 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
259 /* I2C EDID Chip ID, Slave Address */
260 #define I2C_EDID_DEVICE_ADDR 0x50
261 #define I2C_E_EDID_DEVICE_ADDR 0x30
263 #define EDID_BLOCK_LENGTH 0x80
264 #define EDID_HEADER_PATTERN 0x00
265 #define EDID_EXTENSION_FLAG 0x7e
266 #define EDID_CHECKSUM 0x7f
268 /* DP_MAX_LANE_COUNT */
269 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
270 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
272 /* DP_LANE_COUNT_SET */
273 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
275 /* DP_TRAINING_LANE0_SET */
276 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
277 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
278 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
279 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
281 #endif /* _EXYNOS_DP_CORE_H */