kernel/drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21
  22 struct armada_frame_work {
  23         struct drm_pending_vblank_event *event;
  24         struct armada_regs regs[4];
  25         struct drm_framebuffer *old_fb;
  26 };
  27
  28 enum csc_mode {
  29         CSC_AUTO = 0,
  30         CSC_YUV_CCIR601 = 1,
  31         CSC_YUV_CCIR709 = 2,
  32         CSC_RGB_COMPUTER = 1,
  33         CSC_RGB_STUDIO = 2,
  34 };
  35
  36 /*
  37  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  38  * The timing parameters we have from X are:
  39  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  40  *  1920 2448 2492 2640  1080 1084 1094 1125
  41  * Which get translated to:
  42  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  43  *  1920 2448 2492 2640   540  542  547  562
  44  *
  45  * This is how it is defined by CEA-861-D - line and pixel numbers are
  46  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  47  * line: 2640.  The odd frame, the first active line is at line 21, and
  48  * the even frame, the first active line is 584.
  49  *
  50  * LN:    560     561     562     563             567     568    569
  51  * DE:    ~~~|____________________________//__________________________
  52  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  53  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  54  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  55  *
  56  * LN:    1123   1124    1125      1               5       6      7
  57  * DE:    ~~~|____________________________//__________________________
  58  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  59  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  60  *  23 blanking lines
  61  *
  62  * The Armada LCD Controller line and pixel numbers are, like X timings,
  63  * referenced to the top left of the active frame.
  64  *
  65  * So, translating these to our LCD controller:
  66  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  67  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  68  * Note: Vsync front porch remains constant!
  69  *
  70  * if (odd_frame) {
  71  *   vtotal = mode->crtc_vtotal + 1;
  72  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  73  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  74  * } else {
  75  *   vtotal = mode->crtc_vtotal;
  76  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  77  *   vhorizpos = mode->crtc_hsync_start;
  78  * }
  79  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  80  *
  81  * So, we need to reprogram these registers on each vsync event:
  82  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  83  *
  84  * Note: we do not use the frame done interrupts because these appear
  85  * to happen too early, and lead to jitter on the display (presumably
  86  * they occur at the end of the last active line, before the vsync back
  87  * porch, which we're reprogramming.)
  88  */
  89
  90 void
  91 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
  92 {
  93         while (regs->offset != ~0) {
  94                 void __iomem *reg = dcrtc->base + regs->offset;
  95                 uint32_t val;
  96
  97                 val = regs->mask;
  98                 if (val != 0)
  99                         val &= readl_relaxed(reg);
 100                 writel_relaxed(val | regs->val, reg);
 101                 ++regs;
 102         }
 103 }
 104
 105 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 106
 107 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 108 {
 109         uint32_t dumb_ctrl;
 110
 111         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 112
 113         if (!dpms_blanked(dcrtc->dpms))
 114                 dumb_ctrl |= CFG_DUMB_ENA;
 115
 116         /*
 117          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 118          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 119          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 120          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 121          */
 122         if (dpms_blanked(dcrtc->dpms) &&
 123             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 124                 dumb_ctrl &= ~DUMB_MASK;
 125                 dumb_ctrl |= DUMB_BLANK;
 126         }
 127
 128         /*
 129          * The documentation doesn't indicate what the normal state of
 130          * the sync signals are.  Sebastian Hesselbart kindly probed
 131          * these signals on his board to determine their state.
 132          *
 133          * The non-inverted state of the sync signals is active high.
 134          * Setting these bits makes the appropriate signal active low.
 135          */
 136         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 137                 dumb_ctrl |= CFG_INV_CSYNC;
 138         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 139                 dumb_ctrl |= CFG_INV_HSYNC;
 140         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 141                 dumb_ctrl |= CFG_INV_VSYNC;
 142
 143         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 144                 dcrtc->dumb_ctrl = dumb_ctrl;
 145                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 146         }
 147 }
 148
 149 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 150         int x, int y, struct armada_regs *regs, bool interlaced)
 151 {
 152         struct armada_gem_object *obj = drm_fb_obj(fb);
 153         unsigned pitch = fb->pitches[0];
 154         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
 155         uint32_t addr_odd, addr_even;
 156         unsigned i = 0;
 157
 158         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 159                 pitch, x, y, fb->bits_per_pixel);
 160
 161         addr_odd = addr_even = obj->dev_addr + offset;
 162
 163         if (interlaced) {
 164                 addr_even += pitch;
 165                 pitch *= 2;
 166         }
 167
 168         /* write offset, base, and pitch */
 169         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 170         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 171         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 172
 173         return i;
 174 }
 175
 176 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 177         struct armada_frame_work *work)
 178 {
 179         struct drm_device *dev = dcrtc->crtc.dev;
 180         unsigned long flags;
 181         int ret;
 182
 183         ret = drm_vblank_get(dev, dcrtc->num);
 184         if (ret) {
 185                 DRM_ERROR("failed to acquire vblank counter\n");
 186                 return ret;
 187         }
 188
 189         spin_lock_irqsave(&dev->event_lock, flags);
 190         if (!dcrtc->frame_work)
 191                 dcrtc->frame_work = work;
 192         else
 193                 ret = -EBUSY;
 194         spin_unlock_irqrestore(&dev->event_lock, flags);
 195
 196         if (ret)
 197                 drm_vblank_put(dev, dcrtc->num);
 198
 199         return ret;
 200 }
 201
 202 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
 203 {
 204         struct drm_device *dev = dcrtc->crtc.dev;
 205         struct armada_frame_work *work = dcrtc->frame_work;
 206
 207         dcrtc->frame_work = NULL;
 208
 209         armada_drm_crtc_update_regs(dcrtc, work->regs);
 210
 211         if (work->event)
 212                 drm_send_vblank_event(dev, dcrtc->num, work->event);
 213
 214         drm_vblank_put(dev, dcrtc->num);
 215
 216         /* Finally, queue the process-half of the cleanup. */
 217         __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
 218         kfree(work);
 219 }
 220
 221 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 222         struct drm_framebuffer *fb, bool force)
 223 {
 224         struct armada_frame_work *work;
 225
 226         if (!fb)
 227                 return;
 228
 229         if (force) {
 230                 /* Display is disabled, so just drop the old fb */
 231                 drm_framebuffer_unreference(fb);
 232                 return;
 233         }
 234
 235         work = kmalloc(sizeof(*work), GFP_KERNEL);
 236         if (work) {
 237                 int i = 0;
 238                 work->event = NULL;
 239                 work->old_fb = fb;
 240                 armada_reg_queue_end(work->regs, i);
 241
 242                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 243                         return;
 244
 245                 kfree(work);
 246         }
 247
 248         /*
 249          * Oops - just drop the reference immediately and hope for
 250          * the best.  The worst that will happen is the buffer gets
 251          * reused before it has finished being displayed.
 252          */
 253         drm_framebuffer_unreference(fb);
 254 }
 255
 256 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 257 {
 258         struct drm_device *dev = dcrtc->crtc.dev;
 259
 260         /*
 261          * Tell the DRM core that vblank IRQs aren't going to happen for
 262          * a while.  This cleans up any pending vblank events for us.
 263          */
 264         drm_crtc_vblank_off(&dcrtc->crtc);
 265
 266         /* Handle any pending flip event. */
 267         spin_lock_irq(&dev->event_lock);
 268         if (dcrtc->frame_work)
 269                 armada_drm_crtc_complete_frame_work(dcrtc);
 270         spin_unlock_irq(&dev->event_lock);
 271 }
 272
 273 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 274         int idx)
 275 {
 276 }
 277
 278 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 279         int idx)
 280 {
 281 }
 282
 283 /* The mode_config.mutex will be held for this call */
 284 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 285 {
 286         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 287
 288         if (dcrtc->dpms != dpms) {
 289                 dcrtc->dpms = dpms;
 290                 armada_drm_crtc_update(dcrtc);
 291                 if (dpms_blanked(dpms))
 292                         armada_drm_vblank_off(dcrtc);
 293                 else
 294                         drm_crtc_vblank_on(&dcrtc->crtc);
 295         }
 296 }
 297
 298 /*
 299  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 300  * up with the overlay size being bigger than the active screen size.
 301  * We rely upon X refreshing this state after the mode set has completed.
 302  *
 303  * The mode_config.mutex will be held for this call
 304  */
 305 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 306 {
 307         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 308         struct drm_plane *plane;
 309
 310         /*
 311          * If we have an overlay plane associated with this CRTC, disable
 312          * it before the modeset to avoid its coordinates being outside
 313          * the new mode parameters.  DRM doesn't provide help with this.
 314          */
 315         plane = dcrtc->plane;
 316         if (plane) {
 317                 struct drm_framebuffer *fb = plane->fb;
 318
 319                 plane->funcs->disable_plane(plane);
 320                 plane->fb = NULL;
 321                 plane->crtc = NULL;
 322                 drm_framebuffer_unreference(fb);
 323         }
 324 }
 325
 326 /* The mode_config.mutex will be held for this call */
 327 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 328 {
 329         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 330
 331         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 332                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 333                 armada_drm_crtc_update(dcrtc);
 334         }
 335 }
 336
 337 /* The mode_config.mutex will be held for this call */
 338 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 339         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 340 {
 341         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 342         int ret;
 343
 344         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 345         if (!dcrtc->variant->has_spu_adv_reg &&
 346             adj->flags & DRM_MODE_FLAG_INTERLACE)
 347                 return false;
 348
 349         /* Check whether the display mode is possible */
 350         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 351         if (ret)
 352                 return false;
 353
 354         return true;
 355 }
 356
 357 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 358 {
 359         struct armada_vbl_event *e, *n;
 360         void __iomem *base = dcrtc->base;
 361
 362         if (stat & DMA_FF_UNDERFLOW)
 363                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 364         if (stat & GRA_FF_UNDERFLOW)
 365                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 366
 367         if (stat & VSYNC_IRQ)
 368                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
 369
 370         spin_lock(&dcrtc->irq_lock);
 371
 372         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
 373                 list_del_init(&e->node);
 374                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 375                 e->fn(dcrtc, e->data);
 376         }
 377
 378         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 379                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 380                 uint32_t val;
 381
 382                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 383                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 384                                base + LCD_SPUT_V_H_TOTAL);
 385
 386                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 387                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 388                 val |= dcrtc->v[i].spu_adv_reg;
 389                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 390         }
 391
 392         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 393                 writel_relaxed(dcrtc->cursor_hw_pos,
 394                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 395                 writel_relaxed(dcrtc->cursor_hw_sz,
 396                                base + LCD_SPU_HWC_HPXL_VLN);
 397                 armada_updatel(CFG_HWC_ENA,
 398                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 399                                base + LCD_SPU_DMA_CTRL0);
 400                 dcrtc->cursor_update = false;
 401                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 402         }
 403
 404         spin_unlock(&dcrtc->irq_lock);
 405
 406         if (stat & GRA_FRAME_IRQ) {
 407                 struct drm_device *dev = dcrtc->crtc.dev;
 408
 409                 spin_lock(&dev->event_lock);
 410                 if (dcrtc->frame_work)
 411                         armada_drm_crtc_complete_frame_work(dcrtc);
 412                 spin_unlock(&dev->event_lock);
 413
 414                 wake_up(&dcrtc->frame_wait);
 415         }
 416 }
 417
 418 static irqreturn_t armada_drm_irq(int irq, void *arg)
 419 {
 420         struct armada_crtc *dcrtc = arg;
 421         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 422
 423         /*
 424          * This is rediculous - rather than writing bits to clear, we
 425          * have to set the actual status register value.  This is racy.
 426          */
 427         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 428
 429         /* Mask out those interrupts we haven't enabled */
 430         v = stat & dcrtc->irq_ena;
 431
 432         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 433                 armada_drm_crtc_irq(dcrtc, stat);
 434                 return IRQ_HANDLED;
 435         }
 436         return IRQ_NONE;
 437 }
 438
 439 /* These are locked by dev->vbl_lock */
 440 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 441 {
 442         if (dcrtc->irq_ena & mask) {
 443                 dcrtc->irq_ena &= ~mask;
 444                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 445         }
 446 }
 447
 448 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 449 {
 450         if ((dcrtc->irq_ena & mask) != mask) {
 451                 dcrtc->irq_ena |= mask;
 452                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 453                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 454                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 455         }
 456 }
 457
 458 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 459 {
 460         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 461         uint32_t val = 0;
 462
 463         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 464                 val |= CFG_CSC_YUV_CCIR709;
 465         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 466                 val |= CFG_CSC_RGB_STUDIO;
 467
 468         /*
 469          * In auto mode, set the colorimetry, based upon the HDMI spec.
 470          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 471          * ITU601.  It may be more appropriate to set this depending on
 472          * the source - but what if the graphic frame is YUV and the
 473          * video frame is RGB?
 474          */
 475         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 476              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 477             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 478                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 479                         val |= CFG_CSC_YUV_CCIR709;
 480         }
 481
 482         /*
 483          * We assume we're connected to a TV-like device, so the YUV->RGB
 484          * conversion should produce a limited range.  We should set this
 485          * depending on the connectors attached to this CRTC, and what
 486          * kind of device they report being connected.
 487          */
 488         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 489                 val |= CFG_CSC_RGB_STUDIO;
 490
 491         return val;
 492 }
 493
 494 /* The mode_config.mutex will be held for this call */
 495 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 496         struct drm_display_mode *mode, struct drm_display_mode *adj,
 497         int x, int y, struct drm_framebuffer *old_fb)
 498 {
 499         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 500         struct armada_regs regs[17];
 501         uint32_t lm, rm, tm, bm, val, sclk;
 502         unsigned long flags;
 503         unsigned i;
 504         bool interlaced;
 505
 506         drm_framebuffer_reference(crtc->primary->fb);
 507
 508         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 509
 510         i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
 511                                     x, y, regs, interlaced);
 512
 513         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 514         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 515         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 516         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 517
 518         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 519                 adj->crtc_hdisplay,
 520                 adj->crtc_hsync_start,
 521                 adj->crtc_hsync_end,
 522                 adj->crtc_htotal, lm, rm);
 523         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 524                 adj->crtc_vdisplay,
 525                 adj->crtc_vsync_start,
 526                 adj->crtc_vsync_end,
 527                 adj->crtc_vtotal, tm, bm);
 528
 529         /* Wait for pending flips to complete */
 530         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 531
 532         drm_crtc_vblank_off(crtc);
 533
 534         crtc->mode = *adj;
 535
 536         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 537         if (val != dcrtc->dumb_ctrl) {
 538                 dcrtc->dumb_ctrl = val;
 539                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 540         }
 541
 542         /* Now compute the divider for real */
 543         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 544
 545         /* Ensure graphic fifo is enabled */
 546         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 547         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 548
 549         if (interlaced ^ dcrtc->interlaced) {
 550                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 551                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 552                 else
 553                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 554                 dcrtc->interlaced = interlaced;
 555         }
 556
 557         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 558
 559         /* Even interlaced/progressive frame */
 560         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 561                                     adj->crtc_htotal;
 562         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 563         val = adj->crtc_hsync_start;
 564         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 565                 dcrtc->variant->spu_adv_reg;
 566
 567         if (interlaced) {
 568                 /* Odd interlaced frame */
 569                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 570                                                 (1 << 16);
 571                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 572                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 573                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 574                         dcrtc->variant->spu_adv_reg;
 575         } else {
 576                 dcrtc->v[0] = dcrtc->v[1];
 577         }
 578
 579         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 580
 581         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 582         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
 583         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
 584         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 585         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 586         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 587                            LCD_SPUT_V_H_TOTAL);
 588
 589         if (dcrtc->variant->has_spu_adv_reg) {
 590                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 591                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 592                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 593         }
 594
 595         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 596         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 597         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 598
 599         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 600                 val |= CFG_PALETTE_ENA;
 601
 602         if (interlaced)
 603                 val |= CFG_GRA_FTOGGLE;
 604
 605         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
 606                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 607                                          CFG_SWAPYU | CFG_YUV2RGB) |
 608                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 609                              LCD_SPU_DMA_CTRL0);
 610
 611         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 612         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 613
 614         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 615         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 616         armada_reg_queue_end(regs, i);
 617
 618         armada_drm_crtc_update_regs(dcrtc, regs);
 619         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 620
 621         armada_drm_crtc_update(dcrtc);
 622
 623         drm_crtc_vblank_on(crtc);
 624         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 625
 626         return 0;
 627 }
 628
 629 /* The mode_config.mutex will be held for this call */
 630 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 631         struct drm_framebuffer *old_fb)
 632 {
 633         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 634         struct armada_regs regs[4];
 635         unsigned i;
 636
 637         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 638                                     dcrtc->interlaced);
 639         armada_reg_queue_end(regs, i);
 640
 641         /* Wait for pending flips to complete */
 642         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 643
 644         /* Take a reference to the new fb as we're using it */
 645         drm_framebuffer_reference(crtc->primary->fb);
 646
 647         /* Update the base in the CRTC */
 648         armada_drm_crtc_update_regs(dcrtc, regs);
 649
 650         /* Drop our previously held reference */
 651         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 652
 653         return 0;
 654 }
 655
 656 /* The mode_config.mutex will be held for this call */
 657 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 658 {
 659         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 660
 661         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 662         armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
 663
 664         /* Power down most RAMs and FIFOs */
 665         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 666                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
 667                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
 668 }
 669
 670 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 671         .dpms           = armada_drm_crtc_dpms,
 672         .prepare        = armada_drm_crtc_prepare,
 673         .commit         = armada_drm_crtc_commit,
 674         .mode_fixup     = armada_drm_crtc_mode_fixup,
 675         .mode_set       = armada_drm_crtc_mode_set,
 676         .mode_set_base  = armada_drm_crtc_mode_set_base,
 677         .disable        = armada_drm_crtc_disable,
 678 };
 679
 680 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 681         unsigned stride, unsigned width, unsigned height)
 682 {
 683         uint32_t addr;
 684         unsigned y;
 685
 686         addr = SRAM_HWC32_RAM1;
 687         for (y = 0; y < height; y++) {
 688                 uint32_t *p = &pix[y * stride];
 689                 unsigned x;
 690
 691                 for (x = 0; x < width; x++, p++) {
 692                         uint32_t val = *p;
 693
 694                         val = (val & 0xff00ff00) |
 695                               (val & 0x000000ff) << 16 |
 696                               (val & 0x00ff0000) >> 16;
 697
 698                         writel_relaxed(val,
 699                                        base + LCD_SPU_SRAM_WRDAT);
 700                         writel_relaxed(addr | SRAM_WRITE,
 701                                        base + LCD_SPU_SRAM_CTRL);
 702                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 703                         addr += 1;
 704                         if ((addr & 0x00ff) == 0)
 705                                 addr += 0xf00;
 706                         if ((addr & 0x30ff) == 0)
 707                                 addr = SRAM_HWC32_RAM2;
 708                 }
 709         }
 710 }
 711
 712 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 713 {
 714         unsigned addr;
 715
 716         for (addr = 0; addr < 256; addr++) {
 717                 /* write the default value */
 718                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 719                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 720                                base + LCD_SPU_SRAM_CTRL);
 721         }
 722 }
 723
 724 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 725 {
 726         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 727         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 728         uint32_t para1;
 729
 730         /*
 731          * Calculate the visible width and height of the cursor,
 732          * screen position, and the position in the cursor bitmap.
 733          */
 734         if (dcrtc->cursor_x < 0) {
 735                 xoff = -dcrtc->cursor_x;
 736                 xscr = 0;
 737                 w -= min(xoff, w);
 738         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 739                 xoff = 0;
 740                 xscr = dcrtc->cursor_x;
 741                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 742         } else {
 743                 xoff = 0;
 744                 xscr = dcrtc->cursor_x;
 745         }
 746
 747         if (dcrtc->cursor_y < 0) {
 748                 yoff = -dcrtc->cursor_y;
 749                 yscr = 0;
 750                 h -= min(yoff, h);
 751         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 752                 yoff = 0;
 753                 yscr = dcrtc->cursor_y;
 754                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 755         } else {
 756                 yoff = 0;
 757                 yscr = dcrtc->cursor_y;
 758         }
 759
 760         /* On interlaced modes, the vertical cursor size must be halved */
 761         s = dcrtc->cursor_w;
 762         if (dcrtc->interlaced) {
 763                 s *= 2;
 764                 yscr /= 2;
 765                 h /= 2;
 766         }
 767
 768         if (!dcrtc->cursor_obj || !h || !w) {
 769                 spin_lock_irq(&dcrtc->irq_lock);
 770                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 771                 dcrtc->cursor_update = false;
 772                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 773                 spin_unlock_irq(&dcrtc->irq_lock);
 774                 return 0;
 775         }
 776
 777         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 778         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 779                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 780
 781         /*
 782          * Initialize the transparency if the SRAM was powered down.
 783          * We must also reload the cursor data as well.
 784          */
 785         if (!(para1 & CFG_CSB_256x32)) {
 786                 armada_drm_crtc_cursor_tran(dcrtc->base);
 787                 reload = true;
 788         }
 789
 790         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 791                 spin_lock_irq(&dcrtc->irq_lock);
 792                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 793                 dcrtc->cursor_update = false;
 794                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 795                 spin_unlock_irq(&dcrtc->irq_lock);
 796                 reload = true;
 797         }
 798         if (reload) {
 799                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 800                 uint32_t *pix;
 801                 /* Set the top-left corner of the cursor image */
 802                 pix = obj->addr;
 803                 pix += yoff * s + xoff;
 804                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 805         }
 806
 807         /* Reload the cursor position, size and enable in the IRQ handler */
 808         spin_lock_irq(&dcrtc->irq_lock);
 809         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 810         dcrtc->cursor_hw_sz = h << 16 | w;
 811         dcrtc->cursor_update = true;
 812         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 813         spin_unlock_irq(&dcrtc->irq_lock);
 814
 815         return 0;
 816 }
 817
 818 static void cursor_update(void *data)
 819 {
 820         armada_drm_crtc_cursor_update(data, true);
 821 }
 822
 823 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 824         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 825 {
 826         struct drm_device *dev = crtc->dev;
 827         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 828         struct armada_gem_object *obj = NULL;
 829         int ret;
 830
 831         /* If no cursor support, replicate drm's return value */
 832         if (!dcrtc->variant->has_spu_adv_reg)
 833                 return -ENXIO;
 834
 835         if (handle && w > 0 && h > 0) {
 836                 /* maximum size is 64x32 or 32x64 */
 837                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 838                         return -ENOMEM;
 839
 840                 obj = armada_gem_object_lookup(dev, file, handle);
 841                 if (!obj)
 842                         return -ENOENT;
 843
 844                 /* Must be a kernel-mapped object */
 845                 if (!obj->addr) {
 846                         drm_gem_object_unreference_unlocked(&obj->obj);
 847                         return -EINVAL;
 848                 }
 849
 850                 if (obj->obj.size < w * h * 4) {
 851                         DRM_ERROR("buffer is too small\n");
 852                         drm_gem_object_unreference_unlocked(&obj->obj);
 853                         return -ENOMEM;
 854                 }
 855         }
 856
 857         mutex_lock(&dev->struct_mutex);
 858         if (dcrtc->cursor_obj) {
 859                 dcrtc->cursor_obj->update = NULL;
 860                 dcrtc->cursor_obj->update_data = NULL;
 861                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 862         }
 863         dcrtc->cursor_obj = obj;
 864         dcrtc->cursor_w = w;
 865         dcrtc->cursor_h = h;
 866         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 867         if (obj) {
 868                 obj->update_data = dcrtc;
 869                 obj->update = cursor_update;
 870         }
 871         mutex_unlock(&dev->struct_mutex);
 872
 873         return ret;
 874 }
 875
 876 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 877 {
 878         struct drm_device *dev = crtc->dev;
 879         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 880         int ret;
 881
 882         /* If no cursor support, replicate drm's return value */
 883         if (!dcrtc->variant->has_spu_adv_reg)
 884                 return -EFAULT;
 885
 886         mutex_lock(&dev->struct_mutex);
 887         dcrtc->cursor_x = x;
 888         dcrtc->cursor_y = y;
 889         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 890         mutex_unlock(&dev->struct_mutex);
 891
 892         return ret;
 893 }
 894
 895 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 896 {
 897         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 898         struct armada_private *priv = crtc->dev->dev_private;
 899
 900         if (dcrtc->cursor_obj)
 901                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 902
 903         priv->dcrtc[dcrtc->num] = NULL;
 904         drm_crtc_cleanup(&dcrtc->crtc);
 905
 906         if (!IS_ERR(dcrtc->clk))
 907                 clk_disable_unprepare(dcrtc->clk);
 908
 909         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
 910
 911         of_node_put(dcrtc->crtc.port);
 912
 913         kfree(dcrtc);
 914 }
 915
 916 /*
 917  * The mode_config lock is held here, to prevent races between this
 918  * and a mode_set.
 919  */
 920 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
 921         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 922 {
 923         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 924         struct armada_frame_work *work;
 925         struct drm_device *dev = crtc->dev;
 926         unsigned long flags;
 927         unsigned i;
 928         int ret;
 929
 930         /* We don't support changing the pixel format */
 931         if (fb->pixel_format != crtc->primary->fb->pixel_format)
 932                 return -EINVAL;
 933
 934         work = kmalloc(sizeof(*work), GFP_KERNEL);
 935         if (!work)
 936                 return -ENOMEM;
 937
 938         work->event = event;
 939         work->old_fb = dcrtc->crtc.primary->fb;
 940
 941         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
 942                                     dcrtc->interlaced);
 943         armada_reg_queue_end(work->regs, i);
 944
 945         /*
 946          * Ensure that we hold a reference on the new framebuffer.
 947          * This has to match the behaviour in mode_set.
 948          */
 949         drm_framebuffer_reference(fb);
 950
 951         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
 952         if (ret) {
 953                 /* Undo our reference above */
 954                 drm_framebuffer_unreference(fb);
 955                 kfree(work);
 956                 return ret;
 957         }
 958
 959         /*
 960          * Don't take a reference on the new framebuffer;
 961          * drm_mode_page_flip_ioctl() has already grabbed a reference and
 962          * will _not_ drop that reference on successful return from this
 963          * function.  Simply mark this new framebuffer as the current one.
 964          */
 965         dcrtc->crtc.primary->fb = fb;
 966
 967         /*
 968          * Finally, if the display is blanked, we won't receive an
 969          * interrupt, so complete it now.
 970          */
 971         if (dpms_blanked(dcrtc->dpms)) {
 972                 spin_lock_irqsave(&dev->event_lock, flags);
 973                 if (dcrtc->frame_work)
 974                         armada_drm_crtc_complete_frame_work(dcrtc);
 975                 spin_unlock_irqrestore(&dev->event_lock, flags);
 976         }
 977
 978         return 0;
 979 }
 980
 981 static int
 982 armada_drm_crtc_set_property(struct drm_crtc *crtc,
 983         struct drm_property *property, uint64_t val)
 984 {
 985         struct armada_private *priv = crtc->dev->dev_private;
 986         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 987         bool update_csc = false;
 988
 989         if (property == priv->csc_yuv_prop) {
 990                 dcrtc->csc_yuv_mode = val;
 991                 update_csc = true;
 992         } else if (property == priv->csc_rgb_prop) {
 993                 dcrtc->csc_rgb_mode = val;
 994                 update_csc = true;
 995         }
 996
 997         if (update_csc) {
 998                 uint32_t val;
 999
1000                 val = dcrtc->spu_iopad_ctrl |
1001                       armada_drm_crtc_calculate_csc(dcrtc);
1002                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1003         }
1004
1005         return 0;
1006 }
1007
1008 static struct drm_crtc_funcs armada_crtc_funcs = {
1009         .cursor_set     = armada_drm_crtc_cursor_set,
1010         .cursor_move    = armada_drm_crtc_cursor_move,
1011         .destroy        = armada_drm_crtc_destroy,
1012         .set_config     = drm_crtc_helper_set_config,
1013         .page_flip      = armada_drm_crtc_page_flip,
1014         .set_property   = armada_drm_crtc_set_property,
1015 };
1016
1017 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1018         { CSC_AUTO,        "Auto" },
1019         { CSC_YUV_CCIR601, "CCIR601" },
1020         { CSC_YUV_CCIR709, "CCIR709" },
1021 };
1022
1023 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1024         { CSC_AUTO,         "Auto" },
1025         { CSC_RGB_COMPUTER, "Computer system" },
1026         { CSC_RGB_STUDIO,   "Studio" },
1027 };
1028
1029 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1030 {
1031         struct armada_private *priv = dev->dev_private;
1032
1033         if (priv->csc_yuv_prop)
1034                 return 0;
1035
1036         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1037                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1038                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1039         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1040                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1041                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1042
1043         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1044                 return -ENOMEM;
1045
1046         return 0;
1047 }
1048
1049 int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1050         struct resource *res, int irq, const struct armada_variant *variant,
1051         struct device_node *port)
1052 {
1053         struct armada_private *priv = drm->dev_private;
1054         struct armada_crtc *dcrtc;
1055         void __iomem *base;
1056         int ret;
1057
1058         ret = armada_drm_crtc_create_properties(drm);
1059         if (ret)
1060                 return ret;
1061
1062         base = devm_ioremap_resource(dev, res);
1063         if (IS_ERR(base))
1064                 return PTR_ERR(base);
1065
1066         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1067         if (!dcrtc) {
1068                 DRM_ERROR("failed to allocate Armada crtc\n");
1069                 return -ENOMEM;
1070         }
1071
1072         if (dev != drm->dev)
1073                 dev_set_drvdata(dev, dcrtc);
1074
1075         dcrtc->variant = variant;
1076         dcrtc->base = base;
1077         dcrtc->num = drm->mode_config.num_crtc;
1078         dcrtc->clk = ERR_PTR(-EINVAL);
1079         dcrtc->csc_yuv_mode = CSC_AUTO;
1080         dcrtc->csc_rgb_mode = CSC_AUTO;
1081         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1082         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1083         spin_lock_init(&dcrtc->irq_lock);
1084         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1085         INIT_LIST_HEAD(&dcrtc->vbl_list);
1086         init_waitqueue_head(&dcrtc->frame_wait);
1087
1088         /* Initialize some registers which we don't otherwise set */
1089         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1090         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1091         writel_relaxed(dcrtc->spu_iopad_ctrl,
1092                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1093         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1094         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1095                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1096                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1097         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1098         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1099         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1100         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1101
1102         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1103                                dcrtc);
1104         if (ret < 0) {
1105                 kfree(dcrtc);
1106                 return ret;
1107         }
1108
1109         if (dcrtc->variant->init) {
1110                 ret = dcrtc->variant->init(dcrtc, dev);
1111                 if (ret) {
1112                         kfree(dcrtc);
1113                         return ret;
1114                 }
1115         }
1116
1117         /* Ensure AXI pipeline is enabled */
1118         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1119
1120         priv->dcrtc[dcrtc->num] = dcrtc;
1121
1122         dcrtc->crtc.port = port;
1123         drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs);
1124         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1125
1126         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1127                                    dcrtc->csc_yuv_mode);
1128         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1129                                    dcrtc->csc_rgb_mode);
1130
1131         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1132 }
1133
1134 static int
1135 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1136 {
1137         struct platform_device *pdev = to_platform_device(dev);
1138         struct drm_device *drm = data;
1139         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1140         int irq = platform_get_irq(pdev, 0);
1141         const struct armada_variant *variant;
1142         struct device_node *port = NULL;
1143
1144         if (irq < 0)
1145                 return irq;
1146
1147         if (!dev->of_node) {
1148                 const struct platform_device_id *id;
1149
1150                 id = platform_get_device_id(pdev);
1151                 if (!id)
1152                         return -ENXIO;
1153
1154                 variant = (const struct armada_variant *)id->driver_data;
1155         } else {
1156                 const struct of_device_id *match;
1157                 struct device_node *np, *parent = dev->of_node;
1158
1159                 match = of_match_device(dev->driver->of_match_table, dev);
1160                 if (!match)
1161                         return -ENXIO;
1162
1163                 np = of_get_child_by_name(parent, "ports");
1164                 if (np)
1165                         parent = np;
1166                 port = of_get_child_by_name(parent, "port");
1167                 of_node_put(np);
1168                 if (!port) {
1169                         dev_err(dev, "no port node found in %s\n",
1170                                 parent->full_name);
1171                         return -ENXIO;
1172                 }
1173
1174                 variant = match->data;
1175         }
1176
1177         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1178 }
1179
1180 static void
1181 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1182 {
1183         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1184
1185         armada_drm_crtc_destroy(&dcrtc->crtc);
1186 }
1187
1188 static const struct component_ops armada_lcd_ops = {
1189         .bind = armada_lcd_bind,
1190         .unbind = armada_lcd_unbind,
1191 };
1192
1193 static int armada_lcd_probe(struct platform_device *pdev)
1194 {
1195         return component_add(&pdev->dev, &armada_lcd_ops);
1196 }
1197
1198 static int armada_lcd_remove(struct platform_device *pdev)
1199 {
1200         component_del(&pdev->dev, &armada_lcd_ops);
1201         return 0;
1202 }
1203
1204 static struct of_device_id armada_lcd_of_match[] = {
1205         {
1206                 .compatible     = "marvell,dove-lcd",
1207                 .data           = &armada510_ops,
1208         },
1209         {}
1210 };
1211 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1212
1213 static const struct platform_device_id armada_lcd_platform_ids[] = {
1214         {
1215                 .name           = "armada-lcd",
1216                 .driver_data    = (unsigned long)&armada510_ops,
1217         }, {
1218                 .name           = "armada-510-lcd",
1219                 .driver_data    = (unsigned long)&armada510_ops,
1220         },
1221         { },
1222 };
1223 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1224
1225 struct platform_driver armada_lcd_platform_driver = {
1226         .probe  = armada_lcd_probe,
1227         .remove = armada_lcd_remove,
1228         .driver = {
1229                 .name   = "armada-lcd",
1230                 .owner  =  THIS_MODULE,
1231                 .of_match_table = armada_lcd_of_match,
1232         },
1233         .id_table = armada_lcd_platform_ids,
1234 };