kernel/drivers/gpu/drm/amd/amdkfd/cik_regs.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef CIK_REGS_H
  24 #define CIK_REGS_H
  25
  26 #define IH_VMID_0_LUT                                   0x3D40u
  27
  28 #define BIF_DOORBELL_CNTL                               0x530Cu
  29
  30 #define SRBM_GFX_CNTL                                   0xE44
  31 #define PIPEID(x)                                       ((x) << 0)
  32 #define MEID(x)                                         ((x) << 2)
  33 #define VMID(x)                                         ((x) << 4)
  34 #define QUEUEID(x)                                      ((x) << 8)
  35
  36 #define SQ_CONFIG                                       0x8C00
  37
  38 #define SH_MEM_BASES                                    0x8C28
  39 /* if PTR32, these are the bases for scratch and lds */
  40 #define PRIVATE_BASE(x)                                 ((x) << 0) /* scratch */
  41 #define SHARED_BASE(x)                                  ((x) << 16) /* LDS */
  42 #define SH_MEM_APE1_BASE                                0x8C2C
  43 /* if PTR32, this is the base location of GPUVM */
  44 #define SH_MEM_APE1_LIMIT                               0x8C30
  45 /* if PTR32, this is the upper limit of GPUVM */
  46 #define SH_MEM_CONFIG                                   0x8C34
  47 #define PTR32                                           (1 << 0)
  48 #define PRIVATE_ATC                                     (1 << 1)
  49 #define ALIGNMENT_MODE(x)                               ((x) << 2)
  50 #define SH_MEM_ALIGNMENT_MODE_DWORD                     0
  51 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT              1
  52 #define SH_MEM_ALIGNMENT_MODE_STRICT                    2
  53 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED                 3
  54 #define DEFAULT_MTYPE(x)                                ((x) << 4)
  55 #define APE1_MTYPE(x)                                   ((x) << 7)
  56
  57 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
  58 #define MTYPE_CACHED                                    0
  59 #define MTYPE_NONCACHED                                 3
  60
  61
  62 #define SH_STATIC_MEM_CONFIG                            0x9604u
  63
  64 #define TC_CFG_L1_LOAD_POLICY0                          0xAC68
  65 #define TC_CFG_L1_LOAD_POLICY1                          0xAC6C
  66 #define TC_CFG_L1_STORE_POLICY                          0xAC70
  67 #define TC_CFG_L2_LOAD_POLICY0                          0xAC74
  68 #define TC_CFG_L2_LOAD_POLICY1                          0xAC78
  69 #define TC_CFG_L2_STORE_POLICY0                         0xAC7C
  70 #define TC_CFG_L2_STORE_POLICY1                         0xAC80
  71 #define TC_CFG_L2_ATOMIC_POLICY                         0xAC84
  72 #define TC_CFG_L1_VOLATILE                              0xAC88
  73 #define TC_CFG_L2_VOLATILE                              0xAC8C
  74
  75 #define CP_PQ_WPTR_POLL_CNTL                            0xC20C
  76 #define WPTR_POLL_EN                                    (1 << 31)
  77
  78 #define CPC_INT_CNTL                                    0xC2D0
  79 #define CP_ME1_PIPE0_INT_CNTL                           0xC214
  80 #define CP_ME1_PIPE1_INT_CNTL                           0xC218
  81 #define CP_ME1_PIPE2_INT_CNTL                           0xC21C
  82 #define CP_ME1_PIPE3_INT_CNTL                           0xC220
  83 #define CP_ME2_PIPE0_INT_CNTL                           0xC224
  84 #define CP_ME2_PIPE1_INT_CNTL                           0xC228
  85 #define CP_ME2_PIPE2_INT_CNTL                           0xC22C
  86 #define CP_ME2_PIPE3_INT_CNTL                           0xC230
  87 #define DEQUEUE_REQUEST_INT_ENABLE                      (1 << 13)
  88 #define WRM_POLL_TIMEOUT_INT_ENABLE                     (1 << 17)
  89 #define PRIV_REG_INT_ENABLE                             (1 << 23)
  90 #define TIME_STAMP_INT_ENABLE                           (1 << 26)
  91 #define GENERIC2_INT_ENABLE                             (1 << 29)
  92 #define GENERIC1_INT_ENABLE                             (1 << 30)
  93 #define GENERIC0_INT_ENABLE                             (1 << 31)
  94 #define CP_ME1_PIPE0_INT_STATUS                         0xC214
  95 #define CP_ME1_PIPE1_INT_STATUS                         0xC218
  96 #define CP_ME1_PIPE2_INT_STATUS                         0xC21C
  97 #define CP_ME1_PIPE3_INT_STATUS                         0xC220
  98 #define CP_ME2_PIPE0_INT_STATUS                         0xC224
  99 #define CP_ME2_PIPE1_INT_STATUS                         0xC228
 100 #define CP_ME2_PIPE2_INT_STATUS                         0xC22C
 101 #define CP_ME2_PIPE3_INT_STATUS                         0xC230
 102 #define DEQUEUE_REQUEST_INT_STATUS                      (1 << 13)
 103 #define WRM_POLL_TIMEOUT_INT_STATUS                     (1 << 17)
 104 #define PRIV_REG_INT_STATUS                             (1 << 23)
 105 #define TIME_STAMP_INT_STATUS                           (1 << 26)
 106 #define GENERIC2_INT_STATUS                             (1 << 29)
 107 #define GENERIC1_INT_STATUS                             (1 << 30)
 108 #define GENERIC0_INT_STATUS                             (1 << 31)
 109
 110 #define CP_HPD_EOP_BASE_ADDR                            0xC904
 111 #define CP_HPD_EOP_BASE_ADDR_HI                         0xC908
 112 #define CP_HPD_EOP_VMID                                 0xC90C
 113 #define CP_HPD_EOP_CONTROL                              0xC910
 114 #define EOP_SIZE(x)                                     ((x) << 0)
 115 #define EOP_SIZE_MASK                                   (0x3f << 0)
 116 #define CP_MQD_BASE_ADDR                                0xC914
 117 #define CP_MQD_BASE_ADDR_HI                             0xC918
 118 #define CP_HQD_ACTIVE                                   0xC91C
 119 #define CP_HQD_VMID                                     0xC920
 120
 121 #define CP_HQD_PERSISTENT_STATE                         0xC924u
 122 #define DEFAULT_CP_HQD_PERSISTENT_STATE                 (0x33U << 8)
 123 #define PRELOAD_REQ                                     (1 << 0)
 124
 125 #define CP_HQD_PIPE_PRIORITY                            0xC928u
 126 #define CP_HQD_QUEUE_PRIORITY                           0xC92Cu
 127 #define CP_HQD_QUANTUM                                  0xC930u
 128 #define QUANTUM_EN                                      1U
 129 #define QUANTUM_SCALE_1MS                               (1U << 4)
 130 #define QUANTUM_DURATION(x)                             ((x) << 8)
 131
 132 #define CP_HQD_PQ_BASE                                  0xC934
 133 #define CP_HQD_PQ_BASE_HI                               0xC938
 134 #define CP_HQD_PQ_RPTR                                  0xC93C
 135 #define CP_HQD_PQ_RPTR_REPORT_ADDR                      0xC940
 136 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI                   0xC944
 137 #define CP_HQD_PQ_WPTR_POLL_ADDR                        0xC948
 138 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI                     0xC94C
 139 #define CP_HQD_PQ_DOORBELL_CONTROL                      0xC950
 140 #define DOORBELL_OFFSET(x)                              ((x) << 2)
 141 #define DOORBELL_OFFSET_MASK                            (0x1fffff << 2)
 142 #define DOORBELL_SOURCE                                 (1 << 28)
 143 #define DOORBELL_SCHD_HIT                               (1 << 29)
 144 #define DOORBELL_EN                                     (1 << 30)
 145 #define DOORBELL_HIT                                    (1 << 31)
 146 #define CP_HQD_PQ_WPTR                                  0xC954
 147 #define CP_HQD_PQ_CONTROL                               0xC958
 148 #define QUEUE_SIZE(x)                                   ((x) << 0)
 149 #define QUEUE_SIZE_MASK                                 (0x3f << 0)
 150 #define RPTR_BLOCK_SIZE(x)                              ((x) << 8)
 151 #define RPTR_BLOCK_SIZE_MASK                            (0x3f << 8)
 152 #define MIN_AVAIL_SIZE(x)                               ((x) << 20)
 153 #define PQ_ATC_EN                                       (1 << 23)
 154 #define PQ_VOLATILE                                     (1 << 26)
 155 #define NO_UPDATE_RPTR                                  (1 << 27)
 156 #define UNORD_DISPATCH                                  (1 << 28)
 157 #define ROQ_PQ_IB_FLIP                                  (1 << 29)
 158 #define PRIV_STATE                                      (1 << 30)
 159 #define KMD_QUEUE                                       (1 << 31)
 160
 161 #define DEFAULT_RPTR_BLOCK_SIZE                         RPTR_BLOCK_SIZE(5)
 162 #define DEFAULT_MIN_AVAIL_SIZE                          MIN_AVAIL_SIZE(3)
 163
 164 #define CP_HQD_IB_BASE_ADDR                             0xC95Cu
 165 #define CP_HQD_IB_BASE_ADDR_HI                          0xC960u
 166 #define CP_HQD_IB_RPTR                                  0xC964u
 167 #define CP_HQD_IB_CONTROL                               0xC968u
 168 #define IB_ATC_EN                                       (1U << 23)
 169 #define DEFAULT_MIN_IB_AVAIL_SIZE                       (3U << 20)
 170
 171 #define AQL_ENABLE                                      1
 172
 173 #define CP_HQD_DEQUEUE_REQUEST                          0xC974
 174 #define DEQUEUE_REQUEST_DRAIN                           1
 175 #define DEQUEUE_REQUEST_RESET                           2
 176 #define         DEQUEUE_INT                                     (1U << 8)
 177
 178 #define CP_HQD_SEMA_CMD                                 0xC97Cu
 179 #define CP_HQD_MSG_TYPE                                 0xC980u
 180 #define CP_HQD_ATOMIC0_PREOP_LO                         0xC984u
 181 #define CP_HQD_ATOMIC0_PREOP_HI                         0xC988u
 182 #define CP_HQD_ATOMIC1_PREOP_LO                         0xC98Cu
 183 #define CP_HQD_ATOMIC1_PREOP_HI                         0xC990u
 184 #define CP_HQD_HQ_SCHEDULER0                            0xC994u
 185 #define CP_HQD_HQ_SCHEDULER1                            0xC998u
 186
 187
 188 #define CP_MQD_CONTROL                                  0xC99C
 189 #define MQD_VMID(x)                                     ((x) << 0)
 190 #define MQD_VMID_MASK                                   (0xf << 0)
 191 #define MQD_CONTROL_PRIV_STATE_EN                       (1U << 8)
 192
 193 #define SDMA_RB_VMID(x)                                 (x << 24)
 194 #define SDMA_RB_ENABLE                                  (1 << 0)
 195 #define SDMA_RB_SIZE(x)                                 ((x) << 1) /* log2 */
 196 #define SDMA_RPTR_WRITEBACK_ENABLE                      (1 << 12)
 197 #define SDMA_RPTR_WRITEBACK_TIMER(x)                    ((x) << 16) /* log2 */
 198 #define SDMA_OFFSET(x)                                  (x << 0)
 199 #define SDMA_DB_ENABLE                                  (1 << 28)
 200 #define SDMA_ATC                                        (1 << 0)
 201 #define SDMA_VA_PTR32                                   (1 << 4)
 202 #define SDMA_VA_SHARED_BASE(x)                          (x << 8)
 203
 204 #define GRBM_GFX_INDEX                                  0x30800
 205 #define INSTANCE_INDEX(x)                               ((x) << 0)
 206 #define SH_INDEX(x)                                     ((x) << 8)
 207 #define SE_INDEX(x)                                     ((x) << 16)
 208 #define SH_BROADCAST_WRITES                             (1 << 29)
 209 #define INSTANCE_BROADCAST_WRITES                       (1 << 30)
 210 #define SE_BROADCAST_WRITES                             (1 << 31)
 211
 212 #define SQC_CACHES                                      0x30d20
 213 #define SQC_POLICY                                      0x8C38u
 214 #define SQC_VOLATILE                                    0x8C3Cu
 215
 216 #define CP_PERFMON_CNTL                                 0x36020
 217
 218 #define ATC_VMID0_PASID_MAPPING                         0x339Cu
 219 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS            0x3398u
 220 #define ATC_VMID_PASID_MAPPING_VALID                    (1U << 31)
 221
 222 #define ATC_VM_APERTURE0_CNTL                           0x3310u
 223 #define ATS_ACCESS_MODE_NEVER                           0
 224 #define ATS_ACCESS_MODE_ALWAYS                          1
 225
 226 #define ATC_VM_APERTURE0_CNTL2                          0x3318u
 227 #define ATC_VM_APERTURE0_HIGH_ADDR                      0x3308u
 228 #define ATC_VM_APERTURE0_LOW_ADDR                       0x3300u
 229 #define ATC_VM_APERTURE1_CNTL                           0x3314u
 230 #define ATC_VM_APERTURE1_CNTL2                          0x331Cu
 231 #define ATC_VM_APERTURE1_HIGH_ADDR                      0x330Cu
 232 #define ATC_VM_APERTURE1_LOW_ADDR                       0x3304u
 233
 234 #endif