kernel/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  72         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  73 };
  74
  75 /*
  76  * sDMA - System DMA
  77  * Starting with CIK, the GPU has new asynchronous
  78  * DMA engines.  These engines are used for compute
  79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  80  * and each one supports 1 ring buffer used for gfx
  81  * and 2 queues used for compute.
  82  *
  83  * The programming model is very similar to the CP
  84  * (ring buffer, IBs, etc.), but sDMA has it's own
  85  * packet format that is different from the PM4 format
  86  * used by the CP. sDMA supports copying data, writing
  87  * embedded data, solid fills, and a number of other
  88  * things.  It also has support for tiling/detiling of
  89  * buffers.
  90  */
  91
  92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  93 {
  94         switch (adev->asic_type) {
  95         case CHIP_TOPAZ:
  96                 amdgpu_program_register_sequence(adev,
  97                                                  iceland_mgcg_cgcg_init,
  98                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  99                 amdgpu_program_register_sequence(adev,
 100                                                  golden_settings_iceland_a11,
 101                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 /**
 109  * sdma_v2_4_init_microcode - load ucode images from disk
 110  *
 111  * @adev: amdgpu_device pointer
 112  *
 113  * Use the firmware interface to load the ucode images into
 114  * the driver (not loaded into hw).
 115  * Returns 0 on success, error on failure.
 116  */
 117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 118 {
 119         const char *chip_name;
 120         char fw_name[30];
 121         int err = 0, i;
 122         struct amdgpu_firmware_info *info = NULL;
 123         const struct common_firmware_header *header = NULL;
 124         const struct sdma_firmware_header_v1_0 *hdr;
 125
 126         DRM_DEBUG("\n");
 127
 128         switch (adev->asic_type) {
 129         case CHIP_TOPAZ:
 130                 chip_name = "topaz";
 131                 break;
 132         default: BUG();
 133         }
 134
 135         for (i = 0; i < adev->sdma.num_instances; i++) {
 136                 if (i == 0)
 137                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 138                 else
 139                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 140                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 141                 if (err)
 142                         goto out;
 143                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 144                 if (err)
 145                         goto out;
 146                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 147                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 148                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 149                 if (adev->sdma.instance[i].feature_version >= 20)
 150                         adev->sdma.instance[i].burst_nop = true;
 151
 152                 if (adev->firmware.smu_load) {
 153                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 154                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 155                         info->fw = adev->sdma.instance[i].fw;
 156                         header = (const struct common_firmware_header *)info->fw->data;
 157                         adev->firmware.fw_size +=
 158                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 159                 }
 160         }
 161
 162 out:
 163         if (err) {
 164                 printk(KERN_ERR
 165                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 166                        fw_name);
 167                 for (i = 0; i < adev->sdma.num_instances; i++) {
 168                         release_firmware(adev->sdma.instance[i].fw);
 169                         adev->sdma.instance[i].fw = NULL;
 170                 }
 171         }
 172         return err;
 173 }
 174
 175 /**
 176  * sdma_v2_4_ring_get_rptr - get the current read pointer
 177  *
 178  * @ring: amdgpu ring pointer
 179  *
 180  * Get the current rptr from the hardware (VI+).
 181  */
 182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 183 {
 184         u32 rptr;
 185
 186         /* XXX check if swapping is necessary on BE */
 187         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 188
 189         return rptr;
 190 }
 191
 192 /**
 193  * sdma_v2_4_ring_get_wptr - get the current write pointer
 194  *
 195  * @ring: amdgpu ring pointer
 196  *
 197  * Get the current wptr from the hardware (VI+).
 198  */
 199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 200 {
 201         struct amdgpu_device *adev = ring->adev;
 202         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 203         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 204
 205         return wptr;
 206 }
 207
 208 /**
 209  * sdma_v2_4_ring_set_wptr - commit the write pointer
 210  *
 211  * @ring: amdgpu ring pointer
 212  *
 213  * Write the wptr back to the hardware (VI+).
 214  */
 215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 216 {
 217         struct amdgpu_device *adev = ring->adev;
 218         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 219
 220         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 221 }
 222
 223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 224 {
 225         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 226         int i;
 227
 228         for (i = 0; i < count; i++)
 229                 if (sdma && sdma->burst_nop && (i == 0))
 230                         amdgpu_ring_write(ring, ring->nop |
 231                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 232                 else
 233                         amdgpu_ring_write(ring, ring->nop);
 234 }
 235
 236 /**
 237  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 238  *
 239  * @ring: amdgpu ring pointer
 240  * @ib: IB object to schedule
 241  *
 242  * Schedule an IB in the DMA ring (VI).
 243  */
 244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 245                                    struct amdgpu_ib *ib)
 246 {
 247         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 248         u32 next_rptr = ring->wptr + 5;
 249
 250         while ((next_rptr & 7) != 2)
 251                 next_rptr++;
 252
 253         next_rptr += 6;
 254
 255         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 256                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 257         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 258         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 259         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 260         amdgpu_ring_write(ring, next_rptr);
 261
 262         /* IB packet must end on a 8 DW boundary */
 263         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 264
 265         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 266                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 267         /* base must be 32 byte aligned */
 268         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 269         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 270         amdgpu_ring_write(ring, ib->length_dw);
 271         amdgpu_ring_write(ring, 0);
 272         amdgpu_ring_write(ring, 0);
 273
 274 }
 275
 276 /**
 277  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 278  *
 279  * @ring: amdgpu ring pointer
 280  *
 281  * Emit an hdp flush packet on the requested DMA ring.
 282  */
 283 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 284 {
 285         u32 ref_and_mask = 0;
 286
 287         if (ring == &ring->adev->sdma.instance[0].ring)
 288                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 289         else
 290                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 291
 292         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 293                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 294                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 295         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 296         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 297         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 298         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 299         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 300                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 301 }
 302
 303 /**
 304  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 305  *
 306  * @ring: amdgpu ring pointer
 307  * @fence: amdgpu fence object
 308  *
 309  * Add a DMA fence packet to the ring to write
 310  * the fence seq number and DMA trap packet to generate
 311  * an interrupt if needed (VI).
 312  */
 313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 314                                       unsigned flags)
 315 {
 316         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 317         /* write the fence */
 318         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 319         amdgpu_ring_write(ring, lower_32_bits(addr));
 320         amdgpu_ring_write(ring, upper_32_bits(addr));
 321         amdgpu_ring_write(ring, lower_32_bits(seq));
 322
 323         /* optionally write high bits as well */
 324         if (write64bit) {
 325                 addr += 4;
 326                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 327                 amdgpu_ring_write(ring, lower_32_bits(addr));
 328                 amdgpu_ring_write(ring, upper_32_bits(addr));
 329                 amdgpu_ring_write(ring, upper_32_bits(seq));
 330         }
 331
 332         /* generate an interrupt */
 333         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 334         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 335 }
 336
 337 /**
 338  * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
 339  *
 340  * @ring: amdgpu_ring structure holding ring information
 341  * @semaphore: amdgpu semaphore object
 342  * @emit_wait: wait or signal semaphore
 343  *
 344  * Add a DMA semaphore packet to the ring wait on or signal
 345  * other rings (VI).
 346  */
 347 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
 348                                           struct amdgpu_semaphore *semaphore,
 349                                           bool emit_wait)
 350 {
 351         u64 addr = semaphore->gpu_addr;
 352         u32 sig = emit_wait ? 0 : 1;
 353
 354         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 355                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 356         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 357         amdgpu_ring_write(ring, upper_32_bits(addr));
 358
 359         return true;
 360 }
 361
 362 /**
 363  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 364  *
 365  * @adev: amdgpu_device pointer
 366  *
 367  * Stop the gfx async dma ring buffers (VI).
 368  */
 369 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 370 {
 371         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 372         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 373         u32 rb_cntl, ib_cntl;
 374         int i;
 375
 376         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 377             (adev->mman.buffer_funcs_ring == sdma1))
 378                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 379
 380         for (i = 0; i < adev->sdma.num_instances; i++) {
 381                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 382                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 383                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 384                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 385                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 386                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 387         }
 388         sdma0->ready = false;
 389         sdma1->ready = false;
 390 }
 391
 392 /**
 393  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 394  *
 395  * @adev: amdgpu_device pointer
 396  *
 397  * Stop the compute async dma queues (VI).
 398  */
 399 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 400 {
 401         /* XXX todo */
 402 }
 403
 404 /**
 405  * sdma_v2_4_enable - stop the async dma engines
 406  *
 407  * @adev: amdgpu_device pointer
 408  * @enable: enable/disable the DMA MEs.
 409  *
 410  * Halt or unhalt the async dma engines (VI).
 411  */
 412 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 413 {
 414         u32 f32_cntl;
 415         int i;
 416
 417         if (enable == false) {
 418                 sdma_v2_4_gfx_stop(adev);
 419                 sdma_v2_4_rlc_stop(adev);
 420         }
 421
 422         for (i = 0; i < adev->sdma.num_instances; i++) {
 423                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 424                 if (enable)
 425                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 426                 else
 427                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 428                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 429         }
 430 }
 431
 432 /**
 433  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 434  *
 435  * @adev: amdgpu_device pointer
 436  *
 437  * Set up the gfx DMA ring buffers and enable them (VI).
 438  * Returns 0 for success, error for failure.
 439  */
 440 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 441 {
 442         struct amdgpu_ring *ring;
 443         u32 rb_cntl, ib_cntl;
 444         u32 rb_bufsz;
 445         u32 wb_offset;
 446         int i, j, r;
 447
 448         for (i = 0; i < adev->sdma.num_instances; i++) {
 449                 ring = &adev->sdma.instance[i].ring;
 450                 wb_offset = (ring->rptr_offs * 4);
 451
 452                 mutex_lock(&adev->srbm_mutex);
 453                 for (j = 0; j < 16; j++) {
 454                         vi_srbm_select(adev, 0, 0, 0, j);
 455                         /* SDMA GFX */
 456                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 457                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 458                 }
 459                 vi_srbm_select(adev, 0, 0, 0, 0);
 460                 mutex_unlock(&adev->srbm_mutex);
 461
 462                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 463
 464                 /* Set ring buffer size in dwords */
 465                 rb_bufsz = order_base_2(ring->ring_size / 4);
 466                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 467                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 468 #ifdef __BIG_ENDIAN
 469                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 470                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 471                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 472 #endif
 473                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 474
 475                 /* Initialize the ring buffer's read and write pointers */
 476                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 477                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 478
 479                 /* set the wb address whether it's enabled or not */
 480                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 481                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 482                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 483                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 484
 485                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 486
 487                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 488                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 489
 490                 ring->wptr = 0;
 491                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 492
 493                 /* enable DMA RB */
 494                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 495                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 496
 497                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 498                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 499 #ifdef __BIG_ENDIAN
 500                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 501 #endif
 502                 /* enable DMA IBs */
 503                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 504
 505                 ring->ready = true;
 506
 507                 r = amdgpu_ring_test_ring(ring);
 508                 if (r) {
 509                         ring->ready = false;
 510                         return r;
 511                 }
 512
 513                 if (adev->mman.buffer_funcs_ring == ring)
 514                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 515         }
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 522  *
 523  * @adev: amdgpu_device pointer
 524  *
 525  * Set up the compute DMA queues and enable them (VI).
 526  * Returns 0 for success, error for failure.
 527  */
 528 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 529 {
 530         /* XXX todo */
 531         return 0;
 532 }
 533
 534 /**
 535  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 536  *
 537  * @adev: amdgpu_device pointer
 538  *
 539  * Loads the sDMA0/1 ucode.
 540  * Returns 0 for success, -EINVAL if the ucode is not available.
 541  */
 542 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 543 {
 544         const struct sdma_firmware_header_v1_0 *hdr;
 545         const __le32 *fw_data;
 546         u32 fw_size;
 547         int i, j;
 548
 549         /* halt the MEs */
 550         sdma_v2_4_enable(adev, false);
 551
 552         for (i = 0; i < adev->sdma.num_instances; i++) {
 553                 if (!adev->sdma.instance[i].fw)
 554                         return -EINVAL;
 555                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 556                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 557                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 558                 fw_data = (const __le32 *)
 559                         (adev->sdma.instance[i].fw->data +
 560                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 561                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 562                 for (j = 0; j < fw_size; j++)
 563                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 564                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 565         }
 566
 567         return 0;
 568 }
 569
 570 /**
 571  * sdma_v2_4_start - setup and start the async dma engines
 572  *
 573  * @adev: amdgpu_device pointer
 574  *
 575  * Set up the DMA engines and enable them (VI).
 576  * Returns 0 for success, error for failure.
 577  */
 578 static int sdma_v2_4_start(struct amdgpu_device *adev)
 579 {
 580         int r;
 581
 582         if (!adev->firmware.smu_load) {
 583                 r = sdma_v2_4_load_microcode(adev);
 584                 if (r)
 585                         return r;
 586         } else {
 587                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 588                                                 AMDGPU_UCODE_ID_SDMA0);
 589                 if (r)
 590                         return -EINVAL;
 591                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 592                                                 AMDGPU_UCODE_ID_SDMA1);
 593                 if (r)
 594                         return -EINVAL;
 595         }
 596
 597         /* unhalt the MEs */
 598         sdma_v2_4_enable(adev, true);
 599
 600         /* start the gfx rings and rlc compute queues */
 601         r = sdma_v2_4_gfx_resume(adev);
 602         if (r)
 603                 return r;
 604         r = sdma_v2_4_rlc_resume(adev);
 605         if (r)
 606                 return r;
 607
 608         return 0;
 609 }
 610
 611 /**
 612  * sdma_v2_4_ring_test_ring - simple async dma engine test
 613  *
 614  * @ring: amdgpu_ring structure holding ring information
 615  *
 616  * Test the DMA engine by writing using it to write an
 617  * value to memory. (VI).
 618  * Returns 0 for success, error for failure.
 619  */
 620 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 621 {
 622         struct amdgpu_device *adev = ring->adev;
 623         unsigned i;
 624         unsigned index;
 625         int r;
 626         u32 tmp;
 627         u64 gpu_addr;
 628
 629         r = amdgpu_wb_get(adev, &index);
 630         if (r) {
 631                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 632                 return r;
 633         }
 634
 635         gpu_addr = adev->wb.gpu_addr + (index * 4);
 636         tmp = 0xCAFEDEAD;
 637         adev->wb.wb[index] = cpu_to_le32(tmp);
 638
 639         r = amdgpu_ring_lock(ring, 5);
 640         if (r) {
 641                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 642                 amdgpu_wb_free(adev, index);
 643                 return r;
 644         }
 645
 646         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 647                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 648         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 649         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 650         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 651         amdgpu_ring_write(ring, 0xDEADBEEF);
 652         amdgpu_ring_unlock_commit(ring);
 653
 654         for (i = 0; i < adev->usec_timeout; i++) {
 655                 tmp = le32_to_cpu(adev->wb.wb[index]);
 656                 if (tmp == 0xDEADBEEF)
 657                         break;
 658                 DRM_UDELAY(1);
 659         }
 660
 661         if (i < adev->usec_timeout) {
 662                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 663         } else {
 664                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 665                           ring->idx, tmp);
 666                 r = -EINVAL;
 667         }
 668         amdgpu_wb_free(adev, index);
 669
 670         return r;
 671 }
 672
 673 /**
 674  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 675  *
 676  * @ring: amdgpu_ring structure holding ring information
 677  *
 678  * Test a simple IB in the DMA ring (VI).
 679  * Returns 0 on success, error on failure.
 680  */
 681 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 682 {
 683         struct amdgpu_device *adev = ring->adev;
 684         struct amdgpu_ib ib;
 685         struct fence *f = NULL;
 686         unsigned i;
 687         unsigned index;
 688         int r;
 689         u32 tmp = 0;
 690         u64 gpu_addr;
 691
 692         r = amdgpu_wb_get(adev, &index);
 693         if (r) {
 694                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 695                 return r;
 696         }
 697
 698         gpu_addr = adev->wb.gpu_addr + (index * 4);
 699         tmp = 0xCAFEDEAD;
 700         adev->wb.wb[index] = cpu_to_le32(tmp);
 701         memset(&ib, 0, sizeof(ib));
 702         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 703         if (r) {
 704                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 705                 goto err0;
 706         }
 707
 708         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 709                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 710         ib.ptr[1] = lower_32_bits(gpu_addr);
 711         ib.ptr[2] = upper_32_bits(gpu_addr);
 712         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 713         ib.ptr[4] = 0xDEADBEEF;
 714         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 715         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 716         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 717         ib.length_dw = 8;
 718
 719         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 720                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 721                                                  &f);
 722         if (r)
 723                 goto err1;
 724
 725         r = fence_wait(f, false);
 726         if (r) {
 727                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 728                 goto err1;
 729         }
 730         for (i = 0; i < adev->usec_timeout; i++) {
 731                 tmp = le32_to_cpu(adev->wb.wb[index]);
 732                 if (tmp == 0xDEADBEEF)
 733                         break;
 734                 DRM_UDELAY(1);
 735         }
 736         if (i < adev->usec_timeout) {
 737                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 738                          ring->idx, i);
 739                 goto err1;
 740         } else {
 741                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 742                 r = -EINVAL;
 743         }
 744
 745 err1:
 746         fence_put(f);
 747         amdgpu_ib_free(adev, &ib);
 748 err0:
 749         amdgpu_wb_free(adev, index);
 750         return r;
 751 }
 752
 753 /**
 754  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 755  *
 756  * @ib: indirect buffer to fill with commands
 757  * @pe: addr of the page entry
 758  * @src: src addr to copy from
 759  * @count: number of page entries to update
 760  *
 761  * Update PTEs by copying them from the GART using sDMA (CIK).
 762  */
 763 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 764                                   uint64_t pe, uint64_t src,
 765                                   unsigned count)
 766 {
 767         while (count) {
 768                 unsigned bytes = count * 8;
 769                 if (bytes > 0x1FFFF8)
 770                         bytes = 0x1FFFF8;
 771
 772                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 773                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 774                 ib->ptr[ib->length_dw++] = bytes;
 775                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 776                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 777                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 778                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 779                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 780
 781                 pe += bytes;
 782                 src += bytes;
 783                 count -= bytes / 8;
 784         }
 785 }
 786
 787 /**
 788  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 789  *
 790  * @ib: indirect buffer to fill with commands
 791  * @pe: addr of the page entry
 792  * @addr: dst addr to write into pe
 793  * @count: number of page entries to update
 794  * @incr: increase next addr by incr bytes
 795  * @flags: access flags
 796  *
 797  * Update PTEs by writing them manually using sDMA (CIK).
 798  */
 799 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 800                                    uint64_t pe,
 801                                    uint64_t addr, unsigned count,
 802                                    uint32_t incr, uint32_t flags)
 803 {
 804         uint64_t value;
 805         unsigned ndw;
 806
 807         while (count) {
 808                 ndw = count * 2;
 809                 if (ndw > 0xFFFFE)
 810                         ndw = 0xFFFFE;
 811
 812                 /* for non-physically contiguous pages (system) */
 813                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 814                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 815                 ib->ptr[ib->length_dw++] = pe;
 816                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 817                 ib->ptr[ib->length_dw++] = ndw;
 818                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 819                         if (flags & AMDGPU_PTE_SYSTEM) {
 820                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 821                                 value &= 0xFFFFFFFFFFFFF000ULL;
 822                         } else if (flags & AMDGPU_PTE_VALID) {
 823                                 value = addr;
 824                         } else {
 825                                 value = 0;
 826                         }
 827                         addr += incr;
 828                         value |= flags;
 829                         ib->ptr[ib->length_dw++] = value;
 830                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 831                 }
 832         }
 833 }
 834
 835 /**
 836  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 837  *
 838  * @ib: indirect buffer to fill with commands
 839  * @pe: addr of the page entry
 840  * @addr: dst addr to write into pe
 841  * @count: number of page entries to update
 842  * @incr: increase next addr by incr bytes
 843  * @flags: access flags
 844  *
 845  * Update the page tables using sDMA (CIK).
 846  */
 847 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 848                                      uint64_t pe,
 849                                      uint64_t addr, unsigned count,
 850                                      uint32_t incr, uint32_t flags)
 851 {
 852         uint64_t value;
 853         unsigned ndw;
 854
 855         while (count) {
 856                 ndw = count;
 857                 if (ndw > 0x7FFFF)
 858                         ndw = 0x7FFFF;
 859
 860                 if (flags & AMDGPU_PTE_VALID)
 861                         value = addr;
 862                 else
 863                         value = 0;
 864
 865                 /* for physically contiguous pages (vram) */
 866                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 867                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 868                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 869                 ib->ptr[ib->length_dw++] = flags; /* mask */
 870                 ib->ptr[ib->length_dw++] = 0;
 871                 ib->ptr[ib->length_dw++] = value; /* value */
 872                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 873                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 874                 ib->ptr[ib->length_dw++] = 0;
 875                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 876
 877                 pe += ndw * 8;
 878                 addr += ndw * incr;
 879                 count -= ndw;
 880         }
 881 }
 882
 883 /**
 884  * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
 885  *
 886  * @ib: indirect buffer to fill with padding
 887  *
 888  */
 889 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 890 {
 891         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
 892         u32 pad_count;
 893         int i;
 894
 895         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 896         for (i = 0; i < pad_count; i++)
 897                 if (sdma && sdma->burst_nop && (i == 0))
 898                         ib->ptr[ib->length_dw++] =
 899                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 900                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 901                 else
 902                         ib->ptr[ib->length_dw++] =
 903                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 904 }
 905
 906 /**
 907  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 908  *
 909  * @ring: amdgpu_ring pointer
 910  * @vm: amdgpu_vm pointer
 911  *
 912  * Update the page table base and flush the VM TLB
 913  * using sDMA (VI).
 914  */
 915 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 916                                          unsigned vm_id, uint64_t pd_addr)
 917 {
 918         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 919                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 920         if (vm_id < 8) {
 921                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 922         } else {
 923                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 924         }
 925         amdgpu_ring_write(ring, pd_addr >> 12);
 926
 927         /* flush TLB */
 928         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 929                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 930         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 931         amdgpu_ring_write(ring, 1 << vm_id);
 932
 933         /* wait for flush */
 934         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 935                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 936                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 937         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 938         amdgpu_ring_write(ring, 0);
 939         amdgpu_ring_write(ring, 0); /* reference */
 940         amdgpu_ring_write(ring, 0); /* mask */
 941         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 942                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 943 }
 944
 945 static int sdma_v2_4_early_init(void *handle)
 946 {
 947         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 948
 949         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 950
 951         sdma_v2_4_set_ring_funcs(adev);
 952         sdma_v2_4_set_buffer_funcs(adev);
 953         sdma_v2_4_set_vm_pte_funcs(adev);
 954         sdma_v2_4_set_irq_funcs(adev);
 955
 956         return 0;
 957 }
 958
 959 static int sdma_v2_4_sw_init(void *handle)
 960 {
 961         struct amdgpu_ring *ring;
 962         int r, i;
 963         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 964
 965         /* SDMA trap event */
 966         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 967         if (r)
 968                 return r;
 969
 970         /* SDMA Privileged inst */
 971         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 972         if (r)
 973                 return r;
 974
 975         /* SDMA Privileged inst */
 976         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 977         if (r)
 978                 return r;
 979
 980         r = sdma_v2_4_init_microcode(adev);
 981         if (r) {
 982                 DRM_ERROR("Failed to load sdma firmware!\n");
 983                 return r;
 984         }
 985
 986         for (i = 0; i < adev->sdma.num_instances; i++) {
 987                 ring = &adev->sdma.instance[i].ring;
 988                 ring->ring_obj = NULL;
 989                 ring->use_doorbell = false;
 990                 sprintf(ring->name, "sdma%d", i);
 991                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 992                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
 993                                      &adev->sdma.trap_irq,
 994                                      (i == 0) ?
 995                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 996                                      AMDGPU_RING_TYPE_SDMA);
 997                 if (r)
 998                         return r;
 999         }
1000
1001         return r;
1002 }
1003
1004 static int sdma_v2_4_sw_fini(void *handle)
1005 {
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007         int i;
1008
1009         for (i = 0; i < adev->sdma.num_instances; i++)
1010                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1011
1012         return 0;
1013 }
1014
1015 static int sdma_v2_4_hw_init(void *handle)
1016 {
1017         int r;
1018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019
1020         sdma_v2_4_init_golden_registers(adev);
1021
1022         r = sdma_v2_4_start(adev);
1023         if (r)
1024                 return r;
1025
1026         return r;
1027 }
1028
1029 static int sdma_v2_4_hw_fini(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032
1033         sdma_v2_4_enable(adev, false);
1034
1035         return 0;
1036 }
1037
1038 static int sdma_v2_4_suspend(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         return sdma_v2_4_hw_fini(adev);
1043 }
1044
1045 static int sdma_v2_4_resume(void *handle)
1046 {
1047         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048
1049         return sdma_v2_4_hw_init(adev);
1050 }
1051
1052 static bool sdma_v2_4_is_idle(void *handle)
1053 {
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055         u32 tmp = RREG32(mmSRBM_STATUS2);
1056
1057         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1058                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1059             return false;
1060
1061         return true;
1062 }
1063
1064 static int sdma_v2_4_wait_for_idle(void *handle)
1065 {
1066         unsigned i;
1067         u32 tmp;
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
1070         for (i = 0; i < adev->usec_timeout; i++) {
1071                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1072                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1073
1074                 if (!tmp)
1075                         return 0;
1076                 udelay(1);
1077         }
1078         return -ETIMEDOUT;
1079 }
1080
1081 static void sdma_v2_4_print_status(void *handle)
1082 {
1083         int i, j;
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         dev_info(adev->dev, "VI SDMA registers\n");
1087         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1088                  RREG32(mmSRBM_STATUS2));
1089         for (i = 0; i < adev->sdma.num_instances; i++) {
1090                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1091                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1092                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1093                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1094                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1095                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1096                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1097                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1098                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1099                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1100                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1101                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1102                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1103                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1104                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1105                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1106                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1107                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1108                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1109                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1110                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1111                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1112                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1113                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1114                 mutex_lock(&adev->srbm_mutex);
1115                 for (j = 0; j < 16; j++) {
1116                         vi_srbm_select(adev, 0, 0, 0, j);
1117                         dev_info(adev->dev, "  VM %d:\n", j);
1118                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1119                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1120                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1121                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1122                 }
1123                 vi_srbm_select(adev, 0, 0, 0, 0);
1124                 mutex_unlock(&adev->srbm_mutex);
1125         }
1126 }
1127
1128 static int sdma_v2_4_soft_reset(void *handle)
1129 {
1130         u32 srbm_soft_reset = 0;
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132         u32 tmp = RREG32(mmSRBM_STATUS2);
1133
1134         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1135                 /* sdma0 */
1136                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1137                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1138                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1139                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1140         }
1141         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1142                 /* sdma1 */
1143                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1144                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1145                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1146                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1147         }
1148
1149         if (srbm_soft_reset) {
1150                 sdma_v2_4_print_status((void *)adev);
1151
1152                 tmp = RREG32(mmSRBM_SOFT_RESET);
1153                 tmp |= srbm_soft_reset;
1154                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1155                 WREG32(mmSRBM_SOFT_RESET, tmp);
1156                 tmp = RREG32(mmSRBM_SOFT_RESET);
1157
1158                 udelay(50);
1159
1160                 tmp &= ~srbm_soft_reset;
1161                 WREG32(mmSRBM_SOFT_RESET, tmp);
1162                 tmp = RREG32(mmSRBM_SOFT_RESET);
1163
1164                 /* Wait a little for things to settle down */
1165                 udelay(50);
1166
1167                 sdma_v2_4_print_status((void *)adev);
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1174                                         struct amdgpu_irq_src *src,
1175                                         unsigned type,
1176                                         enum amdgpu_interrupt_state state)
1177 {
1178         u32 sdma_cntl;
1179
1180         switch (type) {
1181         case AMDGPU_SDMA_IRQ_TRAP0:
1182                 switch (state) {
1183                 case AMDGPU_IRQ_STATE_DISABLE:
1184                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1185                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1186                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1187                         break;
1188                 case AMDGPU_IRQ_STATE_ENABLE:
1189                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1190                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1191                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1192                         break;
1193                 default:
1194                         break;
1195                 }
1196                 break;
1197         case AMDGPU_SDMA_IRQ_TRAP1:
1198                 switch (state) {
1199                 case AMDGPU_IRQ_STATE_DISABLE:
1200                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1201                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1202                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1203                         break;
1204                 case AMDGPU_IRQ_STATE_ENABLE:
1205                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1206                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1207                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1208                         break;
1209                 default:
1210                         break;
1211                 }
1212                 break;
1213         default:
1214                 break;
1215         }
1216         return 0;
1217 }
1218
1219 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1220                                       struct amdgpu_irq_src *source,
1221                                       struct amdgpu_iv_entry *entry)
1222 {
1223         u8 instance_id, queue_id;
1224
1225         instance_id = (entry->ring_id & 0x3) >> 0;
1226         queue_id = (entry->ring_id & 0xc) >> 2;
1227         DRM_DEBUG("IH: SDMA trap\n");
1228         switch (instance_id) {
1229         case 0:
1230                 switch (queue_id) {
1231                 case 0:
1232                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1233                         break;
1234                 case 1:
1235                         /* XXX compute */
1236                         break;
1237                 case 2:
1238                         /* XXX compute */
1239                         break;
1240                 }
1241                 break;
1242         case 1:
1243                 switch (queue_id) {
1244                 case 0:
1245                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1246                         break;
1247                 case 1:
1248                         /* XXX compute */
1249                         break;
1250                 case 2:
1251                         /* XXX compute */
1252                         break;
1253                 }
1254                 break;
1255         }
1256         return 0;
1257 }
1258
1259 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1260                                               struct amdgpu_irq_src *source,
1261                                               struct amdgpu_iv_entry *entry)
1262 {
1263         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1264         schedule_work(&adev->reset_work);
1265         return 0;
1266 }
1267
1268 static int sdma_v2_4_set_clockgating_state(void *handle,
1269                                           enum amd_clockgating_state state)
1270 {
1271         /* XXX handled via the smc on VI */
1272         return 0;
1273 }
1274
1275 static int sdma_v2_4_set_powergating_state(void *handle,
1276                                           enum amd_powergating_state state)
1277 {
1278         return 0;
1279 }
1280
1281 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1282         .early_init = sdma_v2_4_early_init,
1283         .late_init = NULL,
1284         .sw_init = sdma_v2_4_sw_init,
1285         .sw_fini = sdma_v2_4_sw_fini,
1286         .hw_init = sdma_v2_4_hw_init,
1287         .hw_fini = sdma_v2_4_hw_fini,
1288         .suspend = sdma_v2_4_suspend,
1289         .resume = sdma_v2_4_resume,
1290         .is_idle = sdma_v2_4_is_idle,
1291         .wait_for_idle = sdma_v2_4_wait_for_idle,
1292         .soft_reset = sdma_v2_4_soft_reset,
1293         .print_status = sdma_v2_4_print_status,
1294         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1295         .set_powergating_state = sdma_v2_4_set_powergating_state,
1296 };
1297
1298 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1299         .get_rptr = sdma_v2_4_ring_get_rptr,
1300         .get_wptr = sdma_v2_4_ring_get_wptr,
1301         .set_wptr = sdma_v2_4_ring_set_wptr,
1302         .parse_cs = NULL,
1303         .emit_ib = sdma_v2_4_ring_emit_ib,
1304         .emit_fence = sdma_v2_4_ring_emit_fence,
1305         .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1306         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1307         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1308         .test_ring = sdma_v2_4_ring_test_ring,
1309         .test_ib = sdma_v2_4_ring_test_ib,
1310         .insert_nop = sdma_v2_4_ring_insert_nop,
1311 };
1312
1313 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1314 {
1315         int i;
1316
1317         for (i = 0; i < adev->sdma.num_instances; i++)
1318                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1319 }
1320
1321 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1322         .set = sdma_v2_4_set_trap_irq_state,
1323         .process = sdma_v2_4_process_trap_irq,
1324 };
1325
1326 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1327         .process = sdma_v2_4_process_illegal_inst_irq,
1328 };
1329
1330 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1331 {
1332         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1333         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1334         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1335 }
1336
1337 /**
1338  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1339  *
1340  * @ring: amdgpu_ring structure holding ring information
1341  * @src_offset: src GPU address
1342  * @dst_offset: dst GPU address
1343  * @byte_count: number of bytes to xfer
1344  *
1345  * Copy GPU buffers using the DMA engine (VI).
1346  * Used by the amdgpu ttm implementation to move pages if
1347  * registered as the asic copy callback.
1348  */
1349 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1350                                        uint64_t src_offset,
1351                                        uint64_t dst_offset,
1352                                        uint32_t byte_count)
1353 {
1354         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1355                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1356         ib->ptr[ib->length_dw++] = byte_count;
1357         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1358         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1359         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1360         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1361         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1362 }
1363
1364 /**
1365  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1366  *
1367  * @ring: amdgpu_ring structure holding ring information
1368  * @src_data: value to write to buffer
1369  * @dst_offset: dst GPU address
1370  * @byte_count: number of bytes to xfer
1371  *
1372  * Fill GPU buffers using the DMA engine (VI).
1373  */
1374 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1375                                        uint32_t src_data,
1376                                        uint64_t dst_offset,
1377                                        uint32_t byte_count)
1378 {
1379         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1380         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1381         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1382         ib->ptr[ib->length_dw++] = src_data;
1383         ib->ptr[ib->length_dw++] = byte_count;
1384 }
1385
1386 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1387         .copy_max_bytes = 0x1fffff,
1388         .copy_num_dw = 7,
1389         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1390
1391         .fill_max_bytes = 0x1fffff,
1392         .fill_num_dw = 7,
1393         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1394 };
1395
1396 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1397 {
1398         if (adev->mman.buffer_funcs == NULL) {
1399                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1400                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1401         }
1402 }
1403
1404 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1405         .copy_pte = sdma_v2_4_vm_copy_pte,
1406         .write_pte = sdma_v2_4_vm_write_pte,
1407         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1408         .pad_ib = sdma_v2_4_vm_pad_ib,
1409 };
1410
1411 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1412 {
1413         if (adev->vm_manager.vm_pte_funcs == NULL) {
1414                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1415                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1416                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1417         }
1418 }