kernel/drivers/gpu/drm/amd/amdgpu/kv_dpm.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __KV_DPM_H__
  24 #define __KV_DPM_H__
  25
  26 #define SMU__NUM_SCLK_DPM_STATE  8
  27 #define SMU__NUM_MCLK_DPM_LEVELS 4
  28 #define SMU__NUM_LCLK_DPM_LEVELS 8
  29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
  30 #include "smu7_fusion.h"
  31 #include "ppsmc.h"
  32
  33 #define SUMO_MAX_HARDWARE_POWERLEVELS 5
  34
  35 #define SUMO_MAX_NUMBER_VOLTAGES    4
  36
  37 struct sumo_vid_mapping_entry {
  38         u16 vid_2bit;
  39         u16 vid_7bit;
  40 };
  41
  42 struct sumo_vid_mapping_table {
  43         u32 num_entries;
  44         struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
  45 };
  46
  47 struct sumo_sclk_voltage_mapping_entry {
  48         u32 sclk_frequency;
  49         u16 vid_2bit;
  50         u16 rsv;
  51 };
  52
  53 struct sumo_sclk_voltage_mapping_table {
  54         u32 num_max_dpm_entries;
  55         struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
  56 };
  57
  58 #define TRINITY_AT_DFLT            30
  59
  60 #define KV_NUM_NBPSTATES   4
  61
  62 enum kv_pt_config_reg_type {
  63         KV_CONFIGREG_MMR = 0,
  64         KV_CONFIGREG_SMC_IND,
  65         KV_CONFIGREG_DIDT_IND,
  66         KV_CONFIGREG_CACHE,
  67         KV_CONFIGREG_MAX
  68 };
  69
  70 struct kv_pt_config_reg {
  71         u32 offset;
  72         u32 mask;
  73         u32 shift;
  74         u32 value;
  75         enum kv_pt_config_reg_type type;
  76 };
  77
  78 struct kv_lcac_config_values {
  79         u32 block_id;
  80         u32 signal_id;
  81         u32 t;
  82 };
  83
  84 struct kv_lcac_config_reg {
  85         u32 cntl;
  86         u32 block_mask;
  87         u32 block_shift;
  88         u32 signal_mask;
  89         u32 signal_shift;
  90         u32 t_mask;
  91         u32 t_shift;
  92         u32 enable_mask;
  93         u32 enable_shift;
  94 };
  95
  96 struct kv_pl {
  97         u32 sclk;
  98         u8 vddc_index;
  99         u8 ds_divider_index;
 100         u8 ss_divider_index;
 101         u8 allow_gnb_slow;
 102         u8 force_nbp_state;
 103         u8 display_wm;
 104         u8 vce_wm;
 105 };
 106
 107 struct kv_ps {
 108         struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
 109         u32 num_levels;
 110         bool need_dfs_bypass;
 111         u8 dpm0_pg_nb_ps_lo;
 112         u8 dpm0_pg_nb_ps_hi;
 113         u8 dpmx_nb_ps_lo;
 114         u8 dpmx_nb_ps_hi;
 115 };
 116
 117 struct kv_sys_info {
 118         u32 bootup_uma_clk;
 119         u32 bootup_sclk;
 120         u32 dentist_vco_freq;
 121         u32 nb_dpm_enable;
 122         u32 nbp_memory_clock[KV_NUM_NBPSTATES];
 123         u32 nbp_n_clock[KV_NUM_NBPSTATES];
 124         u16 bootup_nb_voltage_index;
 125         u8 htc_tmp_lmt;
 126         u8 htc_hyst_lmt;
 127         struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
 128         struct sumo_vid_mapping_table vid_mapping_table;
 129         u32 uma_channel_number;
 130 };
 131
 132 struct kv_power_info {
 133         u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
 134         u32 voltage_drop_t;
 135         struct kv_sys_info sys_info;
 136         struct kv_pl boot_pl;
 137         bool enable_nb_ps_policy;
 138         bool disable_nb_ps3_in_battery;
 139         bool video_start;
 140         bool battery_state;
 141         u32 lowest_valid;
 142         u32 highest_valid;
 143         u16 high_voltage_t;
 144         bool cac_enabled;
 145         bool bapm_enable;
 146         /* smc offsets */
 147         u32 sram_end;
 148         u32 dpm_table_start;
 149         u32 soft_regs_start;
 150         /* dpm SMU tables */
 151         u8 graphics_dpm_level_count;
 152         u8 uvd_level_count;
 153         u8 vce_level_count;
 154         u8 acp_level_count;
 155         u8 samu_level_count;
 156         u16 fps_high_t;
 157         SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
 158         SMU7_Fusion_ACPILevel acpi_level;
 159         SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
 160         SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
 161         SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
 162         SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
 163         u8 uvd_boot_level;
 164         u8 vce_boot_level;
 165         u8 acp_boot_level;
 166         u8 samu_boot_level;
 167         u8 uvd_interval;
 168         u8 vce_interval;
 169         u8 acp_interval;
 170         u8 samu_interval;
 171         u8 graphics_boot_level;
 172         u8 graphics_interval;
 173         u8 graphics_therm_throttle_enable;
 174         u8 graphics_voltage_change_enable;
 175         u8 graphics_clk_slow_enable;
 176         u8 graphics_clk_slow_divider;
 177         u8 fps_low_t;
 178         u32 low_sclk_interrupt_t;
 179         bool uvd_power_gated;
 180         bool vce_power_gated;
 181         bool acp_power_gated;
 182         bool samu_power_gated;
 183         bool nb_dpm_enabled;
 184         /* flags */
 185         bool enable_didt;
 186         bool enable_dpm;
 187         bool enable_auto_thermal_throttling;
 188         bool enable_nb_dpm;
 189         /* caps */
 190         bool caps_cac;
 191         bool caps_power_containment;
 192         bool caps_sq_ramping;
 193         bool caps_db_ramping;
 194         bool caps_td_ramping;
 195         bool caps_tcp_ramping;
 196         bool caps_sclk_throttle_low_notification;
 197         bool caps_fps;
 198         bool caps_uvd_dpm;
 199         bool caps_uvd_pg;
 200         bool caps_vce_pg;
 201         bool caps_samu_pg;
 202         bool caps_acp_pg;
 203         bool caps_stable_p_state;
 204         bool caps_enable_dfs_bypass;
 205         bool caps_sclk_ds;
 206         struct amdgpu_ps current_rps;
 207         struct kv_ps current_ps;
 208         struct amdgpu_ps requested_rps;
 209         struct kv_ps requested_ps;
 210 };
 211
 212 /* XXX are these ok? */
 213 #define KV_TEMP_RANGE_MIN (90 * 1000)
 214 #define KV_TEMP_RANGE_MAX (120 * 1000)
 215
 216 /* kv_smc.c */
 217 int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id);
 218 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
 219 int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 220                                       PPSMC_Msg msg, u32 parameter);
 221 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
 222                            u32 *value, u32 limit);
 223 int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);
 224 int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);
 225 int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev,
 226                          u32 smc_start_address,
 227                          const u8 *src, u32 byte_count, u32 limit);
 228
 229 #endif