kernel/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44
  45 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  46
  47 static const u32 golden_settings_tonga_a11[] =
  48 {
  49         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  50         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  51         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  52         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56 };
  57
  58 static const u32 tonga_mgcg_cgcg_init[] =
  59 {
  60         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  61 };
  62
  63 static const u32 golden_settings_fiji_a10[] =
  64 {
  65         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  67         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  68         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69 };
  70
  71 static const u32 fiji_mgcg_cgcg_init[] =
  72 {
  73         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  74 };
  75
  76 static const u32 cz_mgcg_cgcg_init[] =
  77 {
  78         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  79 };
  80
  81 static const u32 stoney_mgcg_cgcg_init[] =
  82 {
  83         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  84 };
  85
  86
  87 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
  88 {
  89         switch (adev->asic_type) {
  90         case CHIP_FIJI:
  91                 amdgpu_program_register_sequence(adev,
  92                                                  fiji_mgcg_cgcg_init,
  93                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
  94                 amdgpu_program_register_sequence(adev,
  95                                                  golden_settings_fiji_a10,
  96                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
  97                 break;
  98         case CHIP_TONGA:
  99                 amdgpu_program_register_sequence(adev,
 100                                                  tonga_mgcg_cgcg_init,
 101                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 102                 amdgpu_program_register_sequence(adev,
 103                                                  golden_settings_tonga_a11,
 104                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 105                 break;
 106         case CHIP_CARRIZO:
 107                 amdgpu_program_register_sequence(adev,
 108                                                  cz_mgcg_cgcg_init,
 109                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 110                 break;
 111         case CHIP_STONEY:
 112                 amdgpu_program_register_sequence(adev,
 113                                                  stoney_mgcg_cgcg_init,
 114                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 115                 break;
 116         default:
 117                 break;
 118         }
 119 }
 120
 121 /**
 122  * gmc8_mc_wait_for_idle - wait for MC idle callback.
 123  *
 124  * @adev: amdgpu_device pointer
 125  *
 126  * Wait for the MC (memory controller) to be idle.
 127  * (evergreen+).
 128  * Returns 0 if the MC is idle, -1 if not.
 129  */
 130 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
 131 {
 132         unsigned i;
 133         u32 tmp;
 134
 135         for (i = 0; i < adev->usec_timeout; i++) {
 136                 /* read MC_STATUS */
 137                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
 138                                                SRBM_STATUS__MCB_BUSY_MASK |
 139                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 140                                                SRBM_STATUS__MCC_BUSY_MASK |
 141                                                SRBM_STATUS__MCD_BUSY_MASK |
 142                                                SRBM_STATUS__VMC1_BUSY_MASK);
 143                 if (!tmp)
 144                         return 0;
 145                 udelay(1);
 146         }
 147         return -1;
 148 }
 149
 150 void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 151                       struct amdgpu_mode_mc_save *save)
 152 {
 153         u32 blackout;
 154
 155         if (adev->mode_info.num_crtc)
 156                 amdgpu_display_stop_mc_access(adev, save);
 157
 158         amdgpu_asic_wait_for_mc_idle(adev);
 159
 160         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 161         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 162                 /* Block CPU access */
 163                 WREG32(mmBIF_FB_EN, 0);
 164                 /* blackout the MC */
 165                 blackout = REG_SET_FIELD(blackout,
 166                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 167                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 168         }
 169         /* wait for the MC to settle */
 170         udelay(100);
 171 }
 172
 173 void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 174                         struct amdgpu_mode_mc_save *save)
 175 {
 176         u32 tmp;
 177
 178         /* unblackout the MC */
 179         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 180         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 181         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 182         /* allow CPU access */
 183         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 184         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 185         WREG32(mmBIF_FB_EN, tmp);
 186
 187         if (adev->mode_info.num_crtc)
 188                 amdgpu_display_resume_mc_access(adev, save);
 189 }
 190
 191 /**
 192  * gmc_v8_0_init_microcode - load ucode images from disk
 193  *
 194  * @adev: amdgpu_device pointer
 195  *
 196  * Use the firmware interface to load the ucode images into
 197  * the driver (not loaded into hw).
 198  * Returns 0 on success, error on failure.
 199  */
 200 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 201 {
 202         const char *chip_name;
 203         char fw_name[30];
 204         int err;
 205
 206         DRM_DEBUG("\n");
 207
 208         switch (adev->asic_type) {
 209         case CHIP_TONGA:
 210                 chip_name = "tonga";
 211                 break;
 212         case CHIP_FIJI:
 213         case CHIP_CARRIZO:
 214         case CHIP_STONEY:
 215                 return 0;
 216         default: BUG();
 217         }
 218
 219         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 220         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 221         if (err)
 222                 goto out;
 223         err = amdgpu_ucode_validate(adev->mc.fw);
 224
 225 out:
 226         if (err) {
 227                 printk(KERN_ERR
 228                        "mc: Failed to load firmware \"%s\"\n",
 229                        fw_name);
 230                 release_firmware(adev->mc.fw);
 231                 adev->mc.fw = NULL;
 232         }
 233         return err;
 234 }
 235
 236 /**
 237  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 238  *
 239  * @adev: amdgpu_device pointer
 240  *
 241  * Load the GDDR MC ucode into the hw (CIK).
 242  * Returns 0 on success, error on failure.
 243  */
 244 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 245 {
 246         const struct mc_firmware_header_v1_0 *hdr;
 247         const __le32 *fw_data = NULL;
 248         const __le32 *io_mc_regs = NULL;
 249         u32 running, blackout = 0;
 250         int i, ucode_size, regs_size;
 251
 252         if (!adev->mc.fw)
 253                 return -EINVAL;
 254
 255         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 256         amdgpu_ucode_print_mc_hdr(&hdr->header);
 257
 258         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 259         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 260         io_mc_regs = (const __le32 *)
 261                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 262         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 263         fw_data = (const __le32 *)
 264                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 265
 266         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 267
 268         if (running == 0) {
 269                 if (running) {
 270                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 271                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 272                 }
 273
 274                 /* reset the engine and set to writable */
 275                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 276                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 277
 278                 /* load mc io regs */
 279                 for (i = 0; i < regs_size; i++) {
 280                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 281                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 282                 }
 283                 /* load the MC ucode */
 284                 for (i = 0; i < ucode_size; i++)
 285                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 286
 287                 /* put the engine back into the active state */
 288                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 289                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 290                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 291
 292                 /* wait for training to complete */
 293                 for (i = 0; i < adev->usec_timeout; i++) {
 294                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 295                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 296                                 break;
 297                         udelay(1);
 298                 }
 299                 for (i = 0; i < adev->usec_timeout; i++) {
 300                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 301                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 302                                 break;
 303                         udelay(1);
 304                 }
 305
 306                 if (running)
 307                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 308         }
 309
 310         return 0;
 311 }
 312
 313 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 314                                        struct amdgpu_mc *mc)
 315 {
 316         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 317                 /* leave room for at least 1024M GTT */
 318                 dev_warn(adev->dev, "limiting VRAM\n");
 319                 mc->real_vram_size = 0xFFC0000000ULL;
 320                 mc->mc_vram_size = 0xFFC0000000ULL;
 321         }
 322         amdgpu_vram_location(adev, &adev->mc, 0);
 323         adev->mc.gtt_base_align = 0;
 324         amdgpu_gtt_location(adev, mc);
 325 }
 326
 327 /**
 328  * gmc_v8_0_mc_program - program the GPU memory controller
 329  *
 330  * @adev: amdgpu_device pointer
 331  *
 332  * Set the location of vram, gart, and AGP in the GPU's
 333  * physical address space (CIK).
 334  */
 335 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 336 {
 337         struct amdgpu_mode_mc_save save;
 338         u32 tmp;
 339         int i, j;
 340
 341         /* Initialize HDP */
 342         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 343                 WREG32((0xb05 + j), 0x00000000);
 344                 WREG32((0xb06 + j), 0x00000000);
 345                 WREG32((0xb07 + j), 0x00000000);
 346                 WREG32((0xb08 + j), 0x00000000);
 347                 WREG32((0xb09 + j), 0x00000000);
 348         }
 349         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 350
 351         if (adev->mode_info.num_crtc)
 352                 amdgpu_display_set_vga_render_state(adev, false);
 353
 354         gmc_v8_0_mc_stop(adev, &save);
 355         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 356                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 357         }
 358         /* Update configuration */
 359         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 360                adev->mc.vram_start >> 12);
 361         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 362                adev->mc.vram_end >> 12);
 363         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 364                adev->vram_scratch.gpu_addr >> 12);
 365         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 366         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 367         WREG32(mmMC_VM_FB_LOCATION, tmp);
 368         /* XXX double check these! */
 369         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 370         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 371         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 372         WREG32(mmMC_VM_AGP_BASE, 0);
 373         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 374         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 375         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 376                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 377         }
 378         gmc_v8_0_mc_resume(adev, &save);
 379
 380         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 381
 382         tmp = RREG32(mmHDP_MISC_CNTL);
 383         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 384         WREG32(mmHDP_MISC_CNTL, tmp);
 385
 386         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 387         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 388 }
 389
 390 /**
 391  * gmc_v8_0_mc_init - initialize the memory controller driver params
 392  *
 393  * @adev: amdgpu_device pointer
 394  *
 395  * Look up the amount of vram, vram width, and decide how to place
 396  * vram and gart within the GPU's physical address space (CIK).
 397  * Returns 0 for success.
 398  */
 399 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 400 {
 401         u32 tmp;
 402         int chansize, numchan;
 403
 404         /* Get VRAM informations */
 405         tmp = RREG32(mmMC_ARB_RAMCFG);
 406         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 407                 chansize = 64;
 408         } else {
 409                 chansize = 32;
 410         }
 411         tmp = RREG32(mmMC_SHARED_CHMAP);
 412         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 413         case 0:
 414         default:
 415                 numchan = 1;
 416                 break;
 417         case 1:
 418                 numchan = 2;
 419                 break;
 420         case 2:
 421                 numchan = 4;
 422                 break;
 423         case 3:
 424                 numchan = 8;
 425                 break;
 426         case 4:
 427                 numchan = 3;
 428                 break;
 429         case 5:
 430                 numchan = 6;
 431                 break;
 432         case 6:
 433                 numchan = 10;
 434                 break;
 435         case 7:
 436                 numchan = 12;
 437                 break;
 438         case 8:
 439                 numchan = 16;
 440                 break;
 441         }
 442         adev->mc.vram_width = numchan * chansize;
 443         /* Could aper size report 0 ? */
 444         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 445         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 446         /* size in MB on si */
 447         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 448         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 449         adev->mc.visible_vram_size = adev->mc.aper_size;
 450
 451         /* unless the user had overridden it, set the gart
 452          * size equal to the 1024 or vram, whichever is larger.
 453          */
 454         if (amdgpu_gart_size == -1)
 455                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 456         else
 457                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 458
 459         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 460
 461         return 0;
 462 }
 463
 464 /*
 465  * GART
 466  * VMID 0 is the physical GPU addresses as used by the kernel.
 467  * VMIDs 1-15 are used for userspace clients and are handled
 468  * by the amdgpu vm/hsa code.
 469  */
 470
 471 /**
 472  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 473  *
 474  * @adev: amdgpu_device pointer
 475  * @vmid: vm instance to flush
 476  *
 477  * Flush the TLB for the requested page table (CIK).
 478  */
 479 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 480                                         uint32_t vmid)
 481 {
 482         /* flush hdp cache */
 483         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 484
 485         /* bits 0-15 are the VM contexts0-15 */
 486         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 487 }
 488
 489 /**
 490  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 491  *
 492  * @adev: amdgpu_device pointer
 493  * @cpu_pt_addr: cpu address of the page table
 494  * @gpu_page_idx: entry in the page table to update
 495  * @addr: dst addr to write into pte/pde
 496  * @flags: access flags
 497  *
 498  * Update the page tables using the CPU.
 499  */
 500 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 501                                      void *cpu_pt_addr,
 502                                      uint32_t gpu_page_idx,
 503                                      uint64_t addr,
 504                                      uint32_t flags)
 505 {
 506         void __iomem *ptr = (void *)cpu_pt_addr;
 507         uint64_t value;
 508
 509         /*
 510          * PTE format on VI:
 511          * 63:40 reserved
 512          * 39:12 4k physical page base address
 513          * 11:7 fragment
 514          * 6 write
 515          * 5 read
 516          * 4 exe
 517          * 3 reserved
 518          * 2 snooped
 519          * 1 system
 520          * 0 valid
 521          *
 522          * PDE format on VI:
 523          * 63:59 block fragment size
 524          * 58:40 reserved
 525          * 39:1 physical base address of PTE
 526          * bits 5:1 must be 0.
 527          * 0 valid
 528          */
 529         value = addr & 0x000000FFFFFFF000ULL;
 530         value |= flags;
 531         writeq(value, ptr + (gpu_page_idx * 8));
 532
 533         return 0;
 534 }
 535
 536 /**
 537  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 538  *
 539  * @adev: amdgpu_device pointer
 540  * @value: true redirects VM faults to the default page
 541  */
 542 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 543                                               bool value)
 544 {
 545         u32 tmp;
 546
 547         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 548         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 549                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 550         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 551                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 552         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 553                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 554         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 555                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 556         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 557                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 558         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 559                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 560         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 561                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 562         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 563 }
 564
 565 /**
 566  * gmc_v8_0_gart_enable - gart enable
 567  *
 568  * @adev: amdgpu_device pointer
 569  *
 570  * This sets up the TLBs, programs the page tables for VMID0,
 571  * sets up the hw for VMIDs 1-15 which are allocated on
 572  * demand, and sets up the global locations for the LDS, GDS,
 573  * and GPUVM for FSA64 clients (CIK).
 574  * Returns 0 for success, errors for failure.
 575  */
 576 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 577 {
 578         int r, i;
 579         u32 tmp;
 580
 581         if (adev->gart.robj == NULL) {
 582                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 583                 return -EINVAL;
 584         }
 585         r = amdgpu_gart_table_vram_pin(adev);
 586         if (r)
 587                 return r;
 588         /* Setup TLB control */
 589         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 590         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 591         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 592         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 593         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 594         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 595         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 596         /* Setup L2 cache */
 597         tmp = RREG32(mmVM_L2_CNTL);
 598         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 599         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 600         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 601         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 602         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 603         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 604         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 605         WREG32(mmVM_L2_CNTL, tmp);
 606         tmp = RREG32(mmVM_L2_CNTL2);
 607         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 608         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 609         WREG32(mmVM_L2_CNTL2, tmp);
 610         tmp = RREG32(mmVM_L2_CNTL3);
 611         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 612         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 613         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 614         WREG32(mmVM_L2_CNTL3, tmp);
 615         /* XXX: set to enable PTE/PDE in system memory */
 616         tmp = RREG32(mmVM_L2_CNTL4);
 617         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 618         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 619         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 620         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 621         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 622         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 623         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 624         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 625         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 626         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 627         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 628         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 629         WREG32(mmVM_L2_CNTL4, tmp);
 630         /* setup context0 */
 631         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 632         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 633         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 634         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 635                         (u32)(adev->dummy_page.addr >> 12));
 636         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 637         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 638         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 639         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 640         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 641         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 642
 643         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 644         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 645         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 646
 647         /* empty context1-15 */
 648         /* FIXME start with 4G, once using 2 level pt switch to full
 649          * vm size space
 650          */
 651         /* set vm size, must be a multiple of 4 */
 652         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 653         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 654         for (i = 1; i < 16; i++) {
 655                 if (i < 8)
 656                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 657                                adev->gart.table_addr >> 12);
 658                 else
 659                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 660                                adev->gart.table_addr >> 12);
 661         }
 662
 663         /* enable context1-15 */
 664         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 665                (u32)(adev->dummy_page.addr >> 12));
 666         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 667         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 668         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 669         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 670         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 671         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 672         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 673         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 674         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 675         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 676         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 677         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 678                             amdgpu_vm_block_size - 9);
 679         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 680         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 681                 gmc_v8_0_set_fault_enable_default(adev, false);
 682         else
 683                 gmc_v8_0_set_fault_enable_default(adev, true);
 684
 685         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 686         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 687                  (unsigned)(adev->mc.gtt_size >> 20),
 688                  (unsigned long long)adev->gart.table_addr);
 689         adev->gart.ready = true;
 690         return 0;
 691 }
 692
 693 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 694 {
 695         int r;
 696
 697         if (adev->gart.robj) {
 698                 WARN(1, "R600 PCIE GART already initialized\n");
 699                 return 0;
 700         }
 701         /* Initialize common gart structure */
 702         r = amdgpu_gart_init(adev);
 703         if (r)
 704                 return r;
 705         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 706         return amdgpu_gart_table_vram_alloc(adev);
 707 }
 708
 709 /**
 710  * gmc_v8_0_gart_disable - gart disable
 711  *
 712  * @adev: amdgpu_device pointer
 713  *
 714  * This disables all VM page table (CIK).
 715  */
 716 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 717 {
 718         u32 tmp;
 719
 720         /* Disable all tables */
 721         WREG32(mmVM_CONTEXT0_CNTL, 0);
 722         WREG32(mmVM_CONTEXT1_CNTL, 0);
 723         /* Setup TLB control */
 724         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 725         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 726         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 727         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 728         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 729         /* Setup L2 cache */
 730         tmp = RREG32(mmVM_L2_CNTL);
 731         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 732         WREG32(mmVM_L2_CNTL, tmp);
 733         WREG32(mmVM_L2_CNTL2, 0);
 734         amdgpu_gart_table_vram_unpin(adev);
 735 }
 736
 737 /**
 738  * gmc_v8_0_gart_fini - vm fini callback
 739  *
 740  * @adev: amdgpu_device pointer
 741  *
 742  * Tears down the driver GART/VM setup (CIK).
 743  */
 744 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 745 {
 746         amdgpu_gart_table_vram_free(adev);
 747         amdgpu_gart_fini(adev);
 748 }
 749
 750 /*
 751  * vm
 752  * VMID 0 is the physical GPU addresses as used by the kernel.
 753  * VMIDs 1-15 are used for userspace clients and are handled
 754  * by the amdgpu vm/hsa code.
 755  */
 756 /**
 757  * gmc_v8_0_vm_init - cik vm init callback
 758  *
 759  * @adev: amdgpu_device pointer
 760  *
 761  * Inits cik specific vm parameters (number of VMs, base of vram for
 762  * VMIDs 1-15) (CIK).
 763  * Returns 0 for success.
 764  */
 765 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 766 {
 767         /*
 768          * number of VMs
 769          * VMID 0 is reserved for System
 770          * amdgpu graphics/compute will use VMIDs 1-7
 771          * amdkfd will use VMIDs 8-15
 772          */
 773         adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
 774
 775         /* base offset of vram pages */
 776         if (adev->flags & AMD_IS_APU) {
 777                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 778                 tmp <<= 22;
 779                 adev->vm_manager.vram_base_offset = tmp;
 780         } else
 781                 adev->vm_manager.vram_base_offset = 0;
 782
 783         return 0;
 784 }
 785
 786 /**
 787  * gmc_v8_0_vm_fini - cik vm fini callback
 788  *
 789  * @adev: amdgpu_device pointer
 790  *
 791  * Tear down any asic specific VM setup (CIK).
 792  */
 793 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 794 {
 795 }
 796
 797 /**
 798  * gmc_v8_0_vm_decode_fault - print human readable fault info
 799  *
 800  * @adev: amdgpu_device pointer
 801  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 802  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 803  *
 804  * Print human readable fault information (CIK).
 805  */
 806 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 807                                      u32 status, u32 addr, u32 mc_client)
 808 {
 809         u32 mc_id;
 810         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 811         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 812                                         PROTECTIONS);
 813         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 814                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 815
 816         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 817                               MEMORY_CLIENT_ID);
 818
 819         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 820                protections, vmid, addr,
 821                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 822                              MEMORY_CLIENT_RW) ?
 823                "write" : "read", block, mc_client, mc_id);
 824 }
 825
 826 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 827 {
 828         switch (mc_seq_vram_type) {
 829         case MC_SEQ_MISC0__MT__GDDR1:
 830                 return AMDGPU_VRAM_TYPE_GDDR1;
 831         case MC_SEQ_MISC0__MT__DDR2:
 832                 return AMDGPU_VRAM_TYPE_DDR2;
 833         case MC_SEQ_MISC0__MT__GDDR3:
 834                 return AMDGPU_VRAM_TYPE_GDDR3;
 835         case MC_SEQ_MISC0__MT__GDDR4:
 836                 return AMDGPU_VRAM_TYPE_GDDR4;
 837         case MC_SEQ_MISC0__MT__GDDR5:
 838                 return AMDGPU_VRAM_TYPE_GDDR5;
 839         case MC_SEQ_MISC0__MT__HBM:
 840                 return AMDGPU_VRAM_TYPE_HBM;
 841         case MC_SEQ_MISC0__MT__DDR3:
 842                 return AMDGPU_VRAM_TYPE_DDR3;
 843         default:
 844                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 845         }
 846 }
 847
 848 static int gmc_v8_0_early_init(void *handle)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 851
 852         gmc_v8_0_set_gart_funcs(adev);
 853         gmc_v8_0_set_irq_funcs(adev);
 854
 855         if (adev->flags & AMD_IS_APU) {
 856                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 857         } else {
 858                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 859                 tmp &= MC_SEQ_MISC0__MT__MASK;
 860                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int gmc_v8_0_late_init(void *handle)
 867 {
 868         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 869
 870         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 871 }
 872
 873 static int gmc_v8_0_sw_init(void *handle)
 874 {
 875         int r;
 876         int dma_bits;
 877         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 878
 879         r = amdgpu_gem_init(adev);
 880         if (r)
 881                 return r;
 882
 883         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 884         if (r)
 885                 return r;
 886
 887         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 888         if (r)
 889                 return r;
 890
 891         /* Adjust VM size here.
 892          * Currently set to 4GB ((1 << 20) 4k pages).
 893          * Max GPUVM size for cayman and SI is 40 bits.
 894          */
 895         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 896
 897         /* Set the internal MC address mask
 898          * This is the max address of the GPU's
 899          * internal address space.
 900          */
 901         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 902
 903         /* set DMA mask + need_dma32 flags.
 904          * PCIE - can handle 40-bits.
 905          * IGP - can handle 40-bits
 906          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 907          */
 908         adev->need_dma32 = false;
 909         dma_bits = adev->need_dma32 ? 32 : 40;
 910         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 911         if (r) {
 912                 adev->need_dma32 = true;
 913                 dma_bits = 32;
 914                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 915         }
 916         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 917         if (r) {
 918                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 919                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 920         }
 921
 922         r = gmc_v8_0_init_microcode(adev);
 923         if (r) {
 924                 DRM_ERROR("Failed to load mc firmware!\n");
 925                 return r;
 926         }
 927
 928         r = gmc_v8_0_mc_init(adev);
 929         if (r)
 930                 return r;
 931
 932         /* Memory manager */
 933         r = amdgpu_bo_init(adev);
 934         if (r)
 935                 return r;
 936
 937         r = gmc_v8_0_gart_init(adev);
 938         if (r)
 939                 return r;
 940
 941         if (!adev->vm_manager.enabled) {
 942                 r = gmc_v8_0_vm_init(adev);
 943                 if (r) {
 944                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 945                         return r;
 946                 }
 947                 adev->vm_manager.enabled = true;
 948         }
 949
 950         return r;
 951 }
 952
 953 static int gmc_v8_0_sw_fini(void *handle)
 954 {
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956
 957         if (adev->vm_manager.enabled) {
 958                 amdgpu_vm_manager_fini(adev);
 959                 gmc_v8_0_vm_fini(adev);
 960                 adev->vm_manager.enabled = false;
 961         }
 962         gmc_v8_0_gart_fini(adev);
 963         amdgpu_gem_fini(adev);
 964         amdgpu_bo_fini(adev);
 965
 966         return 0;
 967 }
 968
 969 static int gmc_v8_0_hw_init(void *handle)
 970 {
 971         int r;
 972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 973
 974         gmc_v8_0_init_golden_registers(adev);
 975
 976         gmc_v8_0_mc_program(adev);
 977
 978         if (adev->asic_type == CHIP_TONGA) {
 979                 r = gmc_v8_0_mc_load_microcode(adev);
 980                 if (r) {
 981                         DRM_ERROR("Failed to load MC firmware!\n");
 982                         return r;
 983                 }
 984         }
 985
 986         r = gmc_v8_0_gart_enable(adev);
 987         if (r)
 988                 return r;
 989
 990         return r;
 991 }
 992
 993 static int gmc_v8_0_hw_fini(void *handle)
 994 {
 995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 996
 997         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 998         gmc_v8_0_gart_disable(adev);
 999
1000         return 0;
1001 }
1002
1003 static int gmc_v8_0_suspend(void *handle)
1004 {
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006
1007         if (adev->vm_manager.enabled) {
1008                 amdgpu_vm_manager_fini(adev);
1009                 gmc_v8_0_vm_fini(adev);
1010                 adev->vm_manager.enabled = false;
1011         }
1012         gmc_v8_0_hw_fini(adev);
1013
1014         return 0;
1015 }
1016
1017 static int gmc_v8_0_resume(void *handle)
1018 {
1019         int r;
1020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021
1022         r = gmc_v8_0_hw_init(adev);
1023         if (r)
1024                 return r;
1025
1026         if (!adev->vm_manager.enabled) {
1027                 r = gmc_v8_0_vm_init(adev);
1028                 if (r) {
1029                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1030                         return r;
1031                 }
1032                 adev->vm_manager.enabled = true;
1033         }
1034
1035         return r;
1036 }
1037
1038 static bool gmc_v8_0_is_idle(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041         u32 tmp = RREG32(mmSRBM_STATUS);
1042
1043         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1044                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1045                 return false;
1046
1047         return true;
1048 }
1049
1050 static int gmc_v8_0_wait_for_idle(void *handle)
1051 {
1052         unsigned i;
1053         u32 tmp;
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         for (i = 0; i < adev->usec_timeout; i++) {
1057                 /* read MC_STATUS */
1058                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1059                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1060                                                SRBM_STATUS__MCC_BUSY_MASK |
1061                                                SRBM_STATUS__MCD_BUSY_MASK |
1062                                                SRBM_STATUS__VMC_BUSY_MASK |
1063                                                SRBM_STATUS__VMC1_BUSY_MASK);
1064                 if (!tmp)
1065                         return 0;
1066                 udelay(1);
1067         }
1068         return -ETIMEDOUT;
1069
1070 }
1071
1072 static void gmc_v8_0_print_status(void *handle)
1073 {
1074         int i, j;
1075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1076
1077         dev_info(adev->dev, "GMC 8.x registers\n");
1078         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
1079                 RREG32(mmSRBM_STATUS));
1080         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1081                 RREG32(mmSRBM_STATUS2));
1082
1083         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1084                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1085         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1086                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1087         dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1088                  RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1089         dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
1090                  RREG32(mmVM_L2_CNTL));
1091         dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
1092                  RREG32(mmVM_L2_CNTL2));
1093         dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
1094                  RREG32(mmVM_L2_CNTL3));
1095         dev_info(adev->dev, "  VM_L2_CNTL4=0x%08X\n",
1096                  RREG32(mmVM_L2_CNTL4));
1097         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1098                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1099         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1100                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1101         dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1102                  RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1103         dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
1104                  RREG32(mmVM_CONTEXT0_CNTL2));
1105         dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
1106                  RREG32(mmVM_CONTEXT0_CNTL));
1107         dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1108                  RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1109         dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1110                  RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1111         dev_info(adev->dev, "  mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1112                  RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1113         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1114                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1115         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1116                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1117         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1118                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1119         dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
1120                  RREG32(mmVM_CONTEXT1_CNTL2));
1121         dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
1122                  RREG32(mmVM_CONTEXT1_CNTL));
1123         for (i = 0; i < 16; i++) {
1124                 if (i < 8)
1125                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1126                                  i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1127                 else
1128                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1129                                  i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1130         }
1131         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1132                  RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1133         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1134                  RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1135         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1136                  RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1137         dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
1138                  RREG32(mmMC_VM_FB_LOCATION));
1139         dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
1140                  RREG32(mmMC_VM_AGP_BASE));
1141         dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
1142                  RREG32(mmMC_VM_AGP_TOP));
1143         dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
1144                  RREG32(mmMC_VM_AGP_BOT));
1145
1146         dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1147                  RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1148         dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
1149                  RREG32(mmHDP_NONSURFACE_BASE));
1150         dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
1151                  RREG32(mmHDP_NONSURFACE_INFO));
1152         dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
1153                  RREG32(mmHDP_NONSURFACE_SIZE));
1154         dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
1155                  RREG32(mmHDP_MISC_CNTL));
1156         dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
1157                  RREG32(mmHDP_HOST_PATH_CNTL));
1158
1159         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1160                 dev_info(adev->dev, "  %d:\n", i);
1161                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1162                          0xb05 + j, RREG32(0xb05 + j));
1163                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1164                          0xb06 + j, RREG32(0xb06 + j));
1165                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1166                          0xb07 + j, RREG32(0xb07 + j));
1167                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1168                          0xb08 + j, RREG32(0xb08 + j));
1169                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1170                          0xb09 + j, RREG32(0xb09 + j));
1171         }
1172
1173         dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
1174                  RREG32(mmBIF_FB_EN));
1175 }
1176
1177 static int gmc_v8_0_soft_reset(void *handle)
1178 {
1179         struct amdgpu_mode_mc_save save;
1180         u32 srbm_soft_reset = 0;
1181         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1182         u32 tmp = RREG32(mmSRBM_STATUS);
1183
1184         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1185                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1186                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1187
1188         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1189                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1190                 if (!(adev->flags & AMD_IS_APU))
1191                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1192                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1193         }
1194
1195         if (srbm_soft_reset) {
1196                 gmc_v8_0_print_status((void *)adev);
1197
1198                 gmc_v8_0_mc_stop(adev, &save);
1199                 if (gmc_v8_0_wait_for_idle(adev)) {
1200                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1201                 }
1202
1203
1204                 tmp = RREG32(mmSRBM_SOFT_RESET);
1205                 tmp |= srbm_soft_reset;
1206                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1207                 WREG32(mmSRBM_SOFT_RESET, tmp);
1208                 tmp = RREG32(mmSRBM_SOFT_RESET);
1209
1210                 udelay(50);
1211
1212                 tmp &= ~srbm_soft_reset;
1213                 WREG32(mmSRBM_SOFT_RESET, tmp);
1214                 tmp = RREG32(mmSRBM_SOFT_RESET);
1215
1216                 /* Wait a little for things to settle down */
1217                 udelay(50);
1218
1219                 gmc_v8_0_mc_resume(adev, &save);
1220                 udelay(50);
1221
1222                 gmc_v8_0_print_status((void *)adev);
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1229                                              struct amdgpu_irq_src *src,
1230                                              unsigned type,
1231                                              enum amdgpu_interrupt_state state)
1232 {
1233         u32 tmp;
1234         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1235                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1236                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1237                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1239                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1240                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1241
1242         switch (state) {
1243         case AMDGPU_IRQ_STATE_DISABLE:
1244                 /* system context */
1245                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246                 tmp &= ~bits;
1247                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248                 /* VMs */
1249                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250                 tmp &= ~bits;
1251                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252                 break;
1253         case AMDGPU_IRQ_STATE_ENABLE:
1254                 /* system context */
1255                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1256                 tmp |= bits;
1257                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1258                 /* VMs */
1259                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1260                 tmp |= bits;
1261                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1262                 break;
1263         default:
1264                 break;
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1271                                       struct amdgpu_irq_src *source,
1272                                       struct amdgpu_iv_entry *entry)
1273 {
1274         u32 addr, status, mc_client;
1275
1276         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1277         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1278         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1279         /* reset addr and status */
1280         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1281
1282         if (!addr && !status)
1283                 return 0;
1284
1285         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1286                 gmc_v8_0_set_fault_enable_default(adev, false);
1287
1288         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1289                 entry->src_id, entry->src_data);
1290         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1291                 addr);
1292         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1293                 status);
1294         gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1295
1296         return 0;
1297 }
1298
1299 static int gmc_v8_0_set_clockgating_state(void *handle,
1300                                           enum amd_clockgating_state state)
1301 {
1302         return 0;
1303 }
1304
1305 static int gmc_v8_0_set_powergating_state(void *handle,
1306                                           enum amd_powergating_state state)
1307 {
1308         return 0;
1309 }
1310
1311 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1312         .early_init = gmc_v8_0_early_init,
1313         .late_init = gmc_v8_0_late_init,
1314         .sw_init = gmc_v8_0_sw_init,
1315         .sw_fini = gmc_v8_0_sw_fini,
1316         .hw_init = gmc_v8_0_hw_init,
1317         .hw_fini = gmc_v8_0_hw_fini,
1318         .suspend = gmc_v8_0_suspend,
1319         .resume = gmc_v8_0_resume,
1320         .is_idle = gmc_v8_0_is_idle,
1321         .wait_for_idle = gmc_v8_0_wait_for_idle,
1322         .soft_reset = gmc_v8_0_soft_reset,
1323         .print_status = gmc_v8_0_print_status,
1324         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1325         .set_powergating_state = gmc_v8_0_set_powergating_state,
1326 };
1327
1328 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1329         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1330         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1331 };
1332
1333 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1334         .set = gmc_v8_0_vm_fault_interrupt_state,
1335         .process = gmc_v8_0_process_interrupt,
1336 };
1337
1338 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1339 {
1340         if (adev->gart.gart_funcs == NULL)
1341                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1342 }
1343
1344 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1345 {
1346         adev->mc.vm_fault.num_types = 1;
1347         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1348 }