kernel/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42
  43 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  44 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  45 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  46
  47 static const u32 golden_settings_iceland_a11[] =
  48 {
  49         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  50         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  51         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  52         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  53 };
  54
  55 static const u32 iceland_mgcg_cgcg_init[] =
  56 {
  57         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  58 };
  59
  60 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  61 {
  62         switch (adev->asic_type) {
  63         case CHIP_TOPAZ:
  64                 amdgpu_program_register_sequence(adev,
  65                                                  iceland_mgcg_cgcg_init,
  66                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  67                 amdgpu_program_register_sequence(adev,
  68                                                  golden_settings_iceland_a11,
  69                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  70                 break;
  71         default:
  72                 break;
  73         }
  74 }
  75
  76 /**
  77  * gmc7_mc_wait_for_idle - wait for MC idle callback.
  78  *
  79  * @adev: amdgpu_device pointer
  80  *
  81  * Wait for the MC (memory controller) to be idle.
  82  * (evergreen+).
  83  * Returns 0 if the MC is idle, -1 if not.
  84  */
  85 int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
  86 {
  87         unsigned i;
  88         u32 tmp;
  89
  90         for (i = 0; i < adev->usec_timeout; i++) {
  91                 /* read MC_STATUS */
  92                 tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
  93                 if (!tmp)
  94                         return 0;
  95                 udelay(1);
  96         }
  97         return -1;
  98 }
  99
 100 void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
 101                       struct amdgpu_mode_mc_save *save)
 102 {
 103         u32 blackout;
 104
 105         if (adev->mode_info.num_crtc)
 106                 amdgpu_display_stop_mc_access(adev, save);
 107
 108         amdgpu_asic_wait_for_mc_idle(adev);
 109
 110         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 111         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 112                 /* Block CPU access */
 113                 WREG32(mmBIF_FB_EN, 0);
 114                 /* blackout the MC */
 115                 blackout = REG_SET_FIELD(blackout,
 116                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 117                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 118         }
 119         /* wait for the MC to settle */
 120         udelay(100);
 121 }
 122
 123 void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 124                         struct amdgpu_mode_mc_save *save)
 125 {
 126         u32 tmp;
 127
 128         /* unblackout the MC */
 129         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 130         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 131         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 132         /* allow CPU access */
 133         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 134         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 135         WREG32(mmBIF_FB_EN, tmp);
 136
 137         if (adev->mode_info.num_crtc)
 138                 amdgpu_display_resume_mc_access(adev, save);
 139 }
 140
 141 /**
 142  * gmc_v7_0_init_microcode - load ucode images from disk
 143  *
 144  * @adev: amdgpu_device pointer
 145  *
 146  * Use the firmware interface to load the ucode images into
 147  * the driver (not loaded into hw).
 148  * Returns 0 on success, error on failure.
 149  */
 150 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 151 {
 152         const char *chip_name;
 153         char fw_name[30];
 154         int err;
 155
 156         DRM_DEBUG("\n");
 157
 158         switch (adev->asic_type) {
 159         case CHIP_BONAIRE:
 160                 chip_name = "bonaire";
 161                 break;
 162         case CHIP_HAWAII:
 163                 chip_name = "hawaii";
 164                 break;
 165         case CHIP_TOPAZ:
 166                 chip_name = "topaz";
 167                 break;
 168         case CHIP_KAVERI:
 169         case CHIP_KABINI:
 170         case CHIP_MULLINS:
 171                 return 0;
 172         default: BUG();
 173         }
 174
 175         if (adev->asic_type == CHIP_TOPAZ)
 176                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 177         else
 178                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 179
 180         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 181         if (err)
 182                 goto out;
 183         err = amdgpu_ucode_validate(adev->mc.fw);
 184
 185 out:
 186         if (err) {
 187                 printk(KERN_ERR
 188                        "cik_mc: Failed to load firmware \"%s\"\n",
 189                        fw_name);
 190                 release_firmware(adev->mc.fw);
 191                 adev->mc.fw = NULL;
 192         }
 193         return err;
 194 }
 195
 196 /**
 197  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  * Load the GDDR MC ucode into the hw (CIK).
 202  * Returns 0 on success, error on failure.
 203  */
 204 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 205 {
 206         const struct mc_firmware_header_v1_0 *hdr;
 207         const __le32 *fw_data = NULL;
 208         const __le32 *io_mc_regs = NULL;
 209         u32 running, blackout = 0;
 210         int i, ucode_size, regs_size;
 211
 212         if (!adev->mc.fw)
 213                 return -EINVAL;
 214
 215         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 216         amdgpu_ucode_print_mc_hdr(&hdr->header);
 217
 218         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 219         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 220         io_mc_regs = (const __le32 *)
 221                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 222         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 223         fw_data = (const __le32 *)
 224                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 225
 226         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 227
 228         if (running == 0) {
 229                 if (running) {
 230                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 231                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 232                 }
 233
 234                 /* reset the engine and set to writable */
 235                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 236                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 237
 238                 /* load mc io regs */
 239                 for (i = 0; i < regs_size; i++) {
 240                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 241                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 242                 }
 243                 /* load the MC ucode */
 244                 for (i = 0; i < ucode_size; i++)
 245                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 246
 247                 /* put the engine back into the active state */
 248                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 249                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 250                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 251
 252                 /* wait for training to complete */
 253                 for (i = 0; i < adev->usec_timeout; i++) {
 254                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 255                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 256                                 break;
 257                         udelay(1);
 258                 }
 259                 for (i = 0; i < adev->usec_timeout; i++) {
 260                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 261                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 262                                 break;
 263                         udelay(1);
 264                 }
 265
 266                 if (running)
 267                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 268         }
 269
 270         return 0;
 271 }
 272
 273 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 274                                        struct amdgpu_mc *mc)
 275 {
 276         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 277                 /* leave room for at least 1024M GTT */
 278                 dev_warn(adev->dev, "limiting VRAM\n");
 279                 mc->real_vram_size = 0xFFC0000000ULL;
 280                 mc->mc_vram_size = 0xFFC0000000ULL;
 281         }
 282         amdgpu_vram_location(adev, &adev->mc, 0);
 283         adev->mc.gtt_base_align = 0;
 284         amdgpu_gtt_location(adev, mc);
 285 }
 286
 287 /**
 288  * gmc_v7_0_mc_program - program the GPU memory controller
 289  *
 290  * @adev: amdgpu_device pointer
 291  *
 292  * Set the location of vram, gart, and AGP in the GPU's
 293  * physical address space (CIK).
 294  */
 295 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 296 {
 297         struct amdgpu_mode_mc_save save;
 298         u32 tmp;
 299         int i, j;
 300
 301         /* Initialize HDP */
 302         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 303                 WREG32((0xb05 + j), 0x00000000);
 304                 WREG32((0xb06 + j), 0x00000000);
 305                 WREG32((0xb07 + j), 0x00000000);
 306                 WREG32((0xb08 + j), 0x00000000);
 307                 WREG32((0xb09 + j), 0x00000000);
 308         }
 309         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 310
 311         if (adev->mode_info.num_crtc)
 312                 amdgpu_display_set_vga_render_state(adev, false);
 313
 314         gmc_v7_0_mc_stop(adev, &save);
 315         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 316                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 317         }
 318         /* Update configuration */
 319         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 320                adev->mc.vram_start >> 12);
 321         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 322                adev->mc.vram_end >> 12);
 323         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 324                adev->vram_scratch.gpu_addr >> 12);
 325         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 326         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 327         WREG32(mmMC_VM_FB_LOCATION, tmp);
 328         /* XXX double check these! */
 329         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 330         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 331         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 332         WREG32(mmMC_VM_AGP_BASE, 0);
 333         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 334         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 335         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 336                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 337         }
 338         gmc_v7_0_mc_resume(adev, &save);
 339
 340         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 341
 342         tmp = RREG32(mmHDP_MISC_CNTL);
 343         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 344         WREG32(mmHDP_MISC_CNTL, tmp);
 345
 346         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 347         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 348 }
 349
 350 /**
 351  * gmc_v7_0_mc_init - initialize the memory controller driver params
 352  *
 353  * @adev: amdgpu_device pointer
 354  *
 355  * Look up the amount of vram, vram width, and decide how to place
 356  * vram and gart within the GPU's physical address space (CIK).
 357  * Returns 0 for success.
 358  */
 359 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 360 {
 361         u32 tmp;
 362         int chansize, numchan;
 363
 364         /* Get VRAM informations */
 365         tmp = RREG32(mmMC_ARB_RAMCFG);
 366         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 367                 chansize = 64;
 368         } else {
 369                 chansize = 32;
 370         }
 371         tmp = RREG32(mmMC_SHARED_CHMAP);
 372         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 373         case 0:
 374         default:
 375                 numchan = 1;
 376                 break;
 377         case 1:
 378                 numchan = 2;
 379                 break;
 380         case 2:
 381                 numchan = 4;
 382                 break;
 383         case 3:
 384                 numchan = 8;
 385                 break;
 386         case 4:
 387                 numchan = 3;
 388                 break;
 389         case 5:
 390                 numchan = 6;
 391                 break;
 392         case 6:
 393                 numchan = 10;
 394                 break;
 395         case 7:
 396                 numchan = 12;
 397                 break;
 398         case 8:
 399                 numchan = 16;
 400                 break;
 401         }
 402         adev->mc.vram_width = numchan * chansize;
 403         /* Could aper size report 0 ? */
 404         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 405         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 406         /* size in MB on si */
 407         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 408         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 409         adev->mc.visible_vram_size = adev->mc.aper_size;
 410
 411         /* unless the user had overridden it, set the gart
 412          * size equal to the 1024 or vram, whichever is larger.
 413          */
 414         if (amdgpu_gart_size == -1)
 415                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 416         else
 417                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 418
 419         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 420
 421         return 0;
 422 }
 423
 424 /*
 425  * GART
 426  * VMID 0 is the physical GPU addresses as used by the kernel.
 427  * VMIDs 1-15 are used for userspace clients and are handled
 428  * by the amdgpu vm/hsa code.
 429  */
 430
 431 /**
 432  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 433  *
 434  * @adev: amdgpu_device pointer
 435  * @vmid: vm instance to flush
 436  *
 437  * Flush the TLB for the requested page table (CIK).
 438  */
 439 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 440                                         uint32_t vmid)
 441 {
 442         /* flush hdp cache */
 443         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 444
 445         /* bits 0-15 are the VM contexts0-15 */
 446         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 447 }
 448
 449 /**
 450  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 451  *
 452  * @adev: amdgpu_device pointer
 453  * @cpu_pt_addr: cpu address of the page table
 454  * @gpu_page_idx: entry in the page table to update
 455  * @addr: dst addr to write into pte/pde
 456  * @flags: access flags
 457  *
 458  * Update the page tables using the CPU.
 459  */
 460 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 461                                      void *cpu_pt_addr,
 462                                      uint32_t gpu_page_idx,
 463                                      uint64_t addr,
 464                                      uint32_t flags)
 465 {
 466         void __iomem *ptr = (void *)cpu_pt_addr;
 467         uint64_t value;
 468
 469         value = addr & 0xFFFFFFFFFFFFF000ULL;
 470         value |= flags;
 471         writeq(value, ptr + (gpu_page_idx * 8));
 472
 473         return 0;
 474 }
 475
 476 /**
 477  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 478  *
 479  * @adev: amdgpu_device pointer
 480  * @value: true redirects VM faults to the default page
 481  */
 482 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 483                                               bool value)
 484 {
 485         u32 tmp;
 486
 487         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 488         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 489                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 490         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 491                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 492         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 493                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 494         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 495                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 496         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 497                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 498         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 499                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 500         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 501 }
 502
 503 /**
 504  * gmc_v7_0_gart_enable - gart enable
 505  *
 506  * @adev: amdgpu_device pointer
 507  *
 508  * This sets up the TLBs, programs the page tables for VMID0,
 509  * sets up the hw for VMIDs 1-15 which are allocated on
 510  * demand, and sets up the global locations for the LDS, GDS,
 511  * and GPUVM for FSA64 clients (CIK).
 512  * Returns 0 for success, errors for failure.
 513  */
 514 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 515 {
 516         int r, i;
 517         u32 tmp;
 518
 519         if (adev->gart.robj == NULL) {
 520                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 521                 return -EINVAL;
 522         }
 523         r = amdgpu_gart_table_vram_pin(adev);
 524         if (r)
 525                 return r;
 526         /* Setup TLB control */
 527         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 528         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 529         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 530         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 531         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 532         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 533         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 534         /* Setup L2 cache */
 535         tmp = RREG32(mmVM_L2_CNTL);
 536         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 537         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 538         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 539         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 540         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 541         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 542         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 543         WREG32(mmVM_L2_CNTL, tmp);
 544         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 545         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 546         WREG32(mmVM_L2_CNTL2, tmp);
 547         tmp = RREG32(mmVM_L2_CNTL3);
 548         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 549         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 550         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 551         WREG32(mmVM_L2_CNTL3, tmp);
 552         /* setup context0 */
 553         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 554         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 555         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 556         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 557                         (u32)(adev->dummy_page.addr >> 12));
 558         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 559         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 560         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 561         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 562         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 563         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 564
 565         WREG32(0x575, 0);
 566         WREG32(0x576, 0);
 567         WREG32(0x577, 0);
 568
 569         /* empty context1-15 */
 570         /* FIXME start with 4G, once using 2 level pt switch to full
 571          * vm size space
 572          */
 573         /* set vm size, must be a multiple of 4 */
 574         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 575         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 576         for (i = 1; i < 16; i++) {
 577                 if (i < 8)
 578                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 579                                adev->gart.table_addr >> 12);
 580                 else
 581                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 582                                adev->gart.table_addr >> 12);
 583         }
 584
 585         /* enable context1-15 */
 586         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 587                (u32)(adev->dummy_page.addr >> 12));
 588         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 589         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 590         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 591         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 592         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 593                             amdgpu_vm_block_size - 9);
 594         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 595         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 596                 gmc_v7_0_set_fault_enable_default(adev, false);
 597         else
 598                 gmc_v7_0_set_fault_enable_default(adev, true);
 599
 600         if (adev->asic_type == CHIP_KAVERI) {
 601                 tmp = RREG32(mmCHUB_CONTROL);
 602                 tmp &= ~BYPASS_VM;
 603                 WREG32(mmCHUB_CONTROL, tmp);
 604         }
 605
 606         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 607         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 608                  (unsigned)(adev->mc.gtt_size >> 20),
 609                  (unsigned long long)adev->gart.table_addr);
 610         adev->gart.ready = true;
 611         return 0;
 612 }
 613
 614 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 615 {
 616         int r;
 617
 618         if (adev->gart.robj) {
 619                 WARN(1, "R600 PCIE GART already initialized\n");
 620                 return 0;
 621         }
 622         /* Initialize common gart structure */
 623         r = amdgpu_gart_init(adev);
 624         if (r)
 625                 return r;
 626         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 627         return amdgpu_gart_table_vram_alloc(adev);
 628 }
 629
 630 /**
 631  * gmc_v7_0_gart_disable - gart disable
 632  *
 633  * @adev: amdgpu_device pointer
 634  *
 635  * This disables all VM page table (CIK).
 636  */
 637 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 638 {
 639         u32 tmp;
 640
 641         /* Disable all tables */
 642         WREG32(mmVM_CONTEXT0_CNTL, 0);
 643         WREG32(mmVM_CONTEXT1_CNTL, 0);
 644         /* Setup TLB control */
 645         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 646         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 647         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 648         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 649         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 650         /* Setup L2 cache */
 651         tmp = RREG32(mmVM_L2_CNTL);
 652         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 653         WREG32(mmVM_L2_CNTL, tmp);
 654         WREG32(mmVM_L2_CNTL2, 0);
 655         amdgpu_gart_table_vram_unpin(adev);
 656 }
 657
 658 /**
 659  * gmc_v7_0_gart_fini - vm fini callback
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Tears down the driver GART/VM setup (CIK).
 664  */
 665 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 666 {
 667         amdgpu_gart_table_vram_free(adev);
 668         amdgpu_gart_fini(adev);
 669 }
 670
 671 /*
 672  * vm
 673  * VMID 0 is the physical GPU addresses as used by the kernel.
 674  * VMIDs 1-15 are used for userspace clients and are handled
 675  * by the amdgpu vm/hsa code.
 676  */
 677 /**
 678  * gmc_v7_0_vm_init - cik vm init callback
 679  *
 680  * @adev: amdgpu_device pointer
 681  *
 682  * Inits cik specific vm parameters (number of VMs, base of vram for
 683  * VMIDs 1-15) (CIK).
 684  * Returns 0 for success.
 685  */
 686 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 687 {
 688         /*
 689          * number of VMs
 690          * VMID 0 is reserved for System
 691          * amdgpu graphics/compute will use VMIDs 1-7
 692          * amdkfd will use VMIDs 8-15
 693          */
 694         adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
 695
 696         /* base offset of vram pages */
 697         if (adev->flags & AMD_IS_APU) {
 698                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 699                 tmp <<= 22;
 700                 adev->vm_manager.vram_base_offset = tmp;
 701         } else
 702                 adev->vm_manager.vram_base_offset = 0;
 703
 704         return 0;
 705 }
 706
 707 /**
 708  * gmc_v7_0_vm_fini - cik vm fini callback
 709  *
 710  * @adev: amdgpu_device pointer
 711  *
 712  * Tear down any asic specific VM setup (CIK).
 713  */
 714 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 715 {
 716 }
 717
 718 /**
 719  * gmc_v7_0_vm_decode_fault - print human readable fault info
 720  *
 721  * @adev: amdgpu_device pointer
 722  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 723  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 724  *
 725  * Print human readable fault information (CIK).
 726  */
 727 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 728                                      u32 status, u32 addr, u32 mc_client)
 729 {
 730         u32 mc_id;
 731         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 732         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 733                                         PROTECTIONS);
 734         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 735                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 736
 737         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 738                               MEMORY_CLIENT_ID);
 739
 740         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 741                protections, vmid, addr,
 742                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 743                              MEMORY_CLIENT_RW) ?
 744                "write" : "read", block, mc_client, mc_id);
 745 }
 746
 747
 748 static const u32 mc_cg_registers[] = {
 749         mmMC_HUB_MISC_HUB_CG,
 750         mmMC_HUB_MISC_SIP_CG,
 751         mmMC_HUB_MISC_VM_CG,
 752         mmMC_XPB_CLK_GAT,
 753         mmATC_MISC_CG,
 754         mmMC_CITF_MISC_WR_CG,
 755         mmMC_CITF_MISC_RD_CG,
 756         mmMC_CITF_MISC_VM_CG,
 757         mmVM_L2_CG,
 758 };
 759
 760 static const u32 mc_cg_ls_en[] = {
 761         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 762         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 763         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 764         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 765         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 766         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 767         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 768         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 769         VM_L2_CG__MEM_LS_ENABLE_MASK,
 770 };
 771
 772 static const u32 mc_cg_en[] = {
 773         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 774         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 775         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 776         MC_XPB_CLK_GAT__ENABLE_MASK,
 777         ATC_MISC_CG__ENABLE_MASK,
 778         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 779         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 780         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 781         VM_L2_CG__ENABLE_MASK,
 782 };
 783
 784 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 785                                   bool enable)
 786 {
 787         int i;
 788         u32 orig, data;
 789
 790         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 791                 orig = data = RREG32(mc_cg_registers[i]);
 792                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 793                         data |= mc_cg_ls_en[i];
 794                 else
 795                         data &= ~mc_cg_ls_en[i];
 796                 if (data != orig)
 797                         WREG32(mc_cg_registers[i], data);
 798         }
 799 }
 800
 801 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 802                                     bool enable)
 803 {
 804         int i;
 805         u32 orig, data;
 806
 807         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 808                 orig = data = RREG32(mc_cg_registers[i]);
 809                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 810                         data |= mc_cg_en[i];
 811                 else
 812                         data &= ~mc_cg_en[i];
 813                 if (data != orig)
 814                         WREG32(mc_cg_registers[i], data);
 815         }
 816 }
 817
 818 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 819                                      bool enable)
 820 {
 821         u32 orig, data;
 822
 823         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 824
 825         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 826                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 827                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 828                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 829                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 830         } else {
 831                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 832                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 833                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 834                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 835         }
 836
 837         if (orig != data)
 838                 WREG32_PCIE(ixPCIE_CNTL2, data);
 839 }
 840
 841 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 842                                      bool enable)
 843 {
 844         u32 orig, data;
 845
 846         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 847
 848         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 849                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 850         else
 851                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 852
 853         if (orig != data)
 854                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 855 }
 856
 857 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 858                                    bool enable)
 859 {
 860         u32 orig, data;
 861
 862         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 863
 864         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 865                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 866         else
 867                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 868
 869         if (orig != data)
 870                 WREG32(mmHDP_MEM_POWER_LS, data);
 871 }
 872
 873 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 874 {
 875         switch (mc_seq_vram_type) {
 876         case MC_SEQ_MISC0__MT__GDDR1:
 877                 return AMDGPU_VRAM_TYPE_GDDR1;
 878         case MC_SEQ_MISC0__MT__DDR2:
 879                 return AMDGPU_VRAM_TYPE_DDR2;
 880         case MC_SEQ_MISC0__MT__GDDR3:
 881                 return AMDGPU_VRAM_TYPE_GDDR3;
 882         case MC_SEQ_MISC0__MT__GDDR4:
 883                 return AMDGPU_VRAM_TYPE_GDDR4;
 884         case MC_SEQ_MISC0__MT__GDDR5:
 885                 return AMDGPU_VRAM_TYPE_GDDR5;
 886         case MC_SEQ_MISC0__MT__HBM:
 887                 return AMDGPU_VRAM_TYPE_HBM;
 888         case MC_SEQ_MISC0__MT__DDR3:
 889                 return AMDGPU_VRAM_TYPE_DDR3;
 890         default:
 891                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 892         }
 893 }
 894
 895 static int gmc_v7_0_early_init(void *handle)
 896 {
 897         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 898
 899         gmc_v7_0_set_gart_funcs(adev);
 900         gmc_v7_0_set_irq_funcs(adev);
 901
 902         return 0;
 903 }
 904
 905 static int gmc_v7_0_late_init(void *handle)
 906 {
 907         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 908
 909         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 910 }
 911
 912 static int gmc_v7_0_sw_init(void *handle)
 913 {
 914         int r;
 915         int dma_bits;
 916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 917
 918         r = amdgpu_gem_init(adev);
 919         if (r)
 920                 return r;
 921
 922         if (adev->flags & AMD_IS_APU) {
 923                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 924         } else {
 925                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 926                 tmp &= MC_SEQ_MISC0__MT__MASK;
 927                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 928         }
 929
 930         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 931         if (r)
 932                 return r;
 933
 934         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 935         if (r)
 936                 return r;
 937
 938         /* Adjust VM size here.
 939          * Currently set to 4GB ((1 << 20) 4k pages).
 940          * Max GPUVM size for cayman and SI is 40 bits.
 941          */
 942         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 943
 944         /* Set the internal MC address mask
 945          * This is the max address of the GPU's
 946          * internal address space.
 947          */
 948         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 949
 950         /* set DMA mask + need_dma32 flags.
 951          * PCIE - can handle 40-bits.
 952          * IGP - can handle 40-bits
 953          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 954          */
 955         adev->need_dma32 = false;
 956         dma_bits = adev->need_dma32 ? 32 : 40;
 957         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 958         if (r) {
 959                 adev->need_dma32 = true;
 960                 dma_bits = 32;
 961                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 962         }
 963         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 964         if (r) {
 965                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 966                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 967         }
 968
 969         r = gmc_v7_0_init_microcode(adev);
 970         if (r) {
 971                 DRM_ERROR("Failed to load mc firmware!\n");
 972                 return r;
 973         }
 974
 975         r = gmc_v7_0_mc_init(adev);
 976         if (r)
 977                 return r;
 978
 979         /* Memory manager */
 980         r = amdgpu_bo_init(adev);
 981         if (r)
 982                 return r;
 983
 984         r = gmc_v7_0_gart_init(adev);
 985         if (r)
 986                 return r;
 987
 988         if (!adev->vm_manager.enabled) {
 989                 r = gmc_v7_0_vm_init(adev);
 990                 if (r) {
 991                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 992                         return r;
 993                 }
 994                 adev->vm_manager.enabled = true;
 995         }
 996
 997         return r;
 998 }
 999
1000 static int gmc_v7_0_sw_fini(void *handle)
1001 {
1002         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003
1004         if (adev->vm_manager.enabled) {
1005                 amdgpu_vm_manager_fini(adev);
1006                 gmc_v7_0_vm_fini(adev);
1007                 adev->vm_manager.enabled = false;
1008         }
1009         gmc_v7_0_gart_fini(adev);
1010         amdgpu_gem_fini(adev);
1011         amdgpu_bo_fini(adev);
1012
1013         return 0;
1014 }
1015
1016 static int gmc_v7_0_hw_init(void *handle)
1017 {
1018         int r;
1019         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1020
1021         gmc_v7_0_init_golden_registers(adev);
1022
1023         gmc_v7_0_mc_program(adev);
1024
1025         if (!(adev->flags & AMD_IS_APU)) {
1026                 r = gmc_v7_0_mc_load_microcode(adev);
1027                 if (r) {
1028                         DRM_ERROR("Failed to load MC firmware!\n");
1029                         return r;
1030                 }
1031         }
1032
1033         r = gmc_v7_0_gart_enable(adev);
1034         if (r)
1035                 return r;
1036
1037         return r;
1038 }
1039
1040 static int gmc_v7_0_hw_fini(void *handle)
1041 {
1042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043
1044         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1045         gmc_v7_0_gart_disable(adev);
1046
1047         return 0;
1048 }
1049
1050 static int gmc_v7_0_suspend(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         if (adev->vm_manager.enabled) {
1055                 amdgpu_vm_manager_fini(adev);
1056                 gmc_v7_0_vm_fini(adev);
1057                 adev->vm_manager.enabled = false;
1058         }
1059         gmc_v7_0_hw_fini(adev);
1060
1061         return 0;
1062 }
1063
1064 static int gmc_v7_0_resume(void *handle)
1065 {
1066         int r;
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068
1069         r = gmc_v7_0_hw_init(adev);
1070         if (r)
1071                 return r;
1072
1073         if (!adev->vm_manager.enabled) {
1074                 r = gmc_v7_0_vm_init(adev);
1075                 if (r) {
1076                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1077                         return r;
1078                 }
1079                 adev->vm_manager.enabled = true;
1080         }
1081
1082         return r;
1083 }
1084
1085 static bool gmc_v7_0_is_idle(void *handle)
1086 {
1087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1088         u32 tmp = RREG32(mmSRBM_STATUS);
1089
1090         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1091                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1092                 return false;
1093
1094         return true;
1095 }
1096
1097 static int gmc_v7_0_wait_for_idle(void *handle)
1098 {
1099         unsigned i;
1100         u32 tmp;
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102
1103         for (i = 0; i < adev->usec_timeout; i++) {
1104                 /* read MC_STATUS */
1105                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1106                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1107                                                SRBM_STATUS__MCC_BUSY_MASK |
1108                                                SRBM_STATUS__MCD_BUSY_MASK |
1109                                                SRBM_STATUS__VMC_BUSY_MASK);
1110                 if (!tmp)
1111                         return 0;
1112                 udelay(1);
1113         }
1114         return -ETIMEDOUT;
1115
1116 }
1117
1118 static void gmc_v7_0_print_status(void *handle)
1119 {
1120         int i, j;
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122
1123         dev_info(adev->dev, "GMC 8.x registers\n");
1124         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
1125                 RREG32(mmSRBM_STATUS));
1126         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1127                 RREG32(mmSRBM_STATUS2));
1128
1129         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1130                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1131         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1132                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1133         dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1134                  RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1135         dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
1136                  RREG32(mmVM_L2_CNTL));
1137         dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
1138                  RREG32(mmVM_L2_CNTL2));
1139         dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
1140                  RREG32(mmVM_L2_CNTL3));
1141         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1142                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1143         dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1144                  RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1145         dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1146                  RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1147         dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
1148                  RREG32(mmVM_CONTEXT0_CNTL2));
1149         dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
1150                  RREG32(mmVM_CONTEXT0_CNTL));
1151         dev_info(adev->dev, "  0x15D4=0x%08X\n",
1152                  RREG32(0x575));
1153         dev_info(adev->dev, "  0x15D8=0x%08X\n",
1154                  RREG32(0x576));
1155         dev_info(adev->dev, "  0x15DC=0x%08X\n",
1156                  RREG32(0x577));
1157         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1158                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1159         dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1160                  RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1161         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1162                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1163         dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
1164                  RREG32(mmVM_CONTEXT1_CNTL2));
1165         dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
1166                  RREG32(mmVM_CONTEXT1_CNTL));
1167         for (i = 0; i < 16; i++) {
1168                 if (i < 8)
1169                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1170                                  i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1171                 else
1172                         dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1173                                  i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1174         }
1175         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1176                  RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1177         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1178                  RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1179         dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1180                  RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1181         dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
1182                  RREG32(mmMC_VM_FB_LOCATION));
1183         dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
1184                  RREG32(mmMC_VM_AGP_BASE));
1185         dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
1186                  RREG32(mmMC_VM_AGP_TOP));
1187         dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
1188                  RREG32(mmMC_VM_AGP_BOT));
1189
1190         if (adev->asic_type == CHIP_KAVERI) {
1191                 dev_info(adev->dev, "  CHUB_CONTROL=0x%08X\n",
1192                          RREG32(mmCHUB_CONTROL));
1193         }
1194
1195         dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1196                  RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1197         dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
1198                  RREG32(mmHDP_NONSURFACE_BASE));
1199         dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
1200                  RREG32(mmHDP_NONSURFACE_INFO));
1201         dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
1202                  RREG32(mmHDP_NONSURFACE_SIZE));
1203         dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
1204                  RREG32(mmHDP_MISC_CNTL));
1205         dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
1206                  RREG32(mmHDP_HOST_PATH_CNTL));
1207
1208         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1209                 dev_info(adev->dev, "  %d:\n", i);
1210                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1211                          0xb05 + j, RREG32(0xb05 + j));
1212                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1213                          0xb06 + j, RREG32(0xb06 + j));
1214                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1215                          0xb07 + j, RREG32(0xb07 + j));
1216                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1217                          0xb08 + j, RREG32(0xb08 + j));
1218                 dev_info(adev->dev, "  0x%04X=0x%08X\n",
1219                          0xb09 + j, RREG32(0xb09 + j));
1220         }
1221
1222         dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
1223                  RREG32(mmBIF_FB_EN));
1224 }
1225
1226 static int gmc_v7_0_soft_reset(void *handle)
1227 {
1228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229         struct amdgpu_mode_mc_save save;
1230         u32 srbm_soft_reset = 0;
1231         u32 tmp = RREG32(mmSRBM_STATUS);
1232
1233         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1234                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1235                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1236
1237         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1238                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1239                 if (!(adev->flags & AMD_IS_APU))
1240                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1241                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1242         }
1243
1244         if (srbm_soft_reset) {
1245                 gmc_v7_0_print_status((void *)adev);
1246
1247                 gmc_v7_0_mc_stop(adev, &save);
1248                 if (gmc_v7_0_wait_for_idle(adev)) {
1249                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1250                 }
1251
1252
1253                 tmp = RREG32(mmSRBM_SOFT_RESET);
1254                 tmp |= srbm_soft_reset;
1255                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1256                 WREG32(mmSRBM_SOFT_RESET, tmp);
1257                 tmp = RREG32(mmSRBM_SOFT_RESET);
1258
1259                 udelay(50);
1260
1261                 tmp &= ~srbm_soft_reset;
1262                 WREG32(mmSRBM_SOFT_RESET, tmp);
1263                 tmp = RREG32(mmSRBM_SOFT_RESET);
1264
1265                 /* Wait a little for things to settle down */
1266                 udelay(50);
1267
1268                 gmc_v7_0_mc_resume(adev, &save);
1269                 udelay(50);
1270
1271                 gmc_v7_0_print_status((void *)adev);
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1278                                              struct amdgpu_irq_src *src,
1279                                              unsigned type,
1280                                              enum amdgpu_interrupt_state state)
1281 {
1282         u32 tmp;
1283         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1284                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1285                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1286                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1287                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1288                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1289
1290         switch (state) {
1291         case AMDGPU_IRQ_STATE_DISABLE:
1292                 /* system context */
1293                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1294                 tmp &= ~bits;
1295                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1296                 /* VMs */
1297                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1298                 tmp &= ~bits;
1299                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1300                 break;
1301         case AMDGPU_IRQ_STATE_ENABLE:
1302                 /* system context */
1303                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1304                 tmp |= bits;
1305                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1306                 /* VMs */
1307                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1308                 tmp |= bits;
1309                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1310                 break;
1311         default:
1312                 break;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1319                                       struct amdgpu_irq_src *source,
1320                                       struct amdgpu_iv_entry *entry)
1321 {
1322         u32 addr, status, mc_client;
1323
1324         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1325         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1326         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1327         /* reset addr and status */
1328         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1329
1330         if (!addr && !status)
1331                 return 0;
1332
1333         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1334                 gmc_v7_0_set_fault_enable_default(adev, false);
1335
1336         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1337                 entry->src_id, entry->src_data);
1338         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1339                 addr);
1340         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1341                 status);
1342         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1343
1344         return 0;
1345 }
1346
1347 static int gmc_v7_0_set_clockgating_state(void *handle,
1348                                           enum amd_clockgating_state state)
1349 {
1350         bool gate = false;
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         if (state == AMD_CG_STATE_GATE)
1354                 gate = true;
1355
1356         if (!(adev->flags & AMD_IS_APU)) {
1357                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1358                 gmc_v7_0_enable_mc_ls(adev, gate);
1359         }
1360         gmc_v7_0_enable_bif_mgls(adev, gate);
1361         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1362         gmc_v7_0_enable_hdp_ls(adev, gate);
1363
1364         return 0;
1365 }
1366
1367 static int gmc_v7_0_set_powergating_state(void *handle,
1368                                           enum amd_powergating_state state)
1369 {
1370         return 0;
1371 }
1372
1373 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1374         .early_init = gmc_v7_0_early_init,
1375         .late_init = gmc_v7_0_late_init,
1376         .sw_init = gmc_v7_0_sw_init,
1377         .sw_fini = gmc_v7_0_sw_fini,
1378         .hw_init = gmc_v7_0_hw_init,
1379         .hw_fini = gmc_v7_0_hw_fini,
1380         .suspend = gmc_v7_0_suspend,
1381         .resume = gmc_v7_0_resume,
1382         .is_idle = gmc_v7_0_is_idle,
1383         .wait_for_idle = gmc_v7_0_wait_for_idle,
1384         .soft_reset = gmc_v7_0_soft_reset,
1385         .print_status = gmc_v7_0_print_status,
1386         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1387         .set_powergating_state = gmc_v7_0_set_powergating_state,
1388 };
1389
1390 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1391         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1392         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1393 };
1394
1395 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1396         .set = gmc_v7_0_vm_fault_interrupt_state,
1397         .process = gmc_v7_0_process_interrupt,
1398 };
1399
1400 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1401 {
1402         if (adev->gart.gart_funcs == NULL)
1403                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1404 }
1405
1406 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1407 {
1408         adev->mc.vm_fault.num_types = 1;
1409         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1410 }