kernel/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_enum.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  48
  49 static const u32 crtc_offsets[6] =
  50 {
  51         CRTC0_REGISTER_OFFSET,
  52         CRTC1_REGISTER_OFFSET,
  53         CRTC2_REGISTER_OFFSET,
  54         CRTC3_REGISTER_OFFSET,
  55         CRTC4_REGISTER_OFFSET,
  56         CRTC5_REGISTER_OFFSET
  57 };
  58
  59 static const uint32_t dig_offsets[] = {
  60         CRTC0_REGISTER_OFFSET,
  61         CRTC1_REGISTER_OFFSET,
  62         CRTC2_REGISTER_OFFSET,
  63         CRTC3_REGISTER_OFFSET,
  64         CRTC4_REGISTER_OFFSET,
  65         CRTC5_REGISTER_OFFSET,
  66         (0x13830 - 0x7030) >> 2,
  67 };
  68
  69 static const struct {
  70         uint32_t        reg;
  71         uint32_t        vblank;
  72         uint32_t        vline;
  73         uint32_t        hpd;
  74
  75 } interrupt_status_offsets[6] = { {
  76         .reg = mmDISP_INTERRUPT_STATUS,
  77         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  78         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  79         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  80 }, {
  81         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  82         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  83         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  84         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  85 }, {
  86         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  87         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 105 } };
 106
 107 static const uint32_t hpd_int_control_offsets[6] = {
 108         mmDC_HPD1_INT_CONTROL,
 109         mmDC_HPD2_INT_CONTROL,
 110         mmDC_HPD3_INT_CONTROL,
 111         mmDC_HPD4_INT_CONTROL,
 112         mmDC_HPD5_INT_CONTROL,
 113         mmDC_HPD6_INT_CONTROL,
 114 };
 115
 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 117                                      u32 block_offset, u32 reg)
 118 {
 119         unsigned long flags;
 120         u32 r;
 121
 122         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 123         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 124         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 125         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 126
 127         return r;
 128 }
 129
 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 131                                       u32 block_offset, u32 reg, u32 v)
 132 {
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 136         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 137         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 138         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 139 }
 140
 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 142 {
 143         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 144                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 145                 return true;
 146         else
 147                 return false;
 148 }
 149
 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 151 {
 152         u32 pos1, pos2;
 153
 154         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 155         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 156
 157         if (pos1 != pos2)
 158                 return true;
 159         else
 160                 return false;
 161 }
 162
 163 /**
 164  * dce_v8_0_vblank_wait - vblank wait asic callback.
 165  *
 166  * @adev: amdgpu_device pointer
 167  * @crtc: crtc to wait for vblank on
 168  *
 169  * Wait for vblank on the requested crtc (evergreen+).
 170  */
 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 172 {
 173         unsigned i = 0;
 174
 175         if (crtc >= adev->mode_info.num_crtc)
 176                 return;
 177
 178         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 179                 return;
 180
 181         /* depending on when we hit vblank, we may be close to active; if so,
 182          * wait for another frame.
 183          */
 184         while (dce_v8_0_is_in_vblank(adev, crtc)) {
 185                 if (i++ % 100 == 0) {
 186                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 187                                 break;
 188                 }
 189         }
 190
 191         while (!dce_v8_0_is_in_vblank(adev, crtc)) {
 192                 if (i++ % 100 == 0) {
 193                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 194                                 break;
 195                 }
 196         }
 197 }
 198
 199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 200 {
 201         if (crtc >= adev->mode_info.num_crtc)
 202                 return 0;
 203         else
 204                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 205 }
 206
 207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 208 {
 209         unsigned i;
 210
 211         /* Enable pflip interrupts */
 212         for (i = 0; i < adev->mode_info.num_crtc; i++)
 213                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 214 }
 215
 216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 217 {
 218         unsigned i;
 219
 220         /* Disable pflip interrupts */
 221         for (i = 0; i < adev->mode_info.num_crtc; i++)
 222                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 223 }
 224
 225 /**
 226  * dce_v8_0_page_flip - pageflip callback.
 227  *
 228  * @adev: amdgpu_device pointer
 229  * @crtc_id: crtc to cleanup pageflip on
 230  * @crtc_base: new address of the crtc (GPU MC address)
 231  *
 232  * Triggers the actual pageflip by updating the primary
 233  * surface base address.
 234  */
 235 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 236                               int crtc_id, u64 crtc_base)
 237 {
 238         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 239
 240         /* update the primary scanout addresses */
 241         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 242                upper_32_bits(crtc_base));
 243         /* writing to the low address triggers the update */
 244         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 245                lower_32_bits(crtc_base));
 246         /* post the write */
 247         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 248 }
 249
 250 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 251                                         u32 *vbl, u32 *position)
 252 {
 253         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 254                 return -EINVAL;
 255
 256         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 257         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * dce_v8_0_hpd_sense - hpd sense callback.
 264  *
 265  * @adev: amdgpu_device pointer
 266  * @hpd: hpd (hotplug detect) pin
 267  *
 268  * Checks if a digital monitor is connected (evergreen+).
 269  * Returns true if connected, false if not connected.
 270  */
 271 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 272                                enum amdgpu_hpd_id hpd)
 273 {
 274         bool connected = false;
 275
 276         switch (hpd) {
 277         case AMDGPU_HPD_1:
 278                 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 279                         connected = true;
 280                 break;
 281         case AMDGPU_HPD_2:
 282                 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
 283                         connected = true;
 284                 break;
 285         case AMDGPU_HPD_3:
 286                 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
 287                         connected = true;
 288                 break;
 289         case AMDGPU_HPD_4:
 290                 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
 291                         connected = true;
 292                 break;
 293         case AMDGPU_HPD_5:
 294                 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
 295                         connected = true;
 296                 break;
 297         case AMDGPU_HPD_6:
 298                 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
 299                         connected = true;
 300                 break;
 301         default:
 302                 break;
 303         }
 304
 305         return connected;
 306 }
 307
 308 /**
 309  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 310  *
 311  * @adev: amdgpu_device pointer
 312  * @hpd: hpd (hotplug detect) pin
 313  *
 314  * Set the polarity of the hpd pin (evergreen+).
 315  */
 316 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 317                                       enum amdgpu_hpd_id hpd)
 318 {
 319         u32 tmp;
 320         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 321
 322         switch (hpd) {
 323         case AMDGPU_HPD_1:
 324                 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
 325                 if (connected)
 326                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 327                 else
 328                         tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 329                 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
 330                 break;
 331         case AMDGPU_HPD_2:
 332                 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
 333                 if (connected)
 334                         tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 335                 else
 336                         tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 337                 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
 338                 break;
 339         case AMDGPU_HPD_3:
 340                 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
 341                 if (connected)
 342                         tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 343                 else
 344                         tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 345                 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
 346                 break;
 347         case AMDGPU_HPD_4:
 348                 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
 349                 if (connected)
 350                         tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 351                 else
 352                         tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 353                 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
 354                 break;
 355         case AMDGPU_HPD_5:
 356                 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
 357                 if (connected)
 358                         tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 359                 else
 360                         tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 361                 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
 362                         break;
 363         case AMDGPU_HPD_6:
 364                 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
 365                 if (connected)
 366                         tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 367                 else
 368                         tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 369                 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
 370                 break;
 371         default:
 372                 break;
 373         }
 374 }
 375
 376 /**
 377  * dce_v8_0_hpd_init - hpd setup callback.
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Setup the hpd pins used by the card (evergreen+).
 382  * Enable the pin, set the polarity, and enable the hpd interrupts.
 383  */
 384 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 385 {
 386         struct drm_device *dev = adev->ddev;
 387         struct drm_connector *connector;
 388         u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
 389                 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
 390                 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 391
 392         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 393                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 394
 395                 switch (amdgpu_connector->hpd.hpd) {
 396                 case AMDGPU_HPD_1:
 397                         WREG32(mmDC_HPD1_CONTROL, tmp);
 398                         break;
 399                 case AMDGPU_HPD_2:
 400                         WREG32(mmDC_HPD2_CONTROL, tmp);
 401                         break;
 402                 case AMDGPU_HPD_3:
 403                         WREG32(mmDC_HPD3_CONTROL, tmp);
 404                         break;
 405                 case AMDGPU_HPD_4:
 406                         WREG32(mmDC_HPD4_CONTROL, tmp);
 407                         break;
 408                 case AMDGPU_HPD_5:
 409                         WREG32(mmDC_HPD5_CONTROL, tmp);
 410                         break;
 411                 case AMDGPU_HPD_6:
 412                         WREG32(mmDC_HPD6_CONTROL, tmp);
 413                         break;
 414                 default:
 415                         break;
 416                 }
 417
 418                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 419                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 420                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 421                          * aux dp channel on imac and help (but not completely fix)
 422                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 423                          * also avoid interrupt storms during dpms.
 424                          */
 425                         u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
 426
 427                         switch (amdgpu_connector->hpd.hpd) {
 428                         case AMDGPU_HPD_1:
 429                                 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
 430                                 break;
 431                         case AMDGPU_HPD_2:
 432                                 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
 433                                 break;
 434                         case AMDGPU_HPD_3:
 435                                 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
 436                                 break;
 437                         case AMDGPU_HPD_4:
 438                                 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
 439                                 break;
 440                         case AMDGPU_HPD_5:
 441                                 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
 442                                 break;
 443                         case AMDGPU_HPD_6:
 444                                 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
 445                                 break;
 446                         default:
 447                                 continue;
 448                         }
 449
 450                         dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
 451                         dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 452                         WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
 453                         continue;
 454                 }
 455
 456                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 457                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 458         }
 459 }
 460
 461 /**
 462  * dce_v8_0_hpd_fini - hpd tear down callback.
 463  *
 464  * @adev: amdgpu_device pointer
 465  *
 466  * Tear down the hpd pins used by the card (evergreen+).
 467  * Disable the hpd interrupts.
 468  */
 469 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 470 {
 471         struct drm_device *dev = adev->ddev;
 472         struct drm_connector *connector;
 473
 474         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 475                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 476
 477                 switch (amdgpu_connector->hpd.hpd) {
 478                 case AMDGPU_HPD_1:
 479                         WREG32(mmDC_HPD1_CONTROL, 0);
 480                         break;
 481                 case AMDGPU_HPD_2:
 482                         WREG32(mmDC_HPD2_CONTROL, 0);
 483                         break;
 484                 case AMDGPU_HPD_3:
 485                         WREG32(mmDC_HPD3_CONTROL, 0);
 486                         break;
 487                 case AMDGPU_HPD_4:
 488                         WREG32(mmDC_HPD4_CONTROL, 0);
 489                         break;
 490                 case AMDGPU_HPD_5:
 491                         WREG32(mmDC_HPD5_CONTROL, 0);
 492                         break;
 493                 case AMDGPU_HPD_6:
 494                         WREG32(mmDC_HPD6_CONTROL, 0);
 495                         break;
 496                 default:
 497                         break;
 498                 }
 499                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 500         }
 501 }
 502
 503 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 504 {
 505         return mmDC_GPIO_HPD_A;
 506 }
 507
 508 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 509 {
 510         u32 crtc_hung = 0;
 511         u32 crtc_status[6];
 512         u32 i, j, tmp;
 513
 514         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 515                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 516                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 517                         crtc_hung |= (1 << i);
 518                 }
 519         }
 520
 521         for (j = 0; j < 10; j++) {
 522                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 523                         if (crtc_hung & (1 << i)) {
 524                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 525                                 if (tmp != crtc_status[i])
 526                                         crtc_hung &= ~(1 << i);
 527                         }
 528                 }
 529                 if (crtc_hung == 0)
 530                         return false;
 531                 udelay(100);
 532         }
 533
 534         return true;
 535 }
 536
 537 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
 538                                     struct amdgpu_mode_mc_save *save)
 539 {
 540         u32 crtc_enabled, tmp;
 541         int i;
 542
 543         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 544         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 545
 546         /* disable VGA render */
 547         tmp = RREG32(mmVGA_RENDER_CONTROL);
 548         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 549         WREG32(mmVGA_RENDER_CONTROL, tmp);
 550
 551         /* blank the display controllers */
 552         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 553                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 554                                              CRTC_CONTROL, CRTC_MASTER_EN);
 555                 if (crtc_enabled) {
 556 #if 0
 557                         u32 frame_count;
 558                         int j;
 559
 560                         save->crtc_enabled[i] = true;
 561                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 562                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 563                                 amdgpu_display_vblank_wait(adev, i);
 564                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 565                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 566                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 567                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 568                         }
 569                         /* wait for the next frame */
 570                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 571                         for (j = 0; j < adev->usec_timeout; j++) {
 572                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 573                                         break;
 574                                 udelay(1);
 575                         }
 576                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 577                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 578                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 579                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 580                         }
 581                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 582                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 583                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 584                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 585                         }
 586 #else
 587                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 588                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 589                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 590                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 591                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 592                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 593                         save->crtc_enabled[i] = false;
 594                         /* ***** */
 595 #endif
 596                 } else {
 597                         save->crtc_enabled[i] = false;
 598                 }
 599         }
 600 }
 601
 602 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
 603                                       struct amdgpu_mode_mc_save *save)
 604 {
 605         u32 tmp, frame_count;
 606         int i, j;
 607
 608         /* update crtc base addresses */
 609         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 610                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 611                        upper_32_bits(adev->mc.vram_start));
 612                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 613                        upper_32_bits(adev->mc.vram_start));
 614                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 615                        (u32)adev->mc.vram_start);
 616                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 617                        (u32)adev->mc.vram_start);
 618
 619                 if (save->crtc_enabled[i]) {
 620                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 621                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 622                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 623                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 624                         }
 625                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 626                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 627                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 628                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 629                         }
 630                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 631                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 632                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 633                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 634                         }
 635                         for (j = 0; j < adev->usec_timeout; j++) {
 636                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 637                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 638                                         break;
 639                                 udelay(1);
 640                         }
 641                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 642                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 643                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 644                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 645                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 646                         /* wait for the next frame */
 647                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 648                         for (j = 0; j < adev->usec_timeout; j++) {
 649                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 650                                         break;
 651                                 udelay(1);
 652                         }
 653                 }
 654         }
 655
 656         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 657         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 658
 659         /* Unlock vga access */
 660         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 661         mdelay(1);
 662         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 663 }
 664
 665 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 666                                           bool render)
 667 {
 668         u32 tmp;
 669
 670         /* Lockout access through VGA aperture*/
 671         tmp = RREG32(mmVGA_HDP_CONTROL);
 672         if (render)
 673                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 674         else
 675                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 676         WREG32(mmVGA_HDP_CONTROL, tmp);
 677
 678         /* disable VGA render */
 679         tmp = RREG32(mmVGA_RENDER_CONTROL);
 680         if (render)
 681                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 682         else
 683                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 684         WREG32(mmVGA_RENDER_CONTROL, tmp);
 685 }
 686
 687 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 688 {
 689         struct drm_device *dev = encoder->dev;
 690         struct amdgpu_device *adev = dev->dev_private;
 691         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 692         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 693         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 694         int bpc = 0;
 695         u32 tmp = 0;
 696         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 697
 698         if (connector) {
 699                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 700                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 701                 dither = amdgpu_connector->dither;
 702         }
 703
 704         /* LVDS/eDP FMT is set up by atom */
 705         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 706                 return;
 707
 708         /* not needed for analog */
 709         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 710             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 711                 return;
 712
 713         if (bpc == 0)
 714                 return;
 715
 716         switch (bpc) {
 717         case 6:
 718                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 719                         /* XXX sort out optimal dither settings */
 720                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 721                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 722                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 723                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 724                 else
 725                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 726                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 727                 break;
 728         case 8:
 729                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 730                         /* XXX sort out optimal dither settings */
 731                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 732                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 733                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 734                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 735                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 736                 else
 737                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 738                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 739                 break;
 740         case 10:
 741                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 742                         /* XXX sort out optimal dither settings */
 743                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 744                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 745                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 746                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 747                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 748                 else
 749                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 750                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 751                 break;
 752         default:
 753                 /* not needed */
 754                 break;
 755         }
 756
 757         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 758 }
 759
 760
 761 /* display watermark setup */
 762 /**
 763  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 764  *
 765  * @adev: amdgpu_device pointer
 766  * @amdgpu_crtc: the selected display controller
 767  * @mode: the current display mode on the selected display
 768  * controller
 769  *
 770  * Setup up the line buffer allocation for
 771  * the selected display controller (CIK).
 772  * Returns the line buffer size in pixels.
 773  */
 774 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 775                                        struct amdgpu_crtc *amdgpu_crtc,
 776                                        struct drm_display_mode *mode)
 777 {
 778         u32 tmp, buffer_alloc, i;
 779         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 780         /*
 781          * Line Buffer Setup
 782          * There are 6 line buffers, one for each display controllers.
 783          * There are 3 partitions per LB. Select the number of partitions
 784          * to enable based on the display width.  For display widths larger
 785          * than 4096, you need use to use 2 display controllers and combine
 786          * them using the stereo blender.
 787          */
 788         if (amdgpu_crtc->base.enabled && mode) {
 789                 if (mode->crtc_hdisplay < 1920) {
 790                         tmp = 1;
 791                         buffer_alloc = 2;
 792                 } else if (mode->crtc_hdisplay < 2560) {
 793                         tmp = 2;
 794                         buffer_alloc = 2;
 795                 } else if (mode->crtc_hdisplay < 4096) {
 796                         tmp = 0;
 797                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 798                 } else {
 799                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 800                         tmp = 0;
 801                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 802                 }
 803         } else {
 804                 tmp = 1;
 805                 buffer_alloc = 0;
 806         }
 807
 808         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 809               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 810               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 811
 812         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 813                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 814         for (i = 0; i < adev->usec_timeout; i++) {
 815                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 816                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 817                         break;
 818                 udelay(1);
 819         }
 820
 821         if (amdgpu_crtc->base.enabled && mode) {
 822                 switch (tmp) {
 823                 case 0:
 824                 default:
 825                         return 4096 * 2;
 826                 case 1:
 827                         return 1920 * 2;
 828                 case 2:
 829                         return 2560 * 2;
 830                 }
 831         }
 832
 833         /* controller not enabled, so no lb used */
 834         return 0;
 835 }
 836
 837 /**
 838  * cik_get_number_of_dram_channels - get the number of dram channels
 839  *
 840  * @adev: amdgpu_device pointer
 841  *
 842  * Look up the number of video ram channels (CIK).
 843  * Used for display watermark bandwidth calculations
 844  * Returns the number of dram channels
 845  */
 846 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 847 {
 848         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 849
 850         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 851         case 0:
 852         default:
 853                 return 1;
 854         case 1:
 855                 return 2;
 856         case 2:
 857                 return 4;
 858         case 3:
 859                 return 8;
 860         case 4:
 861                 return 3;
 862         case 5:
 863                 return 6;
 864         case 6:
 865                 return 10;
 866         case 7:
 867                 return 12;
 868         case 8:
 869                 return 16;
 870         }
 871 }
 872
 873 struct dce8_wm_params {
 874         u32 dram_channels; /* number of dram channels */
 875         u32 yclk;          /* bandwidth per dram data pin in kHz */
 876         u32 sclk;          /* engine clock in kHz */
 877         u32 disp_clk;      /* display clock in kHz */
 878         u32 src_width;     /* viewport width */
 879         u32 active_time;   /* active display time in ns */
 880         u32 blank_time;    /* blank time in ns */
 881         bool interlaced;    /* mode is interlaced */
 882         fixed20_12 vsc;    /* vertical scale ratio */
 883         u32 num_heads;     /* number of active crtcs */
 884         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 885         u32 lb_size;       /* line buffer allocated to pipe */
 886         u32 vtaps;         /* vertical scaler taps */
 887 };
 888
 889 /**
 890  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 891  *
 892  * @wm: watermark calculation data
 893  *
 894  * Calculate the raw dram bandwidth (CIK).
 895  * Used for display watermark bandwidth calculations
 896  * Returns the dram bandwidth in MBytes/s
 897  */
 898 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 899 {
 900         /* Calculate raw DRAM Bandwidth */
 901         fixed20_12 dram_efficiency; /* 0.7 */
 902         fixed20_12 yclk, dram_channels, bandwidth;
 903         fixed20_12 a;
 904
 905         a.full = dfixed_const(1000);
 906         yclk.full = dfixed_const(wm->yclk);
 907         yclk.full = dfixed_div(yclk, a);
 908         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 909         a.full = dfixed_const(10);
 910         dram_efficiency.full = dfixed_const(7);
 911         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 912         bandwidth.full = dfixed_mul(dram_channels, yclk);
 913         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 914
 915         return dfixed_trunc(bandwidth);
 916 }
 917
 918 /**
 919  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 920  *
 921  * @wm: watermark calculation data
 922  *
 923  * Calculate the dram bandwidth used for display (CIK).
 924  * Used for display watermark bandwidth calculations
 925  * Returns the dram bandwidth for display in MBytes/s
 926  */
 927 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 928 {
 929         /* Calculate DRAM Bandwidth and the part allocated to display. */
 930         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 931         fixed20_12 yclk, dram_channels, bandwidth;
 932         fixed20_12 a;
 933
 934         a.full = dfixed_const(1000);
 935         yclk.full = dfixed_const(wm->yclk);
 936         yclk.full = dfixed_div(yclk, a);
 937         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 938         a.full = dfixed_const(10);
 939         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 940         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 941         bandwidth.full = dfixed_mul(dram_channels, yclk);
 942         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 943
 944         return dfixed_trunc(bandwidth);
 945 }
 946
 947 /**
 948  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 949  *
 950  * @wm: watermark calculation data
 951  *
 952  * Calculate the data return bandwidth used for display (CIK).
 953  * Used for display watermark bandwidth calculations
 954  * Returns the data return bandwidth in MBytes/s
 955  */
 956 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 957 {
 958         /* Calculate the display Data return Bandwidth */
 959         fixed20_12 return_efficiency; /* 0.8 */
 960         fixed20_12 sclk, bandwidth;
 961         fixed20_12 a;
 962
 963         a.full = dfixed_const(1000);
 964         sclk.full = dfixed_const(wm->sclk);
 965         sclk.full = dfixed_div(sclk, a);
 966         a.full = dfixed_const(10);
 967         return_efficiency.full = dfixed_const(8);
 968         return_efficiency.full = dfixed_div(return_efficiency, a);
 969         a.full = dfixed_const(32);
 970         bandwidth.full = dfixed_mul(a, sclk);
 971         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 972
 973         return dfixed_trunc(bandwidth);
 974 }
 975
 976 /**
 977  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 978  *
 979  * @wm: watermark calculation data
 980  *
 981  * Calculate the dmif bandwidth used for display (CIK).
 982  * Used for display watermark bandwidth calculations
 983  * Returns the dmif bandwidth in MBytes/s
 984  */
 985 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 986 {
 987         /* Calculate the DMIF Request Bandwidth */
 988         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 989         fixed20_12 disp_clk, bandwidth;
 990         fixed20_12 a, b;
 991
 992         a.full = dfixed_const(1000);
 993         disp_clk.full = dfixed_const(wm->disp_clk);
 994         disp_clk.full = dfixed_div(disp_clk, a);
 995         a.full = dfixed_const(32);
 996         b.full = dfixed_mul(a, disp_clk);
 997
 998         a.full = dfixed_const(10);
 999         disp_clk_request_efficiency.full = dfixed_const(8);
1000         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1001
1002         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1003
1004         return dfixed_trunc(bandwidth);
1005 }
1006
1007 /**
1008  * dce_v8_0_available_bandwidth - get the min available bandwidth
1009  *
1010  * @wm: watermark calculation data
1011  *
1012  * Calculate the min available bandwidth used for display (CIK).
1013  * Used for display watermark bandwidth calculations
1014  * Returns the min available bandwidth in MBytes/s
1015  */
1016 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
1017 {
1018         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1019         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
1020         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
1021         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
1022
1023         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1024 }
1025
1026 /**
1027  * dce_v8_0_average_bandwidth - get the average available bandwidth
1028  *
1029  * @wm: watermark calculation data
1030  *
1031  * Calculate the average available bandwidth used for display (CIK).
1032  * Used for display watermark bandwidth calculations
1033  * Returns the average available bandwidth in MBytes/s
1034  */
1035 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
1036 {
1037         /* Calculate the display mode Average Bandwidth
1038          * DisplayMode should contain the source and destination dimensions,
1039          * timing, etc.
1040          */
1041         fixed20_12 bpp;
1042         fixed20_12 line_time;
1043         fixed20_12 src_width;
1044         fixed20_12 bandwidth;
1045         fixed20_12 a;
1046
1047         a.full = dfixed_const(1000);
1048         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1049         line_time.full = dfixed_div(line_time, a);
1050         bpp.full = dfixed_const(wm->bytes_per_pixel);
1051         src_width.full = dfixed_const(wm->src_width);
1052         bandwidth.full = dfixed_mul(src_width, bpp);
1053         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1054         bandwidth.full = dfixed_div(bandwidth, line_time);
1055
1056         return dfixed_trunc(bandwidth);
1057 }
1058
1059 /**
1060  * dce_v8_0_latency_watermark - get the latency watermark
1061  *
1062  * @wm: watermark calculation data
1063  *
1064  * Calculate the latency watermark (CIK).
1065  * Used for display watermark bandwidth calculations
1066  * Returns the latency watermark in ns
1067  */
1068 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1069 {
1070         /* First calculate the latency in ns */
1071         u32 mc_latency = 2000; /* 2000 ns. */
1072         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1073         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1074         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1075         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1076         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1077                 (wm->num_heads * cursor_line_pair_return_time);
1078         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1079         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1080         u32 tmp, dmif_size = 12288;
1081         fixed20_12 a, b, c;
1082
1083         if (wm->num_heads == 0)
1084                 return 0;
1085
1086         a.full = dfixed_const(2);
1087         b.full = dfixed_const(1);
1088         if ((wm->vsc.full > a.full) ||
1089             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1090             (wm->vtaps >= 5) ||
1091             ((wm->vsc.full >= a.full) && wm->interlaced))
1092                 max_src_lines_per_dst_line = 4;
1093         else
1094                 max_src_lines_per_dst_line = 2;
1095
1096         a.full = dfixed_const(available_bandwidth);
1097         b.full = dfixed_const(wm->num_heads);
1098         a.full = dfixed_div(a, b);
1099
1100         b.full = dfixed_const(mc_latency + 512);
1101         c.full = dfixed_const(wm->disp_clk);
1102         b.full = dfixed_div(b, c);
1103
1104         c.full = dfixed_const(dmif_size);
1105         b.full = dfixed_div(c, b);
1106
1107         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1108
1109         b.full = dfixed_const(1000);
1110         c.full = dfixed_const(wm->disp_clk);
1111         b.full = dfixed_div(c, b);
1112         c.full = dfixed_const(wm->bytes_per_pixel);
1113         b.full = dfixed_mul(b, c);
1114
1115         lb_fill_bw = min(tmp, dfixed_trunc(b));
1116
1117         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1118         b.full = dfixed_const(1000);
1119         c.full = dfixed_const(lb_fill_bw);
1120         b.full = dfixed_div(c, b);
1121         a.full = dfixed_div(a, b);
1122         line_fill_time = dfixed_trunc(a);
1123
1124         if (line_fill_time < wm->active_time)
1125                 return latency;
1126         else
1127                 return latency + (line_fill_time - wm->active_time);
1128
1129 }
1130
1131 /**
1132  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1133  * average and available dram bandwidth
1134  *
1135  * @wm: watermark calculation data
1136  *
1137  * Check if the display average bandwidth fits in the display
1138  * dram bandwidth (CIK).
1139  * Used for display watermark bandwidth calculations
1140  * Returns true if the display fits, false if not.
1141  */
1142 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1143 {
1144         if (dce_v8_0_average_bandwidth(wm) <=
1145             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1146                 return true;
1147         else
1148                 return false;
1149 }
1150
1151 /**
1152  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1153  * average and available bandwidth
1154  *
1155  * @wm: watermark calculation data
1156  *
1157  * Check if the display average bandwidth fits in the display
1158  * available bandwidth (CIK).
1159  * Used for display watermark bandwidth calculations
1160  * Returns true if the display fits, false if not.
1161  */
1162 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1163 {
1164         if (dce_v8_0_average_bandwidth(wm) <=
1165             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1166                 return true;
1167         else
1168                 return false;
1169 }
1170
1171 /**
1172  * dce_v8_0_check_latency_hiding - check latency hiding
1173  *
1174  * @wm: watermark calculation data
1175  *
1176  * Check latency hiding (CIK).
1177  * Used for display watermark bandwidth calculations
1178  * Returns true if the display fits, false if not.
1179  */
1180 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1181 {
1182         u32 lb_partitions = wm->lb_size / wm->src_width;
1183         u32 line_time = wm->active_time + wm->blank_time;
1184         u32 latency_tolerant_lines;
1185         u32 latency_hiding;
1186         fixed20_12 a;
1187
1188         a.full = dfixed_const(1);
1189         if (wm->vsc.full > a.full)
1190                 latency_tolerant_lines = 1;
1191         else {
1192                 if (lb_partitions <= (wm->vtaps + 1))
1193                         latency_tolerant_lines = 1;
1194                 else
1195                         latency_tolerant_lines = 2;
1196         }
1197
1198         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1199
1200         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1201                 return true;
1202         else
1203                 return false;
1204 }
1205
1206 /**
1207  * dce_v8_0_program_watermarks - program display watermarks
1208  *
1209  * @adev: amdgpu_device pointer
1210  * @amdgpu_crtc: the selected display controller
1211  * @lb_size: line buffer size
1212  * @num_heads: number of display controllers in use
1213  *
1214  * Calculate and program the display watermarks for the
1215  * selected display controller (CIK).
1216  */
1217 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1218                                         struct amdgpu_crtc *amdgpu_crtc,
1219                                         u32 lb_size, u32 num_heads)
1220 {
1221         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1222         struct dce8_wm_params wm_low, wm_high;
1223         u32 pixel_period;
1224         u32 line_time = 0;
1225         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1226         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1227
1228         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1229                 pixel_period = 1000000 / (u32)mode->clock;
1230                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1231
1232                 /* watermark for high clocks */
1233                 if (adev->pm.dpm_enabled) {
1234                         wm_high.yclk =
1235                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1236                         wm_high.sclk =
1237                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1238                 } else {
1239                         wm_high.yclk = adev->pm.current_mclk * 10;
1240                         wm_high.sclk = adev->pm.current_sclk * 10;
1241                 }
1242
1243                 wm_high.disp_clk = mode->clock;
1244                 wm_high.src_width = mode->crtc_hdisplay;
1245                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1246                 wm_high.blank_time = line_time - wm_high.active_time;
1247                 wm_high.interlaced = false;
1248                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1249                         wm_high.interlaced = true;
1250                 wm_high.vsc = amdgpu_crtc->vsc;
1251                 wm_high.vtaps = 1;
1252                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1253                         wm_high.vtaps = 2;
1254                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1255                 wm_high.lb_size = lb_size;
1256                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1257                 wm_high.num_heads = num_heads;
1258
1259                 /* set for high clocks */
1260                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1261
1262                 /* possibly force display priority to high */
1263                 /* should really do this at mode validation time... */
1264                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1265                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1266                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1267                     (adev->mode_info.disp_priority == 2)) {
1268                         DRM_DEBUG_KMS("force priority to high\n");
1269                 }
1270
1271                 /* watermark for low clocks */
1272                 if (adev->pm.dpm_enabled) {
1273                         wm_low.yclk =
1274                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1275                         wm_low.sclk =
1276                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1277                 } else {
1278                         wm_low.yclk = adev->pm.current_mclk * 10;
1279                         wm_low.sclk = adev->pm.current_sclk * 10;
1280                 }
1281
1282                 wm_low.disp_clk = mode->clock;
1283                 wm_low.src_width = mode->crtc_hdisplay;
1284                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1285                 wm_low.blank_time = line_time - wm_low.active_time;
1286                 wm_low.interlaced = false;
1287                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1288                         wm_low.interlaced = true;
1289                 wm_low.vsc = amdgpu_crtc->vsc;
1290                 wm_low.vtaps = 1;
1291                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1292                         wm_low.vtaps = 2;
1293                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1294                 wm_low.lb_size = lb_size;
1295                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1296                 wm_low.num_heads = num_heads;
1297
1298                 /* set for low clocks */
1299                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1300
1301                 /* possibly force display priority to high */
1302                 /* should really do this at mode validation time... */
1303                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1304                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1305                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1306                     (adev->mode_info.disp_priority == 2)) {
1307                         DRM_DEBUG_KMS("force priority to high\n");
1308                 }
1309                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1310         }
1311
1312         /* select wm A */
1313         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1314         tmp = wm_mask;
1315         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1316         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1317         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1318         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1319                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1320                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1321         /* select wm B */
1322         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1323         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1324         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1325         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1326         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1327                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1328                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1329         /* restore original selection */
1330         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1331
1332         /* save values for DPM */
1333         amdgpu_crtc->line_time = line_time;
1334         amdgpu_crtc->wm_high = latency_watermark_a;
1335         amdgpu_crtc->wm_low = latency_watermark_b;
1336         /* Save number of lines the linebuffer leads before the scanout */
1337         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1338 }
1339
1340 /**
1341  * dce_v8_0_bandwidth_update - program display watermarks
1342  *
1343  * @adev: amdgpu_device pointer
1344  *
1345  * Calculate and program the display watermarks and line
1346  * buffer allocation (CIK).
1347  */
1348 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1349 {
1350         struct drm_display_mode *mode = NULL;
1351         u32 num_heads = 0, lb_size;
1352         int i;
1353
1354         amdgpu_update_display_priority(adev);
1355
1356         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1357                 if (adev->mode_info.crtcs[i]->base.enabled)
1358                         num_heads++;
1359         }
1360         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1361                 mode = &adev->mode_info.crtcs[i]->base.mode;
1362                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1363                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1364                                             lb_size, num_heads);
1365         }
1366 }
1367
1368 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1369 {
1370         int i;
1371         u32 offset, tmp;
1372
1373         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1374                 offset = adev->mode_info.audio.pin[i].offset;
1375                 tmp = RREG32_AUDIO_ENDPT(offset,
1376                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1377                 if (((tmp &
1378                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1379                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1380                         adev->mode_info.audio.pin[i].connected = false;
1381                 else
1382                         adev->mode_info.audio.pin[i].connected = true;
1383         }
1384 }
1385
1386 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1387 {
1388         int i;
1389
1390         dce_v8_0_audio_get_connected_pins(adev);
1391
1392         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1393                 if (adev->mode_info.audio.pin[i].connected)
1394                         return &adev->mode_info.audio.pin[i];
1395         }
1396         DRM_ERROR("No connected audio pins found!\n");
1397         return NULL;
1398 }
1399
1400 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1401 {
1402         struct amdgpu_device *adev = encoder->dev->dev_private;
1403         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1404         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1405         u32 offset;
1406
1407         if (!dig || !dig->afmt || !dig->afmt->pin)
1408                 return;
1409
1410         offset = dig->afmt->offset;
1411
1412         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1413                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1414 }
1415
1416 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1417                                                 struct drm_display_mode *mode)
1418 {
1419         struct amdgpu_device *adev = encoder->dev->dev_private;
1420         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1421         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1422         struct drm_connector *connector;
1423         struct amdgpu_connector *amdgpu_connector = NULL;
1424         u32 tmp = 0, offset;
1425
1426         if (!dig || !dig->afmt || !dig->afmt->pin)
1427                 return;
1428
1429         offset = dig->afmt->pin->offset;
1430
1431         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1432                 if (connector->encoder == encoder) {
1433                         amdgpu_connector = to_amdgpu_connector(connector);
1434                         break;
1435                 }
1436         }
1437
1438         if (!amdgpu_connector) {
1439                 DRM_ERROR("Couldn't find encoder's connector\n");
1440                 return;
1441         }
1442
1443         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1444                 if (connector->latency_present[1])
1445                         tmp =
1446                         (connector->video_latency[1] <<
1447                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1448                         (connector->audio_latency[1] <<
1449                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1450                 else
1451                         tmp =
1452                         (0 <<
1453                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1454                         (0 <<
1455                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1456         } else {
1457                 if (connector->latency_present[0])
1458                         tmp =
1459                         (connector->video_latency[0] <<
1460                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1461                         (connector->audio_latency[0] <<
1462                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1463                 else
1464                         tmp =
1465                         (0 <<
1466                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1467                         (0 <<
1468                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1469
1470         }
1471         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1472 }
1473
1474 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1475 {
1476         struct amdgpu_device *adev = encoder->dev->dev_private;
1477         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1478         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1479         struct drm_connector *connector;
1480         struct amdgpu_connector *amdgpu_connector = NULL;
1481         u32 offset, tmp;
1482         u8 *sadb = NULL;
1483         int sad_count;
1484
1485         if (!dig || !dig->afmt || !dig->afmt->pin)
1486                 return;
1487
1488         offset = dig->afmt->pin->offset;
1489
1490         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1491                 if (connector->encoder == encoder) {
1492                         amdgpu_connector = to_amdgpu_connector(connector);
1493                         break;
1494                 }
1495         }
1496
1497         if (!amdgpu_connector) {
1498                 DRM_ERROR("Couldn't find encoder's connector\n");
1499                 return;
1500         }
1501
1502         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1503         if (sad_count < 0) {
1504                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1505                 sad_count = 0;
1506         }
1507
1508         /* program the speaker allocation */
1509         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1510         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1511                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1512         /* set HDMI mode */
1513         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1514         if (sad_count)
1515                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1516         else
1517                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1518         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1519
1520         kfree(sadb);
1521 }
1522
1523 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1524 {
1525         struct amdgpu_device *adev = encoder->dev->dev_private;
1526         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1527         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1528         u32 offset;
1529         struct drm_connector *connector;
1530         struct amdgpu_connector *amdgpu_connector = NULL;
1531         struct cea_sad *sads;
1532         int i, sad_count;
1533
1534         static const u16 eld_reg_to_type[][2] = {
1535                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1536                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1537                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1538                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1539                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1540                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1541                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1542                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1543                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1544                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1545                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1546                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1547         };
1548
1549         if (!dig || !dig->afmt || !dig->afmt->pin)
1550                 return;
1551
1552         offset = dig->afmt->pin->offset;
1553
1554         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1555                 if (connector->encoder == encoder) {
1556                         amdgpu_connector = to_amdgpu_connector(connector);
1557                         break;
1558                 }
1559         }
1560
1561         if (!amdgpu_connector) {
1562                 DRM_ERROR("Couldn't find encoder's connector\n");
1563                 return;
1564         }
1565
1566         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1567         if (sad_count <= 0) {
1568                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1569                 return;
1570         }
1571         BUG_ON(!sads);
1572
1573         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1574                 u32 value = 0;
1575                 u8 stereo_freqs = 0;
1576                 int max_channels = -1;
1577                 int j;
1578
1579                 for (j = 0; j < sad_count; j++) {
1580                         struct cea_sad *sad = &sads[j];
1581
1582                         if (sad->format == eld_reg_to_type[i][1]) {
1583                                 if (sad->channels > max_channels) {
1584                                 value = (sad->channels <<
1585                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1586                                 (sad->byte2 <<
1587                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1588                                 (sad->freq <<
1589                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1590                                 max_channels = sad->channels;
1591                                 }
1592
1593                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1594                                         stereo_freqs |= sad->freq;
1595                                 else
1596                                         break;
1597                         }
1598                 }
1599
1600                 value |= (stereo_freqs <<
1601                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1602
1603                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1604         }
1605
1606         kfree(sads);
1607 }
1608
1609 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1610                                   struct amdgpu_audio_pin *pin,
1611                                   bool enable)
1612 {
1613         if (!pin)
1614                 return;
1615
1616         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1617                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1618 }
1619
1620 static const u32 pin_offsets[7] =
1621 {
1622         (0x1780 - 0x1780),
1623         (0x1786 - 0x1780),
1624         (0x178c - 0x1780),
1625         (0x1792 - 0x1780),
1626         (0x1798 - 0x1780),
1627         (0x179d - 0x1780),
1628         (0x17a4 - 0x1780),
1629 };
1630
1631 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1632 {
1633         int i;
1634
1635         if (!amdgpu_audio)
1636                 return 0;
1637
1638         adev->mode_info.audio.enabled = true;
1639
1640         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1641                 adev->mode_info.audio.num_pins = 7;
1642         else if ((adev->asic_type == CHIP_KABINI) ||
1643                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1644                 adev->mode_info.audio.num_pins = 3;
1645         else if ((adev->asic_type == CHIP_BONAIRE) ||
1646                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1647                 adev->mode_info.audio.num_pins = 7;
1648         else
1649                 adev->mode_info.audio.num_pins = 3;
1650
1651         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1652                 adev->mode_info.audio.pin[i].channels = -1;
1653                 adev->mode_info.audio.pin[i].rate = -1;
1654                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1655                 adev->mode_info.audio.pin[i].status_bits = 0;
1656                 adev->mode_info.audio.pin[i].category_code = 0;
1657                 adev->mode_info.audio.pin[i].connected = false;
1658                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1659                 adev->mode_info.audio.pin[i].id = i;
1660                 /* disable audio.  it will be set up later */
1661                 /* XXX remove once we switch to ip funcs */
1662                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1663         }
1664
1665         return 0;
1666 }
1667
1668 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1669 {
1670         int i;
1671
1672         if (!adev->mode_info.audio.enabled)
1673                 return;
1674
1675         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1676                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1677
1678         adev->mode_info.audio.enabled = false;
1679 }
1680
1681 /*
1682  * update the N and CTS parameters for a given pixel clock rate
1683  */
1684 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1685 {
1686         struct drm_device *dev = encoder->dev;
1687         struct amdgpu_device *adev = dev->dev_private;
1688         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1689         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1690         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1691         uint32_t offset = dig->afmt->offset;
1692
1693         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1694         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1695
1696         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1697         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1698
1699         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1700         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1701 }
1702
1703 /*
1704  * build a HDMI Video Info Frame
1705  */
1706 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1707                                                void *buffer, size_t size)
1708 {
1709         struct drm_device *dev = encoder->dev;
1710         struct amdgpu_device *adev = dev->dev_private;
1711         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1712         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1713         uint32_t offset = dig->afmt->offset;
1714         uint8_t *frame = buffer + 3;
1715         uint8_t *header = buffer;
1716
1717         WREG32(mmAFMT_AVI_INFO0 + offset,
1718                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1719         WREG32(mmAFMT_AVI_INFO1 + offset,
1720                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1721         WREG32(mmAFMT_AVI_INFO2 + offset,
1722                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1723         WREG32(mmAFMT_AVI_INFO3 + offset,
1724                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1725 }
1726
1727 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1728 {
1729         struct drm_device *dev = encoder->dev;
1730         struct amdgpu_device *adev = dev->dev_private;
1731         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1732         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1733         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1734         u32 dto_phase = 24 * 1000;
1735         u32 dto_modulo = clock;
1736
1737         if (!dig || !dig->afmt)
1738                 return;
1739
1740         /* XXX two dtos; generally use dto0 for hdmi */
1741         /* Express [24MHz / target pixel clock] as an exact rational
1742          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1743          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1744          */
1745         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1746         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1747         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1748 }
1749
1750 /*
1751  * update the info frames with the data from the current display mode
1752  */
1753 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1754                                   struct drm_display_mode *mode)
1755 {
1756         struct drm_device *dev = encoder->dev;
1757         struct amdgpu_device *adev = dev->dev_private;
1758         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1759         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1760         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1761         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1762         struct hdmi_avi_infoframe frame;
1763         uint32_t offset, val;
1764         ssize_t err;
1765         int bpc = 8;
1766
1767         if (!dig || !dig->afmt)
1768                 return;
1769
1770         /* Silent, r600_hdmi_enable will raise WARN for us */
1771         if (!dig->afmt->enabled)
1772                 return;
1773         offset = dig->afmt->offset;
1774
1775         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1776         if (encoder->crtc) {
1777                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1778                 bpc = amdgpu_crtc->bpc;
1779         }
1780
1781         /* disable audio prior to setting up hw */
1782         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1783         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1784
1785         dce_v8_0_audio_set_dto(encoder, mode->clock);
1786
1787         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1788                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1789
1790         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1791
1792         val = RREG32(mmHDMI_CONTROL + offset);
1793         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1794         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1795
1796         switch (bpc) {
1797         case 0:
1798         case 6:
1799         case 8:
1800         case 16:
1801         default:
1802                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1803                           connector->name, bpc);
1804                 break;
1805         case 10:
1806                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1807                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1808                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1809                           connector->name);
1810                 break;
1811         case 12:
1812                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1813                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1814                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1815                           connector->name);
1816                 break;
1817         }
1818
1819         WREG32(mmHDMI_CONTROL + offset, val);
1820
1821         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1822                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1823                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1824                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1825
1826         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1827                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1828                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1829
1830         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1831                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1832
1833         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1834                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1835
1836         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1837
1838         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1839                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1840                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1841
1842         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1843                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1844
1845         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1846
1847         if (bpc > 8)
1848                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1849                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1850         else
1851                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1852                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1853                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1854
1855         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1856
1857         WREG32(mmAFMT_60958_0 + offset,
1858                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1859
1860         WREG32(mmAFMT_60958_1 + offset,
1861                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1862
1863         WREG32(mmAFMT_60958_2 + offset,
1864                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1865                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1866                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1867                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1868                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1869                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1870
1871         dce_v8_0_audio_write_speaker_allocation(encoder);
1872
1873
1874         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1875                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1876
1877         dce_v8_0_afmt_audio_select_pin(encoder);
1878         dce_v8_0_audio_write_sad_regs(encoder);
1879         dce_v8_0_audio_write_latency_fields(encoder, mode);
1880
1881         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1882         if (err < 0) {
1883                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1884                 return;
1885         }
1886
1887         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1888         if (err < 0) {
1889                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1890                 return;
1891         }
1892
1893         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1894
1895         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1896                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1897                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
1898
1899         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1900                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1901                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1902
1903         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1904                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1905
1906         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1907         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1908         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1909         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1910         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1911
1912         /* enable audio after to setting up hw */
1913         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1914 }
1915
1916 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1917 {
1918         struct drm_device *dev = encoder->dev;
1919         struct amdgpu_device *adev = dev->dev_private;
1920         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1921         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1922
1923         if (!dig || !dig->afmt)
1924                 return;
1925
1926         /* Silent, r600_hdmi_enable will raise WARN for us */
1927         if (enable && dig->afmt->enabled)
1928                 return;
1929         if (!enable && !dig->afmt->enabled)
1930                 return;
1931
1932         if (!enable && dig->afmt->pin) {
1933                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1934                 dig->afmt->pin = NULL;
1935         }
1936
1937         dig->afmt->enabled = enable;
1938
1939         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1940                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1941 }
1942
1943 static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
1944 {
1945         int i;
1946
1947         for (i = 0; i < adev->mode_info.num_dig; i++)
1948                 adev->mode_info.afmt[i] = NULL;
1949
1950         /* DCE8 has audio blocks tied to DIG encoders */
1951         for (i = 0; i < adev->mode_info.num_dig; i++) {
1952                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1953                 if (adev->mode_info.afmt[i]) {
1954                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1955                         adev->mode_info.afmt[i]->id = i;
1956                 }
1957         }
1958 }
1959
1960 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1961 {
1962         int i;
1963
1964         for (i = 0; i < adev->mode_info.num_dig; i++) {
1965                 kfree(adev->mode_info.afmt[i]);
1966                 adev->mode_info.afmt[i] = NULL;
1967         }
1968 }
1969
1970 static const u32 vga_control_regs[6] =
1971 {
1972         mmD1VGA_CONTROL,
1973         mmD2VGA_CONTROL,
1974         mmD3VGA_CONTROL,
1975         mmD4VGA_CONTROL,
1976         mmD5VGA_CONTROL,
1977         mmD6VGA_CONTROL,
1978 };
1979
1980 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1981 {
1982         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1983         struct drm_device *dev = crtc->dev;
1984         struct amdgpu_device *adev = dev->dev_private;
1985         u32 vga_control;
1986
1987         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1988         if (enable)
1989                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1990         else
1991                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1992 }
1993
1994 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1995 {
1996         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1997         struct drm_device *dev = crtc->dev;
1998         struct amdgpu_device *adev = dev->dev_private;
1999
2000         if (enable)
2001                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2002         else
2003                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2004 }
2005
2006 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
2007                                      struct drm_framebuffer *fb,
2008                                      int x, int y, int atomic)
2009 {
2010         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2011         struct drm_device *dev = crtc->dev;
2012         struct amdgpu_device *adev = dev->dev_private;
2013         struct amdgpu_framebuffer *amdgpu_fb;
2014         struct drm_framebuffer *target_fb;
2015         struct drm_gem_object *obj;
2016         struct amdgpu_bo *rbo;
2017         uint64_t fb_location, tiling_flags;
2018         uint32_t fb_format, fb_pitch_pixels;
2019         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2020         u32 pipe_config;
2021         u32 tmp, viewport_w, viewport_h;
2022         int r;
2023         bool bypass_lut = false;
2024
2025         /* no fb bound */
2026         if (!atomic && !crtc->primary->fb) {
2027                 DRM_DEBUG_KMS("No FB bound\n");
2028                 return 0;
2029         }
2030
2031         if (atomic) {
2032                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2033                 target_fb = fb;
2034         }
2035         else {
2036                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2037                 target_fb = crtc->primary->fb;
2038         }
2039
2040         /* If atomic, assume fb object is pinned & idle & fenced and
2041          * just update base pointers
2042          */
2043         obj = amdgpu_fb->obj;
2044         rbo = gem_to_amdgpu_bo(obj);
2045         r = amdgpu_bo_reserve(rbo, false);
2046         if (unlikely(r != 0))
2047                 return r;
2048
2049         if (atomic)
2050                 fb_location = amdgpu_bo_gpu_offset(rbo);
2051         else {
2052                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2053                 if (unlikely(r != 0)) {
2054                         amdgpu_bo_unreserve(rbo);
2055                         return -EINVAL;
2056                 }
2057         }
2058
2059         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2060         amdgpu_bo_unreserve(rbo);
2061
2062         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2063
2064         switch (target_fb->pixel_format) {
2065         case DRM_FORMAT_C8:
2066                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2067                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2068                 break;
2069         case DRM_FORMAT_XRGB4444:
2070         case DRM_FORMAT_ARGB4444:
2071                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2072                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2073 #ifdef __BIG_ENDIAN
2074                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2075 #endif
2076                 break;
2077         case DRM_FORMAT_XRGB1555:
2078         case DRM_FORMAT_ARGB1555:
2079                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2080                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2081 #ifdef __BIG_ENDIAN
2082                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2083 #endif
2084                 break;
2085         case DRM_FORMAT_BGRX5551:
2086         case DRM_FORMAT_BGRA5551:
2087                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2088                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2089 #ifdef __BIG_ENDIAN
2090                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2091 #endif
2092                 break;
2093         case DRM_FORMAT_RGB565:
2094                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2095                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2096 #ifdef __BIG_ENDIAN
2097                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2098 #endif
2099                 break;
2100         case DRM_FORMAT_XRGB8888:
2101         case DRM_FORMAT_ARGB8888:
2102                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2103                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2104 #ifdef __BIG_ENDIAN
2105                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2106 #endif
2107                 break;
2108         case DRM_FORMAT_XRGB2101010:
2109         case DRM_FORMAT_ARGB2101010:
2110                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2111                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2112 #ifdef __BIG_ENDIAN
2113                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2114 #endif
2115                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2116                 bypass_lut = true;
2117                 break;
2118         case DRM_FORMAT_BGRX1010102:
2119         case DRM_FORMAT_BGRA1010102:
2120                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2121                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2122 #ifdef __BIG_ENDIAN
2123                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2124 #endif
2125                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2126                 bypass_lut = true;
2127                 break;
2128         default:
2129                 DRM_ERROR("Unsupported screen format %s\n",
2130                           drm_get_format_name(target_fb->pixel_format));
2131                 return -EINVAL;
2132         }
2133
2134         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2135                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2136
2137                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2138                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2139                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2140                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2141                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2142
2143                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2144                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2145                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2146                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2147                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2148                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2149                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2150         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2151                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2152         }
2153
2154         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2155
2156         dce_v8_0_vga_enable(crtc, false);
2157
2158         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2159                upper_32_bits(fb_location));
2160         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2161                upper_32_bits(fb_location));
2162         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2163                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2164         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2165                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2166         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2167         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2168
2169         /*
2170          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2171          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2172          * retain the full precision throughout the pipeline.
2173          */
2174         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2175                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2176                  ~LUT_10BIT_BYPASS_EN);
2177
2178         if (bypass_lut)
2179                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2180
2181         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2182         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2183         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2184         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2185         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2186         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2187
2188         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2189         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2190
2191         dce_v8_0_grph_enable(crtc, true);
2192
2193         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2194                target_fb->height);
2195
2196         x &= ~3;
2197         y &= ~1;
2198         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2199                (x << 16) | y);
2200         viewport_w = crtc->mode.hdisplay;
2201         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2202         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2203                (viewport_w << 16) | viewport_h);
2204
2205         /* pageflip setup */
2206         /* make sure flip is at vb rather than hb */
2207         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2208         tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK;
2209         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2210
2211         /* set pageflip to happen only at start of vblank interval (front porch) */
2212         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2213
2214         if (!atomic && fb && fb != crtc->primary->fb) {
2215                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2216                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2217                 r = amdgpu_bo_reserve(rbo, false);
2218                 if (unlikely(r != 0))
2219                         return r;
2220                 amdgpu_bo_unpin(rbo);
2221                 amdgpu_bo_unreserve(rbo);
2222         }
2223
2224         /* Bytes per pixel may have changed */
2225         dce_v8_0_bandwidth_update(adev);
2226
2227         return 0;
2228 }
2229
2230 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2231                                     struct drm_display_mode *mode)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct amdgpu_device *adev = dev->dev_private;
2235         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2236
2237         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2238                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2239                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2240         else
2241                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2242 }
2243
2244 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2245 {
2246         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2247         struct drm_device *dev = crtc->dev;
2248         struct amdgpu_device *adev = dev->dev_private;
2249         int i;
2250
2251         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2252
2253         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2254                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2255                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2256         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2257                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2258         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2259                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2260         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2261                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2262                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2263
2264         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2265
2266         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2267         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2268         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2269
2270         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2271         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2272         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2273
2274         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2275         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2276
2277         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2278         for (i = 0; i < 256; i++) {
2279                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2280                        (amdgpu_crtc->lut_r[i] << 20) |
2281                        (amdgpu_crtc->lut_g[i] << 10) |
2282                        (amdgpu_crtc->lut_b[i] << 0));
2283         }
2284
2285         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2286                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2287                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2288                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2289         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2290                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2291                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2292         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2293                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2294                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2295         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2296                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2297                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2298         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2299         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2300         /* XXX this only needs to be programmed once per crtc at startup,
2301          * not sure where the best place for it is
2302          */
2303         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2304                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2305 }
2306
2307 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2308 {
2309         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2310         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2311
2312         switch (amdgpu_encoder->encoder_id) {
2313         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2314                 if (dig->linkb)
2315                         return 1;
2316                 else
2317                         return 0;
2318                 break;
2319         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2320                 if (dig->linkb)
2321                         return 3;
2322                 else
2323                         return 2;
2324                 break;
2325         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2326                 if (dig->linkb)
2327                         return 5;
2328                 else
2329                         return 4;
2330                 break;
2331         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2332                 return 6;
2333                 break;
2334         default:
2335                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2336                 return 0;
2337         }
2338 }
2339
2340 /**
2341  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2342  *
2343  * @crtc: drm crtc
2344  *
2345  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2346  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2347  * monitors a dedicated PPLL must be used.  If a particular board has
2348  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2349  * as there is no need to program the PLL itself.  If we are not able to
2350  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2351  * avoid messing up an existing monitor.
2352  *
2353  * Asic specific PLL information
2354  *
2355  * DCE 8.x
2356  * KB/KV
2357  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2358  * CI
2359  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2360  *
2361  */
2362 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2363 {
2364         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2365         struct drm_device *dev = crtc->dev;
2366         struct amdgpu_device *adev = dev->dev_private;
2367         u32 pll_in_use;
2368         int pll;
2369
2370         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2371                 if (adev->clock.dp_extclk)
2372                         /* skip PPLL programming if using ext clock */
2373                         return ATOM_PPLL_INVALID;
2374                 else {
2375                         /* use the same PPLL for all DP monitors */
2376                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2377                         if (pll != ATOM_PPLL_INVALID)
2378                                 return pll;
2379                 }
2380         } else {
2381                 /* use the same PPLL for all monitors with the same clock */
2382                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2383                 if (pll != ATOM_PPLL_INVALID)
2384                         return pll;
2385         }
2386         /* otherwise, pick one of the plls */
2387         if ((adev->asic_type == CHIP_KABINI) ||
2388             (adev->asic_type == CHIP_MULLINS)) {
2389                 /* KB/ML has PPLL1 and PPLL2 */
2390                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2391                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2392                         return ATOM_PPLL2;
2393                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2394                         return ATOM_PPLL1;
2395                 DRM_ERROR("unable to allocate a PPLL\n");
2396                 return ATOM_PPLL_INVALID;
2397         } else {
2398                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2399                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2400                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2401                         return ATOM_PPLL2;
2402                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2403                         return ATOM_PPLL1;
2404                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2405                         return ATOM_PPLL0;
2406                 DRM_ERROR("unable to allocate a PPLL\n");
2407                 return ATOM_PPLL_INVALID;
2408         }
2409         return ATOM_PPLL_INVALID;
2410 }
2411
2412 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2413 {
2414         struct amdgpu_device *adev = crtc->dev->dev_private;
2415         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2416         uint32_t cur_lock;
2417
2418         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2419         if (lock)
2420                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2421         else
2422                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2423         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2424 }
2425
2426 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2427 {
2428         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2429         struct amdgpu_device *adev = crtc->dev->dev_private;
2430
2431         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2432                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2433                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2434 }
2435
2436 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2437 {
2438         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2439         struct amdgpu_device *adev = crtc->dev->dev_private;
2440
2441         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2442                upper_32_bits(amdgpu_crtc->cursor_addr));
2443         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2444                lower_32_bits(amdgpu_crtc->cursor_addr));
2445
2446         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2447                    CUR_CONTROL__CURSOR_EN_MASK |
2448                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2449                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2450 }
2451
2452 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2453                                        int x, int y)
2454 {
2455         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2456         struct amdgpu_device *adev = crtc->dev->dev_private;
2457         int xorigin = 0, yorigin = 0;
2458
2459         /* avivo cursor are offset into the total surface */
2460         x += crtc->x;
2461         y += crtc->y;
2462         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2463
2464         if (x < 0) {
2465                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2466                 x = 0;
2467         }
2468         if (y < 0) {
2469                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2470                 y = 0;
2471         }
2472
2473         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2474         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2475         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2476                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2477
2478         amdgpu_crtc->cursor_x = x;
2479         amdgpu_crtc->cursor_y = y;
2480
2481         return 0;
2482 }
2483
2484 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2485                                      int x, int y)
2486 {
2487         int ret;
2488
2489         dce_v8_0_lock_cursor(crtc, true);
2490         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2491         dce_v8_0_lock_cursor(crtc, false);
2492
2493         return ret;
2494 }
2495
2496 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2497                                      struct drm_file *file_priv,
2498                                      uint32_t handle,
2499                                      uint32_t width,
2500                                      uint32_t height,
2501                                      int32_t hot_x,
2502                                      int32_t hot_y)
2503 {
2504         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2505         struct drm_gem_object *obj;
2506         struct amdgpu_bo *aobj;
2507         int ret;
2508
2509         if (!handle) {
2510                 /* turn off cursor */
2511                 dce_v8_0_hide_cursor(crtc);
2512                 obj = NULL;
2513                 goto unpin;
2514         }
2515
2516         if ((width > amdgpu_crtc->max_cursor_width) ||
2517             (height > amdgpu_crtc->max_cursor_height)) {
2518                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2519                 return -EINVAL;
2520         }
2521
2522         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2523         if (!obj) {
2524                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2525                 return -ENOENT;
2526         }
2527
2528         aobj = gem_to_amdgpu_bo(obj);
2529         ret = amdgpu_bo_reserve(aobj, false);
2530         if (ret != 0) {
2531                 drm_gem_object_unreference_unlocked(obj);
2532                 return ret;
2533         }
2534
2535         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2536         amdgpu_bo_unreserve(aobj);
2537         if (ret) {
2538                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2539                 drm_gem_object_unreference_unlocked(obj);
2540                 return ret;
2541         }
2542
2543         amdgpu_crtc->cursor_width = width;
2544         amdgpu_crtc->cursor_height = height;
2545
2546         dce_v8_0_lock_cursor(crtc, true);
2547
2548         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2549             hot_y != amdgpu_crtc->cursor_hot_y) {
2550                 int x, y;
2551
2552                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2553                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2554
2555                 dce_v8_0_cursor_move_locked(crtc, x, y);
2556
2557                 amdgpu_crtc->cursor_hot_x = hot_x;
2558                 amdgpu_crtc->cursor_hot_y = hot_y;
2559         }
2560
2561         dce_v8_0_show_cursor(crtc);
2562         dce_v8_0_lock_cursor(crtc, false);
2563
2564 unpin:
2565         if (amdgpu_crtc->cursor_bo) {
2566                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2567                 ret = amdgpu_bo_reserve(aobj, false);
2568                 if (likely(ret == 0)) {
2569                         amdgpu_bo_unpin(aobj);
2570                         amdgpu_bo_unreserve(aobj);
2571                 }
2572                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2573         }
2574
2575         amdgpu_crtc->cursor_bo = obj;
2576         return 0;
2577 }
2578
2579 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2580 {
2581         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2582
2583         if (amdgpu_crtc->cursor_bo) {
2584                 dce_v8_0_lock_cursor(crtc, true);
2585
2586                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2587                                             amdgpu_crtc->cursor_y);
2588
2589                 dce_v8_0_show_cursor(crtc);
2590
2591                 dce_v8_0_lock_cursor(crtc, false);
2592         }
2593 }
2594
2595 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2596                                     u16 *blue, uint32_t start, uint32_t size)
2597 {
2598         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2599         int end = (start + size > 256) ? 256 : start + size, i;
2600
2601         /* userspace palettes are always correct as is */
2602         for (i = start; i < end; i++) {
2603                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2604                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2605                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2606         }
2607         dce_v8_0_crtc_load_lut(crtc);
2608 }
2609
2610 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2611 {
2612         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2613
2614         drm_crtc_cleanup(crtc);
2615         destroy_workqueue(amdgpu_crtc->pflip_queue);
2616         kfree(amdgpu_crtc);
2617 }
2618
2619 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2620         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2621         .cursor_move = dce_v8_0_crtc_cursor_move,
2622         .gamma_set = dce_v8_0_crtc_gamma_set,
2623         .set_config = amdgpu_crtc_set_config,
2624         .destroy = dce_v8_0_crtc_destroy,
2625         .page_flip = amdgpu_crtc_page_flip,
2626 };
2627
2628 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2629 {
2630         struct drm_device *dev = crtc->dev;
2631         struct amdgpu_device *adev = dev->dev_private;
2632         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2633         unsigned type;
2634
2635         switch (mode) {
2636         case DRM_MODE_DPMS_ON:
2637                 amdgpu_crtc->enabled = true;
2638                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2639                 dce_v8_0_vga_enable(crtc, true);
2640                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2641                 dce_v8_0_vga_enable(crtc, false);
2642                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2643                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2644                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2645                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2646                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2647                 dce_v8_0_crtc_load_lut(crtc);
2648                 break;
2649         case DRM_MODE_DPMS_STANDBY:
2650         case DRM_MODE_DPMS_SUSPEND:
2651         case DRM_MODE_DPMS_OFF:
2652                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2653                 if (amdgpu_crtc->enabled) {
2654                         dce_v8_0_vga_enable(crtc, true);
2655                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2656                         dce_v8_0_vga_enable(crtc, false);
2657                 }
2658                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2659                 amdgpu_crtc->enabled = false;
2660                 break;
2661         }
2662         /* adjust pm to dpms */
2663         amdgpu_pm_compute_clocks(adev);
2664 }
2665
2666 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2667 {
2668         /* disable crtc pair power gating before programming */
2669         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2670         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2671         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2672 }
2673
2674 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2675 {
2676         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2677         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2678 }
2679
2680 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2681 {
2682         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2683         struct drm_device *dev = crtc->dev;
2684         struct amdgpu_device *adev = dev->dev_private;
2685         struct amdgpu_atom_ss ss;
2686         int i;
2687
2688         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2689         if (crtc->primary->fb) {
2690                 int r;
2691                 struct amdgpu_framebuffer *amdgpu_fb;
2692                 struct amdgpu_bo *rbo;
2693
2694                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2695                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2696                 r = amdgpu_bo_reserve(rbo, false);
2697                 if (unlikely(r))
2698                         DRM_ERROR("failed to reserve rbo before unpin\n");
2699                 else {
2700                         amdgpu_bo_unpin(rbo);
2701                         amdgpu_bo_unreserve(rbo);
2702                 }
2703         }
2704         /* disable the GRPH */
2705         dce_v8_0_grph_enable(crtc, false);
2706
2707         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2708
2709         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2710                 if (adev->mode_info.crtcs[i] &&
2711                     adev->mode_info.crtcs[i]->enabled &&
2712                     i != amdgpu_crtc->crtc_id &&
2713                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2714                         /* one other crtc is using this pll don't turn
2715                          * off the pll
2716                          */
2717                         goto done;
2718                 }
2719         }
2720
2721         switch (amdgpu_crtc->pll_id) {
2722         case ATOM_PPLL1:
2723         case ATOM_PPLL2:
2724                 /* disable the ppll */
2725                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2726                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2727                 break;
2728         case ATOM_PPLL0:
2729                 /* disable the ppll */
2730                 if ((adev->asic_type == CHIP_KAVERI) ||
2731                     (adev->asic_type == CHIP_BONAIRE) ||
2732                     (adev->asic_type == CHIP_HAWAII))
2733                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2734                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2735                 break;
2736         default:
2737                 break;
2738         }
2739 done:
2740         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2741         amdgpu_crtc->adjusted_clock = 0;
2742         amdgpu_crtc->encoder = NULL;
2743         amdgpu_crtc->connector = NULL;
2744 }
2745
2746 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2747                                   struct drm_display_mode *mode,
2748                                   struct drm_display_mode *adjusted_mode,
2749                                   int x, int y, struct drm_framebuffer *old_fb)
2750 {
2751         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2752
2753         if (!amdgpu_crtc->adjusted_clock)
2754                 return -EINVAL;
2755
2756         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2757         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2758         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2759         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2760         amdgpu_atombios_crtc_scaler_setup(crtc);
2761         dce_v8_0_cursor_reset(crtc);
2762         /* update the hw version fpr dpm */
2763         amdgpu_crtc->hw_mode = *adjusted_mode;
2764
2765         return 0;
2766 }
2767
2768 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2769                                      const struct drm_display_mode *mode,
2770                                      struct drm_display_mode *adjusted_mode)
2771 {
2772         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2773         struct drm_device *dev = crtc->dev;
2774         struct drm_encoder *encoder;
2775
2776         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2777         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2778                 if (encoder->crtc == crtc) {
2779                         amdgpu_crtc->encoder = encoder;
2780                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2781                         break;
2782                 }
2783         }
2784         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2785                 amdgpu_crtc->encoder = NULL;
2786                 amdgpu_crtc->connector = NULL;
2787                 return false;
2788         }
2789         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2790                 return false;
2791         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2792                 return false;
2793         /* pick pll */
2794         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2795         /* if we can't get a PPLL for a non-DP encoder, fail */
2796         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2797             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2798                 return false;
2799
2800         return true;
2801 }
2802
2803 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2804                                   struct drm_framebuffer *old_fb)
2805 {
2806         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2807 }
2808
2809 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2810                                          struct drm_framebuffer *fb,
2811                                          int x, int y, enum mode_set_atomic state)
2812 {
2813        return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2814 }
2815
2816 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2817         .dpms = dce_v8_0_crtc_dpms,
2818         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2819         .mode_set = dce_v8_0_crtc_mode_set,
2820         .mode_set_base = dce_v8_0_crtc_set_base,
2821         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2822         .prepare = dce_v8_0_crtc_prepare,
2823         .commit = dce_v8_0_crtc_commit,
2824         .load_lut = dce_v8_0_crtc_load_lut,
2825         .disable = dce_v8_0_crtc_disable,
2826 };
2827
2828 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2829 {
2830         struct amdgpu_crtc *amdgpu_crtc;
2831         int i;
2832
2833         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2834                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2835         if (amdgpu_crtc == NULL)
2836                 return -ENOMEM;
2837
2838         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2839
2840         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2841         amdgpu_crtc->crtc_id = index;
2842         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2843         adev->mode_info.crtcs[index] = amdgpu_crtc;
2844
2845         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2846         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2847         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2848         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2849
2850         for (i = 0; i < 256; i++) {
2851                 amdgpu_crtc->lut_r[i] = i << 2;
2852                 amdgpu_crtc->lut_g[i] = i << 2;
2853                 amdgpu_crtc->lut_b[i] = i << 2;
2854         }
2855
2856         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2857
2858         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2859         amdgpu_crtc->adjusted_clock = 0;
2860         amdgpu_crtc->encoder = NULL;
2861         amdgpu_crtc->connector = NULL;
2862         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2863
2864         return 0;
2865 }
2866
2867 static int dce_v8_0_early_init(void *handle)
2868 {
2869         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2870
2871         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2872         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2873
2874         dce_v8_0_set_display_funcs(adev);
2875         dce_v8_0_set_irq_funcs(adev);
2876
2877         switch (adev->asic_type) {
2878         case CHIP_BONAIRE:
2879         case CHIP_HAWAII:
2880                 adev->mode_info.num_crtc = 6;
2881                 adev->mode_info.num_hpd = 6;
2882                 adev->mode_info.num_dig = 6;
2883                 break;
2884         case CHIP_KAVERI:
2885                 adev->mode_info.num_crtc = 4;
2886                 adev->mode_info.num_hpd = 6;
2887                 adev->mode_info.num_dig = 7;
2888                 break;
2889         case CHIP_KABINI:
2890         case CHIP_MULLINS:
2891                 adev->mode_info.num_crtc = 2;
2892                 adev->mode_info.num_hpd = 6;
2893                 adev->mode_info.num_dig = 6; /* ? */
2894                 break;
2895         default:
2896                 /* FIXME: not supported yet */
2897                 return -EINVAL;
2898         }
2899
2900         return 0;
2901 }
2902
2903 static int dce_v8_0_sw_init(void *handle)
2904 {
2905         int r, i;
2906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2907
2908         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2909                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2910                 if (r)
2911                         return r;
2912         }
2913
2914         for (i = 8; i < 20; i += 2) {
2915                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2916                 if (r)
2917                         return r;
2918         }
2919
2920         /* HPD hotplug */
2921         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2922         if (r)
2923                 return r;
2924
2925         adev->mode_info.mode_config_initialized = true;
2926
2927         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2928
2929         adev->ddev->mode_config.max_width = 16384;
2930         adev->ddev->mode_config.max_height = 16384;
2931
2932         adev->ddev->mode_config.preferred_depth = 24;
2933         adev->ddev->mode_config.prefer_shadow = 1;
2934
2935         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2936
2937         r = amdgpu_modeset_create_props(adev);
2938         if (r)
2939                 return r;
2940
2941         adev->ddev->mode_config.max_width = 16384;
2942         adev->ddev->mode_config.max_height = 16384;
2943
2944         /* allocate crtcs */
2945         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2946                 r = dce_v8_0_crtc_init(adev, i);
2947                 if (r)
2948                         return r;
2949         }
2950
2951         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2952                 amdgpu_print_display_setup(adev->ddev);
2953         else
2954                 return -EINVAL;
2955
2956         /* setup afmt */
2957         dce_v8_0_afmt_init(adev);
2958
2959         r = dce_v8_0_audio_init(adev);
2960         if (r)
2961                 return r;
2962
2963         drm_kms_helper_poll_init(adev->ddev);
2964
2965         return r;
2966 }
2967
2968 static int dce_v8_0_sw_fini(void *handle)
2969 {
2970         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2971
2972         kfree(adev->mode_info.bios_hardcoded_edid);
2973
2974         drm_kms_helper_poll_fini(adev->ddev);
2975
2976         dce_v8_0_audio_fini(adev);
2977
2978         dce_v8_0_afmt_fini(adev);
2979
2980         drm_mode_config_cleanup(adev->ddev);
2981         adev->mode_info.mode_config_initialized = false;
2982
2983         return 0;
2984 }
2985
2986 static int dce_v8_0_hw_init(void *handle)
2987 {
2988         int i;
2989         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2990
2991         /* init dig PHYs, disp eng pll */
2992         amdgpu_atombios_encoder_init_dig(adev);
2993         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2994
2995         /* initialize hpd */
2996         dce_v8_0_hpd_init(adev);
2997
2998         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2999                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3000         }
3001
3002         dce_v8_0_pageflip_interrupt_init(adev);
3003
3004         return 0;
3005 }
3006
3007 static int dce_v8_0_hw_fini(void *handle)
3008 {
3009         int i;
3010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3011
3012         dce_v8_0_hpd_fini(adev);
3013
3014         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3015                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3016         }
3017
3018         dce_v8_0_pageflip_interrupt_fini(adev);
3019
3020         return 0;
3021 }
3022
3023 static int dce_v8_0_suspend(void *handle)
3024 {
3025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3026
3027         amdgpu_atombios_scratch_regs_save(adev);
3028
3029         return dce_v8_0_hw_fini(handle);
3030 }
3031
3032 static int dce_v8_0_resume(void *handle)
3033 {
3034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3035         int ret;
3036
3037         ret = dce_v8_0_hw_init(handle);
3038
3039         amdgpu_atombios_scratch_regs_restore(adev);
3040
3041         /* turn on the BL */
3042         if (adev->mode_info.bl_encoder) {
3043                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3044                                                                   adev->mode_info.bl_encoder);
3045                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3046                                                     bl_level);
3047         }
3048
3049         return ret;
3050 }
3051
3052 static bool dce_v8_0_is_idle(void *handle)
3053 {
3054         return true;
3055 }
3056
3057 static int dce_v8_0_wait_for_idle(void *handle)
3058 {
3059         return 0;
3060 }
3061
3062 static void dce_v8_0_print_status(void *handle)
3063 {
3064         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065
3066         dev_info(adev->dev, "DCE 8.x registers\n");
3067         /* XXX todo */
3068 }
3069
3070 static int dce_v8_0_soft_reset(void *handle)
3071 {
3072         u32 srbm_soft_reset = 0, tmp;
3073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3074
3075         if (dce_v8_0_is_display_hung(adev))
3076                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3077
3078         if (srbm_soft_reset) {
3079                 dce_v8_0_print_status((void *)adev);
3080
3081                 tmp = RREG32(mmSRBM_SOFT_RESET);
3082                 tmp |= srbm_soft_reset;
3083                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3084                 WREG32(mmSRBM_SOFT_RESET, tmp);
3085                 tmp = RREG32(mmSRBM_SOFT_RESET);
3086
3087                 udelay(50);
3088
3089                 tmp &= ~srbm_soft_reset;
3090                 WREG32(mmSRBM_SOFT_RESET, tmp);
3091                 tmp = RREG32(mmSRBM_SOFT_RESET);
3092
3093                 /* Wait a little for things to settle down */
3094                 udelay(50);
3095                 dce_v8_0_print_status((void *)adev);
3096         }
3097         return 0;
3098 }
3099
3100 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3101                                                      int crtc,
3102                                                      enum amdgpu_interrupt_state state)
3103 {
3104         u32 reg_block, lb_interrupt_mask;
3105
3106         if (crtc >= adev->mode_info.num_crtc) {
3107                 DRM_DEBUG("invalid crtc %d\n", crtc);
3108                 return;
3109         }
3110
3111         switch (crtc) {
3112         case 0:
3113                 reg_block = CRTC0_REGISTER_OFFSET;
3114                 break;
3115         case 1:
3116                 reg_block = CRTC1_REGISTER_OFFSET;
3117                 break;
3118         case 2:
3119                 reg_block = CRTC2_REGISTER_OFFSET;
3120                 break;
3121         case 3:
3122                 reg_block = CRTC3_REGISTER_OFFSET;
3123                 break;
3124         case 4:
3125                 reg_block = CRTC4_REGISTER_OFFSET;
3126                 break;
3127         case 5:
3128                 reg_block = CRTC5_REGISTER_OFFSET;
3129                 break;
3130         default:
3131                 DRM_DEBUG("invalid crtc %d\n", crtc);
3132                 return;
3133         }
3134
3135         switch (state) {
3136         case AMDGPU_IRQ_STATE_DISABLE:
3137                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3138                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3139                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3140                 break;
3141         case AMDGPU_IRQ_STATE_ENABLE:
3142                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3143                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3144                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3145                 break;
3146         default:
3147                 break;
3148         }
3149 }
3150
3151 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3152                                                     int crtc,
3153                                                     enum amdgpu_interrupt_state state)
3154 {
3155         u32 reg_block, lb_interrupt_mask;
3156
3157         if (crtc >= adev->mode_info.num_crtc) {
3158                 DRM_DEBUG("invalid crtc %d\n", crtc);
3159                 return;
3160         }
3161
3162         switch (crtc) {
3163         case 0:
3164                 reg_block = CRTC0_REGISTER_OFFSET;
3165                 break;
3166         case 1:
3167                 reg_block = CRTC1_REGISTER_OFFSET;
3168                 break;
3169         case 2:
3170                 reg_block = CRTC2_REGISTER_OFFSET;
3171                 break;
3172         case 3:
3173                 reg_block = CRTC3_REGISTER_OFFSET;
3174                 break;
3175         case 4:
3176                 reg_block = CRTC4_REGISTER_OFFSET;
3177                 break;
3178         case 5:
3179                 reg_block = CRTC5_REGISTER_OFFSET;
3180                 break;
3181         default:
3182                 DRM_DEBUG("invalid crtc %d\n", crtc);
3183                 return;
3184         }
3185
3186         switch (state) {
3187         case AMDGPU_IRQ_STATE_DISABLE:
3188                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3189                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3190                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3191                 break;
3192         case AMDGPU_IRQ_STATE_ENABLE:
3193                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3194                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3195                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3196                 break;
3197         default:
3198                 break;
3199         }
3200 }
3201
3202 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3203                                             struct amdgpu_irq_src *src,
3204                                             unsigned type,
3205                                             enum amdgpu_interrupt_state state)
3206 {
3207         u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3208
3209         switch (type) {
3210         case AMDGPU_HPD_1:
3211                 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3212                 break;
3213         case AMDGPU_HPD_2:
3214                 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3215                 break;
3216         case AMDGPU_HPD_3:
3217                 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3218                 break;
3219         case AMDGPU_HPD_4:
3220                 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3221                 break;
3222         case AMDGPU_HPD_5:
3223                 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3224                 break;
3225         case AMDGPU_HPD_6:
3226                 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3227                 break;
3228         default:
3229                 DRM_DEBUG("invalid hdp %d\n", type);
3230                 return 0;
3231         }
3232
3233         switch (state) {
3234         case AMDGPU_IRQ_STATE_DISABLE:
3235                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3236                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3237                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3238                 break;
3239         case AMDGPU_IRQ_STATE_ENABLE:
3240                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3241                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3242                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3243                 break;
3244         default:
3245                 break;
3246         }
3247
3248         return 0;
3249 }
3250
3251 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3252                                              struct amdgpu_irq_src *src,
3253                                              unsigned type,
3254                                              enum amdgpu_interrupt_state state)
3255 {
3256         switch (type) {
3257         case AMDGPU_CRTC_IRQ_VBLANK1:
3258                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3259                 break;
3260         case AMDGPU_CRTC_IRQ_VBLANK2:
3261                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3262                 break;
3263         case AMDGPU_CRTC_IRQ_VBLANK3:
3264                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3265                 break;
3266         case AMDGPU_CRTC_IRQ_VBLANK4:
3267                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3268                 break;
3269         case AMDGPU_CRTC_IRQ_VBLANK5:
3270                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3271                 break;
3272         case AMDGPU_CRTC_IRQ_VBLANK6:
3273                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3274                 break;
3275         case AMDGPU_CRTC_IRQ_VLINE1:
3276                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3277                 break;
3278         case AMDGPU_CRTC_IRQ_VLINE2:
3279                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3280                 break;
3281         case AMDGPU_CRTC_IRQ_VLINE3:
3282                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3283                 break;
3284         case AMDGPU_CRTC_IRQ_VLINE4:
3285                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3286                 break;
3287         case AMDGPU_CRTC_IRQ_VLINE5:
3288                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3289                 break;
3290         case AMDGPU_CRTC_IRQ_VLINE6:
3291                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3292                 break;
3293         default:
3294                 break;
3295         }
3296         return 0;
3297 }
3298
3299 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3300                              struct amdgpu_irq_src *source,
3301                              struct amdgpu_iv_entry *entry)
3302 {
3303         unsigned crtc = entry->src_id - 1;
3304         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3305         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3306
3307         switch (entry->src_data) {
3308         case 0: /* vblank */
3309                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3310                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3311                 else
3312                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3313
3314                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3315                         drm_handle_vblank(adev->ddev, crtc);
3316                 }
3317                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3318
3319                 break;
3320         case 1: /* vline */
3321                 if (disp_int & interrupt_status_offsets[crtc].vline)
3322                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3323                 else
3324                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3325
3326                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3327
3328                 break;
3329         default:
3330                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3331                 break;
3332         }
3333
3334         return 0;
3335 }
3336
3337 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3338                                                  struct amdgpu_irq_src *src,
3339                                                  unsigned type,
3340                                                  enum amdgpu_interrupt_state state)
3341 {
3342         u32 reg;
3343
3344         if (type >= adev->mode_info.num_crtc) {
3345                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3346                 return -EINVAL;
3347         }
3348
3349         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3350         if (state == AMDGPU_IRQ_STATE_DISABLE)
3351                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3352                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3353         else
3354                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3355                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3356
3357         return 0;
3358 }
3359
3360 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3361                                 struct amdgpu_irq_src *source,
3362                                 struct amdgpu_iv_entry *entry)
3363 {
3364         unsigned long flags;
3365         unsigned crtc_id;
3366         struct amdgpu_crtc *amdgpu_crtc;
3367         struct amdgpu_flip_work *works;
3368
3369         crtc_id = (entry->src_id - 8) >> 1;
3370         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3371
3372         if (crtc_id >= adev->mode_info.num_crtc) {
3373                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3374                 return -EINVAL;
3375         }
3376
3377         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3378             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3379                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3380                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3381
3382         /* IRQ could occur when in initial stage */
3383         if (amdgpu_crtc == NULL)
3384                 return 0;
3385
3386         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3387         works = amdgpu_crtc->pflip_works;
3388         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3389                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3390                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3391                                                 amdgpu_crtc->pflip_status,
3392                                                 AMDGPU_FLIP_SUBMITTED);
3393                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3394                 return 0;
3395         }
3396
3397         /* page flip completed. clean up */
3398         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3399         amdgpu_crtc->pflip_works = NULL;
3400
3401         /* wakeup usersapce */
3402         if (works->event)
3403                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3404
3405         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3406
3407         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3408         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3409
3410         return 0;
3411 }
3412
3413 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3414                             struct amdgpu_irq_src *source,
3415                             struct amdgpu_iv_entry *entry)
3416 {
3417         uint32_t disp_int, mask, int_control, tmp;
3418         unsigned hpd;
3419
3420         if (entry->src_data >= adev->mode_info.num_hpd) {
3421                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3422                 return 0;
3423         }
3424
3425         hpd = entry->src_data;
3426         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3427         mask = interrupt_status_offsets[hpd].hpd;
3428         int_control = hpd_int_control_offsets[hpd];
3429
3430         if (disp_int & mask) {
3431                 tmp = RREG32(int_control);
3432                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3433                 WREG32(int_control, tmp);
3434                 schedule_work(&adev->hotplug_work);
3435                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3436         }
3437
3438         return 0;
3439
3440 }
3441
3442 static int dce_v8_0_set_clockgating_state(void *handle,
3443                                           enum amd_clockgating_state state)
3444 {
3445         return 0;
3446 }
3447
3448 static int dce_v8_0_set_powergating_state(void *handle,
3449                                           enum amd_powergating_state state)
3450 {
3451         return 0;
3452 }
3453
3454 const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3455         .early_init = dce_v8_0_early_init,
3456         .late_init = NULL,
3457         .sw_init = dce_v8_0_sw_init,
3458         .sw_fini = dce_v8_0_sw_fini,
3459         .hw_init = dce_v8_0_hw_init,
3460         .hw_fini = dce_v8_0_hw_fini,
3461         .suspend = dce_v8_0_suspend,
3462         .resume = dce_v8_0_resume,
3463         .is_idle = dce_v8_0_is_idle,
3464         .wait_for_idle = dce_v8_0_wait_for_idle,
3465         .soft_reset = dce_v8_0_soft_reset,
3466         .print_status = dce_v8_0_print_status,
3467         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3468         .set_powergating_state = dce_v8_0_set_powergating_state,
3469 };
3470
3471 static void
3472 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3473                           struct drm_display_mode *mode,
3474                           struct drm_display_mode *adjusted_mode)
3475 {
3476         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3477
3478         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3479
3480         /* need to call this here rather than in prepare() since we need some crtc info */
3481         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3482
3483         /* set scaler clears this on some chips */
3484         dce_v8_0_set_interleave(encoder->crtc, mode);
3485
3486         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3487                 dce_v8_0_afmt_enable(encoder, true);
3488                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3489         }
3490 }
3491
3492 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3493 {
3494         struct amdgpu_device *adev = encoder->dev->dev_private;
3495         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3496         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3497
3498         if ((amdgpu_encoder->active_device &
3499              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3500             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3501              ENCODER_OBJECT_ID_NONE)) {
3502                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3503                 if (dig) {
3504                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3505                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3506                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3507                 }
3508         }
3509
3510         amdgpu_atombios_scratch_regs_lock(adev, true);
3511
3512         if (connector) {
3513                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3514
3515                 /* select the clock/data port if it uses a router */
3516                 if (amdgpu_connector->router.cd_valid)
3517                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3518
3519                 /* turn eDP panel on for mode set */
3520                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3521                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3522                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3523         }
3524
3525         /* this is needed for the pll/ss setup to work correctly in some cases */
3526         amdgpu_atombios_encoder_set_crtc_source(encoder);
3527         /* set up the FMT blocks */
3528         dce_v8_0_program_fmt(encoder);
3529 }
3530
3531 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3532 {
3533         struct drm_device *dev = encoder->dev;
3534         struct amdgpu_device *adev = dev->dev_private;
3535
3536         /* need to call this here as we need the crtc set up */
3537         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3538         amdgpu_atombios_scratch_regs_lock(adev, false);
3539 }
3540
3541 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3542 {
3543         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3544         struct amdgpu_encoder_atom_dig *dig;
3545
3546         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3547
3548         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3549                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3550                         dce_v8_0_afmt_enable(encoder, false);
3551                 dig = amdgpu_encoder->enc_priv;
3552                 dig->dig_encoder = -1;
3553         }
3554         amdgpu_encoder->active_device = 0;
3555 }
3556
3557 /* these are handled by the primary encoders */
3558 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3559 {
3560
3561 }
3562
3563 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3564 {
3565
3566 }
3567
3568 static void
3569 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3570                       struct drm_display_mode *mode,
3571                       struct drm_display_mode *adjusted_mode)
3572 {
3573
3574 }
3575
3576 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3577 {
3578
3579 }
3580
3581 static void
3582 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3583 {
3584
3585 }
3586
3587 static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder,
3588                                     const struct drm_display_mode *mode,
3589                                     struct drm_display_mode *adjusted_mode)
3590 {
3591         return true;
3592 }
3593
3594 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3595         .dpms = dce_v8_0_ext_dpms,
3596         .mode_fixup = dce_v8_0_ext_mode_fixup,
3597         .prepare = dce_v8_0_ext_prepare,
3598         .mode_set = dce_v8_0_ext_mode_set,
3599         .commit = dce_v8_0_ext_commit,
3600         .disable = dce_v8_0_ext_disable,
3601         /* no detect for TMDS/LVDS yet */
3602 };
3603
3604 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3605         .dpms = amdgpu_atombios_encoder_dpms,
3606         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3607         .prepare = dce_v8_0_encoder_prepare,
3608         .mode_set = dce_v8_0_encoder_mode_set,
3609         .commit = dce_v8_0_encoder_commit,
3610         .disable = dce_v8_0_encoder_disable,
3611         .detect = amdgpu_atombios_encoder_dig_detect,
3612 };
3613
3614 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3615         .dpms = amdgpu_atombios_encoder_dpms,
3616         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3617         .prepare = dce_v8_0_encoder_prepare,
3618         .mode_set = dce_v8_0_encoder_mode_set,
3619         .commit = dce_v8_0_encoder_commit,
3620         .detect = amdgpu_atombios_encoder_dac_detect,
3621 };
3622
3623 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3624 {
3625         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3626         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3627                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3628         kfree(amdgpu_encoder->enc_priv);
3629         drm_encoder_cleanup(encoder);
3630         kfree(amdgpu_encoder);
3631 }
3632
3633 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3634         .destroy = dce_v8_0_encoder_destroy,
3635 };
3636
3637 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3638                                  uint32_t encoder_enum,
3639                                  uint32_t supported_device,
3640                                  u16 caps)
3641 {
3642         struct drm_device *dev = adev->ddev;
3643         struct drm_encoder *encoder;
3644         struct amdgpu_encoder *amdgpu_encoder;
3645
3646         /* see if we already added it */
3647         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3648                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3649                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3650                         amdgpu_encoder->devices |= supported_device;
3651                         return;
3652                 }
3653
3654         }
3655
3656         /* add a new one */
3657         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3658         if (!amdgpu_encoder)
3659                 return;
3660
3661         encoder = &amdgpu_encoder->base;
3662         switch (adev->mode_info.num_crtc) {
3663         case 1:
3664                 encoder->possible_crtcs = 0x1;
3665                 break;
3666         case 2:
3667         default:
3668                 encoder->possible_crtcs = 0x3;
3669                 break;
3670         case 4:
3671                 encoder->possible_crtcs = 0xf;
3672                 break;
3673         case 6:
3674                 encoder->possible_crtcs = 0x3f;
3675                 break;
3676         }
3677
3678         amdgpu_encoder->enc_priv = NULL;
3679
3680         amdgpu_encoder->encoder_enum = encoder_enum;
3681         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3682         amdgpu_encoder->devices = supported_device;
3683         amdgpu_encoder->rmx_type = RMX_OFF;
3684         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3685         amdgpu_encoder->is_ext_encoder = false;
3686         amdgpu_encoder->caps = caps;
3687
3688         switch (amdgpu_encoder->encoder_id) {
3689         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3690         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3691                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3692                                  DRM_MODE_ENCODER_DAC);
3693                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3694                 break;
3695         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3696         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3697         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3698         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3699         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3700                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3701                         amdgpu_encoder->rmx_type = RMX_FULL;
3702                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3703                                          DRM_MODE_ENCODER_LVDS);
3704                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3705                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3706                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3707                                          DRM_MODE_ENCODER_DAC);
3708                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3709                 } else {
3710                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3711                                          DRM_MODE_ENCODER_TMDS);
3712                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3713                 }
3714                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3715                 break;
3716         case ENCODER_OBJECT_ID_SI170B:
3717         case ENCODER_OBJECT_ID_CH7303:
3718         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3719         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3720         case ENCODER_OBJECT_ID_TITFP513:
3721         case ENCODER_OBJECT_ID_VT1623:
3722         case ENCODER_OBJECT_ID_HDMI_SI1930:
3723         case ENCODER_OBJECT_ID_TRAVIS:
3724         case ENCODER_OBJECT_ID_NUTMEG:
3725                 /* these are handled by the primary encoders */
3726                 amdgpu_encoder->is_ext_encoder = true;
3727                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3728                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3729                                          DRM_MODE_ENCODER_LVDS);
3730                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3731                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3732                                          DRM_MODE_ENCODER_DAC);
3733                 else
3734                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3735                                          DRM_MODE_ENCODER_TMDS);
3736                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3737                 break;
3738         }
3739 }
3740
3741 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3742         .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3743         .bandwidth_update = &dce_v8_0_bandwidth_update,
3744         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3745         .vblank_wait = &dce_v8_0_vblank_wait,
3746         .is_display_hung = &dce_v8_0_is_display_hung,
3747         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3748         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3749         .hpd_sense = &dce_v8_0_hpd_sense,
3750         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3751         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3752         .page_flip = &dce_v8_0_page_flip,
3753         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3754         .add_encoder = &dce_v8_0_encoder_add,
3755         .add_connector = &amdgpu_connector_add,
3756         .stop_mc_access = &dce_v8_0_stop_mc_access,
3757         .resume_mc_access = &dce_v8_0_resume_mc_access,
3758 };
3759
3760 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3761 {
3762         if (adev->mode_info.funcs == NULL)
3763                 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3764 }
3765
3766 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3767         .set = dce_v8_0_set_crtc_interrupt_state,
3768         .process = dce_v8_0_crtc_irq,
3769 };
3770
3771 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3772         .set = dce_v8_0_set_pageflip_interrupt_state,
3773         .process = dce_v8_0_pageflip_irq,
3774 };
3775
3776 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3777         .set = dce_v8_0_set_hpd_interrupt_state,
3778         .process = dce_v8_0_hpd_irq,
3779 };
3780
3781 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3782 {
3783         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3784         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3785
3786         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3787         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3788
3789         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3790         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3791 }