kernel/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static const u32 tonga_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 golden_settings_fiji_a10[] =
 130 {
 131         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 132         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 133         mmFBC_MISC, 0x1f311fff, 0x12300000,
 134         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 135 };
 136
 137 static const u32 fiji_mgcg_cgcg_init[] =
 138 {
 139         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 140         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 141 };
 142
 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 144 {
 145         switch (adev->asic_type) {
 146         case CHIP_FIJI:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  fiji_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_fiji_a10,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 153                 break;
 154         case CHIP_TONGA:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  tonga_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_tonga_a11,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 168                                      u32 block_offset, u32 reg)
 169 {
 170         unsigned long flags;
 171         u32 r;
 172
 173         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 174         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 175         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 176         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 177
 178         return r;
 179 }
 180
 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 182                                       u32 block_offset, u32 reg, u32 v)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 187         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 189         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 190 }
 191
 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 193 {
 194         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 195                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 196                 return true;
 197         else
 198                 return false;
 199 }
 200
 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 202 {
 203         u32 pos1, pos2;
 204
 205         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207
 208         if (pos1 != pos2)
 209                 return true;
 210         else
 211                 return false;
 212 }
 213
 214 /**
 215  * dce_v10_0_vblank_wait - vblank wait asic callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @crtc: crtc to wait for vblank on
 219  *
 220  * Wait for vblank on the requested crtc (evergreen+).
 221  */
 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 223 {
 224         unsigned i = 0;
 225
 226         if (crtc >= adev->mode_info.num_crtc)
 227                 return;
 228
 229         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 230                 return;
 231
 232         /* depending on when we hit vblank, we may be close to active; if so,
 233          * wait for another frame.
 234          */
 235         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 236                 if (i++ % 100 == 0) {
 237                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 238                                 break;
 239                 }
 240         }
 241
 242         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 243                 if (i++ % 100 == 0) {
 244                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 245                                 break;
 246                 }
 247         }
 248 }
 249
 250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 251 {
 252         if (crtc >= adev->mode_info.num_crtc)
 253                 return 0;
 254         else
 255                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 256 }
 257
 258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 259 {
 260         unsigned i;
 261
 262         /* Enable pflip interrupts */
 263         for (i = 0; i < adev->mode_info.num_crtc; i++)
 264                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 265 }
 266
 267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 268 {
 269         unsigned i;
 270
 271         /* Disable pflip interrupts */
 272         for (i = 0; i < adev->mode_info.num_crtc; i++)
 273                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 274 }
 275
 276 /**
 277  * dce_v10_0_page_flip - pageflip callback.
 278  *
 279  * @adev: amdgpu_device pointer
 280  * @crtc_id: crtc to cleanup pageflip on
 281  * @crtc_base: new address of the crtc (GPU MC address)
 282  *
 283  * Triggers the actual pageflip by updating the primary
 284  * surface base address.
 285  */
 286 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 287                               int crtc_id, u64 crtc_base)
 288 {
 289         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 290
 291         /* update the primary scanout address */
 292         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 293                upper_32_bits(crtc_base));
 294         /* writing to the low address triggers the update */
 295         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 296                lower_32_bits(crtc_base));
 297         /* post the write */
 298         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 299 }
 300
 301 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 302                                         u32 *vbl, u32 *position)
 303 {
 304         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 305                 return -EINVAL;
 306
 307         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 308         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 309
 310         return 0;
 311 }
 312
 313 /**
 314  * dce_v10_0_hpd_sense - hpd sense callback.
 315  *
 316  * @adev: amdgpu_device pointer
 317  * @hpd: hpd (hotplug detect) pin
 318  *
 319  * Checks if a digital monitor is connected (evergreen+).
 320  * Returns true if connected, false if not connected.
 321  */
 322 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 323                                enum amdgpu_hpd_id hpd)
 324 {
 325         int idx;
 326         bool connected = false;
 327
 328         switch (hpd) {
 329         case AMDGPU_HPD_1:
 330                 idx = 0;
 331                 break;
 332         case AMDGPU_HPD_2:
 333                 idx = 1;
 334                 break;
 335         case AMDGPU_HPD_3:
 336                 idx = 2;
 337                 break;
 338         case AMDGPU_HPD_4:
 339                 idx = 3;
 340                 break;
 341         case AMDGPU_HPD_5:
 342                 idx = 4;
 343                 break;
 344         case AMDGPU_HPD_6:
 345                 idx = 5;
 346                 break;
 347         default:
 348                 return connected;
 349         }
 350
 351         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 352             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 353                 connected = true;
 354
 355         return connected;
 356 }
 357
 358 /**
 359  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 360  *
 361  * @adev: amdgpu_device pointer
 362  * @hpd: hpd (hotplug detect) pin
 363  *
 364  * Set the polarity of the hpd pin (evergreen+).
 365  */
 366 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 367                                       enum amdgpu_hpd_id hpd)
 368 {
 369         u32 tmp;
 370         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 371         int idx;
 372
 373         switch (hpd) {
 374         case AMDGPU_HPD_1:
 375                 idx = 0;
 376                 break;
 377         case AMDGPU_HPD_2:
 378                 idx = 1;
 379                 break;
 380         case AMDGPU_HPD_3:
 381                 idx = 2;
 382                 break;
 383         case AMDGPU_HPD_4:
 384                 idx = 3;
 385                 break;
 386         case AMDGPU_HPD_5:
 387                 idx = 4;
 388                 break;
 389         case AMDGPU_HPD_6:
 390                 idx = 5;
 391                 break;
 392         default:
 393                 return;
 394         }
 395
 396         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 397         if (connected)
 398                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 399         else
 400                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 401         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 402 }
 403
 404 /**
 405  * dce_v10_0_hpd_init - hpd setup callback.
 406  *
 407  * @adev: amdgpu_device pointer
 408  *
 409  * Setup the hpd pins used by the card (evergreen+).
 410  * Enable the pin, set the polarity, and enable the hpd interrupts.
 411  */
 412 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 413 {
 414         struct drm_device *dev = adev->ddev;
 415         struct drm_connector *connector;
 416         u32 tmp;
 417         int idx;
 418
 419         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 420                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 421
 422                 switch (amdgpu_connector->hpd.hpd) {
 423                 case AMDGPU_HPD_1:
 424                         idx = 0;
 425                         break;
 426                 case AMDGPU_HPD_2:
 427                         idx = 1;
 428                         break;
 429                 case AMDGPU_HPD_3:
 430                         idx = 2;
 431                         break;
 432                 case AMDGPU_HPD_4:
 433                         idx = 3;
 434                         break;
 435                 case AMDGPU_HPD_5:
 436                         idx = 4;
 437                         break;
 438                 case AMDGPU_HPD_6:
 439                         idx = 5;
 440                         break;
 441                 default:
 442                         continue;
 443                 }
 444
 445                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 446                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 447                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 448                          * aux dp channel on imac and help (but not completely fix)
 449                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 450                          * also avoid interrupt storms during dpms.
 451                          */
 452                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 453                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 454                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 455                         continue;
 456                 }
 457
 458                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 459                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 460                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 461
 462                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 463                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 464                                     DC_HPD_CONNECT_INT_DELAY,
 465                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 466                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 467                                     DC_HPD_DISCONNECT_INT_DELAY,
 468                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 469                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 470
 471                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 472                 amdgpu_irq_get(adev, &adev->hpd_irq,
 473                                amdgpu_connector->hpd.hpd);
 474         }
 475 }
 476
 477 /**
 478  * dce_v10_0_hpd_fini - hpd tear down callback.
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * Tear down the hpd pins used by the card (evergreen+).
 483  * Disable the hpd interrupts.
 484  */
 485 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 486 {
 487         struct drm_device *dev = adev->ddev;
 488         struct drm_connector *connector;
 489         u32 tmp;
 490         int idx;
 491
 492         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 493                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 494
 495                 switch (amdgpu_connector->hpd.hpd) {
 496                 case AMDGPU_HPD_1:
 497                         idx = 0;
 498                         break;
 499                 case AMDGPU_HPD_2:
 500                         idx = 1;
 501                         break;
 502                 case AMDGPU_HPD_3:
 503                         idx = 2;
 504                         break;
 505                 case AMDGPU_HPD_4:
 506                         idx = 3;
 507                         break;
 508                 case AMDGPU_HPD_5:
 509                         idx = 4;
 510                         break;
 511                 case AMDGPU_HPD_6:
 512                         idx = 5;
 513                         break;
 514                 default:
 515                         continue;
 516                 }
 517
 518                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 519                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 520                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 521
 522                 amdgpu_irq_put(adev, &adev->hpd_irq,
 523                                amdgpu_connector->hpd.hpd);
 524         }
 525 }
 526
 527 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 528 {
 529         return mmDC_GPIO_HPD_A;
 530 }
 531
 532 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 533 {
 534         u32 crtc_hung = 0;
 535         u32 crtc_status[6];
 536         u32 i, j, tmp;
 537
 538         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 539                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 540                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 541                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 542                         crtc_hung |= (1 << i);
 543                 }
 544         }
 545
 546         for (j = 0; j < 10; j++) {
 547                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 548                         if (crtc_hung & (1 << i)) {
 549                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 550                                 if (tmp != crtc_status[i])
 551                                         crtc_hung &= ~(1 << i);
 552                         }
 553                 }
 554                 if (crtc_hung == 0)
 555                         return false;
 556                 udelay(100);
 557         }
 558
 559         return true;
 560 }
 561
 562 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 563                                      struct amdgpu_mode_mc_save *save)
 564 {
 565         u32 crtc_enabled, tmp;
 566         int i;
 567
 568         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 569         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 570
 571         /* disable VGA render */
 572         tmp = RREG32(mmVGA_RENDER_CONTROL);
 573         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 574         WREG32(mmVGA_RENDER_CONTROL, tmp);
 575
 576         /* blank the display controllers */
 577         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 578                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 579                                              CRTC_CONTROL, CRTC_MASTER_EN);
 580                 if (crtc_enabled) {
 581 #if 0
 582                         u32 frame_count;
 583                         int j;
 584
 585                         save->crtc_enabled[i] = true;
 586                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 587                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 588                                 amdgpu_display_vblank_wait(adev, i);
 589                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 590                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 591                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 592                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 593                         }
 594                         /* wait for the next frame */
 595                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 596                         for (j = 0; j < adev->usec_timeout; j++) {
 597                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 598                                         break;
 599                                 udelay(1);
 600                         }
 601                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 602                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 603                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 604                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 605                         }
 606                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 607                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 608                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 609                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 610                         }
 611 #else
 612                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 613                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 614                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 615                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 616                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 617                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 618                         save->crtc_enabled[i] = false;
 619                         /* ***** */
 620 #endif
 621                 } else {
 622                         save->crtc_enabled[i] = false;
 623                 }
 624         }
 625 }
 626
 627 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 628                                        struct amdgpu_mode_mc_save *save)
 629 {
 630         u32 tmp, frame_count;
 631         int i, j;
 632
 633         /* update crtc base addresses */
 634         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 635                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 636                        upper_32_bits(adev->mc.vram_start));
 637                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 638                        upper_32_bits(adev->mc.vram_start));
 639                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 640                        (u32)adev->mc.vram_start);
 641                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 642                        (u32)adev->mc.vram_start);
 643
 644                 if (save->crtc_enabled[i]) {
 645                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 646                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 647                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 648                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 649                         }
 650                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 651                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 652                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 653                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 654                         }
 655                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 656                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 657                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 658                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 659                         }
 660                         for (j = 0; j < adev->usec_timeout; j++) {
 661                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 662                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 663                                         break;
 664                                 udelay(1);
 665                         }
 666                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 667                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 668                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 669                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 670                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 671                         /* wait for the next frame */
 672                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 673                         for (j = 0; j < adev->usec_timeout; j++) {
 674                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 675                                         break;
 676                                 udelay(1);
 677                         }
 678                 }
 679         }
 680
 681         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 682         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 683
 684         /* Unlock vga access */
 685         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 686         mdelay(1);
 687         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 688 }
 689
 690 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 691                                            bool render)
 692 {
 693         u32 tmp;
 694
 695         /* Lockout access through VGA aperture*/
 696         tmp = RREG32(mmVGA_HDP_CONTROL);
 697         if (render)
 698                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 699         else
 700                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 701         WREG32(mmVGA_HDP_CONTROL, tmp);
 702
 703         /* disable VGA render */
 704         tmp = RREG32(mmVGA_RENDER_CONTROL);
 705         if (render)
 706                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 707         else
 708                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 709         WREG32(mmVGA_RENDER_CONTROL, tmp);
 710 }
 711
 712 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 713 {
 714         struct drm_device *dev = encoder->dev;
 715         struct amdgpu_device *adev = dev->dev_private;
 716         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 717         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 718         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 719         int bpc = 0;
 720         u32 tmp = 0;
 721         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 722
 723         if (connector) {
 724                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 725                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 726                 dither = amdgpu_connector->dither;
 727         }
 728
 729         /* LVDS/eDP FMT is set up by atom */
 730         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 731                 return;
 732
 733         /* not needed for analog */
 734         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 735             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 736                 return;
 737
 738         if (bpc == 0)
 739                 return;
 740
 741         switch (bpc) {
 742         case 6:
 743                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 744                         /* XXX sort out optimal dither settings */
 745                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 746                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 747                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 749                 } else {
 750                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 752                 }
 753                 break;
 754         case 8:
 755                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 756                         /* XXX sort out optimal dither settings */
 757                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 758                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 759                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 760                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 762                 } else {
 763                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 764                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 765                 }
 766                 break;
 767         case 10:
 768                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 769                         /* XXX sort out optimal dither settings */
 770                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 771                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 772                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 773                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 774                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 775                 } else {
 776                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 777                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 778                 }
 779                 break;
 780         default:
 781                 /* not needed */
 782                 break;
 783         }
 784
 785         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 786 }
 787
 788
 789 /* display watermark setup */
 790 /**
 791  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 792  *
 793  * @adev: amdgpu_device pointer
 794  * @amdgpu_crtc: the selected display controller
 795  * @mode: the current display mode on the selected display
 796  * controller
 797  *
 798  * Setup up the line buffer allocation for
 799  * the selected display controller (CIK).
 800  * Returns the line buffer size in pixels.
 801  */
 802 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 803                                        struct amdgpu_crtc *amdgpu_crtc,
 804                                        struct drm_display_mode *mode)
 805 {
 806         u32 tmp, buffer_alloc, i, mem_cfg;
 807         u32 pipe_offset = amdgpu_crtc->crtc_id;
 808         /*
 809          * Line Buffer Setup
 810          * There are 6 line buffers, one for each display controllers.
 811          * There are 3 partitions per LB. Select the number of partitions
 812          * to enable based on the display width.  For display widths larger
 813          * than 4096, you need use to use 2 display controllers and combine
 814          * them using the stereo blender.
 815          */
 816         if (amdgpu_crtc->base.enabled && mode) {
 817                 if (mode->crtc_hdisplay < 1920) {
 818                         mem_cfg = 1;
 819                         buffer_alloc = 2;
 820                 } else if (mode->crtc_hdisplay < 2560) {
 821                         mem_cfg = 2;
 822                         buffer_alloc = 2;
 823                 } else if (mode->crtc_hdisplay < 4096) {
 824                         mem_cfg = 0;
 825                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 826                 } else {
 827                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 828                         mem_cfg = 0;
 829                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 830                 }
 831         } else {
 832                 mem_cfg = 1;
 833                 buffer_alloc = 0;
 834         }
 835
 836         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 837         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 838         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 839
 840         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 841         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 842         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 843
 844         for (i = 0; i < adev->usec_timeout; i++) {
 845                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 846                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 847                         break;
 848                 udelay(1);
 849         }
 850
 851         if (amdgpu_crtc->base.enabled && mode) {
 852                 switch (mem_cfg) {
 853                 case 0:
 854                 default:
 855                         return 4096 * 2;
 856                 case 1:
 857                         return 1920 * 2;
 858                 case 2:
 859                         return 2560 * 2;
 860                 }
 861         }
 862
 863         /* controller not enabled, so no lb used */
 864         return 0;
 865 }
 866
 867 /**
 868  * cik_get_number_of_dram_channels - get the number of dram channels
 869  *
 870  * @adev: amdgpu_device pointer
 871  *
 872  * Look up the number of video ram channels (CIK).
 873  * Used for display watermark bandwidth calculations
 874  * Returns the number of dram channels
 875  */
 876 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 877 {
 878         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 879
 880         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 881         case 0:
 882         default:
 883                 return 1;
 884         case 1:
 885                 return 2;
 886         case 2:
 887                 return 4;
 888         case 3:
 889                 return 8;
 890         case 4:
 891                 return 3;
 892         case 5:
 893                 return 6;
 894         case 6:
 895                 return 10;
 896         case 7:
 897                 return 12;
 898         case 8:
 899                 return 16;
 900         }
 901 }
 902
 903 struct dce10_wm_params {
 904         u32 dram_channels; /* number of dram channels */
 905         u32 yclk;          /* bandwidth per dram data pin in kHz */
 906         u32 sclk;          /* engine clock in kHz */
 907         u32 disp_clk;      /* display clock in kHz */
 908         u32 src_width;     /* viewport width */
 909         u32 active_time;   /* active display time in ns */
 910         u32 blank_time;    /* blank time in ns */
 911         bool interlaced;    /* mode is interlaced */
 912         fixed20_12 vsc;    /* vertical scale ratio */
 913         u32 num_heads;     /* number of active crtcs */
 914         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 915         u32 lb_size;       /* line buffer allocated to pipe */
 916         u32 vtaps;         /* vertical scaler taps */
 917 };
 918
 919 /**
 920  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 921  *
 922  * @wm: watermark calculation data
 923  *
 924  * Calculate the raw dram bandwidth (CIK).
 925  * Used for display watermark bandwidth calculations
 926  * Returns the dram bandwidth in MBytes/s
 927  */
 928 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 929 {
 930         /* Calculate raw DRAM Bandwidth */
 931         fixed20_12 dram_efficiency; /* 0.7 */
 932         fixed20_12 yclk, dram_channels, bandwidth;
 933         fixed20_12 a;
 934
 935         a.full = dfixed_const(1000);
 936         yclk.full = dfixed_const(wm->yclk);
 937         yclk.full = dfixed_div(yclk, a);
 938         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 939         a.full = dfixed_const(10);
 940         dram_efficiency.full = dfixed_const(7);
 941         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 942         bandwidth.full = dfixed_mul(dram_channels, yclk);
 943         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 944
 945         return dfixed_trunc(bandwidth);
 946 }
 947
 948 /**
 949  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 950  *
 951  * @wm: watermark calculation data
 952  *
 953  * Calculate the dram bandwidth used for display (CIK).
 954  * Used for display watermark bandwidth calculations
 955  * Returns the dram bandwidth for display in MBytes/s
 956  */
 957 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 958 {
 959         /* Calculate DRAM Bandwidth and the part allocated to display. */
 960         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 961         fixed20_12 yclk, dram_channels, bandwidth;
 962         fixed20_12 a;
 963
 964         a.full = dfixed_const(1000);
 965         yclk.full = dfixed_const(wm->yclk);
 966         yclk.full = dfixed_div(yclk, a);
 967         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 968         a.full = dfixed_const(10);
 969         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 970         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 971         bandwidth.full = dfixed_mul(dram_channels, yclk);
 972         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 973
 974         return dfixed_trunc(bandwidth);
 975 }
 976
 977 /**
 978  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 979  *
 980  * @wm: watermark calculation data
 981  *
 982  * Calculate the data return bandwidth used for display (CIK).
 983  * Used for display watermark bandwidth calculations
 984  * Returns the data return bandwidth in MBytes/s
 985  */
 986 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 987 {
 988         /* Calculate the display Data return Bandwidth */
 989         fixed20_12 return_efficiency; /* 0.8 */
 990         fixed20_12 sclk, bandwidth;
 991         fixed20_12 a;
 992
 993         a.full = dfixed_const(1000);
 994         sclk.full = dfixed_const(wm->sclk);
 995         sclk.full = dfixed_div(sclk, a);
 996         a.full = dfixed_const(10);
 997         return_efficiency.full = dfixed_const(8);
 998         return_efficiency.full = dfixed_div(return_efficiency, a);
 999         a.full = dfixed_const(32);
1000         bandwidth.full = dfixed_mul(a, sclk);
1001         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1002
1003         return dfixed_trunc(bandwidth);
1004 }
1005
1006 /**
1007  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1008  *
1009  * @wm: watermark calculation data
1010  *
1011  * Calculate the dmif bandwidth used for display (CIK).
1012  * Used for display watermark bandwidth calculations
1013  * Returns the dmif bandwidth in MBytes/s
1014  */
1015 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1016 {
1017         /* Calculate the DMIF Request Bandwidth */
1018         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1019         fixed20_12 disp_clk, bandwidth;
1020         fixed20_12 a, b;
1021
1022         a.full = dfixed_const(1000);
1023         disp_clk.full = dfixed_const(wm->disp_clk);
1024         disp_clk.full = dfixed_div(disp_clk, a);
1025         a.full = dfixed_const(32);
1026         b.full = dfixed_mul(a, disp_clk);
1027
1028         a.full = dfixed_const(10);
1029         disp_clk_request_efficiency.full = dfixed_const(8);
1030         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1031
1032         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1033
1034         return dfixed_trunc(bandwidth);
1035 }
1036
1037 /**
1038  * dce_v10_0_available_bandwidth - get the min available bandwidth
1039  *
1040  * @wm: watermark calculation data
1041  *
1042  * Calculate the min available bandwidth used for display (CIK).
1043  * Used for display watermark bandwidth calculations
1044  * Returns the min available bandwidth in MBytes/s
1045  */
1046 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1047 {
1048         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1049         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1050         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1051         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1052
1053         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1054 }
1055
1056 /**
1057  * dce_v10_0_average_bandwidth - get the average available bandwidth
1058  *
1059  * @wm: watermark calculation data
1060  *
1061  * Calculate the average available bandwidth used for display (CIK).
1062  * Used for display watermark bandwidth calculations
1063  * Returns the average available bandwidth in MBytes/s
1064  */
1065 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1066 {
1067         /* Calculate the display mode Average Bandwidth
1068          * DisplayMode should contain the source and destination dimensions,
1069          * timing, etc.
1070          */
1071         fixed20_12 bpp;
1072         fixed20_12 line_time;
1073         fixed20_12 src_width;
1074         fixed20_12 bandwidth;
1075         fixed20_12 a;
1076
1077         a.full = dfixed_const(1000);
1078         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1079         line_time.full = dfixed_div(line_time, a);
1080         bpp.full = dfixed_const(wm->bytes_per_pixel);
1081         src_width.full = dfixed_const(wm->src_width);
1082         bandwidth.full = dfixed_mul(src_width, bpp);
1083         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1084         bandwidth.full = dfixed_div(bandwidth, line_time);
1085
1086         return dfixed_trunc(bandwidth);
1087 }
1088
1089 /**
1090  * dce_v10_0_latency_watermark - get the latency watermark
1091  *
1092  * @wm: watermark calculation data
1093  *
1094  * Calculate the latency watermark (CIK).
1095  * Used for display watermark bandwidth calculations
1096  * Returns the latency watermark in ns
1097  */
1098 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1099 {
1100         /* First calculate the latency in ns */
1101         u32 mc_latency = 2000; /* 2000 ns. */
1102         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1103         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1104         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1105         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1106         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1107                 (wm->num_heads * cursor_line_pair_return_time);
1108         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1109         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1110         u32 tmp, dmif_size = 12288;
1111         fixed20_12 a, b, c;
1112
1113         if (wm->num_heads == 0)
1114                 return 0;
1115
1116         a.full = dfixed_const(2);
1117         b.full = dfixed_const(1);
1118         if ((wm->vsc.full > a.full) ||
1119             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1120             (wm->vtaps >= 5) ||
1121             ((wm->vsc.full >= a.full) && wm->interlaced))
1122                 max_src_lines_per_dst_line = 4;
1123         else
1124                 max_src_lines_per_dst_line = 2;
1125
1126         a.full = dfixed_const(available_bandwidth);
1127         b.full = dfixed_const(wm->num_heads);
1128         a.full = dfixed_div(a, b);
1129
1130         b.full = dfixed_const(mc_latency + 512);
1131         c.full = dfixed_const(wm->disp_clk);
1132         b.full = dfixed_div(b, c);
1133
1134         c.full = dfixed_const(dmif_size);
1135         b.full = dfixed_div(c, b);
1136
1137         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1138
1139         b.full = dfixed_const(1000);
1140         c.full = dfixed_const(wm->disp_clk);
1141         b.full = dfixed_div(c, b);
1142         c.full = dfixed_const(wm->bytes_per_pixel);
1143         b.full = dfixed_mul(b, c);
1144
1145         lb_fill_bw = min(tmp, dfixed_trunc(b));
1146
1147         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1148         b.full = dfixed_const(1000);
1149         c.full = dfixed_const(lb_fill_bw);
1150         b.full = dfixed_div(c, b);
1151         a.full = dfixed_div(a, b);
1152         line_fill_time = dfixed_trunc(a);
1153
1154         if (line_fill_time < wm->active_time)
1155                 return latency;
1156         else
1157                 return latency + (line_fill_time - wm->active_time);
1158
1159 }
1160
1161 /**
1162  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1163  * average and available dram bandwidth
1164  *
1165  * @wm: watermark calculation data
1166  *
1167  * Check if the display average bandwidth fits in the display
1168  * dram bandwidth (CIK).
1169  * Used for display watermark bandwidth calculations
1170  * Returns true if the display fits, false if not.
1171  */
1172 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1173 {
1174         if (dce_v10_0_average_bandwidth(wm) <=
1175             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1176                 return true;
1177         else
1178                 return false;
1179 }
1180
1181 /**
1182  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1183  * average and available bandwidth
1184  *
1185  * @wm: watermark calculation data
1186  *
1187  * Check if the display average bandwidth fits in the display
1188  * available bandwidth (CIK).
1189  * Used for display watermark bandwidth calculations
1190  * Returns true if the display fits, false if not.
1191  */
1192 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1193 {
1194         if (dce_v10_0_average_bandwidth(wm) <=
1195             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1196                 return true;
1197         else
1198                 return false;
1199 }
1200
1201 /**
1202  * dce_v10_0_check_latency_hiding - check latency hiding
1203  *
1204  * @wm: watermark calculation data
1205  *
1206  * Check latency hiding (CIK).
1207  * Used for display watermark bandwidth calculations
1208  * Returns true if the display fits, false if not.
1209  */
1210 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1211 {
1212         u32 lb_partitions = wm->lb_size / wm->src_width;
1213         u32 line_time = wm->active_time + wm->blank_time;
1214         u32 latency_tolerant_lines;
1215         u32 latency_hiding;
1216         fixed20_12 a;
1217
1218         a.full = dfixed_const(1);
1219         if (wm->vsc.full > a.full)
1220                 latency_tolerant_lines = 1;
1221         else {
1222                 if (lb_partitions <= (wm->vtaps + 1))
1223                         latency_tolerant_lines = 1;
1224                 else
1225                         latency_tolerant_lines = 2;
1226         }
1227
1228         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1229
1230         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1231                 return true;
1232         else
1233                 return false;
1234 }
1235
1236 /**
1237  * dce_v10_0_program_watermarks - program display watermarks
1238  *
1239  * @adev: amdgpu_device pointer
1240  * @amdgpu_crtc: the selected display controller
1241  * @lb_size: line buffer size
1242  * @num_heads: number of display controllers in use
1243  *
1244  * Calculate and program the display watermarks for the
1245  * selected display controller (CIK).
1246  */
1247 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1248                                         struct amdgpu_crtc *amdgpu_crtc,
1249                                         u32 lb_size, u32 num_heads)
1250 {
1251         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1252         struct dce10_wm_params wm_low, wm_high;
1253         u32 pixel_period;
1254         u32 line_time = 0;
1255         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1256         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1257
1258         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1259                 pixel_period = 1000000 / (u32)mode->clock;
1260                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1261
1262                 /* watermark for high clocks */
1263                 if (adev->pm.dpm_enabled) {
1264                         wm_high.yclk =
1265                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1266                         wm_high.sclk =
1267                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1268                 } else {
1269                         wm_high.yclk = adev->pm.current_mclk * 10;
1270                         wm_high.sclk = adev->pm.current_sclk * 10;
1271                 }
1272
1273                 wm_high.disp_clk = mode->clock;
1274                 wm_high.src_width = mode->crtc_hdisplay;
1275                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1276                 wm_high.blank_time = line_time - wm_high.active_time;
1277                 wm_high.interlaced = false;
1278                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1279                         wm_high.interlaced = true;
1280                 wm_high.vsc = amdgpu_crtc->vsc;
1281                 wm_high.vtaps = 1;
1282                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1283                         wm_high.vtaps = 2;
1284                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1285                 wm_high.lb_size = lb_size;
1286                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1287                 wm_high.num_heads = num_heads;
1288
1289                 /* set for high clocks */
1290                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1291
1292                 /* possibly force display priority to high */
1293                 /* should really do this at mode validation time... */
1294                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1295                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1296                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1297                     (adev->mode_info.disp_priority == 2)) {
1298                         DRM_DEBUG_KMS("force priority to high\n");
1299                 }
1300
1301                 /* watermark for low clocks */
1302                 if (adev->pm.dpm_enabled) {
1303                         wm_low.yclk =
1304                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1305                         wm_low.sclk =
1306                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1307                 } else {
1308                         wm_low.yclk = adev->pm.current_mclk * 10;
1309                         wm_low.sclk = adev->pm.current_sclk * 10;
1310                 }
1311
1312                 wm_low.disp_clk = mode->clock;
1313                 wm_low.src_width = mode->crtc_hdisplay;
1314                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1315                 wm_low.blank_time = line_time - wm_low.active_time;
1316                 wm_low.interlaced = false;
1317                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1318                         wm_low.interlaced = true;
1319                 wm_low.vsc = amdgpu_crtc->vsc;
1320                 wm_low.vtaps = 1;
1321                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1322                         wm_low.vtaps = 2;
1323                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1324                 wm_low.lb_size = lb_size;
1325                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1326                 wm_low.num_heads = num_heads;
1327
1328                 /* set for low clocks */
1329                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1330
1331                 /* possibly force display priority to high */
1332                 /* should really do this at mode validation time... */
1333                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1334                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1335                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1336                     (adev->mode_info.disp_priority == 2)) {
1337                         DRM_DEBUG_KMS("force priority to high\n");
1338                 }
1339                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1340         }
1341
1342         /* select wm A */
1343         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1344         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1345         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1346         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1347         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1348         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1349         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1350         /* select wm B */
1351         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1352         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1353         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1354         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1355         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1356         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1357         /* restore original selection */
1358         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1359
1360         /* save values for DPM */
1361         amdgpu_crtc->line_time = line_time;
1362         amdgpu_crtc->wm_high = latency_watermark_a;
1363         amdgpu_crtc->wm_low = latency_watermark_b;
1364         /* Save number of lines the linebuffer leads before the scanout */
1365         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1366 }
1367
1368 /**
1369  * dce_v10_0_bandwidth_update - program display watermarks
1370  *
1371  * @adev: amdgpu_device pointer
1372  *
1373  * Calculate and program the display watermarks and line
1374  * buffer allocation (CIK).
1375  */
1376 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1377 {
1378         struct drm_display_mode *mode = NULL;
1379         u32 num_heads = 0, lb_size;
1380         int i;
1381
1382         amdgpu_update_display_priority(adev);
1383
1384         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1385                 if (adev->mode_info.crtcs[i]->base.enabled)
1386                         num_heads++;
1387         }
1388         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1389                 mode = &adev->mode_info.crtcs[i]->base.mode;
1390                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1391                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1392                                             lb_size, num_heads);
1393         }
1394 }
1395
1396 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1397 {
1398         int i;
1399         u32 offset, tmp;
1400
1401         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1402                 offset = adev->mode_info.audio.pin[i].offset;
1403                 tmp = RREG32_AUDIO_ENDPT(offset,
1404                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1405                 if (((tmp &
1406                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1407                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1408                         adev->mode_info.audio.pin[i].connected = false;
1409                 else
1410                         adev->mode_info.audio.pin[i].connected = true;
1411         }
1412 }
1413
1414 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1415 {
1416         int i;
1417
1418         dce_v10_0_audio_get_connected_pins(adev);
1419
1420         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1421                 if (adev->mode_info.audio.pin[i].connected)
1422                         return &adev->mode_info.audio.pin[i];
1423         }
1424         DRM_ERROR("No connected audio pins found!\n");
1425         return NULL;
1426 }
1427
1428 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1429 {
1430         struct amdgpu_device *adev = encoder->dev->dev_private;
1431         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1432         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1433         u32 tmp;
1434
1435         if (!dig || !dig->afmt || !dig->afmt->pin)
1436                 return;
1437
1438         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1439         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1440         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1441 }
1442
1443 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1444                                                 struct drm_display_mode *mode)
1445 {
1446         struct amdgpu_device *adev = encoder->dev->dev_private;
1447         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1448         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1449         struct drm_connector *connector;
1450         struct amdgpu_connector *amdgpu_connector = NULL;
1451         u32 tmp;
1452         int interlace = 0;
1453
1454         if (!dig || !dig->afmt || !dig->afmt->pin)
1455                 return;
1456
1457         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1458                 if (connector->encoder == encoder) {
1459                         amdgpu_connector = to_amdgpu_connector(connector);
1460                         break;
1461                 }
1462         }
1463
1464         if (!amdgpu_connector) {
1465                 DRM_ERROR("Couldn't find encoder's connector\n");
1466                 return;
1467         }
1468
1469         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1470                 interlace = 1;
1471         if (connector->latency_present[interlace]) {
1472                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1473                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1474                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1475                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1476         } else {
1477                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1478                                     VIDEO_LIPSYNC, 0);
1479                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1480                                     AUDIO_LIPSYNC, 0);
1481         }
1482         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1483                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1484 }
1485
1486 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1487 {
1488         struct amdgpu_device *adev = encoder->dev->dev_private;
1489         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1490         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1491         struct drm_connector *connector;
1492         struct amdgpu_connector *amdgpu_connector = NULL;
1493         u32 tmp;
1494         u8 *sadb = NULL;
1495         int sad_count;
1496
1497         if (!dig || !dig->afmt || !dig->afmt->pin)
1498                 return;
1499
1500         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1501                 if (connector->encoder == encoder) {
1502                         amdgpu_connector = to_amdgpu_connector(connector);
1503                         break;
1504                 }
1505         }
1506
1507         if (!amdgpu_connector) {
1508                 DRM_ERROR("Couldn't find encoder's connector\n");
1509                 return;
1510         }
1511
1512         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1513         if (sad_count < 0) {
1514                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1515                 sad_count = 0;
1516         }
1517
1518         /* program the speaker allocation */
1519         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1520                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1521         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1522                             DP_CONNECTION, 0);
1523         /* set HDMI mode */
1524         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1525                             HDMI_CONNECTION, 1);
1526         if (sad_count)
1527                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1528                                     SPEAKER_ALLOCATION, sadb[0]);
1529         else
1530                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1531                                     SPEAKER_ALLOCATION, 5); /* stereo */
1532         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1533                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1534
1535         kfree(sadb);
1536 }
1537
1538 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1539 {
1540         struct amdgpu_device *adev = encoder->dev->dev_private;
1541         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1542         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1543         struct drm_connector *connector;
1544         struct amdgpu_connector *amdgpu_connector = NULL;
1545         struct cea_sad *sads;
1546         int i, sad_count;
1547
1548         static const u16 eld_reg_to_type[][2] = {
1549                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1550                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1551                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1552                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1553                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1554                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1555                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1556                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1557                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1558                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1559                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1560                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1561         };
1562
1563         if (!dig || !dig->afmt || !dig->afmt->pin)
1564                 return;
1565
1566         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1567                 if (connector->encoder == encoder) {
1568                         amdgpu_connector = to_amdgpu_connector(connector);
1569                         break;
1570                 }
1571         }
1572
1573         if (!amdgpu_connector) {
1574                 DRM_ERROR("Couldn't find encoder's connector\n");
1575                 return;
1576         }
1577
1578         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1579         if (sad_count <= 0) {
1580                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1581                 return;
1582         }
1583         BUG_ON(!sads);
1584
1585         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1586                 u32 tmp = 0;
1587                 u8 stereo_freqs = 0;
1588                 int max_channels = -1;
1589                 int j;
1590
1591                 for (j = 0; j < sad_count; j++) {
1592                         struct cea_sad *sad = &sads[j];
1593
1594                         if (sad->format == eld_reg_to_type[i][1]) {
1595                                 if (sad->channels > max_channels) {
1596                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1597                                                             MAX_CHANNELS, sad->channels);
1598                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1599                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1600                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1601                                                             SUPPORTED_FREQUENCIES, sad->freq);
1602                                         max_channels = sad->channels;
1603                                 }
1604
1605                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1606                                         stereo_freqs |= sad->freq;
1607                                 else
1608                                         break;
1609                         }
1610                 }
1611
1612                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1613                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1614                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1615         }
1616
1617         kfree(sads);
1618 }
1619
1620 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1621                                   struct amdgpu_audio_pin *pin,
1622                                   bool enable)
1623 {
1624         if (!pin)
1625                 return;
1626
1627         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1628                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1629 }
1630
1631 static const u32 pin_offsets[] =
1632 {
1633         AUD0_REGISTER_OFFSET,
1634         AUD1_REGISTER_OFFSET,
1635         AUD2_REGISTER_OFFSET,
1636         AUD3_REGISTER_OFFSET,
1637         AUD4_REGISTER_OFFSET,
1638         AUD5_REGISTER_OFFSET,
1639         AUD6_REGISTER_OFFSET,
1640 };
1641
1642 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1643 {
1644         int i;
1645
1646         if (!amdgpu_audio)
1647                 return 0;
1648
1649         adev->mode_info.audio.enabled = true;
1650
1651         adev->mode_info.audio.num_pins = 7;
1652
1653         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1654                 adev->mode_info.audio.pin[i].channels = -1;
1655                 adev->mode_info.audio.pin[i].rate = -1;
1656                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1657                 adev->mode_info.audio.pin[i].status_bits = 0;
1658                 adev->mode_info.audio.pin[i].category_code = 0;
1659                 adev->mode_info.audio.pin[i].connected = false;
1660                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1661                 adev->mode_info.audio.pin[i].id = i;
1662                 /* disable audio.  it will be set up later */
1663                 /* XXX remove once we switch to ip funcs */
1664                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1671 {
1672         int i;
1673
1674         if (!adev->mode_info.audio.enabled)
1675                 return;
1676
1677         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1678                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1679
1680         adev->mode_info.audio.enabled = false;
1681 }
1682
1683 /*
1684  * update the N and CTS parameters for a given pixel clock rate
1685  */
1686 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1687 {
1688         struct drm_device *dev = encoder->dev;
1689         struct amdgpu_device *adev = dev->dev_private;
1690         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1691         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1692         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1693         u32 tmp;
1694
1695         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1696         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1697         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1698         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1699         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1700         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1701
1702         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1703         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1704         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1705         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1706         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1707         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1708
1709         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1710         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1711         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1712         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1713         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1714         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1715
1716 }
1717
1718 /*
1719  * build a HDMI Video Info Frame
1720  */
1721 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1722                                                void *buffer, size_t size)
1723 {
1724         struct drm_device *dev = encoder->dev;
1725         struct amdgpu_device *adev = dev->dev_private;
1726         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1727         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1728         uint8_t *frame = buffer + 3;
1729         uint8_t *header = buffer;
1730
1731         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1732                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1733         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1734                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1735         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1736                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1737         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1738                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1739 }
1740
1741 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1742 {
1743         struct drm_device *dev = encoder->dev;
1744         struct amdgpu_device *adev = dev->dev_private;
1745         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1746         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1747         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1748         u32 dto_phase = 24 * 1000;
1749         u32 dto_modulo = clock;
1750         u32 tmp;
1751
1752         if (!dig || !dig->afmt)
1753                 return;
1754
1755         /* XXX two dtos; generally use dto0 for hdmi */
1756         /* Express [24MHz / target pixel clock] as an exact rational
1757          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1758          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1759          */
1760         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1761         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1762                             amdgpu_crtc->crtc_id);
1763         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1764         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1765         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1766 }
1767
1768 /*
1769  * update the info frames with the data from the current display mode
1770  */
1771 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1772                                   struct drm_display_mode *mode)
1773 {
1774         struct drm_device *dev = encoder->dev;
1775         struct amdgpu_device *adev = dev->dev_private;
1776         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1777         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1778         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1779         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1780         struct hdmi_avi_infoframe frame;
1781         ssize_t err;
1782         u32 tmp;
1783         int bpc = 8;
1784
1785         if (!dig || !dig->afmt)
1786                 return;
1787
1788         /* Silent, r600_hdmi_enable will raise WARN for us */
1789         if (!dig->afmt->enabled)
1790                 return;
1791
1792         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1793         if (encoder->crtc) {
1794                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1795                 bpc = amdgpu_crtc->bpc;
1796         }
1797
1798         /* disable audio prior to setting up hw */
1799         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1800         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1801
1802         dce_v10_0_audio_set_dto(encoder, mode->clock);
1803
1804         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1805         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1806         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1807
1808         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1809
1810         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1811         switch (bpc) {
1812         case 0:
1813         case 6:
1814         case 8:
1815         case 16:
1816         default:
1817                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1818                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1819                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1820                           connector->name, bpc);
1821                 break;
1822         case 10:
1823                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1824                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1825                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1826                           connector->name);
1827                 break;
1828         case 12:
1829                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1830                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1831                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1832                           connector->name);
1833                 break;
1834         }
1835         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1836
1837         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1838         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1839         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1840         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1841         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1842
1843         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1844         /* enable audio info frames (frames won't be set until audio is enabled) */
1845         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1846         /* required for audio info values to be updated */
1847         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1848         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1849
1850         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1851         /* required for audio info values to be updated */
1852         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1853         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1854
1855         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1856         /* anything other than 0 */
1857         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1858         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1859
1860         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1861
1862         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1863         /* set the default audio delay */
1864         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1865         /* should be suffient for all audio modes and small enough for all hblanks */
1866         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1867         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1868
1869         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1870         /* allow 60958 channel status fields to be updated */
1871         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1872         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1873
1874         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1875         if (bpc > 8)
1876                 /* clear SW CTS value */
1877                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1878         else
1879                 /* select SW CTS value */
1880                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1881         /* allow hw to sent ACR packets when required */
1882         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1883         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1884
1885         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1886
1887         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1888         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1889         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1890
1891         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1892         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1893         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1894
1895         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1896         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1897         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1898         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1899         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1900         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1901         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1902         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1903
1904         dce_v10_0_audio_write_speaker_allocation(encoder);
1905
1906         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1907                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1908
1909         dce_v10_0_afmt_audio_select_pin(encoder);
1910         dce_v10_0_audio_write_sad_regs(encoder);
1911         dce_v10_0_audio_write_latency_fields(encoder, mode);
1912
1913         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1914         if (err < 0) {
1915                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1916                 return;
1917         }
1918
1919         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1920         if (err < 0) {
1921                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1922                 return;
1923         }
1924
1925         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1926
1927         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1928         /* enable AVI info frames */
1929         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1930         /* required for audio info values to be updated */
1931         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1932         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1933
1934         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1935         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1936         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1937
1938         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1939         /* send audio packets */
1940         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1941         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1942
1943         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1944         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1945         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1946         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1947
1948         /* enable audio after to setting up hw */
1949         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1950 }
1951
1952 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1953 {
1954         struct drm_device *dev = encoder->dev;
1955         struct amdgpu_device *adev = dev->dev_private;
1956         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1957         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1958
1959         if (!dig || !dig->afmt)
1960                 return;
1961
1962         /* Silent, r600_hdmi_enable will raise WARN for us */
1963         if (enable && dig->afmt->enabled)
1964                 return;
1965         if (!enable && !dig->afmt->enabled)
1966                 return;
1967
1968         if (!enable && dig->afmt->pin) {
1969                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1970                 dig->afmt->pin = NULL;
1971         }
1972
1973         dig->afmt->enabled = enable;
1974
1975         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1976                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1977 }
1978
1979 static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
1980 {
1981         int i;
1982
1983         for (i = 0; i < adev->mode_info.num_dig; i++)
1984                 adev->mode_info.afmt[i] = NULL;
1985
1986         /* DCE10 has audio blocks tied to DIG encoders */
1987         for (i = 0; i < adev->mode_info.num_dig; i++) {
1988                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1989                 if (adev->mode_info.afmt[i]) {
1990                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1991                         adev->mode_info.afmt[i]->id = i;
1992                 }
1993         }
1994 }
1995
1996 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1997 {
1998         int i;
1999
2000         for (i = 0; i < adev->mode_info.num_dig; i++) {
2001                 kfree(adev->mode_info.afmt[i]);
2002                 adev->mode_info.afmt[i] = NULL;
2003         }
2004 }
2005
2006 static const u32 vga_control_regs[6] =
2007 {
2008         mmD1VGA_CONTROL,
2009         mmD2VGA_CONTROL,
2010         mmD3VGA_CONTROL,
2011         mmD4VGA_CONTROL,
2012         mmD5VGA_CONTROL,
2013         mmD6VGA_CONTROL,
2014 };
2015
2016 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2017 {
2018         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2019         struct drm_device *dev = crtc->dev;
2020         struct amdgpu_device *adev = dev->dev_private;
2021         u32 vga_control;
2022
2023         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2024         if (enable)
2025                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2026         else
2027                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2028 }
2029
2030 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2031 {
2032         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2033         struct drm_device *dev = crtc->dev;
2034         struct amdgpu_device *adev = dev->dev_private;
2035
2036         if (enable)
2037                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2038         else
2039                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2040 }
2041
2042 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2043                                      struct drm_framebuffer *fb,
2044                                      int x, int y, int atomic)
2045 {
2046         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2047         struct drm_device *dev = crtc->dev;
2048         struct amdgpu_device *adev = dev->dev_private;
2049         struct amdgpu_framebuffer *amdgpu_fb;
2050         struct drm_framebuffer *target_fb;
2051         struct drm_gem_object *obj;
2052         struct amdgpu_bo *rbo;
2053         uint64_t fb_location, tiling_flags;
2054         uint32_t fb_format, fb_pitch_pixels;
2055         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2056         u32 pipe_config;
2057         u32 tmp, viewport_w, viewport_h;
2058         int r;
2059         bool bypass_lut = false;
2060
2061         /* no fb bound */
2062         if (!atomic && !crtc->primary->fb) {
2063                 DRM_DEBUG_KMS("No FB bound\n");
2064                 return 0;
2065         }
2066
2067         if (atomic) {
2068                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2069                 target_fb = fb;
2070         }
2071         else {
2072                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2073                 target_fb = crtc->primary->fb;
2074         }
2075
2076         /* If atomic, assume fb object is pinned & idle & fenced and
2077          * just update base pointers
2078          */
2079         obj = amdgpu_fb->obj;
2080         rbo = gem_to_amdgpu_bo(obj);
2081         r = amdgpu_bo_reserve(rbo, false);
2082         if (unlikely(r != 0))
2083                 return r;
2084
2085         if (atomic)
2086                 fb_location = amdgpu_bo_gpu_offset(rbo);
2087         else {
2088                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2089                 if (unlikely(r != 0)) {
2090                         amdgpu_bo_unreserve(rbo);
2091                         return -EINVAL;
2092                 }
2093         }
2094
2095         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2096         amdgpu_bo_unreserve(rbo);
2097
2098         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2099
2100         switch (target_fb->pixel_format) {
2101         case DRM_FORMAT_C8:
2102                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2103                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2104                 break;
2105         case DRM_FORMAT_XRGB4444:
2106         case DRM_FORMAT_ARGB4444:
2107                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2108                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2109 #ifdef __BIG_ENDIAN
2110                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2111                                         ENDIAN_8IN16);
2112 #endif
2113                 break;
2114         case DRM_FORMAT_XRGB1555:
2115         case DRM_FORMAT_ARGB1555:
2116                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2117                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2118 #ifdef __BIG_ENDIAN
2119                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2120                                         ENDIAN_8IN16);
2121 #endif
2122                 break;
2123         case DRM_FORMAT_BGRX5551:
2124         case DRM_FORMAT_BGRA5551:
2125                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2126                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2127 #ifdef __BIG_ENDIAN
2128                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2129                                         ENDIAN_8IN16);
2130 #endif
2131                 break;
2132         case DRM_FORMAT_RGB565:
2133                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2134                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2135 #ifdef __BIG_ENDIAN
2136                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2137                                         ENDIAN_8IN16);
2138 #endif
2139                 break;
2140         case DRM_FORMAT_XRGB8888:
2141         case DRM_FORMAT_ARGB8888:
2142                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2143                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2144 #ifdef __BIG_ENDIAN
2145                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2146                                         ENDIAN_8IN32);
2147 #endif
2148                 break;
2149         case DRM_FORMAT_XRGB2101010:
2150         case DRM_FORMAT_ARGB2101010:
2151                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2152                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2153 #ifdef __BIG_ENDIAN
2154                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2155                                         ENDIAN_8IN32);
2156 #endif
2157                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2158                 bypass_lut = true;
2159                 break;
2160         case DRM_FORMAT_BGRX1010102:
2161         case DRM_FORMAT_BGRA1010102:
2162                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2163                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2164 #ifdef __BIG_ENDIAN
2165                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2166                                         ENDIAN_8IN32);
2167 #endif
2168                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2169                 bypass_lut = true;
2170                 break;
2171         default:
2172                 DRM_ERROR("Unsupported screen format %s\n",
2173                         drm_get_format_name(target_fb->pixel_format));
2174                 return -EINVAL;
2175         }
2176
2177         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2178                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2179
2180                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2181                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2182                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2183                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2184                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2185
2186                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2187                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2188                                           ARRAY_2D_TILED_THIN1);
2189                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2190                                           tile_split);
2191                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2192                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2193                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2194                                           mtaspect);
2195                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2196                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2197         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2198                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2199                                           ARRAY_1D_TILED_THIN1);
2200         }
2201
2202         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2203                                   pipe_config);
2204
2205         dce_v10_0_vga_enable(crtc, false);
2206
2207         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2208                upper_32_bits(fb_location));
2209         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2210                upper_32_bits(fb_location));
2211         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2212                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2213         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2214                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2215         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2216         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2217
2218         /*
2219          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2220          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2221          * retain the full precision throughout the pipeline.
2222          */
2223         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2224         if (bypass_lut)
2225                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2226         else
2227                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2228         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2229
2230         if (bypass_lut)
2231                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2232
2233         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2234         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2235         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2236         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2237         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2238         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2239
2240         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2241         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2242
2243         dce_v10_0_grph_enable(crtc, true);
2244
2245         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2246                target_fb->height);
2247
2248         x &= ~3;
2249         y &= ~1;
2250         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2251                (x << 16) | y);
2252         viewport_w = crtc->mode.hdisplay;
2253         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2254         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2255                (viewport_w << 16) | viewport_h);
2256
2257         /* pageflip setup */
2258         /* make sure flip is at vb rather than hb */
2259         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2260         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2261                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2262         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2263
2264         /* set pageflip to happen only at start of vblank interval (front porch) */
2265         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2266
2267         if (!atomic && fb && fb != crtc->primary->fb) {
2268                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2269                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2270                 r = amdgpu_bo_reserve(rbo, false);
2271                 if (unlikely(r != 0))
2272                         return r;
2273                 amdgpu_bo_unpin(rbo);
2274                 amdgpu_bo_unreserve(rbo);
2275         }
2276
2277         /* Bytes per pixel may have changed */
2278         dce_v10_0_bandwidth_update(adev);
2279
2280         return 0;
2281 }
2282
2283 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2284                                      struct drm_display_mode *mode)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct amdgpu_device *adev = dev->dev_private;
2288         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2289         u32 tmp;
2290
2291         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2292         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2293                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2294         else
2295                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2296         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2297 }
2298
2299 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2300 {
2301         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2302         struct drm_device *dev = crtc->dev;
2303         struct amdgpu_device *adev = dev->dev_private;
2304         int i;
2305         u32 tmp;
2306
2307         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2308
2309         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2310         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2311         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2312         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2313
2314         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2315         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2316         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2317
2318         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2319         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2320         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2321
2322         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2323         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2324         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2325         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2326
2327         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2328
2329         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2330         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2331         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2332
2333         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2334         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2335         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2336
2337         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2338         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2339
2340         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2341         for (i = 0; i < 256; i++) {
2342                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2343                        (amdgpu_crtc->lut_r[i] << 20) |
2344                        (amdgpu_crtc->lut_g[i] << 10) |
2345                        (amdgpu_crtc->lut_b[i] << 0));
2346         }
2347
2348         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2349         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2350         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2351         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2352         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353
2354         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2355         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2356         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2357         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2358
2359         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2360         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2361         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2362         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2363
2364         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2365         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2366         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2367         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2368
2369         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2370         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2371         /* XXX this only needs to be programmed once per crtc at startup,
2372          * not sure where the best place for it is
2373          */
2374         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2375         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2376         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2377 }
2378
2379 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2380 {
2381         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2382         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2383
2384         switch (amdgpu_encoder->encoder_id) {
2385         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2386                 if (dig->linkb)
2387                         return 1;
2388                 else
2389                         return 0;
2390                 break;
2391         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2392                 if (dig->linkb)
2393                         return 3;
2394                 else
2395                         return 2;
2396                 break;
2397         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2398                 if (dig->linkb)
2399                         return 5;
2400                 else
2401                         return 4;
2402                 break;
2403         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2404                 return 6;
2405                 break;
2406         default:
2407                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2408                 return 0;
2409         }
2410 }
2411
2412 /**
2413  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2414  *
2415  * @crtc: drm crtc
2416  *
2417  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2418  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2419  * monitors a dedicated PPLL must be used.  If a particular board has
2420  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2421  * as there is no need to program the PLL itself.  If we are not able to
2422  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2423  * avoid messing up an existing monitor.
2424  *
2425  * Asic specific PLL information
2426  *
2427  * DCE 10.x
2428  * Tonga
2429  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2430  * CI
2431  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2432  *
2433  */
2434 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2435 {
2436         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2437         struct drm_device *dev = crtc->dev;
2438         struct amdgpu_device *adev = dev->dev_private;
2439         u32 pll_in_use;
2440         int pll;
2441
2442         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2443                 if (adev->clock.dp_extclk)
2444                         /* skip PPLL programming if using ext clock */
2445                         return ATOM_PPLL_INVALID;
2446                 else {
2447                         /* use the same PPLL for all DP monitors */
2448                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2449                         if (pll != ATOM_PPLL_INVALID)
2450                                 return pll;
2451                 }
2452         } else {
2453                 /* use the same PPLL for all monitors with the same clock */
2454                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2455                 if (pll != ATOM_PPLL_INVALID)
2456                         return pll;
2457         }
2458
2459         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2460         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2461         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2462                 return ATOM_PPLL2;
2463         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2464                 return ATOM_PPLL1;
2465         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2466                 return ATOM_PPLL0;
2467         DRM_ERROR("unable to allocate a PPLL\n");
2468         return ATOM_PPLL_INVALID;
2469 }
2470
2471 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2472 {
2473         struct amdgpu_device *adev = crtc->dev->dev_private;
2474         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475         uint32_t cur_lock;
2476
2477         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2478         if (lock)
2479                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2480         else
2481                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2482         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2483 }
2484
2485 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2486 {
2487         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2488         struct amdgpu_device *adev = crtc->dev->dev_private;
2489         u32 tmp;
2490
2491         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2492         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2493         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2494 }
2495
2496 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2497 {
2498         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2499         struct amdgpu_device *adev = crtc->dev->dev_private;
2500         u32 tmp;
2501
2502         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2503                upper_32_bits(amdgpu_crtc->cursor_addr));
2504         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2505                lower_32_bits(amdgpu_crtc->cursor_addr));
2506
2507         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2508         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2509         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2510         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2511 }
2512
2513 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2514                                         int x, int y)
2515 {
2516         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2517         struct amdgpu_device *adev = crtc->dev->dev_private;
2518         int xorigin = 0, yorigin = 0;
2519
2520         /* avivo cursor are offset into the total surface */
2521         x += crtc->x;
2522         y += crtc->y;
2523         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2524
2525         if (x < 0) {
2526                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2527                 x = 0;
2528         }
2529         if (y < 0) {
2530                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2531                 y = 0;
2532         }
2533
2534         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2535         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2536         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2537                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2538
2539         amdgpu_crtc->cursor_x = x;
2540         amdgpu_crtc->cursor_y = y;
2541
2542         return 0;
2543 }
2544
2545 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2546                                       int x, int y)
2547 {
2548         int ret;
2549
2550         dce_v10_0_lock_cursor(crtc, true);
2551         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2552         dce_v10_0_lock_cursor(crtc, false);
2553
2554         return ret;
2555 }
2556
2557 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2558                                       struct drm_file *file_priv,
2559                                       uint32_t handle,
2560                                       uint32_t width,
2561                                       uint32_t height,
2562                                       int32_t hot_x,
2563                                       int32_t hot_y)
2564 {
2565         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2566         struct drm_gem_object *obj;
2567         struct amdgpu_bo *aobj;
2568         int ret;
2569
2570         if (!handle) {
2571                 /* turn off cursor */
2572                 dce_v10_0_hide_cursor(crtc);
2573                 obj = NULL;
2574                 goto unpin;
2575         }
2576
2577         if ((width > amdgpu_crtc->max_cursor_width) ||
2578             (height > amdgpu_crtc->max_cursor_height)) {
2579                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2580                 return -EINVAL;
2581         }
2582
2583         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2584         if (!obj) {
2585                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2586                 return -ENOENT;
2587         }
2588
2589         aobj = gem_to_amdgpu_bo(obj);
2590         ret = amdgpu_bo_reserve(aobj, false);
2591         if (ret != 0) {
2592                 drm_gem_object_unreference_unlocked(obj);
2593                 return ret;
2594         }
2595
2596         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2597         amdgpu_bo_unreserve(aobj);
2598         if (ret) {
2599                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2600                 drm_gem_object_unreference_unlocked(obj);
2601                 return ret;
2602         }
2603
2604         amdgpu_crtc->cursor_width = width;
2605         amdgpu_crtc->cursor_height = height;
2606
2607         dce_v10_0_lock_cursor(crtc, true);
2608
2609         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2610             hot_y != amdgpu_crtc->cursor_hot_y) {
2611                 int x, y;
2612
2613                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2614                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2615
2616                 dce_v10_0_cursor_move_locked(crtc, x, y);
2617
2618                 amdgpu_crtc->cursor_hot_x = hot_x;
2619                 amdgpu_crtc->cursor_hot_y = hot_y;
2620         }
2621
2622         dce_v10_0_show_cursor(crtc);
2623         dce_v10_0_lock_cursor(crtc, false);
2624
2625 unpin:
2626         if (amdgpu_crtc->cursor_bo) {
2627                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2628                 ret = amdgpu_bo_reserve(aobj, false);
2629                 if (likely(ret == 0)) {
2630                         amdgpu_bo_unpin(aobj);
2631                         amdgpu_bo_unreserve(aobj);
2632                 }
2633                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2634         }
2635
2636         amdgpu_crtc->cursor_bo = obj;
2637         return 0;
2638 }
2639
2640 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2641 {
2642         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2643
2644         if (amdgpu_crtc->cursor_bo) {
2645                 dce_v10_0_lock_cursor(crtc, true);
2646
2647                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2648                                              amdgpu_crtc->cursor_y);
2649
2650                 dce_v10_0_show_cursor(crtc);
2651
2652                 dce_v10_0_lock_cursor(crtc, false);
2653         }
2654 }
2655
2656 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2657                                     u16 *blue, uint32_t start, uint32_t size)
2658 {
2659         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2660         int end = (start + size > 256) ? 256 : start + size, i;
2661
2662         /* userspace palettes are always correct as is */
2663         for (i = start; i < end; i++) {
2664                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2665                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2666                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2667         }
2668         dce_v10_0_crtc_load_lut(crtc);
2669 }
2670
2671 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2672 {
2673         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2674
2675         drm_crtc_cleanup(crtc);
2676         destroy_workqueue(amdgpu_crtc->pflip_queue);
2677         kfree(amdgpu_crtc);
2678 }
2679
2680 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2681         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2682         .cursor_move = dce_v10_0_crtc_cursor_move,
2683         .gamma_set = dce_v10_0_crtc_gamma_set,
2684         .set_config = amdgpu_crtc_set_config,
2685         .destroy = dce_v10_0_crtc_destroy,
2686         .page_flip = amdgpu_crtc_page_flip,
2687 };
2688
2689 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2690 {
2691         struct drm_device *dev = crtc->dev;
2692         struct amdgpu_device *adev = dev->dev_private;
2693         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2694         unsigned type;
2695
2696         switch (mode) {
2697         case DRM_MODE_DPMS_ON:
2698                 amdgpu_crtc->enabled = true;
2699                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2700                 dce_v10_0_vga_enable(crtc, true);
2701                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2702                 dce_v10_0_vga_enable(crtc, false);
2703                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2704                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2705                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2706                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2707                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2708                 dce_v10_0_crtc_load_lut(crtc);
2709                 break;
2710         case DRM_MODE_DPMS_STANDBY:
2711         case DRM_MODE_DPMS_SUSPEND:
2712         case DRM_MODE_DPMS_OFF:
2713                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2714                 if (amdgpu_crtc->enabled) {
2715                         dce_v10_0_vga_enable(crtc, true);
2716                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2717                         dce_v10_0_vga_enable(crtc, false);
2718                 }
2719                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2720                 amdgpu_crtc->enabled = false;
2721                 break;
2722         }
2723         /* adjust pm to dpms */
2724         amdgpu_pm_compute_clocks(adev);
2725 }
2726
2727 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2728 {
2729         /* disable crtc pair power gating before programming */
2730         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2731         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2732         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2733 }
2734
2735 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2736 {
2737         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2738         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2739 }
2740
2741 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2742 {
2743         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2744         struct drm_device *dev = crtc->dev;
2745         struct amdgpu_device *adev = dev->dev_private;
2746         struct amdgpu_atom_ss ss;
2747         int i;
2748
2749         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2750         if (crtc->primary->fb) {
2751                 int r;
2752                 struct amdgpu_framebuffer *amdgpu_fb;
2753                 struct amdgpu_bo *rbo;
2754
2755                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2756                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2757                 r = amdgpu_bo_reserve(rbo, false);
2758                 if (unlikely(r))
2759                         DRM_ERROR("failed to reserve rbo before unpin\n");
2760                 else {
2761                         amdgpu_bo_unpin(rbo);
2762                         amdgpu_bo_unreserve(rbo);
2763                 }
2764         }
2765         /* disable the GRPH */
2766         dce_v10_0_grph_enable(crtc, false);
2767
2768         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2769
2770         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2771                 if (adev->mode_info.crtcs[i] &&
2772                     adev->mode_info.crtcs[i]->enabled &&
2773                     i != amdgpu_crtc->crtc_id &&
2774                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2775                         /* one other crtc is using this pll don't turn
2776                          * off the pll
2777                          */
2778                         goto done;
2779                 }
2780         }
2781
2782         switch (amdgpu_crtc->pll_id) {
2783         case ATOM_PPLL0:
2784         case ATOM_PPLL1:
2785         case ATOM_PPLL2:
2786                 /* disable the ppll */
2787                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2788                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2789                 break;
2790         default:
2791                 break;
2792         }
2793 done:
2794         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2795         amdgpu_crtc->adjusted_clock = 0;
2796         amdgpu_crtc->encoder = NULL;
2797         amdgpu_crtc->connector = NULL;
2798 }
2799
2800 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2801                                   struct drm_display_mode *mode,
2802                                   struct drm_display_mode *adjusted_mode,
2803                                   int x, int y, struct drm_framebuffer *old_fb)
2804 {
2805         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2806
2807         if (!amdgpu_crtc->adjusted_clock)
2808                 return -EINVAL;
2809
2810         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2811         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2812         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2813         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2814         amdgpu_atombios_crtc_scaler_setup(crtc);
2815         dce_v10_0_cursor_reset(crtc);
2816         /* update the hw version fpr dpm */
2817         amdgpu_crtc->hw_mode = *adjusted_mode;
2818
2819         return 0;
2820 }
2821
2822 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2823                                      const struct drm_display_mode *mode,
2824                                      struct drm_display_mode *adjusted_mode)
2825 {
2826         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_encoder *encoder;
2829
2830         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2831         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2832                 if (encoder->crtc == crtc) {
2833                         amdgpu_crtc->encoder = encoder;
2834                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2835                         break;
2836                 }
2837         }
2838         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2839                 amdgpu_crtc->encoder = NULL;
2840                 amdgpu_crtc->connector = NULL;
2841                 return false;
2842         }
2843         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2844                 return false;
2845         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2846                 return false;
2847         /* pick pll */
2848         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2849         /* if we can't get a PPLL for a non-DP encoder, fail */
2850         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2851             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2852                 return false;
2853
2854         return true;
2855 }
2856
2857 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2858                                   struct drm_framebuffer *old_fb)
2859 {
2860         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2861 }
2862
2863 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2864                                          struct drm_framebuffer *fb,
2865                                          int x, int y, enum mode_set_atomic state)
2866 {
2867        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2868 }
2869
2870 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2871         .dpms = dce_v10_0_crtc_dpms,
2872         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2873         .mode_set = dce_v10_0_crtc_mode_set,
2874         .mode_set_base = dce_v10_0_crtc_set_base,
2875         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2876         .prepare = dce_v10_0_crtc_prepare,
2877         .commit = dce_v10_0_crtc_commit,
2878         .load_lut = dce_v10_0_crtc_load_lut,
2879         .disable = dce_v10_0_crtc_disable,
2880 };
2881
2882 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2883 {
2884         struct amdgpu_crtc *amdgpu_crtc;
2885         int i;
2886
2887         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2888                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2889         if (amdgpu_crtc == NULL)
2890                 return -ENOMEM;
2891
2892         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2893
2894         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2895         amdgpu_crtc->crtc_id = index;
2896         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2897         adev->mode_info.crtcs[index] = amdgpu_crtc;
2898
2899         amdgpu_crtc->max_cursor_width = 128;
2900         amdgpu_crtc->max_cursor_height = 128;
2901         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2902         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2903
2904         for (i = 0; i < 256; i++) {
2905                 amdgpu_crtc->lut_r[i] = i << 2;
2906                 amdgpu_crtc->lut_g[i] = i << 2;
2907                 amdgpu_crtc->lut_b[i] = i << 2;
2908         }
2909
2910         switch (amdgpu_crtc->crtc_id) {
2911         case 0:
2912         default:
2913                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2914                 break;
2915         case 1:
2916                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2917                 break;
2918         case 2:
2919                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2920                 break;
2921         case 3:
2922                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2923                 break;
2924         case 4:
2925                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2926                 break;
2927         case 5:
2928                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2929                 break;
2930         }
2931
2932         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2933         amdgpu_crtc->adjusted_clock = 0;
2934         amdgpu_crtc->encoder = NULL;
2935         amdgpu_crtc->connector = NULL;
2936         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2937
2938         return 0;
2939 }
2940
2941 static int dce_v10_0_early_init(void *handle)
2942 {
2943         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2944
2945         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2946         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2947
2948         dce_v10_0_set_display_funcs(adev);
2949         dce_v10_0_set_irq_funcs(adev);
2950
2951         switch (adev->asic_type) {
2952         case CHIP_FIJI:
2953         case CHIP_TONGA:
2954                 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2955                 adev->mode_info.num_hpd = 6;
2956                 adev->mode_info.num_dig = 7;
2957                 break;
2958         default:
2959                 /* FIXME: not supported yet */
2960                 return -EINVAL;
2961         }
2962
2963         return 0;
2964 }
2965
2966 static int dce_v10_0_sw_init(void *handle)
2967 {
2968         int r, i;
2969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2970
2971         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2972                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2973                 if (r)
2974                         return r;
2975         }
2976
2977         for (i = 8; i < 20; i += 2) {
2978                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2979                 if (r)
2980                         return r;
2981         }
2982
2983         /* HPD hotplug */
2984         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2985         if (r)
2986                 return r;
2987
2988         adev->mode_info.mode_config_initialized = true;
2989
2990         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2991
2992         adev->ddev->mode_config.max_width = 16384;
2993         adev->ddev->mode_config.max_height = 16384;
2994
2995         adev->ddev->mode_config.preferred_depth = 24;
2996         adev->ddev->mode_config.prefer_shadow = 1;
2997
2998         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2999
3000         r = amdgpu_modeset_create_props(adev);
3001         if (r)
3002                 return r;
3003
3004         adev->ddev->mode_config.max_width = 16384;
3005         adev->ddev->mode_config.max_height = 16384;
3006
3007         /* allocate crtcs */
3008         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3009                 r = dce_v10_0_crtc_init(adev, i);
3010                 if (r)
3011                         return r;
3012         }
3013
3014         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3015                 amdgpu_print_display_setup(adev->ddev);
3016         else
3017                 return -EINVAL;
3018
3019         /* setup afmt */
3020         dce_v10_0_afmt_init(adev);
3021
3022         r = dce_v10_0_audio_init(adev);
3023         if (r)
3024                 return r;
3025
3026         drm_kms_helper_poll_init(adev->ddev);
3027
3028         return r;
3029 }
3030
3031 static int dce_v10_0_sw_fini(void *handle)
3032 {
3033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035         kfree(adev->mode_info.bios_hardcoded_edid);
3036
3037         drm_kms_helper_poll_fini(adev->ddev);
3038
3039         dce_v10_0_audio_fini(adev);
3040
3041         dce_v10_0_afmt_fini(adev);
3042
3043         drm_mode_config_cleanup(adev->ddev);
3044         adev->mode_info.mode_config_initialized = false;
3045
3046         return 0;
3047 }
3048
3049 static int dce_v10_0_hw_init(void *handle)
3050 {
3051         int i;
3052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3053
3054         dce_v10_0_init_golden_registers(adev);
3055
3056         /* init dig PHYs, disp eng pll */
3057         amdgpu_atombios_encoder_init_dig(adev);
3058         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3059
3060         /* initialize hpd */
3061         dce_v10_0_hpd_init(adev);
3062
3063         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3064                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3065         }
3066
3067         dce_v10_0_pageflip_interrupt_init(adev);
3068
3069         return 0;
3070 }
3071
3072 static int dce_v10_0_hw_fini(void *handle)
3073 {
3074         int i;
3075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076
3077         dce_v10_0_hpd_fini(adev);
3078
3079         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3080                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3081         }
3082
3083         dce_v10_0_pageflip_interrupt_fini(adev);
3084
3085         return 0;
3086 }
3087
3088 static int dce_v10_0_suspend(void *handle)
3089 {
3090         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3091
3092         amdgpu_atombios_scratch_regs_save(adev);
3093
3094         return dce_v10_0_hw_fini(handle);
3095 }
3096
3097 static int dce_v10_0_resume(void *handle)
3098 {
3099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3100         int ret;
3101
3102         ret = dce_v10_0_hw_init(handle);
3103
3104         amdgpu_atombios_scratch_regs_restore(adev);
3105
3106         /* turn on the BL */
3107         if (adev->mode_info.bl_encoder) {
3108                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3109                                                                   adev->mode_info.bl_encoder);
3110                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3111                                                     bl_level);
3112         }
3113
3114         return ret;
3115 }
3116
3117 static bool dce_v10_0_is_idle(void *handle)
3118 {
3119         return true;
3120 }
3121
3122 static int dce_v10_0_wait_for_idle(void *handle)
3123 {
3124         return 0;
3125 }
3126
3127 static void dce_v10_0_print_status(void *handle)
3128 {
3129         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3130
3131         dev_info(adev->dev, "DCE 10.x registers\n");
3132         /* XXX todo */
3133 }
3134
3135 static int dce_v10_0_soft_reset(void *handle)
3136 {
3137         u32 srbm_soft_reset = 0, tmp;
3138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3139
3140         if (dce_v10_0_is_display_hung(adev))
3141                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3142
3143         if (srbm_soft_reset) {
3144                 dce_v10_0_print_status((void *)adev);
3145
3146                 tmp = RREG32(mmSRBM_SOFT_RESET);
3147                 tmp |= srbm_soft_reset;
3148                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3149                 WREG32(mmSRBM_SOFT_RESET, tmp);
3150                 tmp = RREG32(mmSRBM_SOFT_RESET);
3151
3152                 udelay(50);
3153
3154                 tmp &= ~srbm_soft_reset;
3155                 WREG32(mmSRBM_SOFT_RESET, tmp);
3156                 tmp = RREG32(mmSRBM_SOFT_RESET);
3157
3158                 /* Wait a little for things to settle down */
3159                 udelay(50);
3160                 dce_v10_0_print_status((void *)adev);
3161         }
3162         return 0;
3163 }
3164
3165 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3166                                                      int crtc,
3167                                                      enum amdgpu_interrupt_state state)
3168 {
3169         u32 lb_interrupt_mask;
3170
3171         if (crtc >= adev->mode_info.num_crtc) {
3172                 DRM_DEBUG("invalid crtc %d\n", crtc);
3173                 return;
3174         }
3175
3176         switch (state) {
3177         case AMDGPU_IRQ_STATE_DISABLE:
3178                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3179                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3180                                                   VBLANK_INTERRUPT_MASK, 0);
3181                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3182                 break;
3183         case AMDGPU_IRQ_STATE_ENABLE:
3184                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3185                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3186                                                   VBLANK_INTERRUPT_MASK, 1);
3187                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3188                 break;
3189         default:
3190                 break;
3191         }
3192 }
3193
3194 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3195                                                     int crtc,
3196                                                     enum amdgpu_interrupt_state state)
3197 {
3198         u32 lb_interrupt_mask;
3199
3200         if (crtc >= adev->mode_info.num_crtc) {
3201                 DRM_DEBUG("invalid crtc %d\n", crtc);
3202                 return;
3203         }
3204
3205         switch (state) {
3206         case AMDGPU_IRQ_STATE_DISABLE:
3207                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3208                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3209                                                   VLINE_INTERRUPT_MASK, 0);
3210                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3211                 break;
3212         case AMDGPU_IRQ_STATE_ENABLE:
3213                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3214                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3215                                                   VLINE_INTERRUPT_MASK, 1);
3216                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3217                 break;
3218         default:
3219                 break;
3220         }
3221 }
3222
3223 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3224                                        struct amdgpu_irq_src *source,
3225                                        unsigned hpd,
3226                                        enum amdgpu_interrupt_state state)
3227 {
3228         u32 tmp;
3229
3230         if (hpd >= adev->mode_info.num_hpd) {
3231                 DRM_DEBUG("invalid hdp %d\n", hpd);
3232                 return 0;
3233         }
3234
3235         switch (state) {
3236         case AMDGPU_IRQ_STATE_DISABLE:
3237                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3238                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3239                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3240                 break;
3241         case AMDGPU_IRQ_STATE_ENABLE:
3242                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3243                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3244                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3245                 break;
3246         default:
3247                 break;
3248         }
3249
3250         return 0;
3251 }
3252
3253 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3254                                         struct amdgpu_irq_src *source,
3255                                         unsigned type,
3256                                         enum amdgpu_interrupt_state state)
3257 {
3258         switch (type) {
3259         case AMDGPU_CRTC_IRQ_VBLANK1:
3260                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3261                 break;
3262         case AMDGPU_CRTC_IRQ_VBLANK2:
3263                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3264                 break;
3265         case AMDGPU_CRTC_IRQ_VBLANK3:
3266                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3267                 break;
3268         case AMDGPU_CRTC_IRQ_VBLANK4:
3269                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3270                 break;
3271         case AMDGPU_CRTC_IRQ_VBLANK5:
3272                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3273                 break;
3274         case AMDGPU_CRTC_IRQ_VBLANK6:
3275                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3276                 break;
3277         case AMDGPU_CRTC_IRQ_VLINE1:
3278                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3279                 break;
3280         case AMDGPU_CRTC_IRQ_VLINE2:
3281                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3282                 break;
3283         case AMDGPU_CRTC_IRQ_VLINE3:
3284                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3285                 break;
3286         case AMDGPU_CRTC_IRQ_VLINE4:
3287                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3288                 break;
3289         case AMDGPU_CRTC_IRQ_VLINE5:
3290                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3291                 break;
3292         case AMDGPU_CRTC_IRQ_VLINE6:
3293                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3294                 break;
3295         default:
3296                 break;
3297         }
3298         return 0;
3299 }
3300
3301 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3302                                             struct amdgpu_irq_src *src,
3303                                             unsigned type,
3304                                             enum amdgpu_interrupt_state state)
3305 {
3306         u32 reg;
3307
3308         if (type >= adev->mode_info.num_crtc) {
3309                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3310                 return -EINVAL;
3311         }
3312
3313         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3314         if (state == AMDGPU_IRQ_STATE_DISABLE)
3315                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3316                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3317         else
3318                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3319                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3320
3321         return 0;
3322 }
3323
3324 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3325                                   struct amdgpu_irq_src *source,
3326                                   struct amdgpu_iv_entry *entry)
3327 {
3328         unsigned long flags;
3329         unsigned crtc_id;
3330         struct amdgpu_crtc *amdgpu_crtc;
3331         struct amdgpu_flip_work *works;
3332
3333         crtc_id = (entry->src_id - 8) >> 1;
3334         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3335
3336         if (crtc_id >= adev->mode_info.num_crtc) {
3337                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3338                 return -EINVAL;
3339         }
3340
3341         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3342             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3343                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3344                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3345
3346         /* IRQ could occur when in initial stage */
3347         if (amdgpu_crtc == NULL)
3348                 return 0;
3349
3350         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3351         works = amdgpu_crtc->pflip_works;
3352         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3353                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3354                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3355                                                  amdgpu_crtc->pflip_status,
3356                                                  AMDGPU_FLIP_SUBMITTED);
3357                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3358                 return 0;
3359         }
3360
3361         /* page flip completed. clean up */
3362         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3363         amdgpu_crtc->pflip_works = NULL;
3364
3365         /* wakeup usersapce */
3366         if (works->event)
3367                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3368
3369         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3370
3371         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3372         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3373
3374         return 0;
3375 }
3376
3377 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3378                                   int hpd)
3379 {
3380         u32 tmp;
3381
3382         if (hpd >= adev->mode_info.num_hpd) {
3383                 DRM_DEBUG("invalid hdp %d\n", hpd);
3384                 return;
3385         }
3386
3387         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3388         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3389         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3390 }
3391
3392 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3393                                           int crtc)
3394 {
3395         u32 tmp;
3396
3397         if (crtc >= adev->mode_info.num_crtc) {
3398                 DRM_DEBUG("invalid crtc %d\n", crtc);
3399                 return;
3400         }
3401
3402         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3403         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3404         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3405 }
3406
3407 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3408                                          int crtc)
3409 {
3410         u32 tmp;
3411
3412         if (crtc >= adev->mode_info.num_crtc) {
3413                 DRM_DEBUG("invalid crtc %d\n", crtc);
3414                 return;
3415         }
3416
3417         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3418         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3419         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3420 }
3421
3422 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3423                               struct amdgpu_irq_src *source,
3424                               struct amdgpu_iv_entry *entry)
3425 {
3426         unsigned crtc = entry->src_id - 1;
3427         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3428         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3429
3430         switch (entry->src_data) {
3431         case 0: /* vblank */
3432                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3433                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3434                 else
3435                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3436
3437                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3438                         drm_handle_vblank(adev->ddev, crtc);
3439                 }
3440                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3441
3442                 break;
3443         case 1: /* vline */
3444                 if (disp_int & interrupt_status_offsets[crtc].vline)
3445                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3446                 else
3447                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3448
3449                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3450
3451                 break;
3452         default:
3453                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3454                 break;
3455         }
3456
3457         return 0;
3458 }
3459
3460 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3461                              struct amdgpu_irq_src *source,
3462                              struct amdgpu_iv_entry *entry)
3463 {
3464         uint32_t disp_int, mask;
3465         unsigned hpd;
3466
3467         if (entry->src_data >= adev->mode_info.num_hpd) {
3468                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3469                 return 0;
3470         }
3471
3472         hpd = entry->src_data;
3473         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3474         mask = interrupt_status_offsets[hpd].hpd;
3475
3476         if (disp_int & mask) {
3477                 dce_v10_0_hpd_int_ack(adev, hpd);
3478                 schedule_work(&adev->hotplug_work);
3479                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3480         }
3481
3482         return 0;
3483 }
3484
3485 static int dce_v10_0_set_clockgating_state(void *handle,
3486                                           enum amd_clockgating_state state)
3487 {
3488         return 0;
3489 }
3490
3491 static int dce_v10_0_set_powergating_state(void *handle,
3492                                           enum amd_powergating_state state)
3493 {
3494         return 0;
3495 }
3496
3497 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3498         .early_init = dce_v10_0_early_init,
3499         .late_init = NULL,
3500         .sw_init = dce_v10_0_sw_init,
3501         .sw_fini = dce_v10_0_sw_fini,
3502         .hw_init = dce_v10_0_hw_init,
3503         .hw_fini = dce_v10_0_hw_fini,
3504         .suspend = dce_v10_0_suspend,
3505         .resume = dce_v10_0_resume,
3506         .is_idle = dce_v10_0_is_idle,
3507         .wait_for_idle = dce_v10_0_wait_for_idle,
3508         .soft_reset = dce_v10_0_soft_reset,
3509         .print_status = dce_v10_0_print_status,
3510         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3511         .set_powergating_state = dce_v10_0_set_powergating_state,
3512 };
3513
3514 static void
3515 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3516                           struct drm_display_mode *mode,
3517                           struct drm_display_mode *adjusted_mode)
3518 {
3519         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3520
3521         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3522
3523         /* need to call this here rather than in prepare() since we need some crtc info */
3524         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3525
3526         /* set scaler clears this on some chips */
3527         dce_v10_0_set_interleave(encoder->crtc, mode);
3528
3529         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3530                 dce_v10_0_afmt_enable(encoder, true);
3531                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3532         }
3533 }
3534
3535 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3536 {
3537         struct amdgpu_device *adev = encoder->dev->dev_private;
3538         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3539         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3540
3541         if ((amdgpu_encoder->active_device &
3542              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3543             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3544              ENCODER_OBJECT_ID_NONE)) {
3545                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3546                 if (dig) {
3547                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3548                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3549                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3550                 }
3551         }
3552
3553         amdgpu_atombios_scratch_regs_lock(adev, true);
3554
3555         if (connector) {
3556                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3557
3558                 /* select the clock/data port if it uses a router */
3559                 if (amdgpu_connector->router.cd_valid)
3560                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3561
3562                 /* turn eDP panel on for mode set */
3563                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3564                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3565                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3566         }
3567
3568         /* this is needed for the pll/ss setup to work correctly in some cases */
3569         amdgpu_atombios_encoder_set_crtc_source(encoder);
3570         /* set up the FMT blocks */
3571         dce_v10_0_program_fmt(encoder);
3572 }
3573
3574 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3575 {
3576         struct drm_device *dev = encoder->dev;
3577         struct amdgpu_device *adev = dev->dev_private;
3578
3579         /* need to call this here as we need the crtc set up */
3580         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3581         amdgpu_atombios_scratch_regs_lock(adev, false);
3582 }
3583
3584 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3585 {
3586         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3587         struct amdgpu_encoder_atom_dig *dig;
3588
3589         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3590
3591         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3592                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3593                         dce_v10_0_afmt_enable(encoder, false);
3594                 dig = amdgpu_encoder->enc_priv;
3595                 dig->dig_encoder = -1;
3596         }
3597         amdgpu_encoder->active_device = 0;
3598 }
3599
3600 /* these are handled by the primary encoders */
3601 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3602 {
3603
3604 }
3605
3606 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3607 {
3608
3609 }
3610
3611 static void
3612 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3613                       struct drm_display_mode *mode,
3614                       struct drm_display_mode *adjusted_mode)
3615 {
3616
3617 }
3618
3619 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3620 {
3621
3622 }
3623
3624 static void
3625 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3626 {
3627
3628 }
3629
3630 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder,
3631                                     const struct drm_display_mode *mode,
3632                                     struct drm_display_mode *adjusted_mode)
3633 {
3634         return true;
3635 }
3636
3637 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3638         .dpms = dce_v10_0_ext_dpms,
3639         .mode_fixup = dce_v10_0_ext_mode_fixup,
3640         .prepare = dce_v10_0_ext_prepare,
3641         .mode_set = dce_v10_0_ext_mode_set,
3642         .commit = dce_v10_0_ext_commit,
3643         .disable = dce_v10_0_ext_disable,
3644         /* no detect for TMDS/LVDS yet */
3645 };
3646
3647 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3648         .dpms = amdgpu_atombios_encoder_dpms,
3649         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3650         .prepare = dce_v10_0_encoder_prepare,
3651         .mode_set = dce_v10_0_encoder_mode_set,
3652         .commit = dce_v10_0_encoder_commit,
3653         .disable = dce_v10_0_encoder_disable,
3654         .detect = amdgpu_atombios_encoder_dig_detect,
3655 };
3656
3657 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3658         .dpms = amdgpu_atombios_encoder_dpms,
3659         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3660         .prepare = dce_v10_0_encoder_prepare,
3661         .mode_set = dce_v10_0_encoder_mode_set,
3662         .commit = dce_v10_0_encoder_commit,
3663         .detect = amdgpu_atombios_encoder_dac_detect,
3664 };
3665
3666 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3667 {
3668         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3669         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3670                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3671         kfree(amdgpu_encoder->enc_priv);
3672         drm_encoder_cleanup(encoder);
3673         kfree(amdgpu_encoder);
3674 }
3675
3676 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3677         .destroy = dce_v10_0_encoder_destroy,
3678 };
3679
3680 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3681                                  uint32_t encoder_enum,
3682                                  uint32_t supported_device,
3683                                  u16 caps)
3684 {
3685         struct drm_device *dev = adev->ddev;
3686         struct drm_encoder *encoder;
3687         struct amdgpu_encoder *amdgpu_encoder;
3688
3689         /* see if we already added it */
3690         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3691                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3692                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3693                         amdgpu_encoder->devices |= supported_device;
3694                         return;
3695                 }
3696
3697         }
3698
3699         /* add a new one */
3700         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3701         if (!amdgpu_encoder)
3702                 return;
3703
3704         encoder = &amdgpu_encoder->base;
3705         switch (adev->mode_info.num_crtc) {
3706         case 1:
3707                 encoder->possible_crtcs = 0x1;
3708                 break;
3709         case 2:
3710         default:
3711                 encoder->possible_crtcs = 0x3;
3712                 break;
3713         case 4:
3714                 encoder->possible_crtcs = 0xf;
3715                 break;
3716         case 6:
3717                 encoder->possible_crtcs = 0x3f;
3718                 break;
3719         }
3720
3721         amdgpu_encoder->enc_priv = NULL;
3722
3723         amdgpu_encoder->encoder_enum = encoder_enum;
3724         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3725         amdgpu_encoder->devices = supported_device;
3726         amdgpu_encoder->rmx_type = RMX_OFF;
3727         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3728         amdgpu_encoder->is_ext_encoder = false;
3729         amdgpu_encoder->caps = caps;
3730
3731         switch (amdgpu_encoder->encoder_id) {
3732         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3733         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3734                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3735                                  DRM_MODE_ENCODER_DAC);
3736                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3737                 break;
3738         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3739         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3740         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3741         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3742         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3743                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3744                         amdgpu_encoder->rmx_type = RMX_FULL;
3745                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3746                                          DRM_MODE_ENCODER_LVDS);
3747                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3748                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3749                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3750                                          DRM_MODE_ENCODER_DAC);
3751                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3752                 } else {
3753                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3754                                          DRM_MODE_ENCODER_TMDS);
3755                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3756                 }
3757                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3758                 break;
3759         case ENCODER_OBJECT_ID_SI170B:
3760         case ENCODER_OBJECT_ID_CH7303:
3761         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3762         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3763         case ENCODER_OBJECT_ID_TITFP513:
3764         case ENCODER_OBJECT_ID_VT1623:
3765         case ENCODER_OBJECT_ID_HDMI_SI1930:
3766         case ENCODER_OBJECT_ID_TRAVIS:
3767         case ENCODER_OBJECT_ID_NUTMEG:
3768                 /* these are handled by the primary encoders */
3769                 amdgpu_encoder->is_ext_encoder = true;
3770                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3771                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3772                                          DRM_MODE_ENCODER_LVDS);
3773                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3774                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3775                                          DRM_MODE_ENCODER_DAC);
3776                 else
3777                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3778                                          DRM_MODE_ENCODER_TMDS);
3779                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3780                 break;
3781         }
3782 }
3783
3784 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3785         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3786         .bandwidth_update = &dce_v10_0_bandwidth_update,
3787         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3788         .vblank_wait = &dce_v10_0_vblank_wait,
3789         .is_display_hung = &dce_v10_0_is_display_hung,
3790         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3791         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3792         .hpd_sense = &dce_v10_0_hpd_sense,
3793         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3794         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3795         .page_flip = &dce_v10_0_page_flip,
3796         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3797         .add_encoder = &dce_v10_0_encoder_add,
3798         .add_connector = &amdgpu_connector_add,
3799         .stop_mc_access = &dce_v10_0_stop_mc_access,
3800         .resume_mc_access = &dce_v10_0_resume_mc_access,
3801 };
3802
3803 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3804 {
3805         if (adev->mode_info.funcs == NULL)
3806                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3807 }
3808
3809 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3810         .set = dce_v10_0_set_crtc_irq_state,
3811         .process = dce_v10_0_crtc_irq,
3812 };
3813
3814 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3815         .set = dce_v10_0_set_pageflip_irq_state,
3816         .process = dce_v10_0_pageflip_irq,
3817 };
3818
3819 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3820         .set = dce_v10_0_set_hpd_irq_state,
3821         .process = dce_v10_0_hpd_irq,
3822 };
3823
3824 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3825 {
3826         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3827         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3828
3829         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3830         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3831
3832         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3833         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3834 }