kernel/drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static int cik_sdma_soft_reset(void *handle);
  56
  57 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  58 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  60 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  62 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  64 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  66 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  67
  68 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  69
  70 /*
  71  * sDMA - System DMA
  72  * Starting with CIK, the GPU has new asynchronous
  73  * DMA engines.  These engines are used for compute
  74  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  75  * and each one supports 1 ring buffer used for gfx
  76  * and 2 queues used for compute.
  77  *
  78  * The programming model is very similar to the CP
  79  * (ring buffer, IBs, etc.), but sDMA has it's own
  80  * packet format that is different from the PM4 format
  81  * used by the CP. sDMA supports copying data, writing
  82  * embedded data, solid fills, and a number of other
  83  * things.  It also has support for tiling/detiling of
  84  * buffers.
  85  */
  86
  87 /**
  88  * cik_sdma_init_microcode - load ucode images from disk
  89  *
  90  * @adev: amdgpu_device pointer
  91  *
  92  * Use the firmware interface to load the ucode images into
  93  * the driver (not loaded into hw).
  94  * Returns 0 on success, error on failure.
  95  */
  96 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  97 {
  98         const char *chip_name;
  99         char fw_name[30];
 100         int err = 0, i;
 101
 102         DRM_DEBUG("\n");
 103
 104         switch (adev->asic_type) {
 105         case CHIP_BONAIRE:
 106                 chip_name = "bonaire";
 107                 break;
 108         case CHIP_HAWAII:
 109                 chip_name = "hawaii";
 110                 break;
 111         case CHIP_KAVERI:
 112                 chip_name = "kaveri";
 113                 break;
 114         case CHIP_KABINI:
 115                 chip_name = "kabini";
 116                 break;
 117         case CHIP_MULLINS:
 118                 chip_name = "mullins";
 119                 break;
 120         default: BUG();
 121         }
 122
 123         for (i = 0; i < adev->sdma.num_instances; i++) {
 124                 if (i == 0)
 125                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 126                 else
 127                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 128                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 129                 if (err)
 130                         goto out;
 131                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 132         }
 133 out:
 134         if (err) {
 135                 printk(KERN_ERR
 136                        "cik_sdma: Failed to load firmware \"%s\"\n",
 137                        fw_name);
 138                 for (i = 0; i < adev->sdma.num_instances; i++) {
 139                         release_firmware(adev->sdma.instance[i].fw);
 140                         adev->sdma.instance[i].fw = NULL;
 141                 }
 142         }
 143         return err;
 144 }
 145
 146 /**
 147  * cik_sdma_ring_get_rptr - get the current read pointer
 148  *
 149  * @ring: amdgpu ring pointer
 150  *
 151  * Get the current rptr from the hardware (CIK+).
 152  */
 153 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 154 {
 155         u32 rptr;
 156
 157         rptr = ring->adev->wb.wb[ring->rptr_offs];
 158
 159         return (rptr & 0x3fffc) >> 2;
 160 }
 161
 162 /**
 163  * cik_sdma_ring_get_wptr - get the current write pointer
 164  *
 165  * @ring: amdgpu ring pointer
 166  *
 167  * Get the current wptr from the hardware (CIK+).
 168  */
 169 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 170 {
 171         struct amdgpu_device *adev = ring->adev;
 172         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 173
 174         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 175 }
 176
 177 /**
 178  * cik_sdma_ring_set_wptr - commit the write pointer
 179  *
 180  * @ring: amdgpu ring pointer
 181  *
 182  * Write the wptr back to the hardware (CIK+).
 183  */
 184 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 185 {
 186         struct amdgpu_device *adev = ring->adev;
 187         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 188
 189         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 190 }
 191
 192 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 193 {
 194         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 195         int i;
 196
 197         for (i = 0; i < count; i++)
 198                 if (sdma && sdma->burst_nop && (i == 0))
 199                         amdgpu_ring_write(ring, ring->nop |
 200                                           SDMA_NOP_COUNT(count - 1));
 201                 else
 202                         amdgpu_ring_write(ring, ring->nop);
 203 }
 204
 205 /**
 206  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 207  *
 208  * @ring: amdgpu ring pointer
 209  * @ib: IB object to schedule
 210  *
 211  * Schedule an IB in the DMA ring (CIK).
 212  */
 213 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 214                            struct amdgpu_ib *ib)
 215 {
 216         u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 217         u32 next_rptr = ring->wptr + 5;
 218
 219         while ((next_rptr & 7) != 4)
 220                 next_rptr++;
 221
 222         next_rptr += 4;
 223         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 224         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 225         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 226         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 227         amdgpu_ring_write(ring, next_rptr);
 228
 229         /* IB packet must end on a 8 DW boundary */
 230         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 231
 232         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 233         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 234         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 235         amdgpu_ring_write(ring, ib->length_dw);
 236
 237 }
 238
 239 /**
 240  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 241  *
 242  * @ring: amdgpu ring pointer
 243  *
 244  * Emit an hdp flush packet on the requested DMA ring.
 245  */
 246 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 247 {
 248         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 249                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 250         u32 ref_and_mask;
 251
 252         if (ring == &ring->adev->sdma.instance[0].ring)
 253                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 254         else
 255                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 256
 257         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 259         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 260         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 261         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 262         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 263 }
 264
 265 /**
 266  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 267  *
 268  * @ring: amdgpu ring pointer
 269  * @fence: amdgpu fence object
 270  *
 271  * Add a DMA fence packet to the ring to write
 272  * the fence seq number and DMA trap packet to generate
 273  * an interrupt if needed (CIK).
 274  */
 275 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 276                                      unsigned flags)
 277 {
 278         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 279         /* write the fence */
 280         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 281         amdgpu_ring_write(ring, lower_32_bits(addr));
 282         amdgpu_ring_write(ring, upper_32_bits(addr));
 283         amdgpu_ring_write(ring, lower_32_bits(seq));
 284
 285         /* optionally write high bits as well */
 286         if (write64bit) {
 287                 addr += 4;
 288                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 289                 amdgpu_ring_write(ring, lower_32_bits(addr));
 290                 amdgpu_ring_write(ring, upper_32_bits(addr));
 291                 amdgpu_ring_write(ring, upper_32_bits(seq));
 292         }
 293
 294         /* generate an interrupt */
 295         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 296 }
 297
 298 /**
 299  * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
 300  *
 301  * @ring: amdgpu_ring structure holding ring information
 302  * @semaphore: amdgpu semaphore object
 303  * @emit_wait: wait or signal semaphore
 304  *
 305  * Add a DMA semaphore packet to the ring wait on or signal
 306  * other rings (CIK).
 307  */
 308 static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
 309                                          struct amdgpu_semaphore *semaphore,
 310                                          bool emit_wait)
 311 {
 312         u64 addr = semaphore->gpu_addr;
 313         u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
 314
 315         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
 316         amdgpu_ring_write(ring, addr & 0xfffffff8);
 317         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 318
 319         return true;
 320 }
 321
 322 /**
 323  * cik_sdma_gfx_stop - stop the gfx async dma engines
 324  *
 325  * @adev: amdgpu_device pointer
 326  *
 327  * Stop the gfx async dma ring buffers (CIK).
 328  */
 329 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 330 {
 331         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 332         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 333         u32 rb_cntl;
 334         int i;
 335
 336         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 337             (adev->mman.buffer_funcs_ring == sdma1))
 338                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 339
 340         for (i = 0; i < adev->sdma.num_instances; i++) {
 341                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 342                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 343                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 344                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 345         }
 346         sdma0->ready = false;
 347         sdma1->ready = false;
 348 }
 349
 350 /**
 351  * cik_sdma_rlc_stop - stop the compute async dma engines
 352  *
 353  * @adev: amdgpu_device pointer
 354  *
 355  * Stop the compute async dma queues (CIK).
 356  */
 357 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 358 {
 359         /* XXX todo */
 360 }
 361
 362 /**
 363  * cik_sdma_enable - stop the async dma engines
 364  *
 365  * @adev: amdgpu_device pointer
 366  * @enable: enable/disable the DMA MEs.
 367  *
 368  * Halt or unhalt the async dma engines (CIK).
 369  */
 370 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 371 {
 372         u32 me_cntl;
 373         int i;
 374
 375         if (enable == false) {
 376                 cik_sdma_gfx_stop(adev);
 377                 cik_sdma_rlc_stop(adev);
 378         }
 379
 380         for (i = 0; i < adev->sdma.num_instances; i++) {
 381                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 382                 if (enable)
 383                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 384                 else
 385                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 386                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 387         }
 388 }
 389
 390 /**
 391  * cik_sdma_gfx_resume - setup and start the async dma engines
 392  *
 393  * @adev: amdgpu_device pointer
 394  *
 395  * Set up the gfx DMA ring buffers and enable them (CIK).
 396  * Returns 0 for success, error for failure.
 397  */
 398 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 399 {
 400         struct amdgpu_ring *ring;
 401         u32 rb_cntl, ib_cntl;
 402         u32 rb_bufsz;
 403         u32 wb_offset;
 404         int i, j, r;
 405
 406         for (i = 0; i < adev->sdma.num_instances; i++) {
 407                 ring = &adev->sdma.instance[i].ring;
 408                 wb_offset = (ring->rptr_offs * 4);
 409
 410                 mutex_lock(&adev->srbm_mutex);
 411                 for (j = 0; j < 16; j++) {
 412                         cik_srbm_select(adev, 0, 0, 0, j);
 413                         /* SDMA GFX */
 414                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 415                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 416                         /* XXX SDMA RLC - todo */
 417                 }
 418                 cik_srbm_select(adev, 0, 0, 0, 0);
 419                 mutex_unlock(&adev->srbm_mutex);
 420
 421                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 422                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 423
 424                 /* Set ring buffer size in dwords */
 425                 rb_bufsz = order_base_2(ring->ring_size / 4);
 426                 rb_cntl = rb_bufsz << 1;
 427 #ifdef __BIG_ENDIAN
 428                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 429                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 430 #endif
 431                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 432
 433                 /* Initialize the ring buffer's read and write pointers */
 434                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 435                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 436
 437                 /* set the wb address whether it's enabled or not */
 438                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 439                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 440                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 441                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 442
 443                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 444
 445                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 446                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 447
 448                 ring->wptr = 0;
 449                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 450
 451                 /* enable DMA RB */
 452                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 453                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 454
 455                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 456 #ifdef __BIG_ENDIAN
 457                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 458 #endif
 459                 /* enable DMA IBs */
 460                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 461
 462                 ring->ready = true;
 463
 464                 r = amdgpu_ring_test_ring(ring);
 465                 if (r) {
 466                         ring->ready = false;
 467                         return r;
 468                 }
 469
 470                 if (adev->mman.buffer_funcs_ring == ring)
 471                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 472         }
 473
 474         return 0;
 475 }
 476
 477 /**
 478  * cik_sdma_rlc_resume - setup and start the async dma engines
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * Set up the compute DMA queues and enable them (CIK).
 483  * Returns 0 for success, error for failure.
 484  */
 485 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 486 {
 487         /* XXX todo */
 488         return 0;
 489 }
 490
 491 /**
 492  * cik_sdma_load_microcode - load the sDMA ME ucode
 493  *
 494  * @adev: amdgpu_device pointer
 495  *
 496  * Loads the sDMA0/1 ucode.
 497  * Returns 0 for success, -EINVAL if the ucode is not available.
 498  */
 499 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 500 {
 501         const struct sdma_firmware_header_v1_0 *hdr;
 502         const __le32 *fw_data;
 503         u32 fw_size;
 504         int i, j;
 505
 506         /* halt the MEs */
 507         cik_sdma_enable(adev, false);
 508
 509         for (i = 0; i < adev->sdma.num_instances; i++) {
 510                 if (!adev->sdma.instance[i].fw)
 511                         return -EINVAL;
 512                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 513                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 514                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 515                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 516                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 517                 if (adev->sdma.instance[i].feature_version >= 20)
 518                         adev->sdma.instance[i].burst_nop = true;
 519                 fw_data = (const __le32 *)
 520                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 521                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 522                 for (j = 0; j < fw_size; j++)
 523                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 524                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 525         }
 526
 527         return 0;
 528 }
 529
 530 /**
 531  * cik_sdma_start - setup and start the async dma engines
 532  *
 533  * @adev: amdgpu_device pointer
 534  *
 535  * Set up the DMA engines and enable them (CIK).
 536  * Returns 0 for success, error for failure.
 537  */
 538 static int cik_sdma_start(struct amdgpu_device *adev)
 539 {
 540         int r;
 541
 542         r = cik_sdma_load_microcode(adev);
 543         if (r)
 544                 return r;
 545
 546         /* unhalt the MEs */
 547         cik_sdma_enable(adev, true);
 548
 549         /* start the gfx rings and rlc compute queues */
 550         r = cik_sdma_gfx_resume(adev);
 551         if (r)
 552                 return r;
 553         r = cik_sdma_rlc_resume(adev);
 554         if (r)
 555                 return r;
 556
 557         return 0;
 558 }
 559
 560 /**
 561  * cik_sdma_ring_test_ring - simple async dma engine test
 562  *
 563  * @ring: amdgpu_ring structure holding ring information
 564  *
 565  * Test the DMA engine by writing using it to write an
 566  * value to memory. (CIK).
 567  * Returns 0 for success, error for failure.
 568  */
 569 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 570 {
 571         struct amdgpu_device *adev = ring->adev;
 572         unsigned i;
 573         unsigned index;
 574         int r;
 575         u32 tmp;
 576         u64 gpu_addr;
 577
 578         r = amdgpu_wb_get(adev, &index);
 579         if (r) {
 580                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 581                 return r;
 582         }
 583
 584         gpu_addr = adev->wb.gpu_addr + (index * 4);
 585         tmp = 0xCAFEDEAD;
 586         adev->wb.wb[index] = cpu_to_le32(tmp);
 587
 588         r = amdgpu_ring_lock(ring, 5);
 589         if (r) {
 590                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 591                 amdgpu_wb_free(adev, index);
 592                 return r;
 593         }
 594         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 595         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 596         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 597         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 598         amdgpu_ring_write(ring, 0xDEADBEEF);
 599         amdgpu_ring_unlock_commit(ring);
 600
 601         for (i = 0; i < adev->usec_timeout; i++) {
 602                 tmp = le32_to_cpu(adev->wb.wb[index]);
 603                 if (tmp == 0xDEADBEEF)
 604                         break;
 605                 DRM_UDELAY(1);
 606         }
 607
 608         if (i < adev->usec_timeout) {
 609                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 610         } else {
 611                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 612                           ring->idx, tmp);
 613                 r = -EINVAL;
 614         }
 615         amdgpu_wb_free(adev, index);
 616
 617         return r;
 618 }
 619
 620 /**
 621  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 622  *
 623  * @ring: amdgpu_ring structure holding ring information
 624  *
 625  * Test a simple IB in the DMA ring (CIK).
 626  * Returns 0 on success, error on failure.
 627  */
 628 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 629 {
 630         struct amdgpu_device *adev = ring->adev;
 631         struct amdgpu_ib ib;
 632         struct fence *f = NULL;
 633         unsigned i;
 634         unsigned index;
 635         int r;
 636         u32 tmp = 0;
 637         u64 gpu_addr;
 638
 639         r = amdgpu_wb_get(adev, &index);
 640         if (r) {
 641                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 642                 return r;
 643         }
 644
 645         gpu_addr = adev->wb.gpu_addr + (index * 4);
 646         tmp = 0xCAFEDEAD;
 647         adev->wb.wb[index] = cpu_to_le32(tmp);
 648         memset(&ib, 0, sizeof(ib));
 649         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 650         if (r) {
 651                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 652                 goto err0;
 653         }
 654
 655         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 656         ib.ptr[1] = lower_32_bits(gpu_addr);
 657         ib.ptr[2] = upper_32_bits(gpu_addr);
 658         ib.ptr[3] = 1;
 659         ib.ptr[4] = 0xDEADBEEF;
 660         ib.length_dw = 5;
 661         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 662                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 663                                                  &f);
 664         if (r)
 665                 goto err1;
 666
 667         r = fence_wait(f, false);
 668         if (r) {
 669                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 670                 goto err1;
 671         }
 672         for (i = 0; i < adev->usec_timeout; i++) {
 673                 tmp = le32_to_cpu(adev->wb.wb[index]);
 674                 if (tmp == 0xDEADBEEF)
 675                         break;
 676                 DRM_UDELAY(1);
 677         }
 678         if (i < adev->usec_timeout) {
 679                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 680                          ring->idx, i);
 681                 goto err1;
 682         } else {
 683                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 684                 r = -EINVAL;
 685         }
 686
 687 err1:
 688         fence_put(f);
 689         amdgpu_ib_free(adev, &ib);
 690 err0:
 691         amdgpu_wb_free(adev, index);
 692         return r;
 693 }
 694
 695 /**
 696  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 697  *
 698  * @ib: indirect buffer to fill with commands
 699  * @pe: addr of the page entry
 700  * @src: src addr to copy from
 701  * @count: number of page entries to update
 702  *
 703  * Update PTEs by copying them from the GART using sDMA (CIK).
 704  */
 705 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 706                                  uint64_t pe, uint64_t src,
 707                                  unsigned count)
 708 {
 709         while (count) {
 710                 unsigned bytes = count * 8;
 711                 if (bytes > 0x1FFFF8)
 712                         bytes = 0x1FFFF8;
 713
 714                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 715                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 716                 ib->ptr[ib->length_dw++] = bytes;
 717                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 718                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 719                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 720                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 721                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 722
 723                 pe += bytes;
 724                 src += bytes;
 725                 count -= bytes / 8;
 726         }
 727 }
 728
 729 /**
 730  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 731  *
 732  * @ib: indirect buffer to fill with commands
 733  * @pe: addr of the page entry
 734  * @addr: dst addr to write into pe
 735  * @count: number of page entries to update
 736  * @incr: increase next addr by incr bytes
 737  * @flags: access flags
 738  *
 739  * Update PTEs by writing them manually using sDMA (CIK).
 740  */
 741 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 742                                   uint64_t pe,
 743                                   uint64_t addr, unsigned count,
 744                                   uint32_t incr, uint32_t flags)
 745 {
 746         uint64_t value;
 747         unsigned ndw;
 748
 749         while (count) {
 750                 ndw = count * 2;
 751                 if (ndw > 0xFFFFE)
 752                         ndw = 0xFFFFE;
 753
 754                 /* for non-physically contiguous pages (system) */
 755                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 756                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 757                 ib->ptr[ib->length_dw++] = pe;
 758                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 759                 ib->ptr[ib->length_dw++] = ndw;
 760                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 761                         if (flags & AMDGPU_PTE_SYSTEM) {
 762                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 763                                 value &= 0xFFFFFFFFFFFFF000ULL;
 764                         } else if (flags & AMDGPU_PTE_VALID) {
 765                                 value = addr;
 766                         } else {
 767                                 value = 0;
 768                         }
 769                         addr += incr;
 770                         value |= flags;
 771                         ib->ptr[ib->length_dw++] = value;
 772                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 773                 }
 774         }
 775 }
 776
 777 /**
 778  * cik_sdma_vm_set_pages - update the page tables using sDMA
 779  *
 780  * @ib: indirect buffer to fill with commands
 781  * @pe: addr of the page entry
 782  * @addr: dst addr to write into pe
 783  * @count: number of page entries to update
 784  * @incr: increase next addr by incr bytes
 785  * @flags: access flags
 786  *
 787  * Update the page tables using sDMA (CIK).
 788  */
 789 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 790                                     uint64_t pe,
 791                                     uint64_t addr, unsigned count,
 792                                     uint32_t incr, uint32_t flags)
 793 {
 794         uint64_t value;
 795         unsigned ndw;
 796
 797         while (count) {
 798                 ndw = count;
 799                 if (ndw > 0x7FFFF)
 800                         ndw = 0x7FFFF;
 801
 802                 if (flags & AMDGPU_PTE_VALID)
 803                         value = addr;
 804                 else
 805                         value = 0;
 806
 807                 /* for physically contiguous pages (vram) */
 808                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 809                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 810                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 811                 ib->ptr[ib->length_dw++] = flags; /* mask */
 812                 ib->ptr[ib->length_dw++] = 0;
 813                 ib->ptr[ib->length_dw++] = value; /* value */
 814                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 815                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 816                 ib->ptr[ib->length_dw++] = 0;
 817                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 818
 819                 pe += ndw * 8;
 820                 addr += ndw * incr;
 821                 count -= ndw;
 822         }
 823 }
 824
 825 /**
 826  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 827  *
 828  * @ib: indirect buffer to fill with padding
 829  *
 830  */
 831 static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
 832 {
 833         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
 834         u32 pad_count;
 835         int i;
 836
 837         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 838         for (i = 0; i < pad_count; i++)
 839                 if (sdma && sdma->burst_nop && (i == 0))
 840                         ib->ptr[ib->length_dw++] =
 841                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 842                                         SDMA_NOP_COUNT(pad_count - 1);
 843                 else
 844                         ib->ptr[ib->length_dw++] =
 845                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 846 }
 847
 848 /**
 849  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 850  *
 851  * @ring: amdgpu_ring pointer
 852  * @vm: amdgpu_vm pointer
 853  *
 854  * Update the page table base and flush the VM TLB
 855  * using sDMA (CIK).
 856  */
 857 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 858                                         unsigned vm_id, uint64_t pd_addr)
 859 {
 860         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 861                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 862
 863         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 864         if (vm_id < 8) {
 865                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 866         } else {
 867                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 868         }
 869         amdgpu_ring_write(ring, pd_addr >> 12);
 870
 871         /* flush TLB */
 872         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 873         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 874         amdgpu_ring_write(ring, 1 << vm_id);
 875
 876         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 877         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 878         amdgpu_ring_write(ring, 0);
 879         amdgpu_ring_write(ring, 0); /* reference */
 880         amdgpu_ring_write(ring, 0); /* mask */
 881         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 882 }
 883
 884 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 885                                  bool enable)
 886 {
 887         u32 orig, data;
 888
 889         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
 890                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 891                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 892         } else {
 893                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 894                 data |= 0xff000000;
 895                 if (data != orig)
 896                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 897
 898                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 899                 data |= 0xff000000;
 900                 if (data != orig)
 901                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 902         }
 903 }
 904
 905 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 906                                  bool enable)
 907 {
 908         u32 orig, data;
 909
 910         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
 911                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 912                 data |= 0x100;
 913                 if (orig != data)
 914                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 915
 916                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 917                 data |= 0x100;
 918                 if (orig != data)
 919                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 920         } else {
 921                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 922                 data &= ~0x100;
 923                 if (orig != data)
 924                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 925
 926                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 927                 data &= ~0x100;
 928                 if (orig != data)
 929                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 930         }
 931 }
 932
 933 static int cik_sdma_early_init(void *handle)
 934 {
 935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 936
 937         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 938
 939         cik_sdma_set_ring_funcs(adev);
 940         cik_sdma_set_irq_funcs(adev);
 941         cik_sdma_set_buffer_funcs(adev);
 942         cik_sdma_set_vm_pte_funcs(adev);
 943
 944         return 0;
 945 }
 946
 947 static int cik_sdma_sw_init(void *handle)
 948 {
 949         struct amdgpu_ring *ring;
 950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 951         int r, i;
 952
 953         r = cik_sdma_init_microcode(adev);
 954         if (r) {
 955                 DRM_ERROR("Failed to load sdma firmware!\n");
 956                 return r;
 957         }
 958
 959         /* SDMA trap event */
 960         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 961         if (r)
 962                 return r;
 963
 964         /* SDMA Privileged inst */
 965         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 966         if (r)
 967                 return r;
 968
 969         /* SDMA Privileged inst */
 970         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 971         if (r)
 972                 return r;
 973
 974         for (i = 0; i < adev->sdma.num_instances; i++) {
 975                 ring = &adev->sdma.instance[i].ring;
 976                 ring->ring_obj = NULL;
 977                 sprintf(ring->name, "sdma%d", i);
 978                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 979                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 980                                      &adev->sdma.trap_irq,
 981                                      (i == 0) ?
 982                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 983                                      AMDGPU_RING_TYPE_SDMA);
 984                 if (r)
 985                         return r;
 986         }
 987
 988         return r;
 989 }
 990
 991 static int cik_sdma_sw_fini(void *handle)
 992 {
 993         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 994         int i;
 995
 996         for (i = 0; i < adev->sdma.num_instances; i++)
 997                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 998
 999         return 0;
1000 }
1001
1002 static int cik_sdma_hw_init(void *handle)
1003 {
1004         int r;
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006
1007         r = cik_sdma_start(adev);
1008         if (r)
1009                 return r;
1010
1011         return r;
1012 }
1013
1014 static int cik_sdma_hw_fini(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018         cik_sdma_enable(adev, false);
1019
1020         return 0;
1021 }
1022
1023 static int cik_sdma_suspend(void *handle)
1024 {
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         return cik_sdma_hw_fini(adev);
1028 }
1029
1030 static int cik_sdma_resume(void *handle)
1031 {
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034         cik_sdma_soft_reset(handle);
1035
1036         return cik_sdma_hw_init(adev);
1037 }
1038
1039 static bool cik_sdma_is_idle(void *handle)
1040 {
1041         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042         u32 tmp = RREG32(mmSRBM_STATUS2);
1043
1044         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1045                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1046             return false;
1047
1048         return true;
1049 }
1050
1051 static int cik_sdma_wait_for_idle(void *handle)
1052 {
1053         unsigned i;
1054         u32 tmp;
1055         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056
1057         for (i = 0; i < adev->usec_timeout; i++) {
1058                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1059                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1060
1061                 if (!tmp)
1062                         return 0;
1063                 udelay(1);
1064         }
1065         return -ETIMEDOUT;
1066 }
1067
1068 static void cik_sdma_print_status(void *handle)
1069 {
1070         int i, j;
1071         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072
1073         dev_info(adev->dev, "CIK SDMA registers\n");
1074         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1075                  RREG32(mmSRBM_STATUS2));
1076         for (i = 0; i < adev->sdma.num_instances; i++) {
1077                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1078                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1079                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
1080                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1081                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1082                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1083                 dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1084                          i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1085                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1086                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1087                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1088                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1089                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1090                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1091                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1092                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1093                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1094                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1095                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1096                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1097                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1098                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1099                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1100                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1101                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1102                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1103                 mutex_lock(&adev->srbm_mutex);
1104                 for (j = 0; j < 16; j++) {
1105                         cik_srbm_select(adev, 0, 0, 0, j);
1106                         dev_info(adev->dev, "  VM %d:\n", j);
1107                         dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1108                                  RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1109                         dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
1110                                  RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1111                 }
1112                 cik_srbm_select(adev, 0, 0, 0, 0);
1113                 mutex_unlock(&adev->srbm_mutex);
1114         }
1115 }
1116
1117 static int cik_sdma_soft_reset(void *handle)
1118 {
1119         u32 srbm_soft_reset = 0;
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121         u32 tmp = RREG32(mmSRBM_STATUS2);
1122
1123         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1124                 /* sdma0 */
1125                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1126                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1127                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1128                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1129         }
1130         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1131                 /* sdma1 */
1132                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1133                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1134                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1135                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1136         }
1137
1138         if (srbm_soft_reset) {
1139                 cik_sdma_print_status((void *)adev);
1140
1141                 tmp = RREG32(mmSRBM_SOFT_RESET);
1142                 tmp |= srbm_soft_reset;
1143                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1144                 WREG32(mmSRBM_SOFT_RESET, tmp);
1145                 tmp = RREG32(mmSRBM_SOFT_RESET);
1146
1147                 udelay(50);
1148
1149                 tmp &= ~srbm_soft_reset;
1150                 WREG32(mmSRBM_SOFT_RESET, tmp);
1151                 tmp = RREG32(mmSRBM_SOFT_RESET);
1152
1153                 /* Wait a little for things to settle down */
1154                 udelay(50);
1155
1156                 cik_sdma_print_status((void *)adev);
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1163                                        struct amdgpu_irq_src *src,
1164                                        unsigned type,
1165                                        enum amdgpu_interrupt_state state)
1166 {
1167         u32 sdma_cntl;
1168
1169         switch (type) {
1170         case AMDGPU_SDMA_IRQ_TRAP0:
1171                 switch (state) {
1172                 case AMDGPU_IRQ_STATE_DISABLE:
1173                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1174                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1175                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1176                         break;
1177                 case AMDGPU_IRQ_STATE_ENABLE:
1178                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1179                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1180                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1181                         break;
1182                 default:
1183                         break;
1184                 }
1185                 break;
1186         case AMDGPU_SDMA_IRQ_TRAP1:
1187                 switch (state) {
1188                 case AMDGPU_IRQ_STATE_DISABLE:
1189                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1190                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1191                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1192                         break;
1193                 case AMDGPU_IRQ_STATE_ENABLE:
1194                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1195                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1196                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1197                         break;
1198                 default:
1199                         break;
1200                 }
1201                 break;
1202         default:
1203                 break;
1204         }
1205         return 0;
1206 }
1207
1208 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1209                                      struct amdgpu_irq_src *source,
1210                                      struct amdgpu_iv_entry *entry)
1211 {
1212         u8 instance_id, queue_id;
1213
1214         instance_id = (entry->ring_id & 0x3) >> 0;
1215         queue_id = (entry->ring_id & 0xc) >> 2;
1216         DRM_DEBUG("IH: SDMA trap\n");
1217         switch (instance_id) {
1218         case 0:
1219                 switch (queue_id) {
1220                 case 0:
1221                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1222                         break;
1223                 case 1:
1224                         /* XXX compute */
1225                         break;
1226                 case 2:
1227                         /* XXX compute */
1228                         break;
1229                 }
1230                 break;
1231         case 1:
1232                 switch (queue_id) {
1233                 case 0:
1234                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1235                         break;
1236                 case 1:
1237                         /* XXX compute */
1238                         break;
1239                 case 2:
1240                         /* XXX compute */
1241                         break;
1242                 }
1243                 break;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1250                                              struct amdgpu_irq_src *source,
1251                                              struct amdgpu_iv_entry *entry)
1252 {
1253         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1254         schedule_work(&adev->reset_work);
1255         return 0;
1256 }
1257
1258 static int cik_sdma_set_clockgating_state(void *handle,
1259                                           enum amd_clockgating_state state)
1260 {
1261         bool gate = false;
1262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263
1264         if (state == AMD_CG_STATE_GATE)
1265                 gate = true;
1266
1267         cik_enable_sdma_mgcg(adev, gate);
1268         cik_enable_sdma_mgls(adev, gate);
1269
1270         return 0;
1271 }
1272
1273 static int cik_sdma_set_powergating_state(void *handle,
1274                                           enum amd_powergating_state state)
1275 {
1276         return 0;
1277 }
1278
1279 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1280         .early_init = cik_sdma_early_init,
1281         .late_init = NULL,
1282         .sw_init = cik_sdma_sw_init,
1283         .sw_fini = cik_sdma_sw_fini,
1284         .hw_init = cik_sdma_hw_init,
1285         .hw_fini = cik_sdma_hw_fini,
1286         .suspend = cik_sdma_suspend,
1287         .resume = cik_sdma_resume,
1288         .is_idle = cik_sdma_is_idle,
1289         .wait_for_idle = cik_sdma_wait_for_idle,
1290         .soft_reset = cik_sdma_soft_reset,
1291         .print_status = cik_sdma_print_status,
1292         .set_clockgating_state = cik_sdma_set_clockgating_state,
1293         .set_powergating_state = cik_sdma_set_powergating_state,
1294 };
1295
1296 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1297         .get_rptr = cik_sdma_ring_get_rptr,
1298         .get_wptr = cik_sdma_ring_get_wptr,
1299         .set_wptr = cik_sdma_ring_set_wptr,
1300         .parse_cs = NULL,
1301         .emit_ib = cik_sdma_ring_emit_ib,
1302         .emit_fence = cik_sdma_ring_emit_fence,
1303         .emit_semaphore = cik_sdma_ring_emit_semaphore,
1304         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1305         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1306         .test_ring = cik_sdma_ring_test_ring,
1307         .test_ib = cik_sdma_ring_test_ib,
1308         .insert_nop = cik_sdma_ring_insert_nop,
1309 };
1310
1311 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1312 {
1313         int i;
1314
1315         for (i = 0; i < adev->sdma.num_instances; i++)
1316                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1317 }
1318
1319 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1320         .set = cik_sdma_set_trap_irq_state,
1321         .process = cik_sdma_process_trap_irq,
1322 };
1323
1324 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1325         .process = cik_sdma_process_illegal_inst_irq,
1326 };
1327
1328 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1329 {
1330         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1331         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1332         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1333 }
1334
1335 /**
1336  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1337  *
1338  * @ring: amdgpu_ring structure holding ring information
1339  * @src_offset: src GPU address
1340  * @dst_offset: dst GPU address
1341  * @byte_count: number of bytes to xfer
1342  *
1343  * Copy GPU buffers using the DMA engine (CIK).
1344  * Used by the amdgpu ttm implementation to move pages if
1345  * registered as the asic copy callback.
1346  */
1347 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1348                                       uint64_t src_offset,
1349                                       uint64_t dst_offset,
1350                                       uint32_t byte_count)
1351 {
1352         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1353         ib->ptr[ib->length_dw++] = byte_count;
1354         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1355         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1356         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1357         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1358         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1359 }
1360
1361 /**
1362  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1363  *
1364  * @ring: amdgpu_ring structure holding ring information
1365  * @src_data: value to write to buffer
1366  * @dst_offset: dst GPU address
1367  * @byte_count: number of bytes to xfer
1368  *
1369  * Fill GPU buffers using the DMA engine (CIK).
1370  */
1371 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1372                                       uint32_t src_data,
1373                                       uint64_t dst_offset,
1374                                       uint32_t byte_count)
1375 {
1376         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1377         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1378         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1379         ib->ptr[ib->length_dw++] = src_data;
1380         ib->ptr[ib->length_dw++] = byte_count;
1381 }
1382
1383 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1384         .copy_max_bytes = 0x1fffff,
1385         .copy_num_dw = 7,
1386         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1387
1388         .fill_max_bytes = 0x1fffff,
1389         .fill_num_dw = 5,
1390         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1391 };
1392
1393 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1394 {
1395         if (adev->mman.buffer_funcs == NULL) {
1396                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1397                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1398         }
1399 }
1400
1401 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1402         .copy_pte = cik_sdma_vm_copy_pte,
1403         .write_pte = cik_sdma_vm_write_pte,
1404         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1405         .pad_ib = cik_sdma_vm_pad_ib,
1406 };
1407
1408 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1409 {
1410         if (adev->vm_manager.vm_pte_funcs == NULL) {
1411                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1412                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1413                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1414         }
1415 }