kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #ifdef CONFIG_DRM_AMDGPU_CIK
  42 #include "cik.h"
  43 #endif
  44 #include "vi.h"
  45 #include "bif/bif_4_1_d.h"
  46
  47 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  49
  50 static const char *amdgpu_asic_name[] = {
  51         "BONAIRE",
  52         "KAVERI",
  53         "KABINI",
  54         "HAWAII",
  55         "MULLINS",
  56         "TOPAZ",
  57         "TONGA",
  58         "FIJI",
  59         "CARRIZO",
  60         "STONEY",
  61         "LAST",
  62 };
  63
  64 bool amdgpu_device_is_px(struct drm_device *dev)
  65 {
  66         struct amdgpu_device *adev = dev->dev_private;
  67
  68         if (adev->flags & AMD_IS_PX)
  69                 return true;
  70         return false;
  71 }
  72
  73 /*
  74  * MMIO register access helper functions.
  75  */
  76 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  77                         bool always_indirect)
  78 {
  79         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  80                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  81         else {
  82                 unsigned long flags;
  83                 uint32_t ret;
  84
  85                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  86                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  87                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  88                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  89
  90                 return ret;
  91         }
  92 }
  93
  94 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  95                     bool always_indirect)
  96 {
  97         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  98                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  99         else {
 100                 unsigned long flags;
 101
 102                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 103                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 104                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 105                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 106         }
 107 }
 108
 109 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 110 {
 111         if ((reg * 4) < adev->rio_mem_size)
 112                 return ioread32(adev->rio_mem + (reg * 4));
 113         else {
 114                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 115                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 116         }
 117 }
 118
 119 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 120 {
 121
 122         if ((reg * 4) < adev->rio_mem_size)
 123                 iowrite32(v, adev->rio_mem + (reg * 4));
 124         else {
 125                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 126                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 127         }
 128 }
 129
 130 /**
 131  * amdgpu_mm_rdoorbell - read a doorbell dword
 132  *
 133  * @adev: amdgpu_device pointer
 134  * @index: doorbell index
 135  *
 136  * Returns the value in the doorbell aperture at the
 137  * requested doorbell index (CIK).
 138  */
 139 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 140 {
 141         if (index < adev->doorbell.num_doorbells) {
 142                 return readl(adev->doorbell.ptr + index);
 143         } else {
 144                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 145                 return 0;
 146         }
 147 }
 148
 149 /**
 150  * amdgpu_mm_wdoorbell - write a doorbell dword
 151  *
 152  * @adev: amdgpu_device pointer
 153  * @index: doorbell index
 154  * @v: value to write
 155  *
 156  * Writes @v to the doorbell aperture at the
 157  * requested doorbell index (CIK).
 158  */
 159 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 160 {
 161         if (index < adev->doorbell.num_doorbells) {
 162                 writel(v, adev->doorbell.ptr + index);
 163         } else {
 164                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 165         }
 166 }
 167
 168 /**
 169  * amdgpu_invalid_rreg - dummy reg read function
 170  *
 171  * @adev: amdgpu device pointer
 172  * @reg: offset of register
 173  *
 174  * Dummy register read function.  Used for register blocks
 175  * that certain asics don't have (all asics).
 176  * Returns the value in the register.
 177  */
 178 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 179 {
 180         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 181         BUG();
 182         return 0;
 183 }
 184
 185 /**
 186  * amdgpu_invalid_wreg - dummy reg write function
 187  *
 188  * @adev: amdgpu device pointer
 189  * @reg: offset of register
 190  * @v: value to write to the register
 191  *
 192  * Dummy register read function.  Used for register blocks
 193  * that certain asics don't have (all asics).
 194  */
 195 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 196 {
 197         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 198                   reg, v);
 199         BUG();
 200 }
 201
 202 /**
 203  * amdgpu_block_invalid_rreg - dummy reg read function
 204  *
 205  * @adev: amdgpu device pointer
 206  * @block: offset of instance
 207  * @reg: offset of register
 208  *
 209  * Dummy register read function.  Used for register blocks
 210  * that certain asics don't have (all asics).
 211  * Returns the value in the register.
 212  */
 213 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 214                                           uint32_t block, uint32_t reg)
 215 {
 216         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 217                   reg, block);
 218         BUG();
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_block_invalid_wreg - dummy reg write function
 224  *
 225  * @adev: amdgpu device pointer
 226  * @block: offset of instance
 227  * @reg: offset of register
 228  * @v: value to write to the register
 229  *
 230  * Dummy register read function.  Used for register blocks
 231  * that certain asics don't have (all asics).
 232  */
 233 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 234                                       uint32_t block,
 235                                       uint32_t reg, uint32_t v)
 236 {
 237         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 238                   reg, block, v);
 239         BUG();
 240 }
 241
 242 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 243 {
 244         int r;
 245
 246         if (adev->vram_scratch.robj == NULL) {
 247                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 248                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 249                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 250                                      NULL, NULL, &adev->vram_scratch.robj);
 251                 if (r) {
 252                         return r;
 253                 }
 254         }
 255
 256         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 257         if (unlikely(r != 0))
 258                 return r;
 259         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 260                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 261         if (r) {
 262                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 263                 return r;
 264         }
 265         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 266                                 (void **)&adev->vram_scratch.ptr);
 267         if (r)
 268                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 269         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 270
 271         return r;
 272 }
 273
 274 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 275 {
 276         int r;
 277
 278         if (adev->vram_scratch.robj == NULL) {
 279                 return;
 280         }
 281         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 282         if (likely(r == 0)) {
 283                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 284                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 285                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 286         }
 287         amdgpu_bo_unref(&adev->vram_scratch.robj);
 288 }
 289
 290 /**
 291  * amdgpu_program_register_sequence - program an array of registers.
 292  *
 293  * @adev: amdgpu_device pointer
 294  * @registers: pointer to the register array
 295  * @array_size: size of the register array
 296  *
 297  * Programs an array or registers with and and or masks.
 298  * This is a helper for setting golden registers.
 299  */
 300 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 301                                       const u32 *registers,
 302                                       const u32 array_size)
 303 {
 304         u32 tmp, reg, and_mask, or_mask;
 305         int i;
 306
 307         if (array_size % 3)
 308                 return;
 309
 310         for (i = 0; i < array_size; i +=3) {
 311                 reg = registers[i + 0];
 312                 and_mask = registers[i + 1];
 313                 or_mask = registers[i + 2];
 314
 315                 if (and_mask == 0xffffffff) {
 316                         tmp = or_mask;
 317                 } else {
 318                         tmp = RREG32(reg);
 319                         tmp &= ~and_mask;
 320                         tmp |= or_mask;
 321                 }
 322                 WREG32(reg, tmp);
 323         }
 324 }
 325
 326 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 327 {
 328         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 329 }
 330
 331 /*
 332  * GPU doorbell aperture helpers function.
 333  */
 334 /**
 335  * amdgpu_doorbell_init - Init doorbell driver information.
 336  *
 337  * @adev: amdgpu_device pointer
 338  *
 339  * Init doorbell driver information (CIK)
 340  * Returns 0 on success, error on failure.
 341  */
 342 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 343 {
 344         /* doorbell bar mapping */
 345         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 346         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 347
 348         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 349                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 350         if (adev->doorbell.num_doorbells == 0)
 351                 return -EINVAL;
 352
 353         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 354         if (adev->doorbell.ptr == NULL) {
 355                 return -ENOMEM;
 356         }
 357         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 358         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 359
 360         return 0;
 361 }
 362
 363 /**
 364  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 365  *
 366  * @adev: amdgpu_device pointer
 367  *
 368  * Tear down doorbell driver information (CIK)
 369  */
 370 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 371 {
 372         iounmap(adev->doorbell.ptr);
 373         adev->doorbell.ptr = NULL;
 374 }
 375
 376 /**
 377  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 378  *                                setup amdkfd
 379  *
 380  * @adev: amdgpu_device pointer
 381  * @aperture_base: output returning doorbell aperture base physical address
 382  * @aperture_size: output returning doorbell aperture size in bytes
 383  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 384  *
 385  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 386  * takes doorbells required for its own rings and reports the setup to amdkfd.
 387  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 388  */
 389 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 390                                 phys_addr_t *aperture_base,
 391                                 size_t *aperture_size,
 392                                 size_t *start_offset)
 393 {
 394         /*
 395          * The first num_doorbells are used by amdgpu.
 396          * amdkfd takes whatever's left in the aperture.
 397          */
 398         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 399                 *aperture_base = adev->doorbell.base;
 400                 *aperture_size = adev->doorbell.size;
 401                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 402         } else {
 403                 *aperture_base = 0;
 404                 *aperture_size = 0;
 405                 *start_offset = 0;
 406         }
 407 }
 408
 409 /*
 410  * amdgpu_wb_*()
 411  * Writeback is the the method by which the the GPU updates special pages
 412  * in memory with the status of certain GPU events (fences, ring pointers,
 413  * etc.).
 414  */
 415
 416 /**
 417  * amdgpu_wb_fini - Disable Writeback and free memory
 418  *
 419  * @adev: amdgpu_device pointer
 420  *
 421  * Disables Writeback and frees the Writeback memory (all asics).
 422  * Used at driver shutdown.
 423  */
 424 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 425 {
 426         if (adev->wb.wb_obj) {
 427                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 428                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 429                         amdgpu_bo_unpin(adev->wb.wb_obj);
 430                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 431                 }
 432                 amdgpu_bo_unref(&adev->wb.wb_obj);
 433                 adev->wb.wb = NULL;
 434                 adev->wb.wb_obj = NULL;
 435         }
 436 }
 437
 438 /**
 439  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 440  *
 441  * @adev: amdgpu_device pointer
 442  *
 443  * Disables Writeback and frees the Writeback memory (all asics).
 444  * Used at driver startup.
 445  * Returns 0 on success or an -error on failure.
 446  */
 447 static int amdgpu_wb_init(struct amdgpu_device *adev)
 448 {
 449         int r;
 450
 451         if (adev->wb.wb_obj == NULL) {
 452                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 453                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 454                                      &adev->wb.wb_obj);
 455                 if (r) {
 456                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 457                         return r;
 458                 }
 459                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 460                 if (unlikely(r != 0)) {
 461                         amdgpu_wb_fini(adev);
 462                         return r;
 463                 }
 464                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 465                                 &adev->wb.gpu_addr);
 466                 if (r) {
 467                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 468                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 469                         amdgpu_wb_fini(adev);
 470                         return r;
 471                 }
 472                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 473                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 474                 if (r) {
 475                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 476                         amdgpu_wb_fini(adev);
 477                         return r;
 478                 }
 479
 480                 adev->wb.num_wb = AMDGPU_MAX_WB;
 481                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 482
 483                 /* clear wb memory */
 484                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 485         }
 486
 487         return 0;
 488 }
 489
 490 /**
 491  * amdgpu_wb_get - Allocate a wb entry
 492  *
 493  * @adev: amdgpu_device pointer
 494  * @wb: wb index
 495  *
 496  * Allocate a wb slot for use by the driver (all asics).
 497  * Returns 0 on success or -EINVAL on failure.
 498  */
 499 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 500 {
 501         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 502         if (offset < adev->wb.num_wb) {
 503                 __set_bit(offset, adev->wb.used);
 504                 *wb = offset;
 505                 return 0;
 506         } else {
 507                 return -EINVAL;
 508         }
 509 }
 510
 511 /**
 512  * amdgpu_wb_free - Free a wb entry
 513  *
 514  * @adev: amdgpu_device pointer
 515  * @wb: wb index
 516  *
 517  * Free a wb slot allocated for use by the driver (all asics)
 518  */
 519 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 520 {
 521         if (wb < adev->wb.num_wb)
 522                 __clear_bit(wb, adev->wb.used);
 523 }
 524
 525 /**
 526  * amdgpu_vram_location - try to find VRAM location
 527  * @adev: amdgpu device structure holding all necessary informations
 528  * @mc: memory controller structure holding memory informations
 529  * @base: base address at which to put VRAM
 530  *
 531  * Function will place try to place VRAM at base address provided
 532  * as parameter (which is so far either PCI aperture address or
 533  * for IGP TOM base address).
 534  *
 535  * If there is not enough space to fit the unvisible VRAM in the 32bits
 536  * address space then we limit the VRAM size to the aperture.
 537  *
 538  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 539  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 540  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 541  * not IGP.
 542  *
 543  * Note: we use mc_vram_size as on some board we need to program the mc to
 544  * cover the whole aperture even if VRAM size is inferior to aperture size
 545  * Novell bug 204882 + along with lots of ubuntu ones
 546  *
 547  * Note: when limiting vram it's safe to overwritte real_vram_size because
 548  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 549  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 550  * ones)
 551  *
 552  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 553  * explicitly check for that thought.
 554  *
 555  * FIXME: when reducing VRAM size align new size on power of 2.
 556  */
 557 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 558 {
 559         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 560
 561         mc->vram_start = base;
 562         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 563                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 564                 mc->real_vram_size = mc->aper_size;
 565                 mc->mc_vram_size = mc->aper_size;
 566         }
 567         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 568         if (limit && limit < mc->real_vram_size)
 569                 mc->real_vram_size = limit;
 570         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 571                         mc->mc_vram_size >> 20, mc->vram_start,
 572                         mc->vram_end, mc->real_vram_size >> 20);
 573 }
 574
 575 /**
 576  * amdgpu_gtt_location - try to find GTT location
 577  * @adev: amdgpu device structure holding all necessary informations
 578  * @mc: memory controller structure holding memory informations
 579  *
 580  * Function will place try to place GTT before or after VRAM.
 581  *
 582  * If GTT size is bigger than space left then we ajust GTT size.
 583  * Thus function will never fails.
 584  *
 585  * FIXME: when reducing GTT size align new size on power of 2.
 586  */
 587 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 588 {
 589         u64 size_af, size_bf;
 590
 591         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 592         size_bf = mc->vram_start & ~mc->gtt_base_align;
 593         if (size_bf > size_af) {
 594                 if (mc->gtt_size > size_bf) {
 595                         dev_warn(adev->dev, "limiting GTT\n");
 596                         mc->gtt_size = size_bf;
 597                 }
 598                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 599         } else {
 600                 if (mc->gtt_size > size_af) {
 601                         dev_warn(adev->dev, "limiting GTT\n");
 602                         mc->gtt_size = size_af;
 603                 }
 604                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 605         }
 606         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 607         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 608                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 609 }
 610
 611 /*
 612  * GPU helpers function.
 613  */
 614 /**
 615  * amdgpu_card_posted - check if the hw has already been initialized
 616  *
 617  * @adev: amdgpu_device pointer
 618  *
 619  * Check if the asic has been initialized (all asics).
 620  * Used at driver startup.
 621  * Returns true if initialized or false if not.
 622  */
 623 bool amdgpu_card_posted(struct amdgpu_device *adev)
 624 {
 625         uint32_t reg;
 626
 627         /* then check MEM_SIZE, in case the crtcs are off */
 628         reg = RREG32(mmCONFIG_MEMSIZE);
 629
 630         if (reg)
 631                 return true;
 632
 633         return false;
 634
 635 }
 636
 637 /**
 638  * amdgpu_boot_test_post_card - check and possibly initialize the hw
 639  *
 640  * @adev: amdgpu_device pointer
 641  *
 642  * Check if the asic is initialized and if not, attempt to initialize
 643  * it (all asics).
 644  * Returns true if initialized or false if not.
 645  */
 646 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
 647 {
 648         if (amdgpu_card_posted(adev))
 649                 return true;
 650
 651         if (adev->bios) {
 652                 DRM_INFO("GPU not posted. posting now...\n");
 653                 if (adev->is_atom_bios)
 654                         amdgpu_atom_asic_init(adev->mode_info.atom_context);
 655                 return true;
 656         } else {
 657                 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
 658                 return false;
 659         }
 660 }
 661
 662 /**
 663  * amdgpu_dummy_page_init - init dummy page used by the driver
 664  *
 665  * @adev: amdgpu_device pointer
 666  *
 667  * Allocate the dummy page used by the driver (all asics).
 668  * This dummy page is used by the driver as a filler for gart entries
 669  * when pages are taken out of the GART
 670  * Returns 0 on sucess, -ENOMEM on failure.
 671  */
 672 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 673 {
 674         if (adev->dummy_page.page)
 675                 return 0;
 676         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 677         if (adev->dummy_page.page == NULL)
 678                 return -ENOMEM;
 679         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 680                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 681         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 682                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 683                 __free_page(adev->dummy_page.page);
 684                 adev->dummy_page.page = NULL;
 685                 return -ENOMEM;
 686         }
 687         return 0;
 688 }
 689
 690 /**
 691  * amdgpu_dummy_page_fini - free dummy page used by the driver
 692  *
 693  * @adev: amdgpu_device pointer
 694  *
 695  * Frees the dummy page used by the driver (all asics).
 696  */
 697 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 698 {
 699         if (adev->dummy_page.page == NULL)
 700                 return;
 701         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 702                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 703         __free_page(adev->dummy_page.page);
 704         adev->dummy_page.page = NULL;
 705 }
 706
 707
 708 /* ATOM accessor methods */
 709 /*
 710  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 711  * driver registers callbacks to access registers and the interpreter
 712  * in the driver parses the tables and executes then to program specific
 713  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 714  * atombios.h, and atom.c
 715  */
 716
 717 /**
 718  * cail_pll_read - read PLL register
 719  *
 720  * @info: atom card_info pointer
 721  * @reg: PLL register offset
 722  *
 723  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 724  * Returns the value of the PLL register.
 725  */
 726 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 727 {
 728         return 0;
 729 }
 730
 731 /**
 732  * cail_pll_write - write PLL register
 733  *
 734  * @info: atom card_info pointer
 735  * @reg: PLL register offset
 736  * @val: value to write to the pll register
 737  *
 738  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 739  */
 740 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 741 {
 742
 743 }
 744
 745 /**
 746  * cail_mc_read - read MC (Memory Controller) register
 747  *
 748  * @info: atom card_info pointer
 749  * @reg: MC register offset
 750  *
 751  * Provides an MC register accessor for the atom interpreter (r4xx+).
 752  * Returns the value of the MC register.
 753  */
 754 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 755 {
 756         return 0;
 757 }
 758
 759 /**
 760  * cail_mc_write - write MC (Memory Controller) register
 761  *
 762  * @info: atom card_info pointer
 763  * @reg: MC register offset
 764  * @val: value to write to the pll register
 765  *
 766  * Provides a MC register accessor for the atom interpreter (r4xx+).
 767  */
 768 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 769 {
 770
 771 }
 772
 773 /**
 774  * cail_reg_write - write MMIO register
 775  *
 776  * @info: atom card_info pointer
 777  * @reg: MMIO register offset
 778  * @val: value to write to the pll register
 779  *
 780  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 781  */
 782 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 783 {
 784         struct amdgpu_device *adev = info->dev->dev_private;
 785
 786         WREG32(reg, val);
 787 }
 788
 789 /**
 790  * cail_reg_read - read MMIO register
 791  *
 792  * @info: atom card_info pointer
 793  * @reg: MMIO register offset
 794  *
 795  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 796  * Returns the value of the MMIO register.
 797  */
 798 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 799 {
 800         struct amdgpu_device *adev = info->dev->dev_private;
 801         uint32_t r;
 802
 803         r = RREG32(reg);
 804         return r;
 805 }
 806
 807 /**
 808  * cail_ioreg_write - write IO register
 809  *
 810  * @info: atom card_info pointer
 811  * @reg: IO register offset
 812  * @val: value to write to the pll register
 813  *
 814  * Provides a IO register accessor for the atom interpreter (r4xx+).
 815  */
 816 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 817 {
 818         struct amdgpu_device *adev = info->dev->dev_private;
 819
 820         WREG32_IO(reg, val);
 821 }
 822
 823 /**
 824  * cail_ioreg_read - read IO register
 825  *
 826  * @info: atom card_info pointer
 827  * @reg: IO register offset
 828  *
 829  * Provides an IO register accessor for the atom interpreter (r4xx+).
 830  * Returns the value of the IO register.
 831  */
 832 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 833 {
 834         struct amdgpu_device *adev = info->dev->dev_private;
 835         uint32_t r;
 836
 837         r = RREG32_IO(reg);
 838         return r;
 839 }
 840
 841 /**
 842  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 843  *
 844  * @adev: amdgpu_device pointer
 845  *
 846  * Frees the driver info and register access callbacks for the ATOM
 847  * interpreter (r4xx+).
 848  * Called at driver shutdown.
 849  */
 850 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 851 {
 852         if (adev->mode_info.atom_context)
 853                 kfree(adev->mode_info.atom_context->scratch);
 854         kfree(adev->mode_info.atom_context);
 855         adev->mode_info.atom_context = NULL;
 856         kfree(adev->mode_info.atom_card_info);
 857         adev->mode_info.atom_card_info = NULL;
 858 }
 859
 860 /**
 861  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 862  *
 863  * @adev: amdgpu_device pointer
 864  *
 865  * Initializes the driver info and register access callbacks for the
 866  * ATOM interpreter (r4xx+).
 867  * Returns 0 on sucess, -ENOMEM on failure.
 868  * Called at driver startup.
 869  */
 870 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 871 {
 872         struct card_info *atom_card_info =
 873             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 874
 875         if (!atom_card_info)
 876                 return -ENOMEM;
 877
 878         adev->mode_info.atom_card_info = atom_card_info;
 879         atom_card_info->dev = adev->ddev;
 880         atom_card_info->reg_read = cail_reg_read;
 881         atom_card_info->reg_write = cail_reg_write;
 882         /* needed for iio ops */
 883         if (adev->rio_mem) {
 884                 atom_card_info->ioreg_read = cail_ioreg_read;
 885                 atom_card_info->ioreg_write = cail_ioreg_write;
 886         } else {
 887                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 888                 atom_card_info->ioreg_read = cail_reg_read;
 889                 atom_card_info->ioreg_write = cail_reg_write;
 890         }
 891         atom_card_info->mc_read = cail_mc_read;
 892         atom_card_info->mc_write = cail_mc_write;
 893         atom_card_info->pll_read = cail_pll_read;
 894         atom_card_info->pll_write = cail_pll_write;
 895
 896         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 897         if (!adev->mode_info.atom_context) {
 898                 amdgpu_atombios_fini(adev);
 899                 return -ENOMEM;
 900         }
 901
 902         mutex_init(&adev->mode_info.atom_context->mutex);
 903         amdgpu_atombios_scratch_regs_init(adev);
 904         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 905         return 0;
 906 }
 907
 908 /* if we get transitioned to only one device, take VGA back */
 909 /**
 910  * amdgpu_vga_set_decode - enable/disable vga decode
 911  *
 912  * @cookie: amdgpu_device pointer
 913  * @state: enable/disable vga decode
 914  *
 915  * Enable/disable vga decode (all asics).
 916  * Returns VGA resource flags.
 917  */
 918 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 919 {
 920         struct amdgpu_device *adev = cookie;
 921         amdgpu_asic_set_vga_state(adev, state);
 922         if (state)
 923                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 924                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 925         else
 926                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 927 }
 928
 929 /**
 930  * amdgpu_check_pot_argument - check that argument is a power of two
 931  *
 932  * @arg: value to check
 933  *
 934  * Validates that a certain argument is a power of two (all asics).
 935  * Returns true if argument is valid.
 936  */
 937 static bool amdgpu_check_pot_argument(int arg)
 938 {
 939         return (arg & (arg - 1)) == 0;
 940 }
 941
 942 /**
 943  * amdgpu_check_arguments - validate module params
 944  *
 945  * @adev: amdgpu_device pointer
 946  *
 947  * Validates certain module parameters and updates
 948  * the associated values used by the driver (all asics).
 949  */
 950 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 951 {
 952         /* vramlimit must be a power of two */
 953         if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
 954                 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
 955                                 amdgpu_vram_limit);
 956                 amdgpu_vram_limit = 0;
 957         }
 958
 959         if (amdgpu_gart_size != -1) {
 960                 /* gtt size must be power of two and greater or equal to 32M */
 961                 if (amdgpu_gart_size < 32) {
 962                         dev_warn(adev->dev, "gart size (%d) too small\n",
 963                                  amdgpu_gart_size);
 964                         amdgpu_gart_size = -1;
 965                 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
 966                         dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
 967                                  amdgpu_gart_size);
 968                         amdgpu_gart_size = -1;
 969                 }
 970         }
 971
 972         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 973                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 974                          amdgpu_vm_size);
 975                 amdgpu_vm_size = 8;
 976         }
 977
 978         if (amdgpu_vm_size < 1) {
 979                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 980                          amdgpu_vm_size);
 981                 amdgpu_vm_size = 8;
 982         }
 983
 984         /*
 985          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 986          */
 987         if (amdgpu_vm_size > 1024) {
 988                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 989                          amdgpu_vm_size);
 990                 amdgpu_vm_size = 8;
 991         }
 992
 993         /* defines number of bits in page table versus page directory,
 994          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 995          * page table and the remaining bits are in the page directory */
 996         if (amdgpu_vm_block_size == -1) {
 997
 998                 /* Total bits covered by PD + PTs */
 999                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1000
1001                 /* Make sure the PD is 4K in size up to 8GB address space.
1002                    Above that split equal between PD and PTs */
1003                 if (amdgpu_vm_size <= 8)
1004                         amdgpu_vm_block_size = bits - 9;
1005                 else
1006                         amdgpu_vm_block_size = (bits + 3) / 2;
1007
1008         } else if (amdgpu_vm_block_size < 9) {
1009                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1010                          amdgpu_vm_block_size);
1011                 amdgpu_vm_block_size = 9;
1012         }
1013
1014         if (amdgpu_vm_block_size > 24 ||
1015             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1016                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1017                          amdgpu_vm_block_size);
1018                 amdgpu_vm_block_size = 9;
1019         }
1020 }
1021
1022 /**
1023  * amdgpu_switcheroo_set_state - set switcheroo state
1024  *
1025  * @pdev: pci dev pointer
1026  * @state: vga_switcheroo state
1027  *
1028  * Callback for the switcheroo driver.  Suspends or resumes the
1029  * the asics before or after it is powered up using ACPI methods.
1030  */
1031 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1032 {
1033         struct drm_device *dev = pci_get_drvdata(pdev);
1034
1035         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1036                 return;
1037
1038         if (state == VGA_SWITCHEROO_ON) {
1039                 unsigned d3_delay = dev->pdev->d3_delay;
1040
1041                 printk(KERN_INFO "amdgpu: switched on\n");
1042                 /* don't suspend or resume card normally */
1043                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1044
1045                 amdgpu_resume_kms(dev, true, true);
1046
1047                 dev->pdev->d3_delay = d3_delay;
1048
1049                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1050                 drm_kms_helper_poll_enable(dev);
1051         } else {
1052                 printk(KERN_INFO "amdgpu: switched off\n");
1053                 drm_kms_helper_poll_disable(dev);
1054                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1055                 amdgpu_suspend_kms(dev, true, true);
1056                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1057         }
1058 }
1059
1060 /**
1061  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1062  *
1063  * @pdev: pci dev pointer
1064  *
1065  * Callback for the switcheroo driver.  Check of the switcheroo
1066  * state can be changed.
1067  * Returns true if the state can be changed, false if not.
1068  */
1069 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1070 {
1071         struct drm_device *dev = pci_get_drvdata(pdev);
1072
1073         /*
1074         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1075         * locking inversion with the driver load path. And the access here is
1076         * completely racy anyway. So don't bother with locking for now.
1077         */
1078         return dev->open_count == 0;
1079 }
1080
1081 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1082         .set_gpu_state = amdgpu_switcheroo_set_state,
1083         .reprobe = NULL,
1084         .can_switch = amdgpu_switcheroo_can_switch,
1085 };
1086
1087 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1088                                   enum amd_ip_block_type block_type,
1089                                   enum amd_clockgating_state state)
1090 {
1091         int i, r = 0;
1092
1093         for (i = 0; i < adev->num_ip_blocks; i++) {
1094                 if (adev->ip_blocks[i].type == block_type) {
1095                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1096                                                                             state);
1097                         if (r)
1098                                 return r;
1099                 }
1100         }
1101         return r;
1102 }
1103
1104 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1105                                   enum amd_ip_block_type block_type,
1106                                   enum amd_powergating_state state)
1107 {
1108         int i, r = 0;
1109
1110         for (i = 0; i < adev->num_ip_blocks; i++) {
1111                 if (adev->ip_blocks[i].type == block_type) {
1112                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1113                                                                             state);
1114                         if (r)
1115                                 return r;
1116                 }
1117         }
1118         return r;
1119 }
1120
1121 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1122                                         struct amdgpu_device *adev,
1123                                         enum amd_ip_block_type type)
1124 {
1125         int i;
1126
1127         for (i = 0; i < adev->num_ip_blocks; i++)
1128                 if (adev->ip_blocks[i].type == type)
1129                         return &adev->ip_blocks[i];
1130
1131         return NULL;
1132 }
1133
1134 /**
1135  * amdgpu_ip_block_version_cmp
1136  *
1137  * @adev: amdgpu_device pointer
1138  * @type: enum amd_ip_block_type
1139  * @major: major version
1140  * @minor: minor version
1141  *
1142  * return 0 if equal or greater
1143  * return 1 if smaller or the ip_block doesn't exist
1144  */
1145 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1146                                 enum amd_ip_block_type type,
1147                                 u32 major, u32 minor)
1148 {
1149         const struct amdgpu_ip_block_version *ip_block;
1150         ip_block = amdgpu_get_ip_block(adev, type);
1151
1152         if (ip_block && ((ip_block->major > major) ||
1153                         ((ip_block->major == major) &&
1154                         (ip_block->minor >= minor))))
1155                 return 0;
1156
1157         return 1;
1158 }
1159
1160 static int amdgpu_early_init(struct amdgpu_device *adev)
1161 {
1162         int i, r;
1163
1164         switch (adev->asic_type) {
1165         case CHIP_TOPAZ:
1166         case CHIP_TONGA:
1167         case CHIP_FIJI:
1168         case CHIP_CARRIZO:
1169         case CHIP_STONEY:
1170                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1171                         adev->family = AMDGPU_FAMILY_CZ;
1172                 else
1173                         adev->family = AMDGPU_FAMILY_VI;
1174
1175                 r = vi_set_ip_blocks(adev);
1176                 if (r)
1177                         return r;
1178                 break;
1179 #ifdef CONFIG_DRM_AMDGPU_CIK
1180         case CHIP_BONAIRE:
1181         case CHIP_HAWAII:
1182         case CHIP_KAVERI:
1183         case CHIP_KABINI:
1184         case CHIP_MULLINS:
1185                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1186                         adev->family = AMDGPU_FAMILY_CI;
1187                 else
1188                         adev->family = AMDGPU_FAMILY_KV;
1189
1190                 r = cik_set_ip_blocks(adev);
1191                 if (r)
1192                         return r;
1193                 break;
1194 #endif
1195         default:
1196                 /* FIXME: not supported yet */
1197                 return -EINVAL;
1198         }
1199
1200         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1201                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1202         if (adev->ip_block_status == NULL)
1203                 return -ENOMEM;
1204
1205         if (adev->ip_blocks == NULL) {
1206                 DRM_ERROR("No IP blocks found!\n");
1207                 return r;
1208         }
1209
1210         for (i = 0; i < adev->num_ip_blocks; i++) {
1211                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1212                         DRM_ERROR("disabled ip block: %d\n", i);
1213                         adev->ip_block_status[i].valid = false;
1214                 } else {
1215                         if (adev->ip_blocks[i].funcs->early_init) {
1216                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1217                                 if (r == -ENOENT)
1218                                         adev->ip_block_status[i].valid = false;
1219                                 else if (r)
1220                                         return r;
1221                                 else
1222                                         adev->ip_block_status[i].valid = true;
1223                         } else {
1224                                 adev->ip_block_status[i].valid = true;
1225                         }
1226                 }
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int amdgpu_init(struct amdgpu_device *adev)
1233 {
1234         int i, r;
1235
1236         for (i = 0; i < adev->num_ip_blocks; i++) {
1237                 if (!adev->ip_block_status[i].valid)
1238                         continue;
1239                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1240                 if (r)
1241                         return r;
1242                 adev->ip_block_status[i].sw = true;
1243                 /* need to do gmc hw init early so we can allocate gpu mem */
1244                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1245                         r = amdgpu_vram_scratch_init(adev);
1246                         if (r)
1247                                 return r;
1248                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1249                         if (r)
1250                                 return r;
1251                         r = amdgpu_wb_init(adev);
1252                         if (r)
1253                                 return r;
1254                         adev->ip_block_status[i].hw = true;
1255                 }
1256         }
1257
1258         for (i = 0; i < adev->num_ip_blocks; i++) {
1259                 if (!adev->ip_block_status[i].sw)
1260                         continue;
1261                 /* gmc hw init is done early */
1262                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1263                         continue;
1264                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1265                 if (r)
1266                         return r;
1267                 adev->ip_block_status[i].hw = true;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static int amdgpu_late_init(struct amdgpu_device *adev)
1274 {
1275         int i = 0, r;
1276
1277         for (i = 0; i < adev->num_ip_blocks; i++) {
1278                 if (!adev->ip_block_status[i].valid)
1279                         continue;
1280                 /* enable clockgating to save power */
1281                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1282                                                                     AMD_CG_STATE_GATE);
1283                 if (r)
1284                         return r;
1285                 if (adev->ip_blocks[i].funcs->late_init) {
1286                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1287                         if (r)
1288                                 return r;
1289                 }
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int amdgpu_fini(struct amdgpu_device *adev)
1296 {
1297         int i, r;
1298
1299         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1300                 if (!adev->ip_block_status[i].hw)
1301                         continue;
1302                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1303                         amdgpu_wb_fini(adev);
1304                         amdgpu_vram_scratch_fini(adev);
1305                 }
1306                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1307                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1308                                                                     AMD_CG_STATE_UNGATE);
1309                 if (r)
1310                         return r;
1311                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1312                 /* XXX handle errors */
1313                 adev->ip_block_status[i].hw = false;
1314         }
1315
1316         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1317                 if (!adev->ip_block_status[i].sw)
1318                         continue;
1319                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1320                 /* XXX handle errors */
1321                 adev->ip_block_status[i].sw = false;
1322                 adev->ip_block_status[i].valid = false;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int amdgpu_suspend(struct amdgpu_device *adev)
1329 {
1330         int i, r;
1331
1332         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1333                 if (!adev->ip_block_status[i].valid)
1334                         continue;
1335                 /* ungate blocks so that suspend can properly shut them down */
1336                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1337                                                                     AMD_CG_STATE_UNGATE);
1338                 /* XXX handle errors */
1339                 r = adev->ip_blocks[i].funcs->suspend(adev);
1340                 /* XXX handle errors */
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int amdgpu_resume(struct amdgpu_device *adev)
1347 {
1348         int i, r;
1349
1350         for (i = 0; i < adev->num_ip_blocks; i++) {
1351                 if (!adev->ip_block_status[i].valid)
1352                         continue;
1353                 r = adev->ip_blocks[i].funcs->resume(adev);
1354                 if (r)
1355                         return r;
1356         }
1357
1358         return 0;
1359 }
1360
1361 /**
1362  * amdgpu_device_init - initialize the driver
1363  *
1364  * @adev: amdgpu_device pointer
1365  * @pdev: drm dev pointer
1366  * @pdev: pci dev pointer
1367  * @flags: driver flags
1368  *
1369  * Initializes the driver info and hw (all asics).
1370  * Returns 0 for success or an error on failure.
1371  * Called at driver startup.
1372  */
1373 int amdgpu_device_init(struct amdgpu_device *adev,
1374                        struct drm_device *ddev,
1375                        struct pci_dev *pdev,
1376                        uint32_t flags)
1377 {
1378         int r, i;
1379         bool runtime = false;
1380
1381         adev->shutdown = false;
1382         adev->dev = &pdev->dev;
1383         adev->ddev = ddev;
1384         adev->pdev = pdev;
1385         adev->flags = flags;
1386         adev->asic_type = flags & AMD_ASIC_MASK;
1387         adev->is_atom_bios = false;
1388         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1389         adev->mc.gtt_size = 512 * 1024 * 1024;
1390         adev->accel_working = false;
1391         adev->num_rings = 0;
1392         adev->mman.buffer_funcs = NULL;
1393         adev->mman.buffer_funcs_ring = NULL;
1394         adev->vm_manager.vm_pte_funcs = NULL;
1395         adev->vm_manager.vm_pte_funcs_ring = NULL;
1396         adev->gart.gart_funcs = NULL;
1397         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1398
1399         adev->smc_rreg = &amdgpu_invalid_rreg;
1400         adev->smc_wreg = &amdgpu_invalid_wreg;
1401         adev->pcie_rreg = &amdgpu_invalid_rreg;
1402         adev->pcie_wreg = &amdgpu_invalid_wreg;
1403         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1404         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1405         adev->didt_rreg = &amdgpu_invalid_rreg;
1406         adev->didt_wreg = &amdgpu_invalid_wreg;
1407         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1408         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1409
1410         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1411                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1412                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1413
1414         /* mutex initialization are all done here so we
1415          * can recall function without having locking issues */
1416         mutex_init(&adev->ring_lock);
1417         atomic_set(&adev->irq.ih.lock, 0);
1418         mutex_init(&adev->gem.mutex);
1419         mutex_init(&adev->pm.mutex);
1420         mutex_init(&adev->gfx.gpu_clock_mutex);
1421         mutex_init(&adev->srbm_mutex);
1422         mutex_init(&adev->grbm_idx_mutex);
1423         mutex_init(&adev->mn_lock);
1424         hash_init(adev->mn_hash);
1425
1426         amdgpu_check_arguments(adev);
1427
1428         /* Registers mapping */
1429         /* TODO: block userspace mapping of io register */
1430         spin_lock_init(&adev->mmio_idx_lock);
1431         spin_lock_init(&adev->smc_idx_lock);
1432         spin_lock_init(&adev->pcie_idx_lock);
1433         spin_lock_init(&adev->uvd_ctx_idx_lock);
1434         spin_lock_init(&adev->didt_idx_lock);
1435         spin_lock_init(&adev->audio_endpt_idx_lock);
1436
1437         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1438         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1439         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1440         if (adev->rmmio == NULL) {
1441                 return -ENOMEM;
1442         }
1443         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1444         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1445
1446         /* doorbell bar mapping */
1447         amdgpu_doorbell_init(adev);
1448
1449         /* io port mapping */
1450         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1451                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1452                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1453                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1454                         break;
1455                 }
1456         }
1457         if (adev->rio_mem == NULL)
1458                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1459
1460         /* early init functions */
1461         r = amdgpu_early_init(adev);
1462         if (r)
1463                 return r;
1464
1465         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1466         /* this will fail for cards that aren't VGA class devices, just
1467          * ignore it */
1468         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1469
1470         if (amdgpu_runtime_pm == 1)
1471                 runtime = true;
1472         if (amdgpu_device_is_px(ddev))
1473                 runtime = true;
1474         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1475         if (runtime)
1476                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1477
1478         /* Read BIOS */
1479         if (!amdgpu_get_bios(adev))
1480                 return -EINVAL;
1481         /* Must be an ATOMBIOS */
1482         if (!adev->is_atom_bios) {
1483                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1484                 return -EINVAL;
1485         }
1486         r = amdgpu_atombios_init(adev);
1487         if (r)
1488                 return r;
1489
1490         /* Post card if necessary */
1491         if (!amdgpu_card_posted(adev)) {
1492                 if (!adev->bios) {
1493                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1494                         return -EINVAL;
1495                 }
1496                 DRM_INFO("GPU not posted. posting now...\n");
1497                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1498         }
1499
1500         /* Initialize clocks */
1501         r = amdgpu_atombios_get_clock_info(adev);
1502         if (r)
1503                 return r;
1504         /* init i2c buses */
1505         amdgpu_atombios_i2c_init(adev);
1506
1507         /* Fence driver */
1508         r = amdgpu_fence_driver_init(adev);
1509         if (r)
1510                 return r;
1511
1512         /* init the mode config */
1513         drm_mode_config_init(adev->ddev);
1514
1515         r = amdgpu_init(adev);
1516         if (r) {
1517                 amdgpu_fini(adev);
1518                 return r;
1519         }
1520
1521         adev->accel_working = true;
1522
1523         amdgpu_fbdev_init(adev);
1524
1525         r = amdgpu_ib_pool_init(adev);
1526         if (r) {
1527                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1528                 return r;
1529         }
1530
1531         r = amdgpu_ctx_init(adev, true, &adev->kernel_ctx);
1532         if (r) {
1533                 dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
1534                 return r;
1535         }
1536         r = amdgpu_ib_ring_tests(adev);
1537         if (r)
1538                 DRM_ERROR("ib ring test failed (%d).\n", r);
1539
1540         r = amdgpu_gem_debugfs_init(adev);
1541         if (r) {
1542                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1543         }
1544
1545         r = amdgpu_debugfs_regs_init(adev);
1546         if (r) {
1547                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1548         }
1549
1550         if ((amdgpu_testing & 1)) {
1551                 if (adev->accel_working)
1552                         amdgpu_test_moves(adev);
1553                 else
1554                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1555         }
1556         if ((amdgpu_testing & 2)) {
1557                 if (adev->accel_working)
1558                         amdgpu_test_syncing(adev);
1559                 else
1560                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1561         }
1562         if (amdgpu_benchmarking) {
1563                 if (adev->accel_working)
1564                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1565                 else
1566                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1567         }
1568
1569         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1570          * explicit gating rather than handling it automatically.
1571          */
1572         r = amdgpu_late_init(adev);
1573         if (r)
1574                 return r;
1575
1576         return 0;
1577 }
1578
1579 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1580
1581 /**
1582  * amdgpu_device_fini - tear down the driver
1583  *
1584  * @adev: amdgpu_device pointer
1585  *
1586  * Tear down the driver info (all asics).
1587  * Called at driver shutdown.
1588  */
1589 void amdgpu_device_fini(struct amdgpu_device *adev)
1590 {
1591         int r;
1592
1593         DRM_INFO("amdgpu: finishing device.\n");
1594         adev->shutdown = true;
1595         /* evict vram memory */
1596         amdgpu_bo_evict_vram(adev);
1597         amdgpu_ctx_fini(&adev->kernel_ctx);
1598         amdgpu_ib_pool_fini(adev);
1599         amdgpu_fence_driver_fini(adev);
1600         amdgpu_fbdev_fini(adev);
1601         r = amdgpu_fini(adev);
1602         kfree(adev->ip_block_status);
1603         adev->ip_block_status = NULL;
1604         adev->accel_working = false;
1605         /* free i2c buses */
1606         amdgpu_i2c_fini(adev);
1607         amdgpu_atombios_fini(adev);
1608         kfree(adev->bios);
1609         adev->bios = NULL;
1610         vga_switcheroo_unregister_client(adev->pdev);
1611         vga_client_register(adev->pdev, NULL, NULL, NULL);
1612         if (adev->rio_mem)
1613                 pci_iounmap(adev->pdev, adev->rio_mem);
1614         adev->rio_mem = NULL;
1615         iounmap(adev->rmmio);
1616         adev->rmmio = NULL;
1617         amdgpu_doorbell_fini(adev);
1618         amdgpu_debugfs_regs_cleanup(adev);
1619         amdgpu_debugfs_remove_files(adev);
1620 }
1621
1622
1623 /*
1624  * Suspend & resume.
1625  */
1626 /**
1627  * amdgpu_suspend_kms - initiate device suspend
1628  *
1629  * @pdev: drm dev pointer
1630  * @state: suspend state
1631  *
1632  * Puts the hw in the suspend state (all asics).
1633  * Returns 0 for success or an error on failure.
1634  * Called at driver suspend.
1635  */
1636 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1637 {
1638         struct amdgpu_device *adev;
1639         struct drm_crtc *crtc;
1640         struct drm_connector *connector;
1641         int r;
1642
1643         if (dev == NULL || dev->dev_private == NULL) {
1644                 return -ENODEV;
1645         }
1646
1647         adev = dev->dev_private;
1648
1649         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1650                 return 0;
1651
1652         drm_kms_helper_poll_disable(dev);
1653
1654         /* turn off display hw */
1655         drm_modeset_lock_all(dev);
1656         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1657                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1658         }
1659         drm_modeset_unlock_all(dev);
1660
1661         /* unpin the front buffers and cursors */
1662         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1663                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1664                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1665                 struct amdgpu_bo *robj;
1666
1667                 if (amdgpu_crtc->cursor_bo) {
1668                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1669                         r = amdgpu_bo_reserve(aobj, false);
1670                         if (r == 0) {
1671                                 amdgpu_bo_unpin(aobj);
1672                                 amdgpu_bo_unreserve(aobj);
1673                         }
1674                 }
1675
1676                 if (rfb == NULL || rfb->obj == NULL) {
1677                         continue;
1678                 }
1679                 robj = gem_to_amdgpu_bo(rfb->obj);
1680                 /* don't unpin kernel fb objects */
1681                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1682                         r = amdgpu_bo_reserve(robj, false);
1683                         if (r == 0) {
1684                                 amdgpu_bo_unpin(robj);
1685                                 amdgpu_bo_unreserve(robj);
1686                         }
1687                 }
1688         }
1689         /* evict vram memory */
1690         amdgpu_bo_evict_vram(adev);
1691
1692         amdgpu_fence_driver_suspend(adev);
1693
1694         r = amdgpu_suspend(adev);
1695
1696         /* evict remaining vram memory */
1697         amdgpu_bo_evict_vram(adev);
1698
1699         pci_save_state(dev->pdev);
1700         if (suspend) {
1701                 /* Shut down the device */
1702                 pci_disable_device(dev->pdev);
1703                 pci_set_power_state(dev->pdev, PCI_D3hot);
1704         }
1705
1706         if (fbcon) {
1707                 console_lock();
1708                 amdgpu_fbdev_set_suspend(adev, 1);
1709                 console_unlock();
1710         }
1711         return 0;
1712 }
1713
1714 /**
1715  * amdgpu_resume_kms - initiate device resume
1716  *
1717  * @pdev: drm dev pointer
1718  *
1719  * Bring the hw back to operating state (all asics).
1720  * Returns 0 for success or an error on failure.
1721  * Called at driver resume.
1722  */
1723 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1724 {
1725         struct drm_connector *connector;
1726         struct amdgpu_device *adev = dev->dev_private;
1727         struct drm_crtc *crtc;
1728         int r;
1729
1730         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1731                 return 0;
1732
1733         if (fbcon) {
1734                 console_lock();
1735         }
1736         if (resume) {
1737                 pci_set_power_state(dev->pdev, PCI_D0);
1738                 pci_restore_state(dev->pdev);
1739                 if (pci_enable_device(dev->pdev)) {
1740                         if (fbcon)
1741                                 console_unlock();
1742                         return -1;
1743                 }
1744         }
1745
1746         /* post card */
1747         if (!amdgpu_card_posted(adev))
1748                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1749
1750         r = amdgpu_resume(adev);
1751         if (r)
1752                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1753
1754         amdgpu_fence_driver_resume(adev);
1755
1756         if (resume) {
1757                 r = amdgpu_ib_ring_tests(adev);
1758                 if (r)
1759                         DRM_ERROR("ib ring test failed (%d).\n", r);
1760         }
1761
1762         r = amdgpu_late_init(adev);
1763         if (r)
1764                 return r;
1765
1766         /* pin cursors */
1767         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1768                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1769
1770                 if (amdgpu_crtc->cursor_bo) {
1771                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1772                         r = amdgpu_bo_reserve(aobj, false);
1773                         if (r == 0) {
1774                                 r = amdgpu_bo_pin(aobj,
1775                                                   AMDGPU_GEM_DOMAIN_VRAM,
1776                                                   &amdgpu_crtc->cursor_addr);
1777                                 if (r != 0)
1778                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1779                                 amdgpu_bo_unreserve(aobj);
1780                         }
1781                 }
1782         }
1783
1784         /* blat the mode back in */
1785         if (fbcon) {
1786                 drm_helper_resume_force_mode(dev);
1787                 /* turn on display hw */
1788                 drm_modeset_lock_all(dev);
1789                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1790                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1791                 }
1792                 drm_modeset_unlock_all(dev);
1793         }
1794
1795         drm_kms_helper_poll_enable(dev);
1796         drm_helper_hpd_irq_event(dev);
1797
1798         if (fbcon) {
1799                 amdgpu_fbdev_set_suspend(adev, 0);
1800                 console_unlock();
1801         }
1802
1803         return 0;
1804 }
1805
1806 /**
1807  * amdgpu_gpu_reset - reset the asic
1808  *
1809  * @adev: amdgpu device pointer
1810  *
1811  * Attempt the reset the GPU if it has hung (all asics).
1812  * Returns 0 for success or an error on failure.
1813  */
1814 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1815 {
1816         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1817         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1818
1819         bool saved = false;
1820
1821         int i, r;
1822         int resched;
1823
1824         atomic_inc(&adev->gpu_reset_counter);
1825
1826         /* block TTM */
1827         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1828
1829         r = amdgpu_suspend(adev);
1830
1831         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1832                 struct amdgpu_ring *ring = adev->rings[i];
1833                 if (!ring)
1834                         continue;
1835
1836                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1837                 if (ring_sizes[i]) {
1838                         saved = true;
1839                         dev_info(adev->dev, "Saved %d dwords of commands "
1840                                  "on ring %d.\n", ring_sizes[i], i);
1841                 }
1842         }
1843
1844 retry:
1845         r = amdgpu_asic_reset(adev);
1846         if (!r) {
1847                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1848                 r = amdgpu_resume(adev);
1849         }
1850
1851         if (!r) {
1852                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1853                         struct amdgpu_ring *ring = adev->rings[i];
1854                         if (!ring)
1855                                 continue;
1856
1857                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1858                         ring_sizes[i] = 0;
1859                         ring_data[i] = NULL;
1860                 }
1861
1862                 r = amdgpu_ib_ring_tests(adev);
1863                 if (r) {
1864                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1865                         if (saved) {
1866                                 saved = false;
1867                                 r = amdgpu_suspend(adev);
1868                                 goto retry;
1869                         }
1870                 }
1871         } else {
1872                 amdgpu_fence_driver_force_completion(adev);
1873                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1874                         if (adev->rings[i])
1875                                 kfree(ring_data[i]);
1876                 }
1877         }
1878
1879         drm_helper_resume_force_mode(adev->ddev);
1880
1881         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1882         if (r) {
1883                 /* bad news, how to tell it to userspace ? */
1884                 dev_info(adev->dev, "GPU reset failed\n");
1885         }
1886
1887         return r;
1888 }
1889
1890
1891 /*
1892  * Debugfs
1893  */
1894 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1895                              struct drm_info_list *files,
1896                              unsigned nfiles)
1897 {
1898         unsigned i;
1899
1900         for (i = 0; i < adev->debugfs_count; i++) {
1901                 if (adev->debugfs[i].files == files) {
1902                         /* Already registered */
1903                         return 0;
1904                 }
1905         }
1906
1907         i = adev->debugfs_count + 1;
1908         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
1909                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1910                 DRM_ERROR("Report so we increase "
1911                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1912                 return -EINVAL;
1913         }
1914         adev->debugfs[adev->debugfs_count].files = files;
1915         adev->debugfs[adev->debugfs_count].num_files = nfiles;
1916         adev->debugfs_count = i;
1917 #if defined(CONFIG_DEBUG_FS)
1918         drm_debugfs_create_files(files, nfiles,
1919                                  adev->ddev->control->debugfs_root,
1920                                  adev->ddev->control);
1921         drm_debugfs_create_files(files, nfiles,
1922                                  adev->ddev->primary->debugfs_root,
1923                                  adev->ddev->primary);
1924 #endif
1925         return 0;
1926 }
1927
1928 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
1929 {
1930 #if defined(CONFIG_DEBUG_FS)
1931         unsigned i;
1932
1933         for (i = 0; i < adev->debugfs_count; i++) {
1934                 drm_debugfs_remove_files(adev->debugfs[i].files,
1935                                          adev->debugfs[i].num_files,
1936                                          adev->ddev->control);
1937                 drm_debugfs_remove_files(adev->debugfs[i].files,
1938                                          adev->debugfs[i].num_files,
1939                                          adev->ddev->primary);
1940         }
1941 #endif
1942 }
1943
1944 #if defined(CONFIG_DEBUG_FS)
1945
1946 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
1947                                         size_t size, loff_t *pos)
1948 {
1949         struct amdgpu_device *adev = f->f_inode->i_private;
1950         ssize_t result = 0;
1951         int r;
1952
1953         if (size & 0x3 || *pos & 0x3)
1954                 return -EINVAL;
1955
1956         while (size) {
1957                 uint32_t value;
1958
1959                 if (*pos > adev->rmmio_size)
1960                         return result;
1961
1962                 value = RREG32(*pos >> 2);
1963                 r = put_user(value, (uint32_t *)buf);
1964                 if (r)
1965                         return r;
1966
1967                 result += 4;
1968                 buf += 4;
1969                 *pos += 4;
1970                 size -= 4;
1971         }
1972
1973         return result;
1974 }
1975
1976 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
1977                                          size_t size, loff_t *pos)
1978 {
1979         struct amdgpu_device *adev = f->f_inode->i_private;
1980         ssize_t result = 0;
1981         int r;
1982
1983         if (size & 0x3 || *pos & 0x3)
1984                 return -EINVAL;
1985
1986         while (size) {
1987                 uint32_t value;
1988
1989                 if (*pos > adev->rmmio_size)
1990                         return result;
1991
1992                 r = get_user(value, (uint32_t *)buf);
1993                 if (r)
1994                         return r;
1995
1996                 WREG32(*pos >> 2, value);
1997
1998                 result += 4;
1999                 buf += 4;
2000                 *pos += 4;
2001                 size -= 4;
2002         }
2003
2004         return result;
2005 }
2006
2007 static const struct file_operations amdgpu_debugfs_regs_fops = {
2008         .owner = THIS_MODULE,
2009         .read = amdgpu_debugfs_regs_read,
2010         .write = amdgpu_debugfs_regs_write,
2011         .llseek = default_llseek
2012 };
2013
2014 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2015 {
2016         struct drm_minor *minor = adev->ddev->primary;
2017         struct dentry *ent, *root = minor->debugfs_root;
2018
2019         ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2020                                   adev, &amdgpu_debugfs_regs_fops);
2021         if (IS_ERR(ent))
2022                 return PTR_ERR(ent);
2023         i_size_write(ent->d_inode, adev->rmmio_size);
2024         adev->debugfs_regs = ent;
2025
2026         return 0;
2027 }
2028
2029 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2030 {
2031         debugfs_remove(adev->debugfs_regs);
2032         adev->debugfs_regs = NULL;
2033 }
2034
2035 int amdgpu_debugfs_init(struct drm_minor *minor)
2036 {
2037         return 0;
2038 }
2039
2040 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2041 {
2042 }
2043 #else
2044 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2045 {
2046         return 0;
2047 }
2048 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2049 #endif