kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev,
 238                                          uint32_t supported_device,
 239                                          int *connector_type,
 240                                          struct amdgpu_i2c_bus_rec *i2c_bus,
 241                                          uint16_t *line_mux,
 242                                          struct amdgpu_hpd *hpd)
 243 {
 244         return true;
 245 }
 246
 247 static const int object_connector_convert[] = {
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_DVII,
 250         DRM_MODE_CONNECTOR_DVII,
 251         DRM_MODE_CONNECTOR_DVID,
 252         DRM_MODE_CONNECTOR_DVID,
 253         DRM_MODE_CONNECTOR_VGA,
 254         DRM_MODE_CONNECTOR_Composite,
 255         DRM_MODE_CONNECTOR_SVIDEO,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_Unknown,
 258         DRM_MODE_CONNECTOR_9PinDIN,
 259         DRM_MODE_CONNECTOR_Unknown,
 260         DRM_MODE_CONNECTOR_HDMIA,
 261         DRM_MODE_CONNECTOR_HDMIB,
 262         DRM_MODE_CONNECTOR_LVDS,
 263         DRM_MODE_CONNECTOR_9PinDIN,
 264         DRM_MODE_CONNECTOR_Unknown,
 265         DRM_MODE_CONNECTOR_Unknown,
 266         DRM_MODE_CONNECTOR_Unknown,
 267         DRM_MODE_CONNECTOR_DisplayPort,
 268         DRM_MODE_CONNECTOR_eDP,
 269         DRM_MODE_CONNECTOR_Unknown
 270 };
 271
 272 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 273 {
 274         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 275         struct atom_context *ctx = mode_info->atom_context;
 276         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 277         u16 size, data_offset;
 278         u8 frev, crev;
 279         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 280         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 281         ATOM_OBJECT_TABLE *router_obj;
 282         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 283         ATOM_OBJECT_HEADER *obj_header;
 284         int i, j, k, path_size, device_support;
 285         int connector_type;
 286         u16 conn_id, connector_object_id;
 287         struct amdgpu_i2c_bus_rec ddc_bus;
 288         struct amdgpu_router router;
 289         struct amdgpu_gpio_rec gpio;
 290         struct amdgpu_hpd hpd;
 291
 292         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 293                 return false;
 294
 295         if (crev < 2)
 296                 return false;
 297
 298         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 299         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 300             (ctx->bios + data_offset +
 301              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 302         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 303             (ctx->bios + data_offset +
 304              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 305         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 306             (ctx->bios + data_offset +
 307              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 308         router_obj = (ATOM_OBJECT_TABLE *)
 309                 (ctx->bios + data_offset +
 310                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 311         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 312
 313         path_size = 0;
 314         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 315                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 316                 ATOM_DISPLAY_OBJECT_PATH *path;
 317                 addr += path_size;
 318                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 319                 path_size += le16_to_cpu(path->usSize);
 320
 321                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 322                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 323
 324                         con_obj_id =
 325                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 326                             >> OBJECT_ID_SHIFT;
 327                         con_obj_num =
 328                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 329                             >> ENUM_ID_SHIFT;
 330                         con_obj_type =
 331                             (le16_to_cpu(path->usConnObjectId) &
 332                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 333
 334                         /* Skip TV/CV support */
 335                         if ((le16_to_cpu(path->usDeviceTag) ==
 336                              ATOM_DEVICE_TV1_SUPPORT) ||
 337                             (le16_to_cpu(path->usDeviceTag) ==
 338                              ATOM_DEVICE_CV_SUPPORT))
 339                                 continue;
 340
 341                         if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 342                                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 343                                           con_obj_id, le16_to_cpu(path->usDeviceTag));
 344                                 continue;
 345                         }
 346
 347                         connector_type =
 348                                 object_connector_convert[con_obj_id];
 349                         connector_object_id = con_obj_id;
 350
 351                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 352                                 continue;
 353
 354                         router.ddc_valid = false;
 355                         router.cd_valid = false;
 356                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 357                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 358
 359                                 grph_obj_id =
 360                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 361                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 362                                 grph_obj_num =
 363                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 364                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 365                                 grph_obj_type =
 366                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 367                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 368
 369                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 370                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 371                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 372                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 373                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 374                                                                 (ctx->bios + data_offset +
 375                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 376                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 377                                                         u16 caps = 0;
 378
 379                                                         while (record->ucRecordSize > 0 &&
 380                                                                record->ucRecordType > 0 &&
 381                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 382                                                                 switch (record->ucRecordType) {
 383                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 384                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 385                                                                                 record;
 386                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 387                                                                         break;
 388                                                                 }
 389                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 390                                                                         ((char *)record + record->ucRecordSize);
 391                                                         }
 392                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 393                                                                                     le16_to_cpu(path->usDeviceTag),
 394                                                                                     caps);
 395                                                 }
 396                                         }
 397                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 398                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 399                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 400                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 401                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 402                                                                 (ctx->bios + data_offset +
 403                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 404                                                         ATOM_I2C_RECORD *i2c_record;
 405                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 406                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 407                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 408                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 409                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 410                                                                 (ctx->bios + data_offset +
 411                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 412                                                         u8 *num_dst_objs = (u8 *)
 413                                                                 ((u8 *)router_src_dst_table + 1 +
 414                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 415                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 416                                                         int enum_id;
 417
 418                                                         router.router_id = router_obj_id;
 419                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 420                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 421                                                                     le16_to_cpu(dst_objs[enum_id]))
 422                                                                         break;
 423                                                         }
 424
 425                                                         while (record->ucRecordSize > 0 &&
 426                                                                record->ucRecordType > 0 &&
 427                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 428                                                                 switch (record->ucRecordType) {
 429                                                                 case ATOM_I2C_RECORD_TYPE:
 430                                                                         i2c_record =
 431                                                                                 (ATOM_I2C_RECORD *)
 432                                                                                 record;
 433                                                                         i2c_config =
 434                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 435                                                                                 &i2c_record->sucI2cId;
 436                                                                         router.i2c_info =
 437                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 438                                                                                                        i2c_config->
 439                                                                                                        ucAccess);
 440                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 441                                                                         break;
 442                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 443                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 444                                                                                 record;
 445                                                                         router.ddc_valid = true;
 446                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 447                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 448                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 449                                                                         break;
 450                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 451                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 452                                                                                 record;
 453                                                                         router.cd_valid = true;
 454                                                                         router.cd_mux_type = cd_path->ucMuxType;
 455                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 456                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 457                                                                         break;
 458                                                                 }
 459                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 460                                                                         ((char *)record + record->ucRecordSize);
 461                                                         }
 462                                                 }
 463                                         }
 464                                 }
 465                         }
 466
 467                         /* look up gpio for ddc, hpd */
 468                         ddc_bus.valid = false;
 469                         hpd.hpd = AMDGPU_HPD_NONE;
 470                         if ((le16_to_cpu(path->usDeviceTag) &
 471                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 472                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 473                                         if (le16_to_cpu(path->usConnObjectId) ==
 474                                             le16_to_cpu(con_obj->asObjects[j].
 475                                                         usObjectID)) {
 476                                                 ATOM_COMMON_RECORD_HEADER
 477                                                     *record =
 478                                                     (ATOM_COMMON_RECORD_HEADER
 479                                                      *)
 480                                                     (ctx->bios + data_offset +
 481                                                      le16_to_cpu(con_obj->
 482                                                                  asObjects[j].
 483                                                                  usRecordOffset));
 484                                                 ATOM_I2C_RECORD *i2c_record;
 485                                                 ATOM_HPD_INT_RECORD *hpd_record;
 486                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 487
 488                                                 while (record->ucRecordSize > 0 &&
 489                                                        record->ucRecordType > 0 &&
 490                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 491                                                         switch (record->ucRecordType) {
 492                                                         case ATOM_I2C_RECORD_TYPE:
 493                                                                 i2c_record =
 494                                                                     (ATOM_I2C_RECORD *)
 495                                                                         record;
 496                                                                 i2c_config =
 497                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 498                                                                         &i2c_record->sucI2cId;
 499                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 500                                                                                                  i2c_config->
 501                                                                                                  ucAccess);
 502                                                                 break;
 503                                                         case ATOM_HPD_INT_RECORD_TYPE:
 504                                                                 hpd_record =
 505                                                                         (ATOM_HPD_INT_RECORD *)
 506                                                                         record;
 507                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 508                                                                                           hpd_record->ucHPDIntGPIOID);
 509                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 510                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 511                                                                 break;
 512                                                         }
 513                                                         record =
 514                                                             (ATOM_COMMON_RECORD_HEADER
 515                                                              *) ((char *)record
 516                                                                  +
 517                                                                  record->
 518                                                                  ucRecordSize);
 519                                                 }
 520                                                 break;
 521                                         }
 522                                 }
 523                         }
 524
 525                         /* needed for aux chan transactions */
 526                         ddc_bus.hpd = hpd.hpd;
 527
 528                         conn_id = le16_to_cpu(path->usConnObjectId);
 529
 530                         if (!amdgpu_atombios_apply_quirks
 531                             (adev, le16_to_cpu(path->usDeviceTag), &connector_type,
 532                              &ddc_bus, &conn_id, &hpd))
 533                                 continue;
 534
 535                         amdgpu_display_add_connector(adev,
 536                                                       conn_id,
 537                                                       le16_to_cpu(path->usDeviceTag),
 538                                                       connector_type, &ddc_bus,
 539                                                       connector_object_id,
 540                                                       &hpd,
 541                                                       &router);
 542
 543                 }
 544         }
 545
 546         amdgpu_link_encoder_connector(adev->ddev);
 547
 548         return true;
 549 }
 550
 551 union firmware_info {
 552         ATOM_FIRMWARE_INFO info;
 553         ATOM_FIRMWARE_INFO_V1_2 info_12;
 554         ATOM_FIRMWARE_INFO_V1_3 info_13;
 555         ATOM_FIRMWARE_INFO_V1_4 info_14;
 556         ATOM_FIRMWARE_INFO_V2_1 info_21;
 557         ATOM_FIRMWARE_INFO_V2_2 info_22;
 558 };
 559
 560 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 561 {
 562         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 563         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 564         uint8_t frev, crev;
 565         uint16_t data_offset;
 566         int ret = -EINVAL;
 567
 568         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 569                                    &frev, &crev, &data_offset)) {
 570                 int i;
 571                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 572                 struct amdgpu_pll *spll = &adev->clock.spll;
 573                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 574                 union firmware_info *firmware_info =
 575                         (union firmware_info *)(mode_info->atom_context->bios +
 576                                                 data_offset);
 577                 /* pixel clocks */
 578                 ppll->reference_freq =
 579                     le16_to_cpu(firmware_info->info.usReferenceClock);
 580                 ppll->reference_div = 0;
 581
 582                 ppll->pll_out_min =
 583                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 584                 ppll->pll_out_max =
 585                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 586
 587                 ppll->lcd_pll_out_min =
 588                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 589                 if (ppll->lcd_pll_out_min == 0)
 590                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 591                 ppll->lcd_pll_out_max =
 592                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 593                 if (ppll->lcd_pll_out_max == 0)
 594                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 595
 596                 if (ppll->pll_out_min == 0)
 597                         ppll->pll_out_min = 64800;
 598
 599                 ppll->pll_in_min =
 600                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 601                 ppll->pll_in_max =
 602                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 603
 604                 ppll->min_post_div = 2;
 605                 ppll->max_post_div = 0x7f;
 606                 ppll->min_frac_feedback_div = 0;
 607                 ppll->max_frac_feedback_div = 9;
 608                 ppll->min_ref_div = 2;
 609                 ppll->max_ref_div = 0x3ff;
 610                 ppll->min_feedback_div = 4;
 611                 ppll->max_feedback_div = 0xfff;
 612                 ppll->best_vco = 0;
 613
 614                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 615                         adev->clock.ppll[i] = *ppll;
 616
 617                 /* system clock */
 618                 spll->reference_freq =
 619                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 620                 spll->reference_div = 0;
 621
 622                 spll->pll_out_min =
 623                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 624                 spll->pll_out_max =
 625                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 626
 627                 /* ??? */
 628                 if (spll->pll_out_min == 0)
 629                         spll->pll_out_min = 64800;
 630
 631                 spll->pll_in_min =
 632                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 633                 spll->pll_in_max =
 634                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 635
 636                 spll->min_post_div = 1;
 637                 spll->max_post_div = 1;
 638                 spll->min_ref_div = 2;
 639                 spll->max_ref_div = 0xff;
 640                 spll->min_feedback_div = 4;
 641                 spll->max_feedback_div = 0xff;
 642                 spll->best_vco = 0;
 643
 644                 /* memory clock */
 645                 mpll->reference_freq =
 646                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 647                 mpll->reference_div = 0;
 648
 649                 mpll->pll_out_min =
 650                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 651                 mpll->pll_out_max =
 652                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 653
 654                 /* ??? */
 655                 if (mpll->pll_out_min == 0)
 656                         mpll->pll_out_min = 64800;
 657
 658                 mpll->pll_in_min =
 659                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 660                 mpll->pll_in_max =
 661                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 662
 663                 adev->clock.default_sclk =
 664                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 665                 adev->clock.default_mclk =
 666                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 667
 668                 mpll->min_post_div = 1;
 669                 mpll->max_post_div = 1;
 670                 mpll->min_ref_div = 2;
 671                 mpll->max_ref_div = 0xff;
 672                 mpll->min_feedback_div = 4;
 673                 mpll->max_feedback_div = 0xff;
 674                 mpll->best_vco = 0;
 675
 676                 /* disp clock */
 677                 adev->clock.default_dispclk =
 678                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 679                 /* set a reasonable default for DP */
 680                 if (adev->clock.default_dispclk < 53900) {
 681                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 682                                  adev->clock.default_dispclk / 100);
 683                         adev->clock.default_dispclk = 60000;
 684                 }
 685                 adev->clock.dp_extclk =
 686                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 687                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 688
 689                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 690                 if (adev->clock.max_pixel_clock == 0)
 691                         adev->clock.max_pixel_clock = 40000;
 692
 693                 /* not technically a clock, but... */
 694                 adev->mode_info.firmware_flags =
 695                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 696
 697                 ret = 0;
 698         }
 699
 700         adev->pm.current_sclk = adev->clock.default_sclk;
 701         adev->pm.current_mclk = adev->clock.default_mclk;
 702
 703         return ret;
 704 }
 705
 706 union igp_info {
 707         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 708         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 709         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 710         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 711         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 712         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 713 };
 714
 715 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 716                                                  struct amdgpu_atom_ss *ss,
 717                                                  int id)
 718 {
 719         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 720         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 721         u16 data_offset, size;
 722         union igp_info *igp_info;
 723         u8 frev, crev;
 724         u16 percentage = 0, rate = 0;
 725
 726         /* get any igp specific overrides */
 727         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 728                                    &frev, &crev, &data_offset)) {
 729                 igp_info = (union igp_info *)
 730                         (mode_info->atom_context->bios + data_offset);
 731                 switch (crev) {
 732                 case 6:
 733                         switch (id) {
 734                         case ASIC_INTERNAL_SS_ON_TMDS:
 735                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 736                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 737                                 break;
 738                         case ASIC_INTERNAL_SS_ON_HDMI:
 739                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 740                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 741                                 break;
 742                         case ASIC_INTERNAL_SS_ON_LVDS:
 743                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 744                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 745                                 break;
 746                         }
 747                         break;
 748                 case 7:
 749                         switch (id) {
 750                         case ASIC_INTERNAL_SS_ON_TMDS:
 751                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 752                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 753                                 break;
 754                         case ASIC_INTERNAL_SS_ON_HDMI:
 755                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 756                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 757                                 break;
 758                         case ASIC_INTERNAL_SS_ON_LVDS:
 759                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 760                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 761                                 break;
 762                         }
 763                         break;
 764                 case 8:
 765                         switch (id) {
 766                         case ASIC_INTERNAL_SS_ON_TMDS:
 767                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 768                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 769                                 break;
 770                         case ASIC_INTERNAL_SS_ON_HDMI:
 771                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 772                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 773                                 break;
 774                         case ASIC_INTERNAL_SS_ON_LVDS:
 775                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 776                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 777                                 break;
 778                         }
 779                         break;
 780                 case 9:
 781                         switch (id) {
 782                         case ASIC_INTERNAL_SS_ON_TMDS:
 783                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 784                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 785                                 break;
 786                         case ASIC_INTERNAL_SS_ON_HDMI:
 787                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 788                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 789                                 break;
 790                         case ASIC_INTERNAL_SS_ON_LVDS:
 791                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 792                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 793                                 break;
 794                         }
 795                         break;
 796                 default:
 797                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 798                         break;
 799                 }
 800                 if (percentage)
 801                         ss->percentage = percentage;
 802                 if (rate)
 803                         ss->rate = rate;
 804         }
 805 }
 806
 807 union asic_ss_info {
 808         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 809         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 810         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 811 };
 812
 813 union asic_ss_assignment {
 814         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 815         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 816         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 817 };
 818
 819 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 820                                       struct amdgpu_atom_ss *ss,
 821                                       int id, u32 clock)
 822 {
 823         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 824         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 825         uint16_t data_offset, size;
 826         union asic_ss_info *ss_info;
 827         union asic_ss_assignment *ss_assign;
 828         uint8_t frev, crev;
 829         int i, num_indices;
 830
 831         if (id == ASIC_INTERNAL_MEMORY_SS) {
 832                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 833                         return false;
 834         }
 835         if (id == ASIC_INTERNAL_ENGINE_SS) {
 836                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 837                         return false;
 838         }
 839
 840         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 841         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 842                                    &frev, &crev, &data_offset)) {
 843
 844                 ss_info =
 845                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 846
 847                 switch (frev) {
 848                 case 1:
 849                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 850                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 851
 852                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 853                         for (i = 0; i < num_indices; i++) {
 854                                 if ((ss_assign->v1.ucClockIndication == id) &&
 855                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 856                                         ss->percentage =
 857                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 858                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 859                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 860                                         ss->percentage_divider = 100;
 861                                         return true;
 862                                 }
 863                                 ss_assign = (union asic_ss_assignment *)
 864                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 865                         }
 866                         break;
 867                 case 2:
 868                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 869                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 870                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 871                         for (i = 0; i < num_indices; i++) {
 872                                 if ((ss_assign->v2.ucClockIndication == id) &&
 873                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 874                                         ss->percentage =
 875                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 876                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 877                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 878                                         ss->percentage_divider = 100;
 879                                         if ((crev == 2) &&
 880                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 881                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 882                                                 ss->rate /= 100;
 883                                         return true;
 884                                 }
 885                                 ss_assign = (union asic_ss_assignment *)
 886                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 887                         }
 888                         break;
 889                 case 3:
 890                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 891                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 892                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 893                         for (i = 0; i < num_indices; i++) {
 894                                 if ((ss_assign->v3.ucClockIndication == id) &&
 895                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 896                                         ss->percentage =
 897                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 898                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 899                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 900                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 901                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 902                                                 ss->percentage_divider = 1000;
 903                                         else
 904                                                 ss->percentage_divider = 100;
 905                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 906                                             (id == ASIC_INTERNAL_MEMORY_SS))
 907                                                 ss->rate /= 100;
 908                                         if (adev->flags & AMD_IS_APU)
 909                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 910                                         return true;
 911                                 }
 912                                 ss_assign = (union asic_ss_assignment *)
 913                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 914                         }
 915                         break;
 916                 default:
 917                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 918                         break;
 919                 }
 920
 921         }
 922         return false;
 923 }
 924
 925 union get_clock_dividers {
 926         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 927         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 928         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 929         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 930         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 931         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 932         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 933 };
 934
 935 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 936                                        u8 clock_type,
 937                                        u32 clock,
 938                                        bool strobe_mode,
 939                                        struct atom_clock_dividers *dividers)
 940 {
 941         union get_clock_dividers args;
 942         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 943         u8 frev, crev;
 944
 945         memset(&args, 0, sizeof(args));
 946         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 947
 948         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 949                 return -EINVAL;
 950
 951         switch (crev) {
 952         case 4:
 953                 /* fusion */
 954                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
 955
 956                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 957
 958                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
 959                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
 960                 break;
 961         case 6:
 962                 /* CI */
 963                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
 964                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
 965                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
 966
 967                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 968
 969                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
 970                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
 971                 dividers->ref_div = args.v6_out.ucPllRefDiv;
 972                 dividers->post_div = args.v6_out.ucPllPostDiv;
 973                 dividers->flags = args.v6_out.ucPllCntlFlag;
 974                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
 975                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
 976                 break;
 977         default:
 978                 return -EINVAL;
 979         }
 980         return 0;
 981 }
 982
 983 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
 984                                             u32 clock,
 985                                             bool strobe_mode,
 986                                             struct atom_mpll_param *mpll_param)
 987 {
 988         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
 989         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
 990         u8 frev, crev;
 991
 992         memset(&args, 0, sizeof(args));
 993         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
 994
 995         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 996                 return -EINVAL;
 997
 998         switch (frev) {
 999         case 2:
1000                 switch (crev) {
1001                 case 1:
1002                         /* SI */
1003                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1004                         args.ucInputFlag = 0;
1005                         if (strobe_mode)
1006                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1007
1008                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1009
1010                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1011                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1012                         mpll_param->post_div = args.ucPostDiv;
1013                         mpll_param->dll_speed = args.ucDllSpeed;
1014                         mpll_param->bwcntl = args.ucBWCntl;
1015                         mpll_param->vco_mode =
1016                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1017                         mpll_param->yclk_sel =
1018                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1019                         mpll_param->qdr =
1020                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1021                         mpll_param->half_rate =
1022                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1023                         break;
1024                 default:
1025                         return -EINVAL;
1026                 }
1027                 break;
1028         default:
1029                 return -EINVAL;
1030         }
1031         return 0;
1032 }
1033
1034 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1035 {
1036         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1037         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1038
1039         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1040         return le32_to_cpu(args.ulReturnEngineClock);
1041 }
1042
1043 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1044 {
1045         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1046         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1047
1048         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1049         return le32_to_cpu(args.ulReturnMemoryClock);
1050 }
1051
1052 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1053                                       uint32_t eng_clock)
1054 {
1055         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1056         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1057
1058         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1059
1060         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1061 }
1062
1063 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1064                                       uint32_t mem_clock)
1065 {
1066         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1067         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1068
1069         if (adev->flags & AMD_IS_APU)
1070                 return;
1071
1072         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1073
1074         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1075 }
1076
1077 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1078                                              u32 eng_clock, u32 mem_clock)
1079 {
1080         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1081         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1082         u32 tmp;
1083
1084         memset(&args, 0, sizeof(args));
1085
1086         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1087         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1088
1089         args.ulTargetEngineClock = cpu_to_le32(tmp);
1090         if (mem_clock)
1091                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1092
1093         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1094 }
1095
1096 union set_voltage {
1097         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1098         struct _SET_VOLTAGE_PARAMETERS v1;
1099         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1100         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1101 };
1102
1103 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1104                                  u16 voltage_level,
1105                                  u8 voltage_type)
1106 {
1107         union set_voltage args;
1108         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1109         u8 frev, crev, volt_index = voltage_level;
1110
1111         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1112                 return;
1113
1114         /* 0xff01 is a flag rather then an actual voltage */
1115         if (voltage_level == 0xff01)
1116                 return;
1117
1118         switch (crev) {
1119         case 1:
1120                 args.v1.ucVoltageType = voltage_type;
1121                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1122                 args.v1.ucVoltageIndex = volt_index;
1123                 break;
1124         case 2:
1125                 args.v2.ucVoltageType = voltage_type;
1126                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1127                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1128                 break;
1129         case 3:
1130                 args.v3.ucVoltageType = voltage_type;
1131                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1132                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1133                 break;
1134         default:
1135                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1136                 return;
1137         }
1138
1139         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1140 }
1141
1142 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1143                                               u16 *leakage_id)
1144 {
1145         union set_voltage args;
1146         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1147         u8 frev, crev;
1148
1149         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1150                 return -EINVAL;
1151
1152         switch (crev) {
1153         case 3:
1154         case 4:
1155                 args.v3.ucVoltageType = 0;
1156                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1157                 args.v3.usVoltageLevel = 0;
1158
1159                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1160
1161                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1162                 break;
1163         default:
1164                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1165                 return -EINVAL;
1166         }
1167
1168         return 0;
1169 }
1170
1171 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1172                                                              u16 *vddc, u16 *vddci,
1173                                                              u16 virtual_voltage_id,
1174                                                              u16 vbios_voltage_id)
1175 {
1176         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1177         u8 frev, crev;
1178         u16 data_offset, size;
1179         int i, j;
1180         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1181         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1182
1183         *vddc = 0;
1184         *vddci = 0;
1185
1186         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1187                                     &frev, &crev, &data_offset))
1188                 return -EINVAL;
1189
1190         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1191                 (adev->mode_info.atom_context->bios + data_offset);
1192
1193         switch (frev) {
1194         case 1:
1195                 return -EINVAL;
1196         case 2:
1197                 switch (crev) {
1198                 case 1:
1199                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1200                                 return -EINVAL;
1201                         leakage_bin = (u16 *)
1202                                 (adev->mode_info.atom_context->bios + data_offset +
1203                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1204                         vddc_id_buf = (u16 *)
1205                                 (adev->mode_info.atom_context->bios + data_offset +
1206                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1207                         vddc_buf = (u16 *)
1208                                 (adev->mode_info.atom_context->bios + data_offset +
1209                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1210                         vddci_id_buf = (u16 *)
1211                                 (adev->mode_info.atom_context->bios + data_offset +
1212                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1213                         vddci_buf = (u16 *)
1214                                 (adev->mode_info.atom_context->bios + data_offset +
1215                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1216
1217                         if (profile->ucElbVDDC_Num > 0) {
1218                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1219                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1220                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1221                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1222                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1223                                                                 break;
1224                                                         }
1225                                                 }
1226                                                 break;
1227                                         }
1228                                 }
1229                         }
1230                         if (profile->ucElbVDDCI_Num > 0) {
1231                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1232                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1233                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1234                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1235                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1236                                                                 break;
1237                                                         }
1238                                                 }
1239                                                 break;
1240                                         }
1241                                 }
1242                         }
1243                         break;
1244                 default:
1245                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1246                         return -EINVAL;
1247                 }
1248                 break;
1249         default:
1250                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1251                 return -EINVAL;
1252         }
1253
1254         return 0;
1255 }
1256
1257 union get_voltage_info {
1258         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1259         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1260 };
1261
1262 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1263                                     u16 virtual_voltage_id,
1264                                     u16 *voltage)
1265 {
1266         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1267         u32 entry_id;
1268         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1269         union get_voltage_info args;
1270
1271         for (entry_id = 0; entry_id < count; entry_id++) {
1272                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1273                     virtual_voltage_id)
1274                         break;
1275         }
1276
1277         if (entry_id >= count)
1278                 return -EINVAL;
1279
1280         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1281         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1282         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1283         args.in.ulSCLKFreq =
1284                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1285
1286         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1287
1288         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1289
1290         return 0;
1291 }
1292
1293 union voltage_object_info {
1294         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1295         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1296         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1297 };
1298
1299 union voltage_object {
1300         struct _ATOM_VOLTAGE_OBJECT v1;
1301         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1302         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1303 };
1304
1305
1306 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1307                                                                         u8 voltage_type, u8 voltage_mode)
1308 {
1309         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1310         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1311         u8 *start = (u8*)v3;
1312
1313         while (offset < size) {
1314                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1315                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1316                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1317                         return vo;
1318                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1319         }
1320         return NULL;
1321 }
1322
1323 bool
1324 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1325                                 u8 voltage_type, u8 voltage_mode)
1326 {
1327         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1328         u8 frev, crev;
1329         u16 data_offset, size;
1330         union voltage_object_info *voltage_info;
1331
1332         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1333                                    &frev, &crev, &data_offset)) {
1334                 voltage_info = (union voltage_object_info *)
1335                         (adev->mode_info.atom_context->bios + data_offset);
1336
1337                 switch (frev) {
1338                 case 3:
1339                         switch (crev) {
1340                         case 1:
1341                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1342                                                                   voltage_type, voltage_mode))
1343                                         return true;
1344                                 break;
1345                         default:
1346                                 DRM_ERROR("unknown voltage object table\n");
1347                                 return false;
1348                         }
1349                         break;
1350                 default:
1351                         DRM_ERROR("unknown voltage object table\n");
1352                         return false;
1353                 }
1354
1355         }
1356         return false;
1357 }
1358
1359 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1360                                       u8 voltage_type, u8 voltage_mode,
1361                                       struct atom_voltage_table *voltage_table)
1362 {
1363         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1364         u8 frev, crev;
1365         u16 data_offset, size;
1366         int i;
1367         union voltage_object_info *voltage_info;
1368         union voltage_object *voltage_object = NULL;
1369
1370         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1371                                    &frev, &crev, &data_offset)) {
1372                 voltage_info = (union voltage_object_info *)
1373                         (adev->mode_info.atom_context->bios + data_offset);
1374
1375                 switch (frev) {
1376                 case 3:
1377                         switch (crev) {
1378                         case 1:
1379                                 voltage_object = (union voltage_object *)
1380                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1381                                                                       voltage_type, voltage_mode);
1382                                 if (voltage_object) {
1383                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1384                                                 &voltage_object->v3.asGpioVoltageObj;
1385                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1386                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1387                                                 return -EINVAL;
1388                                         lut = &gpio->asVolGpioLut[0];
1389                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1390                                                 voltage_table->entries[i].value =
1391                                                         le16_to_cpu(lut->usVoltageValue);
1392                                                 voltage_table->entries[i].smio_low =
1393                                                         le32_to_cpu(lut->ulVoltageId);
1394                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1395                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1396                                         }
1397                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1398                                         voltage_table->count = gpio->ucGpioEntryNum;
1399                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1400                                         return 0;
1401                                 }
1402                                 break;
1403                         default:
1404                                 DRM_ERROR("unknown voltage object table\n");
1405                                 return -EINVAL;
1406                         }
1407                         break;
1408                 default:
1409                         DRM_ERROR("unknown voltage object table\n");
1410                         return -EINVAL;
1411                 }
1412         }
1413         return -EINVAL;
1414 }
1415
1416 union vram_info {
1417         struct _ATOM_VRAM_INFO_V3 v1_3;
1418         struct _ATOM_VRAM_INFO_V4 v1_4;
1419         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1420 };
1421
1422 #define MEM_ID_MASK           0xff000000
1423 #define MEM_ID_SHIFT          24
1424 #define CLOCK_RANGE_MASK      0x00ffffff
1425 #define CLOCK_RANGE_SHIFT     0
1426 #define LOW_NIBBLE_MASK       0xf
1427 #define DATA_EQU_PREV         0
1428 #define DATA_FROM_TABLE       4
1429
1430 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1431                                       u8 module_index,
1432                                       struct atom_mc_reg_table *reg_table)
1433 {
1434         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1435         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1436         u32 i = 0, j;
1437         u16 data_offset, size;
1438         union vram_info *vram_info;
1439
1440         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1441
1442         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1443                                    &frev, &crev, &data_offset)) {
1444                 vram_info = (union vram_info *)
1445                         (adev->mode_info.atom_context->bios + data_offset);
1446                 switch (frev) {
1447                 case 1:
1448                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1449                         return -EINVAL;
1450                 case 2:
1451                         switch (crev) {
1452                         case 1:
1453                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1454                                         ATOM_INIT_REG_BLOCK *reg_block =
1455                                                 (ATOM_INIT_REG_BLOCK *)
1456                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1457                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1458                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1459                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1460                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1461                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1462                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1463                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1464                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1465                                                 return -EINVAL;
1466                                         while (i < num_entries) {
1467                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1468                                                         break;
1469                                                 reg_table->mc_reg_address[i].s1 =
1470                                                         (u16)(le16_to_cpu(format->usRegIndex));
1471                                                 reg_table->mc_reg_address[i].pre_reg_data =
1472                                                         (u8)(format->ucPreRegDataLength);
1473                                                 i++;
1474                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1475                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1476                                         }
1477                                         reg_table->last = i;
1478                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1479                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1480                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1481                                                                 >> MEM_ID_SHIFT);
1482                                                 if (module_index == t_mem_id) {
1483                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1484                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1485                                                                       >> CLOCK_RANGE_SHIFT);
1486                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1487                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1488                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1489                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1490                                                                         j++;
1491                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1492                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1493                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1494                                                                 }
1495                                                         }
1496                                                         num_ranges++;
1497                                                 }
1498                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1499                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1500                                         }
1501                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1502                                                 return -EINVAL;
1503                                         reg_table->num_entries = num_ranges;
1504                                 } else
1505                                         return -EINVAL;
1506                                 break;
1507                         default:
1508                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1509                                 return -EINVAL;
1510                         }
1511                         break;
1512                 default:
1513                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1514                         return -EINVAL;
1515                 }
1516                 return 0;
1517         }
1518         return -EINVAL;
1519 }
1520
1521 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1522 {
1523         uint32_t bios_6_scratch;
1524
1525         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1526
1527         if (lock) {
1528                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1529                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1530         } else {
1531                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1532                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1533         }
1534
1535         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1536 }
1537
1538 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1539 {
1540         uint32_t bios_2_scratch, bios_6_scratch;
1541
1542         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1543         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1544
1545         /* let the bios control the backlight */
1546         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1547
1548         /* tell the bios not to handle mode switching */
1549         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1550
1551         /* clear the vbios dpms state */
1552         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1553
1554         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1555         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1556 }
1557
1558 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1559 {
1560         int i;
1561
1562         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1563                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1564 }
1565
1566 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1567 {
1568         int i;
1569
1570         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1571                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1572 }
1573
1574 /* Atom needs data in little endian format
1575  * so swap as appropriate when copying data to
1576  * or from atom. Note that atom operates on
1577  * dw units.
1578  */
1579 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1580 {
1581 #ifdef __BIG_ENDIAN
1582         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1583         u32 *dst32, *src32;
1584         int i;
1585
1586         memcpy(src_tmp, src, num_bytes);
1587         src32 = (u32 *)src_tmp;
1588         dst32 = (u32 *)dst_tmp;
1589         if (to_le) {
1590                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1591                         dst32[i] = cpu_to_le32(src32[i]);
1592                 memcpy(dst, dst_tmp, num_bytes);
1593         } else {
1594                 u8 dws = num_bytes & ~3;
1595                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1596                         dst32[i] = le32_to_cpu(src32[i]);
1597                 memcpy(dst, dst_tmp, dws);
1598                 if (num_bytes % 4) {
1599                         for (i = 0; i < (num_bytes % 4); i++)
1600                                 dst[dws+i] = dst_tmp[dws+i];
1601                 }
1602         }
1603 #else
1604         memcpy(dst, src, num_bytes);
1605 #endif
1606 }