kernel/drivers/dma/pl330.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   6  *      Jaswinder Singh <jassi.brar@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/io.h>
  16 #include <linux/init.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/amba/bus.h>
  25 #include <linux/amba/pl330.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/of.h>
  28 #include <linux/of_dma.h>
  29 #include <linux/err.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "dmaengine.h"
  33 #define PL330_MAX_CHAN          8
  34 #define PL330_MAX_IRQS          32
  35 #define PL330_MAX_PERI          32
  36
  37 enum pl330_cachectrl {
  38         CCTRL0,         /* Noncacheable and nonbufferable */
  39         CCTRL1,         /* Bufferable only */
  40         CCTRL2,         /* Cacheable, but do not allocate */
  41         CCTRL3,         /* Cacheable and bufferable, but do not allocate */
  42         INVALID1,       /* AWCACHE = 0x1000 */
  43         INVALID2,
  44         CCTRL6,         /* Cacheable write-through, allocate on writes only */
  45         CCTRL7,         /* Cacheable write-back, allocate on writes only */
  46 };
  47
  48 enum pl330_byteswap {
  49         SWAP_NO,
  50         SWAP_2,
  51         SWAP_4,
  52         SWAP_8,
  53         SWAP_16,
  54 };
  55
  56 /* Register and Bit field Definitions */
  57 #define DS                      0x0
  58 #define DS_ST_STOP              0x0
  59 #define DS_ST_EXEC              0x1
  60 #define DS_ST_CMISS             0x2
  61 #define DS_ST_UPDTPC            0x3
  62 #define DS_ST_WFE               0x4
  63 #define DS_ST_ATBRR             0x5
  64 #define DS_ST_QBUSY             0x6
  65 #define DS_ST_WFP               0x7
  66 #define DS_ST_KILL              0x8
  67 #define DS_ST_CMPLT             0x9
  68 #define DS_ST_FLTCMP            0xe
  69 #define DS_ST_FAULT             0xf
  70
  71 #define DPC                     0x4
  72 #define INTEN                   0x20
  73 #define ES                      0x24
  74 #define INTSTATUS               0x28
  75 #define INTCLR                  0x2c
  76 #define FSM                     0x30
  77 #define FSC                     0x34
  78 #define FTM                     0x38
  79
  80 #define _FTC                    0x40
  81 #define FTC(n)                  (_FTC + (n)*0x4)
  82
  83 #define _CS                     0x100
  84 #define CS(n)                   (_CS + (n)*0x8)
  85 #define CS_CNS                  (1 << 21)
  86
  87 #define _CPC                    0x104
  88 #define CPC(n)                  (_CPC + (n)*0x8)
  89
  90 #define _SA                     0x400
  91 #define SA(n)                   (_SA + (n)*0x20)
  92
  93 #define _DA                     0x404
  94 #define DA(n)                   (_DA + (n)*0x20)
  95
  96 #define _CC                     0x408
  97 #define CC(n)                   (_CC + (n)*0x20)
  98
  99 #define CC_SRCINC               (1 << 0)
 100 #define CC_DSTINC               (1 << 14)
 101 #define CC_SRCPRI               (1 << 8)
 102 #define CC_DSTPRI               (1 << 22)
 103 #define CC_SRCNS                (1 << 9)
 104 #define CC_DSTNS                (1 << 23)
 105 #define CC_SRCIA                (1 << 10)
 106 #define CC_DSTIA                (1 << 24)
 107 #define CC_SRCBRSTLEN_SHFT      4
 108 #define CC_DSTBRSTLEN_SHFT      18
 109 #define CC_SRCBRSTSIZE_SHFT     1
 110 #define CC_DSTBRSTSIZE_SHFT     15
 111 #define CC_SRCCCTRL_SHFT        11
 112 #define CC_SRCCCTRL_MASK        0x7
 113 #define CC_DSTCCTRL_SHFT        25
 114 #define CC_DRCCCTRL_MASK        0x7
 115 #define CC_SWAP_SHFT            28
 116
 117 #define _LC0                    0x40c
 118 #define LC0(n)                  (_LC0 + (n)*0x20)
 119
 120 #define _LC1                    0x410
 121 #define LC1(n)                  (_LC1 + (n)*0x20)
 122
 123 #define DBGSTATUS               0xd00
 124 #define DBG_BUSY                (1 << 0)
 125
 126 #define DBGCMD                  0xd04
 127 #define DBGINST0                0xd08
 128 #define DBGINST1                0xd0c
 129
 130 #define CR0                     0xe00
 131 #define CR1                     0xe04
 132 #define CR2                     0xe08
 133 #define CR3                     0xe0c
 134 #define CR4                     0xe10
 135 #define CRD                     0xe14
 136
 137 #define PERIPH_ID               0xfe0
 138 #define PERIPH_REV_SHIFT        20
 139 #define PERIPH_REV_MASK         0xf
 140 #define PERIPH_REV_R0P0         0
 141 #define PERIPH_REV_R1P0         1
 142 #define PERIPH_REV_R1P1         2
 143
 144 #define CR0_PERIPH_REQ_SET      (1 << 0)
 145 #define CR0_BOOT_EN_SET         (1 << 1)
 146 #define CR0_BOOT_MAN_NS         (1 << 2)
 147 #define CR0_NUM_CHANS_SHIFT     4
 148 #define CR0_NUM_CHANS_MASK      0x7
 149 #define CR0_NUM_PERIPH_SHIFT    12
 150 #define CR0_NUM_PERIPH_MASK     0x1f
 151 #define CR0_NUM_EVENTS_SHIFT    17
 152 #define CR0_NUM_EVENTS_MASK     0x1f
 153
 154 #define CR1_ICACHE_LEN_SHIFT    0
 155 #define CR1_ICACHE_LEN_MASK     0x7
 156 #define CR1_NUM_ICACHELINES_SHIFT       4
 157 #define CR1_NUM_ICACHELINES_MASK        0xf
 158
 159 #define CRD_DATA_WIDTH_SHIFT    0
 160 #define CRD_DATA_WIDTH_MASK     0x7
 161 #define CRD_WR_CAP_SHIFT        4
 162 #define CRD_WR_CAP_MASK         0x7
 163 #define CRD_WR_Q_DEP_SHIFT      8
 164 #define CRD_WR_Q_DEP_MASK       0xf
 165 #define CRD_RD_CAP_SHIFT        12
 166 #define CRD_RD_CAP_MASK         0x7
 167 #define CRD_RD_Q_DEP_SHIFT      16
 168 #define CRD_RD_Q_DEP_MASK       0xf
 169 #define CRD_DATA_BUFF_SHIFT     20
 170 #define CRD_DATA_BUFF_MASK      0x3ff
 171
 172 #define PART                    0x330
 173 #define DESIGNER                0x41
 174 #define REVISION                0x0
 175 #define INTEG_CFG               0x0
 176 #define PERIPH_ID_VAL           ((PART << 0) | (DESIGNER << 12))
 177
 178 #define PL330_STATE_STOPPED             (1 << 0)
 179 #define PL330_STATE_EXECUTING           (1 << 1)
 180 #define PL330_STATE_WFE                 (1 << 2)
 181 #define PL330_STATE_FAULTING            (1 << 3)
 182 #define PL330_STATE_COMPLETING          (1 << 4)
 183 #define PL330_STATE_WFP                 (1 << 5)
 184 #define PL330_STATE_KILLING             (1 << 6)
 185 #define PL330_STATE_FAULT_COMPLETING    (1 << 7)
 186 #define PL330_STATE_CACHEMISS           (1 << 8)
 187 #define PL330_STATE_UPDTPC              (1 << 9)
 188 #define PL330_STATE_ATBARRIER           (1 << 10)
 189 #define PL330_STATE_QUEUEBUSY           (1 << 11)
 190 #define PL330_STATE_INVALID             (1 << 15)
 191
 192 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
 193                                 | PL330_STATE_WFE | PL330_STATE_FAULTING)
 194
 195 #define CMD_DMAADDH             0x54
 196 #define CMD_DMAEND              0x00
 197 #define CMD_DMAFLUSHP           0x35
 198 #define CMD_DMAGO               0xa0
 199 #define CMD_DMALD               0x04
 200 #define CMD_DMALDP              0x25
 201 #define CMD_DMALP               0x20
 202 #define CMD_DMALPEND            0x28
 203 #define CMD_DMAKILL             0x01
 204 #define CMD_DMAMOV              0xbc
 205 #define CMD_DMANOP              0x18
 206 #define CMD_DMARMB              0x12
 207 #define CMD_DMASEV              0x34
 208 #define CMD_DMAST               0x08
 209 #define CMD_DMASTP              0x29
 210 #define CMD_DMASTZ              0x0c
 211 #define CMD_DMAWFE              0x36
 212 #define CMD_DMAWFP              0x30
 213 #define CMD_DMAWMB              0x13
 214
 215 #define SZ_DMAADDH              3
 216 #define SZ_DMAEND               1
 217 #define SZ_DMAFLUSHP            2
 218 #define SZ_DMALD                1
 219 #define SZ_DMALDP               2
 220 #define SZ_DMALP                2
 221 #define SZ_DMALPEND             2
 222 #define SZ_DMAKILL              1
 223 #define SZ_DMAMOV               6
 224 #define SZ_DMANOP               1
 225 #define SZ_DMARMB               1
 226 #define SZ_DMASEV               2
 227 #define SZ_DMAST                1
 228 #define SZ_DMASTP               2
 229 #define SZ_DMASTZ               1
 230 #define SZ_DMAWFE               2
 231 #define SZ_DMAWFP               2
 232 #define SZ_DMAWMB               1
 233 #define SZ_DMAGO                6
 234
 235 #define BRST_LEN(ccr)           ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
 236 #define BRST_SIZE(ccr)          (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
 237
 238 #define BYTE_TO_BURST(b, ccr)   ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
 239 #define BURST_TO_BYTE(c, ccr)   ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
 240
 241 /*
 242  * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
 243  * at 1byte/burst for P<->M and M<->M respectively.
 244  * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
 245  * should be enough for P<->M and M<->M respectively.
 246  */
 247 #define MCODE_BUFF_PER_REQ      256
 248
 249 /* Use this _only_ to wait on transient states */
 250 #define UNTIL(t, s)     while (!(_state(t) & (s))) cpu_relax();
 251
 252 #ifdef PL330_DEBUG_MCGEN
 253 static unsigned cmd_line;
 254 #define PL330_DBGCMD_DUMP(off, x...)    do { \
 255                                                 printk("%x:", cmd_line); \
 256                                                 printk(x); \
 257                                                 cmd_line += off; \
 258                                         } while (0)
 259 #define PL330_DBGMC_START(addr)         (cmd_line = addr)
 260 #else
 261 #define PL330_DBGCMD_DUMP(off, x...)    do {} while (0)
 262 #define PL330_DBGMC_START(addr)         do {} while (0)
 263 #endif
 264
 265 /* The number of default descriptors */
 266
 267 #define NR_DEFAULT_DESC 16
 268
 269 /* Delay for runtime PM autosuspend, ms */
 270 #define PL330_AUTOSUSPEND_DELAY 20
 271
 272 /* Populated by the PL330 core driver for DMA API driver's info */
 273 struct pl330_config {
 274         u32     periph_id;
 275 #define DMAC_MODE_NS    (1 << 0)
 276         unsigned int    mode;
 277         unsigned int    data_bus_width:10; /* In number of bits */
 278         unsigned int    data_buf_dep:11;
 279         unsigned int    num_chan:4;
 280         unsigned int    num_peri:6;
 281         u32             peri_ns;
 282         unsigned int    num_events:6;
 283         u32             irq_ns;
 284 };
 285
 286 /**
 287  * Request Configuration.
 288  * The PL330 core does not modify this and uses the last
 289  * working configuration if the request doesn't provide any.
 290  *
 291  * The Client may want to provide this info only for the
 292  * first request and a request with new settings.
 293  */
 294 struct pl330_reqcfg {
 295         /* Address Incrementing */
 296         unsigned dst_inc:1;
 297         unsigned src_inc:1;
 298
 299         /*
 300          * For now, the SRC & DST protection levels
 301          * and burst size/length are assumed same.
 302          */
 303         bool nonsecure;
 304         bool privileged;
 305         bool insnaccess;
 306         unsigned brst_len:5;
 307         unsigned brst_size:3; /* in power of 2 */
 308
 309         enum pl330_cachectrl dcctl;
 310         enum pl330_cachectrl scctl;
 311         enum pl330_byteswap swap;
 312         struct pl330_config *pcfg;
 313 };
 314
 315 /*
 316  * One cycle of DMAC operation.
 317  * There may be more than one xfer in a request.
 318  */
 319 struct pl330_xfer {
 320         u32 src_addr;
 321         u32 dst_addr;
 322         /* Size to xfer */
 323         u32 bytes;
 324 };
 325
 326 /* The xfer callbacks are made with one of these arguments. */
 327 enum pl330_op_err {
 328         /* The all xfers in the request were success. */
 329         PL330_ERR_NONE,
 330         /* If req aborted due to global error. */
 331         PL330_ERR_ABORT,
 332         /* If req failed due to problem with Channel. */
 333         PL330_ERR_FAIL,
 334 };
 335
 336 enum dmamov_dst {
 337         SAR = 0,
 338         CCR,
 339         DAR,
 340 };
 341
 342 enum pl330_dst {
 343         SRC = 0,
 344         DST,
 345 };
 346
 347 enum pl330_cond {
 348         SINGLE,
 349         BURST,
 350         ALWAYS,
 351 };
 352
 353 struct dma_pl330_desc;
 354
 355 struct _pl330_req {
 356         u32 mc_bus;
 357         void *mc_cpu;
 358         struct dma_pl330_desc *desc;
 359 };
 360
 361 /* ToBeDone for tasklet */
 362 struct _pl330_tbd {
 363         bool reset_dmac;
 364         bool reset_mngr;
 365         u8 reset_chan;
 366 };
 367
 368 /* A DMAC Thread */
 369 struct pl330_thread {
 370         u8 id;
 371         int ev;
 372         /* If the channel is not yet acquired by any client */
 373         bool free;
 374         /* Parent DMAC */
 375         struct pl330_dmac *dmac;
 376         /* Only two at a time */
 377         struct _pl330_req req[2];
 378         /* Index of the last enqueued request */
 379         unsigned lstenq;
 380         /* Index of the last submitted request or -1 if the DMA is stopped */
 381         int req_running;
 382 };
 383
 384 enum pl330_dmac_state {
 385         UNINIT,
 386         INIT,
 387         DYING,
 388 };
 389
 390 enum desc_status {
 391         /* In the DMAC pool */
 392         FREE,
 393         /*
 394          * Allocated to some channel during prep_xxx
 395          * Also may be sitting on the work_list.
 396          */
 397         PREP,
 398         /*
 399          * Sitting on the work_list and already submitted
 400          * to the PL330 core. Not more than two descriptors
 401          * of a channel can be BUSY at any time.
 402          */
 403         BUSY,
 404         /*
 405          * Sitting on the channel work_list but xfer done
 406          * by PL330 core
 407          */
 408         DONE,
 409 };
 410
 411 struct dma_pl330_chan {
 412         /* Schedule desc completion */
 413         struct tasklet_struct task;
 414
 415         /* DMA-Engine Channel */
 416         struct dma_chan chan;
 417
 418         /* List of submitted descriptors */
 419         struct list_head submitted_list;
 420         /* List of issued descriptors */
 421         struct list_head work_list;
 422         /* List of completed descriptors */
 423         struct list_head completed_list;
 424
 425         /* Pointer to the DMAC that manages this channel,
 426          * NULL if the channel is available to be acquired.
 427          * As the parent, this DMAC also provides descriptors
 428          * to the channel.
 429          */
 430         struct pl330_dmac *dmac;
 431
 432         /* To protect channel manipulation */
 433         spinlock_t lock;
 434
 435         /*
 436          * Hardware channel thread of PL330 DMAC. NULL if the channel is
 437          * available.
 438          */
 439         struct pl330_thread *thread;
 440
 441         /* For D-to-M and M-to-D channels */
 442         int burst_sz; /* the peripheral fifo width */
 443         int burst_len; /* the number of burst */
 444         dma_addr_t fifo_addr;
 445
 446         /* for cyclic capability */
 447         bool cyclic;
 448
 449         /* for runtime pm tracking */
 450         bool active;
 451 };
 452
 453 struct pl330_dmac {
 454         /* DMA-Engine Device */
 455         struct dma_device ddma;
 456
 457         /* Holds info about sg limitations */
 458         struct device_dma_parameters dma_parms;
 459
 460         /* Pool of descriptors available for the DMAC's channels */
 461         struct list_head desc_pool;
 462         /* To protect desc_pool manipulation */
 463         spinlock_t pool_lock;
 464
 465         /* Size of MicroCode buffers for each channel. */
 466         unsigned mcbufsz;
 467         /* ioremap'ed address of PL330 registers. */
 468         void __iomem    *base;
 469         /* Populated by the PL330 core driver during pl330_add */
 470         struct pl330_config     pcfg;
 471
 472         spinlock_t              lock;
 473         /* Maximum possible events/irqs */
 474         int                     events[32];
 475         /* BUS address of MicroCode buffer */
 476         dma_addr_t              mcode_bus;
 477         /* CPU address of MicroCode buffer */
 478         void                    *mcode_cpu;
 479         /* List of all Channel threads */
 480         struct pl330_thread     *channels;
 481         /* Pointer to the MANAGER thread */
 482         struct pl330_thread     *manager;
 483         /* To handle bad news in interrupt */
 484         struct tasklet_struct   tasks;
 485         struct _pl330_tbd       dmac_tbd;
 486         /* State of DMAC operation */
 487         enum pl330_dmac_state   state;
 488         /* Holds list of reqs with due callbacks */
 489         struct list_head        req_done;
 490
 491         /* Peripheral channels connected to this DMAC */
 492         unsigned int num_peripherals;
 493         struct dma_pl330_chan *peripherals; /* keep at end */
 494 };
 495
 496 struct dma_pl330_desc {
 497         /* To attach to a queue as child */
 498         struct list_head node;
 499
 500         /* Descriptor for the DMA Engine API */
 501         struct dma_async_tx_descriptor txd;
 502
 503         /* Xfer for PL330 core */
 504         struct pl330_xfer px;
 505
 506         struct pl330_reqcfg rqcfg;
 507
 508         enum desc_status status;
 509
 510         int bytes_requested;
 511         bool last;
 512
 513         /* The channel which currently holds this desc */
 514         struct dma_pl330_chan *pchan;
 515
 516         enum dma_transfer_direction rqtype;
 517         /* Index of peripheral for the xfer. */
 518         unsigned peri:5;
 519         /* Hook to attach to DMAC's list of reqs with due callback */
 520         struct list_head rqd;
 521 };
 522
 523 struct _xfer_spec {
 524         u32 ccr;
 525         struct dma_pl330_desc *desc;
 526 };
 527
 528 static inline bool _queue_empty(struct pl330_thread *thrd)
 529 {
 530         return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
 531 }
 532
 533 static inline bool _queue_full(struct pl330_thread *thrd)
 534 {
 535         return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
 536 }
 537
 538 static inline bool is_manager(struct pl330_thread *thrd)
 539 {
 540         return thrd->dmac->manager == thrd;
 541 }
 542
 543 /* If manager of the thread is in Non-Secure mode */
 544 static inline bool _manager_ns(struct pl330_thread *thrd)
 545 {
 546         return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
 547 }
 548
 549 static inline u32 get_revision(u32 periph_id)
 550 {
 551         return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
 552 }
 553
 554 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
 555                 enum pl330_dst da, u16 val)
 556 {
 557         if (dry_run)
 558                 return SZ_DMAADDH;
 559
 560         buf[0] = CMD_DMAADDH;
 561         buf[0] |= (da << 1);
 562         *((__le16 *)&buf[1]) = cpu_to_le16(val);
 563
 564         PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
 565                 da == 1 ? "DA" : "SA", val);
 566
 567         return SZ_DMAADDH;
 568 }
 569
 570 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
 571 {
 572         if (dry_run)
 573                 return SZ_DMAEND;
 574
 575         buf[0] = CMD_DMAEND;
 576
 577         PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
 578
 579         return SZ_DMAEND;
 580 }
 581
 582 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
 583 {
 584         if (dry_run)
 585                 return SZ_DMAFLUSHP;
 586
 587         buf[0] = CMD_DMAFLUSHP;
 588
 589         peri &= 0x1f;
 590         peri <<= 3;
 591         buf[1] = peri;
 592
 593         PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
 594
 595         return SZ_DMAFLUSHP;
 596 }
 597
 598 static inline u32 _emit_LD(unsigned dry_run, u8 buf[],  enum pl330_cond cond)
 599 {
 600         if (dry_run)
 601                 return SZ_DMALD;
 602
 603         buf[0] = CMD_DMALD;
 604
 605         if (cond == SINGLE)
 606                 buf[0] |= (0 << 1) | (1 << 0);
 607         else if (cond == BURST)
 608                 buf[0] |= (1 << 1) | (1 << 0);
 609
 610         PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
 611                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
 612
 613         return SZ_DMALD;
 614 }
 615
 616 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
 617                 enum pl330_cond cond, u8 peri)
 618 {
 619         if (dry_run)
 620                 return SZ_DMALDP;
 621
 622         buf[0] = CMD_DMALDP;
 623
 624         if (cond == BURST)
 625                 buf[0] |= (1 << 1);
 626
 627         peri &= 0x1f;
 628         peri <<= 3;
 629         buf[1] = peri;
 630
 631         PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
 632                 cond == SINGLE ? 'S' : 'B', peri >> 3);
 633
 634         return SZ_DMALDP;
 635 }
 636
 637 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
 638                 unsigned loop, u8 cnt)
 639 {
 640         if (dry_run)
 641                 return SZ_DMALP;
 642
 643         buf[0] = CMD_DMALP;
 644
 645         if (loop)
 646                 buf[0] |= (1 << 1);
 647
 648         cnt--; /* DMAC increments by 1 internally */
 649         buf[1] = cnt;
 650
 651         PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
 652
 653         return SZ_DMALP;
 654 }
 655
 656 struct _arg_LPEND {
 657         enum pl330_cond cond;
 658         bool forever;
 659         unsigned loop;
 660         u8 bjump;
 661 };
 662
 663 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
 664                 const struct _arg_LPEND *arg)
 665 {
 666         enum pl330_cond cond = arg->cond;
 667         bool forever = arg->forever;
 668         unsigned loop = arg->loop;
 669         u8 bjump = arg->bjump;
 670
 671         if (dry_run)
 672                 return SZ_DMALPEND;
 673
 674         buf[0] = CMD_DMALPEND;
 675
 676         if (loop)
 677                 buf[0] |= (1 << 2);
 678
 679         if (!forever)
 680                 buf[0] |= (1 << 4);
 681
 682         if (cond == SINGLE)
 683                 buf[0] |= (0 << 1) | (1 << 0);
 684         else if (cond == BURST)
 685                 buf[0] |= (1 << 1) | (1 << 0);
 686
 687         buf[1] = bjump;
 688
 689         PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
 690                         forever ? "FE" : "END",
 691                         cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
 692                         loop ? '1' : '0',
 693                         bjump);
 694
 695         return SZ_DMALPEND;
 696 }
 697
 698 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
 699 {
 700         if (dry_run)
 701                 return SZ_DMAKILL;
 702
 703         buf[0] = CMD_DMAKILL;
 704
 705         return SZ_DMAKILL;
 706 }
 707
 708 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
 709                 enum dmamov_dst dst, u32 val)
 710 {
 711         if (dry_run)
 712                 return SZ_DMAMOV;
 713
 714         buf[0] = CMD_DMAMOV;
 715         buf[1] = dst;
 716         *((__le32 *)&buf[2]) = cpu_to_le32(val);
 717
 718         PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
 719                 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
 720
 721         return SZ_DMAMOV;
 722 }
 723
 724 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
 725 {
 726         if (dry_run)
 727                 return SZ_DMANOP;
 728
 729         buf[0] = CMD_DMANOP;
 730
 731         PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
 732
 733         return SZ_DMANOP;
 734 }
 735
 736 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
 737 {
 738         if (dry_run)
 739                 return SZ_DMARMB;
 740
 741         buf[0] = CMD_DMARMB;
 742
 743         PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
 744
 745         return SZ_DMARMB;
 746 }
 747
 748 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
 749 {
 750         if (dry_run)
 751                 return SZ_DMASEV;
 752
 753         buf[0] = CMD_DMASEV;
 754
 755         ev &= 0x1f;
 756         ev <<= 3;
 757         buf[1] = ev;
 758
 759         PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
 760
 761         return SZ_DMASEV;
 762 }
 763
 764 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
 765 {
 766         if (dry_run)
 767                 return SZ_DMAST;
 768
 769         buf[0] = CMD_DMAST;
 770
 771         if (cond == SINGLE)
 772                 buf[0] |= (0 << 1) | (1 << 0);
 773         else if (cond == BURST)
 774                 buf[0] |= (1 << 1) | (1 << 0);
 775
 776         PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
 777                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
 778
 779         return SZ_DMAST;
 780 }
 781
 782 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
 783                 enum pl330_cond cond, u8 peri)
 784 {
 785         if (dry_run)
 786                 return SZ_DMASTP;
 787
 788         buf[0] = CMD_DMASTP;
 789
 790         if (cond == BURST)
 791                 buf[0] |= (1 << 1);
 792
 793         peri &= 0x1f;
 794         peri <<= 3;
 795         buf[1] = peri;
 796
 797         PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
 798                 cond == SINGLE ? 'S' : 'B', peri >> 3);
 799
 800         return SZ_DMASTP;
 801 }
 802
 803 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
 804 {
 805         if (dry_run)
 806                 return SZ_DMASTZ;
 807
 808         buf[0] = CMD_DMASTZ;
 809
 810         PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
 811
 812         return SZ_DMASTZ;
 813 }
 814
 815 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
 816                 unsigned invalidate)
 817 {
 818         if (dry_run)
 819                 return SZ_DMAWFE;
 820
 821         buf[0] = CMD_DMAWFE;
 822
 823         ev &= 0x1f;
 824         ev <<= 3;
 825         buf[1] = ev;
 826
 827         if (invalidate)
 828                 buf[1] |= (1 << 1);
 829
 830         PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
 831                 ev >> 3, invalidate ? ", I" : "");
 832
 833         return SZ_DMAWFE;
 834 }
 835
 836 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
 837                 enum pl330_cond cond, u8 peri)
 838 {
 839         if (dry_run)
 840                 return SZ_DMAWFP;
 841
 842         buf[0] = CMD_DMAWFP;
 843
 844         if (cond == SINGLE)
 845                 buf[0] |= (0 << 1) | (0 << 0);
 846         else if (cond == BURST)
 847                 buf[0] |= (1 << 1) | (0 << 0);
 848         else
 849                 buf[0] |= (0 << 1) | (1 << 0);
 850
 851         peri &= 0x1f;
 852         peri <<= 3;
 853         buf[1] = peri;
 854
 855         PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
 856                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
 857
 858         return SZ_DMAWFP;
 859 }
 860
 861 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
 862 {
 863         if (dry_run)
 864                 return SZ_DMAWMB;
 865
 866         buf[0] = CMD_DMAWMB;
 867
 868         PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
 869
 870         return SZ_DMAWMB;
 871 }
 872
 873 struct _arg_GO {
 874         u8 chan;
 875         u32 addr;
 876         unsigned ns;
 877 };
 878
 879 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
 880                 const struct _arg_GO *arg)
 881 {
 882         u8 chan = arg->chan;
 883         u32 addr = arg->addr;
 884         unsigned ns = arg->ns;
 885
 886         if (dry_run)
 887                 return SZ_DMAGO;
 888
 889         buf[0] = CMD_DMAGO;
 890         buf[0] |= (ns << 1);
 891
 892         buf[1] = chan & 0x7;
 893
 894         *((__le32 *)&buf[2]) = cpu_to_le32(addr);
 895
 896         return SZ_DMAGO;
 897 }
 898
 899 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 900
 901 /* Returns Time-Out */
 902 static bool _until_dmac_idle(struct pl330_thread *thrd)
 903 {
 904         void __iomem *regs = thrd->dmac->base;
 905         unsigned long loops = msecs_to_loops(5);
 906
 907         do {
 908                 /* Until Manager is Idle */
 909                 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
 910                         break;
 911
 912                 cpu_relax();
 913         } while (--loops);
 914
 915         if (!loops)
 916                 return true;
 917
 918         return false;
 919 }
 920
 921 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
 922                 u8 insn[], bool as_manager)
 923 {
 924         void __iomem *regs = thrd->dmac->base;
 925         u32 val;
 926
 927         val = (insn[0] << 16) | (insn[1] << 24);
 928         if (!as_manager) {
 929                 val |= (1 << 0);
 930                 val |= (thrd->id << 8); /* Channel Number */
 931         }
 932         writel(val, regs + DBGINST0);
 933
 934         val = le32_to_cpu(*((__le32 *)&insn[2]));
 935         writel(val, regs + DBGINST1);
 936
 937         /* If timed out due to halted state-machine */
 938         if (_until_dmac_idle(thrd)) {
 939                 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
 940                 return;
 941         }
 942
 943         /* Get going */
 944         writel(0, regs + DBGCMD);
 945 }
 946
 947 static inline u32 _state(struct pl330_thread *thrd)
 948 {
 949         void __iomem *regs = thrd->dmac->base;
 950         u32 val;
 951
 952         if (is_manager(thrd))
 953                 val = readl(regs + DS) & 0xf;
 954         else
 955                 val = readl(regs + CS(thrd->id)) & 0xf;
 956
 957         switch (val) {
 958         case DS_ST_STOP:
 959                 return PL330_STATE_STOPPED;
 960         case DS_ST_EXEC:
 961                 return PL330_STATE_EXECUTING;
 962         case DS_ST_CMISS:
 963                 return PL330_STATE_CACHEMISS;
 964         case DS_ST_UPDTPC:
 965                 return PL330_STATE_UPDTPC;
 966         case DS_ST_WFE:
 967                 return PL330_STATE_WFE;
 968         case DS_ST_FAULT:
 969                 return PL330_STATE_FAULTING;
 970         case DS_ST_ATBRR:
 971                 if (is_manager(thrd))
 972                         return PL330_STATE_INVALID;
 973                 else
 974                         return PL330_STATE_ATBARRIER;
 975         case DS_ST_QBUSY:
 976                 if (is_manager(thrd))
 977                         return PL330_STATE_INVALID;
 978                 else
 979                         return PL330_STATE_QUEUEBUSY;
 980         case DS_ST_WFP:
 981                 if (is_manager(thrd))
 982                         return PL330_STATE_INVALID;
 983                 else
 984                         return PL330_STATE_WFP;
 985         case DS_ST_KILL:
 986                 if (is_manager(thrd))
 987                         return PL330_STATE_INVALID;
 988                 else
 989                         return PL330_STATE_KILLING;
 990         case DS_ST_CMPLT:
 991                 if (is_manager(thrd))
 992                         return PL330_STATE_INVALID;
 993                 else
 994                         return PL330_STATE_COMPLETING;
 995         case DS_ST_FLTCMP:
 996                 if (is_manager(thrd))
 997                         return PL330_STATE_INVALID;
 998                 else
 999                         return PL330_STATE_FAULT_COMPLETING;
1000         default:
1001                 return PL330_STATE_INVALID;
1002         }
1003 }
1004
1005 static void _stop(struct pl330_thread *thrd)
1006 {
1007         void __iomem *regs = thrd->dmac->base;
1008         u8 insn[6] = {0, 0, 0, 0, 0, 0};
1009
1010         if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1011                 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1012
1013         /* Return if nothing needs to be done */
1014         if (_state(thrd) == PL330_STATE_COMPLETING
1015                   || _state(thrd) == PL330_STATE_KILLING
1016                   || _state(thrd) == PL330_STATE_STOPPED)
1017                 return;
1018
1019         _emit_KILL(0, insn);
1020
1021         /* Stop generating interrupts for SEV */
1022         writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1023
1024         _execute_DBGINSN(thrd, insn, is_manager(thrd));
1025 }
1026
1027 /* Start doing req 'idx' of thread 'thrd' */
1028 static bool _trigger(struct pl330_thread *thrd)
1029 {
1030         void __iomem *regs = thrd->dmac->base;
1031         struct _pl330_req *req;
1032         struct dma_pl330_desc *desc;
1033         struct _arg_GO go;
1034         unsigned ns;
1035         u8 insn[6] = {0, 0, 0, 0, 0, 0};
1036         int idx;
1037
1038         /* Return if already ACTIVE */
1039         if (_state(thrd) != PL330_STATE_STOPPED)
1040                 return true;
1041
1042         idx = 1 - thrd->lstenq;
1043         if (thrd->req[idx].desc != NULL) {
1044                 req = &thrd->req[idx];
1045         } else {
1046                 idx = thrd->lstenq;
1047                 if (thrd->req[idx].desc != NULL)
1048                         req = &thrd->req[idx];
1049                 else
1050                         req = NULL;
1051         }
1052
1053         /* Return if no request */
1054         if (!req)
1055                 return true;
1056
1057         /* Return if req is running */
1058         if (idx == thrd->req_running)
1059                 return true;
1060
1061         desc = req->desc;
1062
1063         ns = desc->rqcfg.nonsecure ? 1 : 0;
1064
1065         /* See 'Abort Sources' point-4 at Page 2-25 */
1066         if (_manager_ns(thrd) && !ns)
1067                 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1068                         __func__, __LINE__);
1069
1070         go.chan = thrd->id;
1071         go.addr = req->mc_bus;
1072         go.ns = ns;
1073         _emit_GO(0, insn, &go);
1074
1075         /* Set to generate interrupts for SEV */
1076         writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1077
1078         /* Only manager can execute GO */
1079         _execute_DBGINSN(thrd, insn, true);
1080
1081         thrd->req_running = idx;
1082
1083         return true;
1084 }
1085
1086 static bool _start(struct pl330_thread *thrd)
1087 {
1088         switch (_state(thrd)) {
1089         case PL330_STATE_FAULT_COMPLETING:
1090                 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1091
1092                 if (_state(thrd) == PL330_STATE_KILLING)
1093                         UNTIL(thrd, PL330_STATE_STOPPED)
1094
1095         case PL330_STATE_FAULTING:
1096                 _stop(thrd);
1097
1098         case PL330_STATE_KILLING:
1099         case PL330_STATE_COMPLETING:
1100                 UNTIL(thrd, PL330_STATE_STOPPED)
1101
1102         case PL330_STATE_STOPPED:
1103                 return _trigger(thrd);
1104
1105         case PL330_STATE_WFP:
1106         case PL330_STATE_QUEUEBUSY:
1107         case PL330_STATE_ATBARRIER:
1108         case PL330_STATE_UPDTPC:
1109         case PL330_STATE_CACHEMISS:
1110         case PL330_STATE_EXECUTING:
1111                 return true;
1112
1113         case PL330_STATE_WFE: /* For RESUME, nothing yet */
1114         default:
1115                 return false;
1116         }
1117 }
1118
1119 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1120                 const struct _xfer_spec *pxs, int cyc)
1121 {
1122         int off = 0;
1123         struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1124
1125         /* check lock-up free version */
1126         if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1127                 while (cyc--) {
1128                         off += _emit_LD(dry_run, &buf[off], ALWAYS);
1129                         off += _emit_ST(dry_run, &buf[off], ALWAYS);
1130                 }
1131         } else {
1132                 while (cyc--) {
1133                         off += _emit_LD(dry_run, &buf[off], ALWAYS);
1134                         off += _emit_RMB(dry_run, &buf[off]);
1135                         off += _emit_ST(dry_run, &buf[off], ALWAYS);
1136                         off += _emit_WMB(dry_run, &buf[off]);
1137                 }
1138         }
1139
1140         return off;
1141 }
1142
1143 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1144                 const struct _xfer_spec *pxs, int cyc)
1145 {
1146         int off = 0;
1147
1148         while (cyc--) {
1149                 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1150                 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1151                 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1152                 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1153         }
1154
1155         return off;
1156 }
1157
1158 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1159                 const struct _xfer_spec *pxs, int cyc)
1160 {
1161         int off = 0;
1162
1163         while (cyc--) {
1164                 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1165                 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1166                 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1167                 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1168         }
1169
1170         return off;
1171 }
1172
1173 static int _bursts(unsigned dry_run, u8 buf[],
1174                 const struct _xfer_spec *pxs, int cyc)
1175 {
1176         int off = 0;
1177
1178         switch (pxs->desc->rqtype) {
1179         case DMA_MEM_TO_DEV:
1180                 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1181                 break;
1182         case DMA_DEV_TO_MEM:
1183                 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1184                 break;
1185         case DMA_MEM_TO_MEM:
1186                 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1187                 break;
1188         default:
1189                 off += 0x40000000; /* Scare off the Client */
1190                 break;
1191         }
1192
1193         return off;
1194 }
1195
1196 /* Returns bytes consumed and updates bursts */
1197 static inline int _loop(unsigned dry_run, u8 buf[],
1198                 unsigned long *bursts, const struct _xfer_spec *pxs)
1199 {
1200         int cyc, cycmax, szlp, szlpend, szbrst, off;
1201         unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1202         struct _arg_LPEND lpend;
1203
1204         if (*bursts == 1)
1205                 return _bursts(dry_run, buf, pxs, 1);
1206
1207         /* Max iterations possible in DMALP is 256 */
1208         if (*bursts >= 256*256) {
1209                 lcnt1 = 256;
1210                 lcnt0 = 256;
1211                 cyc = *bursts / lcnt1 / lcnt0;
1212         } else if (*bursts > 256) {
1213                 lcnt1 = 256;
1214                 lcnt0 = *bursts / lcnt1;
1215                 cyc = 1;
1216         } else {
1217                 lcnt1 = *bursts;
1218                 lcnt0 = 0;
1219                 cyc = 1;
1220         }
1221
1222         szlp = _emit_LP(1, buf, 0, 0);
1223         szbrst = _bursts(1, buf, pxs, 1);
1224
1225         lpend.cond = ALWAYS;
1226         lpend.forever = false;
1227         lpend.loop = 0;
1228         lpend.bjump = 0;
1229         szlpend = _emit_LPEND(1, buf, &lpend);
1230
1231         if (lcnt0) {
1232                 szlp *= 2;
1233                 szlpend *= 2;
1234         }
1235
1236         /*
1237          * Max bursts that we can unroll due to limit on the
1238          * size of backward jump that can be encoded in DMALPEND
1239          * which is 8-bits and hence 255
1240          */
1241         cycmax = (255 - (szlp + szlpend)) / szbrst;
1242
1243         cyc = (cycmax < cyc) ? cycmax : cyc;
1244
1245         off = 0;
1246
1247         if (lcnt0) {
1248                 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1249                 ljmp0 = off;
1250         }
1251
1252         off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1253         ljmp1 = off;
1254
1255         off += _bursts(dry_run, &buf[off], pxs, cyc);
1256
1257         lpend.cond = ALWAYS;
1258         lpend.forever = false;
1259         lpend.loop = 1;
1260         lpend.bjump = off - ljmp1;
1261         off += _emit_LPEND(dry_run, &buf[off], &lpend);
1262
1263         if (lcnt0) {
1264                 lpend.cond = ALWAYS;
1265                 lpend.forever = false;
1266                 lpend.loop = 0;
1267                 lpend.bjump = off - ljmp0;
1268                 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1269         }
1270
1271         *bursts = lcnt1 * cyc;
1272         if (lcnt0)
1273                 *bursts *= lcnt0;
1274
1275         return off;
1276 }
1277
1278 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1279                 const struct _xfer_spec *pxs)
1280 {
1281         struct pl330_xfer *x = &pxs->desc->px;
1282         u32 ccr = pxs->ccr;
1283         unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1284         int off = 0;
1285
1286         while (bursts) {
1287                 c = bursts;
1288                 off += _loop(dry_run, &buf[off], &c, pxs);
1289                 bursts -= c;
1290         }
1291
1292         return off;
1293 }
1294
1295 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1296                 const struct _xfer_spec *pxs)
1297 {
1298         struct pl330_xfer *x = &pxs->desc->px;
1299         int off = 0;
1300
1301         /* DMAMOV SAR, x->src_addr */
1302         off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1303         /* DMAMOV DAR, x->dst_addr */
1304         off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1305
1306         /* Setup Loop(s) */
1307         off += _setup_loops(dry_run, &buf[off], pxs);
1308
1309         return off;
1310 }
1311
1312 /*
1313  * A req is a sequence of one or more xfer units.
1314  * Returns the number of bytes taken to setup the MC for the req.
1315  */
1316 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1317                 unsigned index, struct _xfer_spec *pxs)
1318 {
1319         struct _pl330_req *req = &thrd->req[index];
1320         struct pl330_xfer *x;
1321         u8 *buf = req->mc_cpu;
1322         int off = 0;
1323
1324         PL330_DBGMC_START(req->mc_bus);
1325
1326         /* DMAMOV CCR, ccr */
1327         off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1328
1329         x = &pxs->desc->px;
1330         /* Error if xfer length is not aligned at burst size */
1331         if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1332                 return -EINVAL;
1333
1334         off += _setup_xfer(dry_run, &buf[off], pxs);
1335
1336         /* DMASEV peripheral/event */
1337         off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1338         /* DMAEND */
1339         off += _emit_END(dry_run, &buf[off]);
1340
1341         return off;
1342 }
1343
1344 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1345 {
1346         u32 ccr = 0;
1347
1348         if (rqc->src_inc)
1349                 ccr |= CC_SRCINC;
1350
1351         if (rqc->dst_inc)
1352                 ccr |= CC_DSTINC;
1353
1354         /* We set same protection levels for Src and DST for now */
1355         if (rqc->privileged)
1356                 ccr |= CC_SRCPRI | CC_DSTPRI;
1357         if (rqc->nonsecure)
1358                 ccr |= CC_SRCNS | CC_DSTNS;
1359         if (rqc->insnaccess)
1360                 ccr |= CC_SRCIA | CC_DSTIA;
1361
1362         ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1363         ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1364
1365         ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1366         ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1367
1368         ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1369         ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1370
1371         ccr |= (rqc->swap << CC_SWAP_SHFT);
1372
1373         return ccr;
1374 }
1375
1376 /*
1377  * Submit a list of xfers after which the client wants notification.
1378  * Client is not notified after each xfer unit, just once after all
1379  * xfer units are done or some error occurs.
1380  */
1381 static int pl330_submit_req(struct pl330_thread *thrd,
1382         struct dma_pl330_desc *desc)
1383 {
1384         struct pl330_dmac *pl330 = thrd->dmac;
1385         struct _xfer_spec xs;
1386         unsigned long flags;
1387         unsigned idx;
1388         u32 ccr;
1389         int ret = 0;
1390
1391         if (pl330->state == DYING
1392                 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1393                 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1394                         __func__, __LINE__);
1395                 return -EAGAIN;
1396         }
1397
1398         /* If request for non-existing peripheral */
1399         if (desc->rqtype != DMA_MEM_TO_MEM &&
1400             desc->peri >= pl330->pcfg.num_peri) {
1401                 dev_info(thrd->dmac->ddma.dev,
1402                                 "%s:%d Invalid peripheral(%u)!\n",
1403                                 __func__, __LINE__, desc->peri);
1404                 return -EINVAL;
1405         }
1406
1407         spin_lock_irqsave(&pl330->lock, flags);
1408
1409         if (_queue_full(thrd)) {
1410                 ret = -EAGAIN;
1411                 goto xfer_exit;
1412         }
1413
1414         /* Prefer Secure Channel */
1415         if (!_manager_ns(thrd))
1416                 desc->rqcfg.nonsecure = 0;
1417         else
1418                 desc->rqcfg.nonsecure = 1;
1419
1420         ccr = _prepare_ccr(&desc->rqcfg);
1421
1422         idx = thrd->req[0].desc == NULL ? 0 : 1;
1423
1424         xs.ccr = ccr;
1425         xs.desc = desc;
1426
1427         /* First dry run to check if req is acceptable */
1428         ret = _setup_req(1, thrd, idx, &xs);
1429         if (ret < 0)
1430                 goto xfer_exit;
1431
1432         if (ret > pl330->mcbufsz / 2) {
1433                 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1434                                 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1435                 ret = -ENOMEM;
1436                 goto xfer_exit;
1437         }
1438
1439         /* Hook the request */
1440         thrd->lstenq = idx;
1441         thrd->req[idx].desc = desc;
1442         _setup_req(0, thrd, idx, &xs);
1443
1444         ret = 0;
1445
1446 xfer_exit:
1447         spin_unlock_irqrestore(&pl330->lock, flags);
1448
1449         return ret;
1450 }
1451
1452 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1453 {
1454         struct dma_pl330_chan *pch;
1455         unsigned long flags;
1456
1457         if (!desc)
1458                 return;
1459
1460         pch = desc->pchan;
1461
1462         /* If desc aborted */
1463         if (!pch)
1464                 return;
1465
1466         spin_lock_irqsave(&pch->lock, flags);
1467
1468         desc->status = DONE;
1469
1470         spin_unlock_irqrestore(&pch->lock, flags);
1471
1472         tasklet_schedule(&pch->task);
1473 }
1474
1475 static void pl330_dotask(unsigned long data)
1476 {
1477         struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1478         unsigned long flags;
1479         int i;
1480
1481         spin_lock_irqsave(&pl330->lock, flags);
1482
1483         /* The DMAC itself gone nuts */
1484         if (pl330->dmac_tbd.reset_dmac) {
1485                 pl330->state = DYING;
1486                 /* Reset the manager too */
1487                 pl330->dmac_tbd.reset_mngr = true;
1488                 /* Clear the reset flag */
1489                 pl330->dmac_tbd.reset_dmac = false;
1490         }
1491
1492         if (pl330->dmac_tbd.reset_mngr) {
1493                 _stop(pl330->manager);
1494                 /* Reset all channels */
1495                 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1496                 /* Clear the reset flag */
1497                 pl330->dmac_tbd.reset_mngr = false;
1498         }
1499
1500         for (i = 0; i < pl330->pcfg.num_chan; i++) {
1501
1502                 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1503                         struct pl330_thread *thrd = &pl330->channels[i];
1504                         void __iomem *regs = pl330->base;
1505                         enum pl330_op_err err;
1506
1507                         _stop(thrd);
1508
1509                         if (readl(regs + FSC) & (1 << thrd->id))
1510                                 err = PL330_ERR_FAIL;
1511                         else
1512                                 err = PL330_ERR_ABORT;
1513
1514                         spin_unlock_irqrestore(&pl330->lock, flags);
1515                         dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1516                         dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1517                         spin_lock_irqsave(&pl330->lock, flags);
1518
1519                         thrd->req[0].desc = NULL;
1520                         thrd->req[1].desc = NULL;
1521                         thrd->req_running = -1;
1522
1523                         /* Clear the reset flag */
1524                         pl330->dmac_tbd.reset_chan &= ~(1 << i);
1525                 }
1526         }
1527
1528         spin_unlock_irqrestore(&pl330->lock, flags);
1529
1530         return;
1531 }
1532
1533 /* Returns 1 if state was updated, 0 otherwise */
1534 static int pl330_update(struct pl330_dmac *pl330)
1535 {
1536         struct dma_pl330_desc *descdone, *tmp;
1537         unsigned long flags;
1538         void __iomem *regs;
1539         u32 val;
1540         int id, ev, ret = 0;
1541
1542         regs = pl330->base;
1543
1544         spin_lock_irqsave(&pl330->lock, flags);
1545
1546         val = readl(regs + FSM) & 0x1;
1547         if (val)
1548                 pl330->dmac_tbd.reset_mngr = true;
1549         else
1550                 pl330->dmac_tbd.reset_mngr = false;
1551
1552         val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1553         pl330->dmac_tbd.reset_chan |= val;
1554         if (val) {
1555                 int i = 0;
1556                 while (i < pl330->pcfg.num_chan) {
1557                         if (val & (1 << i)) {
1558                                 dev_info(pl330->ddma.dev,
1559                                         "Reset Channel-%d\t CS-%x FTC-%x\n",
1560                                                 i, readl(regs + CS(i)),
1561                                                 readl(regs + FTC(i)));
1562                                 _stop(&pl330->channels[i]);
1563                         }
1564                         i++;
1565                 }
1566         }
1567
1568         /* Check which event happened i.e, thread notified */
1569         val = readl(regs + ES);
1570         if (pl330->pcfg.num_events < 32
1571                         && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1572                 pl330->dmac_tbd.reset_dmac = true;
1573                 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1574                         __LINE__);
1575                 ret = 1;
1576                 goto updt_exit;
1577         }
1578
1579         for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1580                 if (val & (1 << ev)) { /* Event occurred */
1581                         struct pl330_thread *thrd;
1582                         u32 inten = readl(regs + INTEN);
1583                         int active;
1584
1585                         /* Clear the event */
1586                         if (inten & (1 << ev))
1587                                 writel(1 << ev, regs + INTCLR);
1588
1589                         ret = 1;
1590
1591                         id = pl330->events[ev];
1592
1593                         thrd = &pl330->channels[id];
1594
1595                         active = thrd->req_running;
1596                         if (active == -1) /* Aborted */
1597                                 continue;
1598
1599                         /* Detach the req */
1600                         descdone = thrd->req[active].desc;
1601                         thrd->req[active].desc = NULL;
1602
1603                         thrd->req_running = -1;
1604
1605                         /* Get going again ASAP */
1606                         _start(thrd);
1607
1608                         /* For now, just make a list of callbacks to be done */
1609                         list_add_tail(&descdone->rqd, &pl330->req_done);
1610                 }
1611         }
1612
1613         /* Now that we are in no hurry, do the callbacks */
1614         list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1615                 list_del(&descdone->rqd);
1616                 spin_unlock_irqrestore(&pl330->lock, flags);
1617                 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1618                 spin_lock_irqsave(&pl330->lock, flags);
1619         }
1620
1621 updt_exit:
1622         spin_unlock_irqrestore(&pl330->lock, flags);
1623
1624         if (pl330->dmac_tbd.reset_dmac
1625                         || pl330->dmac_tbd.reset_mngr
1626                         || pl330->dmac_tbd.reset_chan) {
1627                 ret = 1;
1628                 tasklet_schedule(&pl330->tasks);
1629         }
1630
1631         return ret;
1632 }
1633
1634 /* Reserve an event */
1635 static inline int _alloc_event(struct pl330_thread *thrd)
1636 {
1637         struct pl330_dmac *pl330 = thrd->dmac;
1638         int ev;
1639
1640         for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1641                 if (pl330->events[ev] == -1) {
1642                         pl330->events[ev] = thrd->id;
1643                         return ev;
1644                 }
1645
1646         return -1;
1647 }
1648
1649 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1650 {
1651         return pl330->pcfg.irq_ns & (1 << i);
1652 }
1653
1654 /* Upon success, returns IdentityToken for the
1655  * allocated channel, NULL otherwise.
1656  */
1657 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1658 {
1659         struct pl330_thread *thrd = NULL;
1660         unsigned long flags;
1661         int chans, i;
1662
1663         if (pl330->state == DYING)
1664                 return NULL;
1665
1666         chans = pl330->pcfg.num_chan;
1667
1668         spin_lock_irqsave(&pl330->lock, flags);
1669
1670         for (i = 0; i < chans; i++) {
1671                 thrd = &pl330->channels[i];
1672                 if ((thrd->free) && (!_manager_ns(thrd) ||
1673                                         _chan_ns(pl330, i))) {
1674                         thrd->ev = _alloc_event(thrd);
1675                         if (thrd->ev >= 0) {
1676                                 thrd->free = false;
1677                                 thrd->lstenq = 1;
1678                                 thrd->req[0].desc = NULL;
1679                                 thrd->req[1].desc = NULL;
1680                                 thrd->req_running = -1;
1681                                 break;
1682                         }
1683                 }
1684                 thrd = NULL;
1685         }
1686
1687         spin_unlock_irqrestore(&pl330->lock, flags);
1688
1689         return thrd;
1690 }
1691
1692 /* Release an event */
1693 static inline void _free_event(struct pl330_thread *thrd, int ev)
1694 {
1695         struct pl330_dmac *pl330 = thrd->dmac;
1696
1697         /* If the event is valid and was held by the thread */
1698         if (ev >= 0 && ev < pl330->pcfg.num_events
1699                         && pl330->events[ev] == thrd->id)
1700                 pl330->events[ev] = -1;
1701 }
1702
1703 static void pl330_release_channel(struct pl330_thread *thrd)
1704 {
1705         struct pl330_dmac *pl330;
1706         unsigned long flags;
1707
1708         if (!thrd || thrd->free)
1709                 return;
1710
1711         _stop(thrd);
1712
1713         dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1714         dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1715
1716         pl330 = thrd->dmac;
1717
1718         spin_lock_irqsave(&pl330->lock, flags);
1719         _free_event(thrd, thrd->ev);
1720         thrd->free = true;
1721         spin_unlock_irqrestore(&pl330->lock, flags);
1722 }
1723
1724 /* Initialize the structure for PL330 configuration, that can be used
1725  * by the client driver the make best use of the DMAC
1726  */
1727 static void read_dmac_config(struct pl330_dmac *pl330)
1728 {
1729         void __iomem *regs = pl330->base;
1730         u32 val;
1731
1732         val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1733         val &= CRD_DATA_WIDTH_MASK;
1734         pl330->pcfg.data_bus_width = 8 * (1 << val);
1735
1736         val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1737         val &= CRD_DATA_BUFF_MASK;
1738         pl330->pcfg.data_buf_dep = val + 1;
1739
1740         val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1741         val &= CR0_NUM_CHANS_MASK;
1742         val += 1;
1743         pl330->pcfg.num_chan = val;
1744
1745         val = readl(regs + CR0);
1746         if (val & CR0_PERIPH_REQ_SET) {
1747                 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1748                 val += 1;
1749                 pl330->pcfg.num_peri = val;
1750                 pl330->pcfg.peri_ns = readl(regs + CR4);
1751         } else {
1752                 pl330->pcfg.num_peri = 0;
1753         }
1754
1755         val = readl(regs + CR0);
1756         if (val & CR0_BOOT_MAN_NS)
1757                 pl330->pcfg.mode |= DMAC_MODE_NS;
1758         else
1759                 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1760
1761         val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1762         val &= CR0_NUM_EVENTS_MASK;
1763         val += 1;
1764         pl330->pcfg.num_events = val;
1765
1766         pl330->pcfg.irq_ns = readl(regs + CR3);
1767 }
1768
1769 static inline void _reset_thread(struct pl330_thread *thrd)
1770 {
1771         struct pl330_dmac *pl330 = thrd->dmac;
1772
1773         thrd->req[0].mc_cpu = pl330->mcode_cpu
1774                                 + (thrd->id * pl330->mcbufsz);
1775         thrd->req[0].mc_bus = pl330->mcode_bus
1776                                 + (thrd->id * pl330->mcbufsz);
1777         thrd->req[0].desc = NULL;
1778
1779         thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1780                                 + pl330->mcbufsz / 2;
1781         thrd->req[1].mc_bus = thrd->req[0].mc_bus
1782                                 + pl330->mcbufsz / 2;
1783         thrd->req[1].desc = NULL;
1784
1785         thrd->req_running = -1;
1786 }
1787
1788 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1789 {
1790         int chans = pl330->pcfg.num_chan;
1791         struct pl330_thread *thrd;
1792         int i;
1793
1794         /* Allocate 1 Manager and 'chans' Channel threads */
1795         pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1796                                         GFP_KERNEL);
1797         if (!pl330->channels)
1798                 return -ENOMEM;
1799
1800         /* Init Channel threads */
1801         for (i = 0; i < chans; i++) {
1802                 thrd = &pl330->channels[i];
1803                 thrd->id = i;
1804                 thrd->dmac = pl330;
1805                 _reset_thread(thrd);
1806                 thrd->free = true;
1807         }
1808
1809         /* MANAGER is indexed at the end */
1810         thrd = &pl330->channels[chans];
1811         thrd->id = chans;
1812         thrd->dmac = pl330;
1813         thrd->free = false;
1814         pl330->manager = thrd;
1815
1816         return 0;
1817 }
1818
1819 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1820 {
1821         int chans = pl330->pcfg.num_chan;
1822         int ret;
1823
1824         /*
1825          * Alloc MicroCode buffer for 'chans' Channel threads.
1826          * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1827          */
1828         pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1829                                 chans * pl330->mcbufsz,
1830                                 &pl330->mcode_bus, GFP_KERNEL);
1831         if (!pl330->mcode_cpu) {
1832                 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1833                         __func__, __LINE__);
1834                 return -ENOMEM;
1835         }
1836
1837         ret = dmac_alloc_threads(pl330);
1838         if (ret) {
1839                 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1840                         __func__, __LINE__);
1841                 dma_free_coherent(pl330->ddma.dev,
1842                                 chans * pl330->mcbufsz,
1843                                 pl330->mcode_cpu, pl330->mcode_bus);
1844                 return ret;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static int pl330_add(struct pl330_dmac *pl330)
1851 {
1852         void __iomem *regs;
1853         int i, ret;
1854
1855         regs = pl330->base;
1856
1857         /* Check if we can handle this DMAC */
1858         if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1859                 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1860                         pl330->pcfg.periph_id);
1861                 return -EINVAL;
1862         }
1863
1864         /* Read the configuration of the DMAC */
1865         read_dmac_config(pl330);
1866
1867         if (pl330->pcfg.num_events == 0) {
1868                 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1869                         __func__, __LINE__);
1870                 return -EINVAL;
1871         }
1872
1873         spin_lock_init(&pl330->lock);
1874
1875         INIT_LIST_HEAD(&pl330->req_done);
1876
1877         /* Use default MC buffer size if not provided */
1878         if (!pl330->mcbufsz)
1879                 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1880
1881         /* Mark all events as free */
1882         for (i = 0; i < pl330->pcfg.num_events; i++)
1883                 pl330->events[i] = -1;
1884
1885         /* Allocate resources needed by the DMAC */
1886         ret = dmac_alloc_resources(pl330);
1887         if (ret) {
1888                 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1889                 return ret;
1890         }
1891
1892         tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1893
1894         pl330->state = INIT;
1895
1896         return 0;
1897 }
1898
1899 static int dmac_free_threads(struct pl330_dmac *pl330)
1900 {
1901         struct pl330_thread *thrd;
1902         int i;
1903
1904         /* Release Channel threads */
1905         for (i = 0; i < pl330->pcfg.num_chan; i++) {
1906                 thrd = &pl330->channels[i];
1907                 pl330_release_channel(thrd);
1908         }
1909
1910         /* Free memory */
1911         kfree(pl330->channels);
1912
1913         return 0;
1914 }
1915
1916 static void pl330_del(struct pl330_dmac *pl330)
1917 {
1918         pl330->state = UNINIT;
1919
1920         tasklet_kill(&pl330->tasks);
1921
1922         /* Free DMAC resources */
1923         dmac_free_threads(pl330);
1924
1925         dma_free_coherent(pl330->ddma.dev,
1926                 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1927                 pl330->mcode_bus);
1928 }
1929
1930 /* forward declaration */
1931 static struct amba_driver pl330_driver;
1932
1933 static inline struct dma_pl330_chan *
1934 to_pchan(struct dma_chan *ch)
1935 {
1936         if (!ch)
1937                 return NULL;
1938
1939         return container_of(ch, struct dma_pl330_chan, chan);
1940 }
1941
1942 static inline struct dma_pl330_desc *
1943 to_desc(struct dma_async_tx_descriptor *tx)
1944 {
1945         return container_of(tx, struct dma_pl330_desc, txd);
1946 }
1947
1948 static inline void fill_queue(struct dma_pl330_chan *pch)
1949 {
1950         struct dma_pl330_desc *desc;
1951         int ret;
1952
1953         list_for_each_entry(desc, &pch->work_list, node) {
1954
1955                 /* If already submitted */
1956                 if (desc->status == BUSY)
1957                         continue;
1958
1959                 ret = pl330_submit_req(pch->thread, desc);
1960                 if (!ret) {
1961                         desc->status = BUSY;
1962                 } else if (ret == -EAGAIN) {
1963                         /* QFull or DMAC Dying */
1964                         break;
1965                 } else {
1966                         /* Unacceptable request */
1967                         desc->status = DONE;
1968                         dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
1969                                         __func__, __LINE__, desc->txd.cookie);
1970                         tasklet_schedule(&pch->task);
1971                 }
1972         }
1973 }
1974
1975 static void pl330_tasklet(unsigned long data)
1976 {
1977         struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1978         struct dma_pl330_desc *desc, *_dt;
1979         unsigned long flags;
1980         bool power_down = false;
1981
1982         spin_lock_irqsave(&pch->lock, flags);
1983
1984         /* Pick up ripe tomatoes */
1985         list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1986                 if (desc->status == DONE) {
1987                         if (!pch->cyclic)
1988                                 dma_cookie_complete(&desc->txd);
1989                         list_move_tail(&desc->node, &pch->completed_list);
1990                 }
1991
1992         /* Try to submit a req imm. next to the last completed cookie */
1993         fill_queue(pch);
1994
1995         if (list_empty(&pch->work_list)) {
1996                 spin_lock(&pch->thread->dmac->lock);
1997                 _stop(pch->thread);
1998                 spin_unlock(&pch->thread->dmac->lock);
1999                 power_down = true;
2000                 pch->active = false;
2001         } else {
2002                 /* Make sure the PL330 Channel thread is active */
2003                 spin_lock(&pch->thread->dmac->lock);
2004                 _start(pch->thread);
2005                 spin_unlock(&pch->thread->dmac->lock);
2006         }
2007
2008         while (!list_empty(&pch->completed_list)) {
2009                 dma_async_tx_callback callback;
2010                 void *callback_param;
2011
2012                 desc = list_first_entry(&pch->completed_list,
2013                                         struct dma_pl330_desc, node);
2014
2015                 callback = desc->txd.callback;
2016                 callback_param = desc->txd.callback_param;
2017
2018                 if (pch->cyclic) {
2019                         desc->status = PREP;
2020                         list_move_tail(&desc->node, &pch->work_list);
2021                         if (power_down) {
2022                                 pch->active = true;
2023                                 spin_lock(&pch->thread->dmac->lock);
2024                                 _start(pch->thread);
2025                                 spin_unlock(&pch->thread->dmac->lock);
2026                                 power_down = false;
2027                         }
2028                 } else {
2029                         desc->status = FREE;
2030                         list_move_tail(&desc->node, &pch->dmac->desc_pool);
2031                 }
2032
2033                 dma_descriptor_unmap(&desc->txd);
2034
2035                 if (callback) {
2036                         spin_unlock_irqrestore(&pch->lock, flags);
2037                         callback(callback_param);
2038                         spin_lock_irqsave(&pch->lock, flags);
2039                 }
2040         }
2041         spin_unlock_irqrestore(&pch->lock, flags);
2042
2043         /* If work list empty, power down */
2044         if (power_down) {
2045                 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2046                 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2047         }
2048 }
2049
2050 bool pl330_filter(struct dma_chan *chan, void *param)
2051 {
2052         u8 *peri_id;
2053
2054         if (chan->device->dev->driver != &pl330_driver.drv)
2055                 return false;
2056
2057         peri_id = chan->private;
2058         return *peri_id == (unsigned long)param;
2059 }
2060 EXPORT_SYMBOL(pl330_filter);
2061
2062 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2063                                                 struct of_dma *ofdma)
2064 {
2065         int count = dma_spec->args_count;
2066         struct pl330_dmac *pl330 = ofdma->of_dma_data;
2067         unsigned int chan_id;
2068
2069         if (!pl330)
2070                 return NULL;
2071
2072         if (count != 1)
2073                 return NULL;
2074
2075         chan_id = dma_spec->args[0];
2076         if (chan_id >= pl330->num_peripherals)
2077                 return NULL;
2078
2079         return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2080 }
2081
2082 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2083 {
2084         struct dma_pl330_chan *pch = to_pchan(chan);
2085         struct pl330_dmac *pl330 = pch->dmac;
2086         unsigned long flags;
2087
2088         spin_lock_irqsave(&pch->lock, flags);
2089
2090         dma_cookie_init(chan);
2091         pch->cyclic = false;
2092
2093         pch->thread = pl330_request_channel(pl330);
2094         if (!pch->thread) {
2095                 spin_unlock_irqrestore(&pch->lock, flags);
2096                 return -ENOMEM;
2097         }
2098
2099         tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2100
2101         spin_unlock_irqrestore(&pch->lock, flags);
2102
2103         return 1;
2104 }
2105
2106 static int pl330_config(struct dma_chan *chan,
2107                         struct dma_slave_config *slave_config)
2108 {
2109         struct dma_pl330_chan *pch = to_pchan(chan);
2110
2111         if (slave_config->direction == DMA_MEM_TO_DEV) {
2112                 if (slave_config->dst_addr)
2113                         pch->fifo_addr = slave_config->dst_addr;
2114                 if (slave_config->dst_addr_width)
2115                         pch->burst_sz = __ffs(slave_config->dst_addr_width);
2116                 if (slave_config->dst_maxburst)
2117                         pch->burst_len = slave_config->dst_maxburst;
2118         } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2119                 if (slave_config->src_addr)
2120                         pch->fifo_addr = slave_config->src_addr;
2121                 if (slave_config->src_addr_width)
2122                         pch->burst_sz = __ffs(slave_config->src_addr_width);
2123                 if (slave_config->src_maxburst)
2124                         pch->burst_len = slave_config->src_maxburst;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int pl330_terminate_all(struct dma_chan *chan)
2131 {
2132         struct dma_pl330_chan *pch = to_pchan(chan);
2133         struct dma_pl330_desc *desc;
2134         unsigned long flags;
2135         struct pl330_dmac *pl330 = pch->dmac;
2136         LIST_HEAD(list);
2137         bool power_down = false;
2138
2139         pm_runtime_get_sync(pl330->ddma.dev);
2140         spin_lock_irqsave(&pch->lock, flags);
2141         spin_lock(&pl330->lock);
2142         _stop(pch->thread);
2143         spin_unlock(&pl330->lock);
2144
2145         pch->thread->req[0].desc = NULL;
2146         pch->thread->req[1].desc = NULL;
2147         pch->thread->req_running = -1;
2148         power_down = pch->active;
2149         pch->active = false;
2150
2151         /* Mark all desc done */
2152         list_for_each_entry(desc, &pch->submitted_list, node) {
2153                 desc->status = FREE;
2154                 dma_cookie_complete(&desc->txd);
2155         }
2156
2157         list_for_each_entry(desc, &pch->work_list , node) {
2158                 desc->status = FREE;
2159                 dma_cookie_complete(&desc->txd);
2160         }
2161
2162         list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2163         list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2164         list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2165         spin_unlock_irqrestore(&pch->lock, flags);
2166         pm_runtime_mark_last_busy(pl330->ddma.dev);
2167         if (power_down)
2168                 pm_runtime_put_autosuspend(pl330->ddma.dev);
2169         pm_runtime_put_autosuspend(pl330->ddma.dev);
2170
2171         return 0;
2172 }
2173
2174 /*
2175  * We don't support DMA_RESUME command because of hardware
2176  * limitations, so after pausing the channel we cannot restore
2177  * it to active state. We have to terminate channel and setup
2178  * DMA transfer again. This pause feature was implemented to
2179  * allow safely read residue before channel termination.
2180  */
2181 static int pl330_pause(struct dma_chan *chan)
2182 {
2183         struct dma_pl330_chan *pch = to_pchan(chan);
2184         struct pl330_dmac *pl330 = pch->dmac;
2185         unsigned long flags;
2186
2187         pm_runtime_get_sync(pl330->ddma.dev);
2188         spin_lock_irqsave(&pch->lock, flags);
2189
2190         spin_lock(&pl330->lock);
2191         _stop(pch->thread);
2192         spin_unlock(&pl330->lock);
2193
2194         spin_unlock_irqrestore(&pch->lock, flags);
2195         pm_runtime_mark_last_busy(pl330->ddma.dev);
2196         pm_runtime_put_autosuspend(pl330->ddma.dev);
2197
2198         return 0;
2199 }
2200
2201 static void pl330_free_chan_resources(struct dma_chan *chan)
2202 {
2203         struct dma_pl330_chan *pch = to_pchan(chan);
2204         unsigned long flags;
2205
2206         tasklet_kill(&pch->task);
2207
2208         pm_runtime_get_sync(pch->dmac->ddma.dev);
2209         spin_lock_irqsave(&pch->lock, flags);
2210
2211         pl330_release_channel(pch->thread);
2212         pch->thread = NULL;
2213
2214         if (pch->cyclic)
2215                 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2216
2217         spin_unlock_irqrestore(&pch->lock, flags);
2218         pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2219         pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2220 }
2221
2222 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2223                                            struct dma_pl330_desc *desc)
2224 {
2225         struct pl330_thread *thrd = pch->thread;
2226         struct pl330_dmac *pl330 = pch->dmac;
2227         void __iomem *regs = thrd->dmac->base;
2228         u32 val, addr;
2229
2230         pm_runtime_get_sync(pl330->ddma.dev);
2231         val = addr = 0;
2232         if (desc->rqcfg.src_inc) {
2233                 val = readl(regs + SA(thrd->id));
2234                 addr = desc->px.src_addr;
2235         } else {
2236                 val = readl(regs + DA(thrd->id));
2237                 addr = desc->px.dst_addr;
2238         }
2239         pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2240         pm_runtime_put_autosuspend(pl330->ddma.dev);
2241         return val - addr;
2242 }
2243
2244 static enum dma_status
2245 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2246                  struct dma_tx_state *txstate)
2247 {
2248         enum dma_status ret;
2249         unsigned long flags;
2250         struct dma_pl330_desc *desc, *running = NULL;
2251         struct dma_pl330_chan *pch = to_pchan(chan);
2252         unsigned int transferred, residual = 0;
2253
2254         ret = dma_cookie_status(chan, cookie, txstate);
2255
2256         if (!txstate)
2257                 return ret;
2258
2259         if (ret == DMA_COMPLETE)
2260                 goto out;
2261
2262         spin_lock_irqsave(&pch->lock, flags);
2263
2264         if (pch->thread->req_running != -1)
2265                 running = pch->thread->req[pch->thread->req_running].desc;
2266
2267         /* Check in pending list */
2268         list_for_each_entry(desc, &pch->work_list, node) {
2269                 if (desc->status == DONE)
2270                         transferred = desc->bytes_requested;
2271                 else if (running && desc == running)
2272                         transferred =
2273                                 pl330_get_current_xferred_count(pch, desc);
2274                 else
2275                         transferred = 0;
2276                 residual += desc->bytes_requested - transferred;
2277                 if (desc->txd.cookie == cookie) {
2278                         switch (desc->status) {
2279                         case DONE:
2280                                 ret = DMA_COMPLETE;
2281                                 break;
2282                         case PREP:
2283                         case BUSY:
2284                                 ret = DMA_IN_PROGRESS;
2285                                 break;
2286                         default:
2287                                 WARN_ON(1);
2288                         }
2289                         break;
2290                 }
2291                 if (desc->last)
2292                         residual = 0;
2293         }
2294         spin_unlock_irqrestore(&pch->lock, flags);
2295
2296 out:
2297         dma_set_residue(txstate, residual);
2298
2299         return ret;
2300 }
2301
2302 static void pl330_issue_pending(struct dma_chan *chan)
2303 {
2304         struct dma_pl330_chan *pch = to_pchan(chan);
2305         unsigned long flags;
2306
2307         spin_lock_irqsave(&pch->lock, flags);
2308         if (list_empty(&pch->work_list)) {
2309                 /*
2310                  * Warn on nothing pending. Empty submitted_list may
2311                  * break our pm_runtime usage counter as it is
2312                  * updated on work_list emptiness status.
2313                  */
2314                 WARN_ON(list_empty(&pch->submitted_list));
2315                 pch->active = true;
2316                 pm_runtime_get_sync(pch->dmac->ddma.dev);
2317         }
2318         list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2319         spin_unlock_irqrestore(&pch->lock, flags);
2320
2321         pl330_tasklet((unsigned long)pch);
2322 }
2323
2324 /*
2325  * We returned the last one of the circular list of descriptor(s)
2326  * from prep_xxx, so the argument to submit corresponds to the last
2327  * descriptor of the list.
2328  */
2329 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2330 {
2331         struct dma_pl330_desc *desc, *last = to_desc(tx);
2332         struct dma_pl330_chan *pch = to_pchan(tx->chan);
2333         dma_cookie_t cookie;
2334         unsigned long flags;
2335
2336         spin_lock_irqsave(&pch->lock, flags);
2337
2338         /* Assign cookies to all nodes */
2339         while (!list_empty(&last->node)) {
2340                 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2341                 if (pch->cyclic) {
2342                         desc->txd.callback = last->txd.callback;
2343                         desc->txd.callback_param = last->txd.callback_param;
2344                 }
2345                 desc->last = false;
2346
2347                 dma_cookie_assign(&desc->txd);
2348
2349                 list_move_tail(&desc->node, &pch->submitted_list);
2350         }
2351
2352         last->last = true;
2353         cookie = dma_cookie_assign(&last->txd);
2354         list_add_tail(&last->node, &pch->submitted_list);
2355         spin_unlock_irqrestore(&pch->lock, flags);
2356
2357         return cookie;
2358 }
2359
2360 static inline void _init_desc(struct dma_pl330_desc *desc)
2361 {
2362         desc->rqcfg.swap = SWAP_NO;
2363         desc->rqcfg.scctl = CCTRL0;
2364         desc->rqcfg.dcctl = CCTRL0;
2365         desc->txd.tx_submit = pl330_tx_submit;
2366
2367         INIT_LIST_HEAD(&desc->node);
2368 }
2369
2370 /* Returns the number of descriptors added to the DMAC pool */
2371 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2372 {
2373         struct dma_pl330_desc *desc;
2374         unsigned long flags;
2375         int i;
2376
2377         desc = kcalloc(count, sizeof(*desc), flg);
2378         if (!desc)
2379                 return 0;
2380
2381         spin_lock_irqsave(&pl330->pool_lock, flags);
2382
2383         for (i = 0; i < count; i++) {
2384                 _init_desc(&desc[i]);
2385                 list_add_tail(&desc[i].node, &pl330->desc_pool);
2386         }
2387
2388         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2389
2390         return count;
2391 }
2392
2393 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2394 {
2395         struct dma_pl330_desc *desc = NULL;
2396         unsigned long flags;
2397
2398         spin_lock_irqsave(&pl330->pool_lock, flags);
2399
2400         if (!list_empty(&pl330->desc_pool)) {
2401                 desc = list_entry(pl330->desc_pool.next,
2402                                 struct dma_pl330_desc, node);
2403
2404                 list_del_init(&desc->node);
2405
2406                 desc->status = PREP;
2407                 desc->txd.callback = NULL;
2408         }
2409
2410         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2411
2412         return desc;
2413 }
2414
2415 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2416 {
2417         struct pl330_dmac *pl330 = pch->dmac;
2418         u8 *peri_id = pch->chan.private;
2419         struct dma_pl330_desc *desc;
2420
2421         /* Pluck one desc from the pool of DMAC */
2422         desc = pluck_desc(pl330);
2423
2424         /* If the DMAC pool is empty, alloc new */
2425         if (!desc) {
2426                 if (!add_desc(pl330, GFP_ATOMIC, 1))
2427                         return NULL;
2428
2429                 /* Try again */
2430                 desc = pluck_desc(pl330);
2431                 if (!desc) {
2432                         dev_err(pch->dmac->ddma.dev,
2433                                 "%s:%d ALERT!\n", __func__, __LINE__);
2434                         return NULL;
2435                 }
2436         }
2437
2438         /* Initialize the descriptor */
2439         desc->pchan = pch;
2440         desc->txd.cookie = 0;
2441         async_tx_ack(&desc->txd);
2442
2443         desc->peri = peri_id ? pch->chan.chan_id : 0;
2444         desc->rqcfg.pcfg = &pch->dmac->pcfg;
2445
2446         dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2447
2448         return desc;
2449 }
2450
2451 static inline void fill_px(struct pl330_xfer *px,
2452                 dma_addr_t dst, dma_addr_t src, size_t len)
2453 {
2454         px->bytes = len;
2455         px->dst_addr = dst;
2456         px->src_addr = src;
2457 }
2458
2459 static struct dma_pl330_desc *
2460 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2461                 dma_addr_t src, size_t len)
2462 {
2463         struct dma_pl330_desc *desc = pl330_get_desc(pch);
2464
2465         if (!desc) {
2466                 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2467                         __func__, __LINE__);
2468                 return NULL;
2469         }
2470
2471         /*
2472          * Ideally we should lookout for reqs bigger than
2473          * those that can be programmed with 256 bytes of
2474          * MC buffer, but considering a req size is seldom
2475          * going to be word-unaligned and more than 200MB,
2476          * we take it easy.
2477          * Also, should the limit is reached we'd rather
2478          * have the platform increase MC buffer size than
2479          * complicating this API driver.
2480          */
2481         fill_px(&desc->px, dst, src, len);
2482
2483         return desc;
2484 }
2485
2486 /* Call after fixing burst size */
2487 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2488 {
2489         struct dma_pl330_chan *pch = desc->pchan;
2490         struct pl330_dmac *pl330 = pch->dmac;
2491         int burst_len;
2492
2493         burst_len = pl330->pcfg.data_bus_width / 8;
2494         burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2495         burst_len >>= desc->rqcfg.brst_size;
2496
2497         /* src/dst_burst_len can't be more than 16 */
2498         if (burst_len > 16)
2499                 burst_len = 16;
2500
2501         while (burst_len > 1) {
2502                 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2503                         break;
2504                 burst_len--;
2505         }
2506
2507         return burst_len;
2508 }
2509
2510 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2511                 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2512                 size_t period_len, enum dma_transfer_direction direction,
2513                 unsigned long flags)
2514 {
2515         struct dma_pl330_desc *desc = NULL, *first = NULL;
2516         struct dma_pl330_chan *pch = to_pchan(chan);
2517         struct pl330_dmac *pl330 = pch->dmac;
2518         unsigned int i;
2519         dma_addr_t dst;
2520         dma_addr_t src;
2521
2522         if (len % period_len != 0)
2523                 return NULL;
2524
2525         if (!is_slave_direction(direction)) {
2526                 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2527                 __func__, __LINE__);
2528                 return NULL;
2529         }
2530
2531         for (i = 0; i < len / period_len; i++) {
2532                 desc = pl330_get_desc(pch);
2533                 if (!desc) {
2534                         dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2535                                 __func__, __LINE__);
2536
2537                         if (!first)
2538                                 return NULL;
2539
2540                         spin_lock_irqsave(&pl330->pool_lock, flags);
2541
2542                         while (!list_empty(&first->node)) {
2543                                 desc = list_entry(first->node.next,
2544                                                 struct dma_pl330_desc, node);
2545                                 list_move_tail(&desc->node, &pl330->desc_pool);
2546                         }
2547
2548                         list_move_tail(&first->node, &pl330->desc_pool);
2549
2550                         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2551
2552                         return NULL;
2553                 }
2554
2555                 switch (direction) {
2556                 case DMA_MEM_TO_DEV:
2557                         desc->rqcfg.src_inc = 1;
2558                         desc->rqcfg.dst_inc = 0;
2559                         src = dma_addr;
2560                         dst = pch->fifo_addr;
2561                         break;
2562                 case DMA_DEV_TO_MEM:
2563                         desc->rqcfg.src_inc = 0;
2564                         desc->rqcfg.dst_inc = 1;
2565                         src = pch->fifo_addr;
2566                         dst = dma_addr;
2567                         break;
2568                 default:
2569                         break;
2570                 }
2571
2572                 desc->rqtype = direction;
2573                 desc->rqcfg.brst_size = pch->burst_sz;
2574                 desc->rqcfg.brst_len = 1;
2575                 desc->bytes_requested = period_len;
2576                 fill_px(&desc->px, dst, src, period_len);
2577
2578                 if (!first)
2579                         first = desc;
2580                 else
2581                         list_add_tail(&desc->node, &first->node);
2582
2583                 dma_addr += period_len;
2584         }
2585
2586         if (!desc)
2587                 return NULL;
2588
2589         pch->cyclic = true;
2590         desc->txd.flags = flags;
2591
2592         return &desc->txd;
2593 }
2594
2595 static struct dma_async_tx_descriptor *
2596 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2597                 dma_addr_t src, size_t len, unsigned long flags)
2598 {
2599         struct dma_pl330_desc *desc;
2600         struct dma_pl330_chan *pch = to_pchan(chan);
2601         struct pl330_dmac *pl330;
2602         int burst;
2603
2604         if (unlikely(!pch || !len))
2605                 return NULL;
2606
2607         pl330 = pch->dmac;
2608
2609         desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2610         if (!desc)
2611                 return NULL;
2612
2613         desc->rqcfg.src_inc = 1;
2614         desc->rqcfg.dst_inc = 1;
2615         desc->rqtype = DMA_MEM_TO_MEM;
2616
2617         /* Select max possible burst size */
2618         burst = pl330->pcfg.data_bus_width / 8;
2619
2620         /*
2621          * Make sure we use a burst size that aligns with all the memcpy
2622          * parameters because our DMA programming algorithm doesn't cope with
2623          * transfers which straddle an entry in the DMA device's MFIFO.
2624          */
2625         while ((src | dst | len) & (burst - 1))
2626                 burst /= 2;
2627
2628         desc->rqcfg.brst_size = 0;
2629         while (burst != (1 << desc->rqcfg.brst_size))
2630                 desc->rqcfg.brst_size++;
2631
2632         /*
2633          * If burst size is smaller than bus width then make sure we only
2634          * transfer one at a time to avoid a burst stradling an MFIFO entry.
2635          */
2636         if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2637                 desc->rqcfg.brst_len = 1;
2638
2639         desc->rqcfg.brst_len = get_burst_len(desc, len);
2640         desc->bytes_requested = len;
2641
2642         desc->txd.flags = flags;
2643
2644         return &desc->txd;
2645 }
2646
2647 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2648                                   struct dma_pl330_desc *first)
2649 {
2650         unsigned long flags;
2651         struct dma_pl330_desc *desc;
2652
2653         if (!first)
2654                 return;
2655
2656         spin_lock_irqsave(&pl330->pool_lock, flags);
2657
2658         while (!list_empty(&first->node)) {
2659                 desc = list_entry(first->node.next,
2660                                 struct dma_pl330_desc, node);
2661                 list_move_tail(&desc->node, &pl330->desc_pool);
2662         }
2663
2664         list_move_tail(&first->node, &pl330->desc_pool);
2665
2666         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2667 }
2668
2669 static struct dma_async_tx_descriptor *
2670 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2671                 unsigned int sg_len, enum dma_transfer_direction direction,
2672                 unsigned long flg, void *context)
2673 {
2674         struct dma_pl330_desc *first, *desc = NULL;
2675         struct dma_pl330_chan *pch = to_pchan(chan);
2676         struct scatterlist *sg;
2677         int i;
2678         dma_addr_t addr;
2679
2680         if (unlikely(!pch || !sgl || !sg_len))
2681                 return NULL;
2682
2683         addr = pch->fifo_addr;
2684
2685         first = NULL;
2686
2687         for_each_sg(sgl, sg, sg_len, i) {
2688
2689                 desc = pl330_get_desc(pch);
2690                 if (!desc) {
2691                         struct pl330_dmac *pl330 = pch->dmac;
2692
2693                         dev_err(pch->dmac->ddma.dev,
2694                                 "%s:%d Unable to fetch desc\n",
2695                                 __func__, __LINE__);
2696                         __pl330_giveback_desc(pl330, first);
2697
2698                         return NULL;
2699                 }
2700
2701                 if (!first)
2702                         first = desc;
2703                 else
2704                         list_add_tail(&desc->node, &first->node);
2705
2706                 if (direction == DMA_MEM_TO_DEV) {
2707                         desc->rqcfg.src_inc = 1;
2708                         desc->rqcfg.dst_inc = 0;
2709                         fill_px(&desc->px,
2710                                 addr, sg_dma_address(sg), sg_dma_len(sg));
2711                 } else {
2712                         desc->rqcfg.src_inc = 0;
2713                         desc->rqcfg.dst_inc = 1;
2714                         fill_px(&desc->px,
2715                                 sg_dma_address(sg), addr, sg_dma_len(sg));
2716                 }
2717
2718                 desc->rqcfg.brst_size = pch->burst_sz;
2719                 desc->rqcfg.brst_len = 1;
2720                 desc->rqtype = direction;
2721                 desc->bytes_requested = sg_dma_len(sg);
2722         }
2723
2724         /* Return the last desc in the chain */
2725         desc->txd.flags = flg;
2726         return &desc->txd;
2727 }
2728
2729 static irqreturn_t pl330_irq_handler(int irq, void *data)
2730 {
2731         if (pl330_update(data))
2732                 return IRQ_HANDLED;
2733         else
2734                 return IRQ_NONE;
2735 }
2736
2737 #define PL330_DMA_BUSWIDTHS \
2738         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2739         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2740         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2741         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2742         BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2743
2744 /*
2745  * Runtime PM callbacks are provided by amba/bus.c driver.
2746  *
2747  * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2748  * bus driver will only disable/enable the clock in runtime PM callbacks.
2749  */
2750 static int __maybe_unused pl330_suspend(struct device *dev)
2751 {
2752         struct amba_device *pcdev = to_amba_device(dev);
2753
2754         pm_runtime_disable(dev);
2755
2756         if (!pm_runtime_status_suspended(dev)) {
2757                 /* amba did not disable the clock */
2758                 amba_pclk_disable(pcdev);
2759         }
2760         amba_pclk_unprepare(pcdev);
2761
2762         return 0;
2763 }
2764
2765 static int __maybe_unused pl330_resume(struct device *dev)
2766 {
2767         struct amba_device *pcdev = to_amba_device(dev);
2768         int ret;
2769
2770         ret = amba_pclk_prepare(pcdev);
2771         if (ret)
2772                 return ret;
2773
2774         if (!pm_runtime_status_suspended(dev))
2775                 ret = amba_pclk_enable(pcdev);
2776
2777         pm_runtime_enable(dev);
2778
2779         return ret;
2780 }
2781
2782 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2783
2784 static int
2785 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2786 {
2787         struct dma_pl330_platdata *pdat;
2788         struct pl330_config *pcfg;
2789         struct pl330_dmac *pl330;
2790         struct dma_pl330_chan *pch, *_p;
2791         struct dma_device *pd;
2792         struct resource *res;
2793         int i, ret, irq;
2794         int num_chan;
2795
2796         pdat = dev_get_platdata(&adev->dev);
2797
2798         ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2799         if (ret)
2800                 return ret;
2801
2802         /* Allocate a new DMAC and its Channels */
2803         pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2804         if (!pl330) {
2805                 dev_err(&adev->dev, "unable to allocate mem\n");
2806                 return -ENOMEM;
2807         }
2808
2809         pd = &pl330->ddma;
2810         pd->dev = &adev->dev;
2811
2812         pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2813
2814         res = &adev->res;
2815         pl330->base = devm_ioremap_resource(&adev->dev, res);
2816         if (IS_ERR(pl330->base))
2817                 return PTR_ERR(pl330->base);
2818
2819         amba_set_drvdata(adev, pl330);
2820
2821         for (i = 0; i < AMBA_NR_IRQS; i++) {
2822                 irq = adev->irq[i];
2823                 if (irq) {
2824                         ret = devm_request_irq(&adev->dev, irq,
2825                                                pl330_irq_handler, 0,
2826                                                dev_name(&adev->dev), pl330);
2827                         if (ret)
2828                                 return ret;
2829                 } else {
2830                         break;
2831                 }
2832         }
2833
2834         pcfg = &pl330->pcfg;
2835
2836         pcfg->periph_id = adev->periphid;
2837         ret = pl330_add(pl330);
2838         if (ret)
2839                 return ret;
2840
2841         INIT_LIST_HEAD(&pl330->desc_pool);
2842         spin_lock_init(&pl330->pool_lock);
2843
2844         /* Create a descriptor pool of default size */
2845         if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2846                 dev_warn(&adev->dev, "unable to allocate desc\n");
2847
2848         INIT_LIST_HEAD(&pd->channels);
2849
2850         /* Initialize channel parameters */
2851         if (pdat)
2852                 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2853         else
2854                 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2855
2856         pl330->num_peripherals = num_chan;
2857
2858         pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2859         if (!pl330->peripherals) {
2860                 ret = -ENOMEM;
2861                 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2862                 goto probe_err2;
2863         }
2864
2865         for (i = 0; i < num_chan; i++) {
2866                 pch = &pl330->peripherals[i];
2867                 if (!adev->dev.of_node)
2868                         pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2869                 else
2870                         pch->chan.private = adev->dev.of_node;
2871
2872                 INIT_LIST_HEAD(&pch->submitted_list);
2873                 INIT_LIST_HEAD(&pch->work_list);
2874                 INIT_LIST_HEAD(&pch->completed_list);
2875                 spin_lock_init(&pch->lock);
2876                 pch->thread = NULL;
2877                 pch->chan.device = pd;
2878                 pch->dmac = pl330;
2879
2880                 /* Add the channel to the DMAC list */
2881                 list_add_tail(&pch->chan.device_node, &pd->channels);
2882         }
2883
2884         if (pdat) {
2885                 pd->cap_mask = pdat->cap_mask;
2886         } else {
2887                 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2888                 if (pcfg->num_peri) {
2889                         dma_cap_set(DMA_SLAVE, pd->cap_mask);
2890                         dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2891                         dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2892                 }
2893         }
2894
2895         pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2896         pd->device_free_chan_resources = pl330_free_chan_resources;
2897         pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2898         pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2899         pd->device_tx_status = pl330_tx_status;
2900         pd->device_prep_slave_sg = pl330_prep_slave_sg;
2901         pd->device_config = pl330_config;
2902         pd->device_pause = pl330_pause;
2903         pd->device_terminate_all = pl330_terminate_all;
2904         pd->device_issue_pending = pl330_issue_pending;
2905         pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2906         pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2907         pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2908         pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2909
2910         ret = dma_async_device_register(pd);
2911         if (ret) {
2912                 dev_err(&adev->dev, "unable to register DMAC\n");
2913                 goto probe_err3;
2914         }
2915
2916         if (adev->dev.of_node) {
2917                 ret = of_dma_controller_register(adev->dev.of_node,
2918                                          of_dma_pl330_xlate, pl330);
2919                 if (ret) {
2920                         dev_err(&adev->dev,
2921                         "unable to register DMA to the generic DT DMA helpers\n");
2922                 }
2923         }
2924
2925         adev->dev.dma_parms = &pl330->dma_parms;
2926
2927         /*
2928          * This is the limit for transfers with a buswidth of 1, larger
2929          * buswidths will have larger limits.
2930          */
2931         ret = dma_set_max_seg_size(&adev->dev, 1900800);
2932         if (ret)
2933                 dev_err(&adev->dev, "unable to set the seg size\n");
2934
2935
2936         dev_info(&adev->dev,
2937                 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2938         dev_info(&adev->dev,
2939                 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2940                 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2941                 pcfg->num_peri, pcfg->num_events);
2942
2943         pm_runtime_irq_safe(&adev->dev);
2944         pm_runtime_use_autosuspend(&adev->dev);
2945         pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2946         pm_runtime_mark_last_busy(&adev->dev);
2947         pm_runtime_put_autosuspend(&adev->dev);
2948
2949         return 0;
2950 probe_err3:
2951         /* Idle the DMAC */
2952         list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2953                         chan.device_node) {
2954
2955                 /* Remove the channel */
2956                 list_del(&pch->chan.device_node);
2957
2958                 /* Flush the channel */
2959                 if (pch->thread) {
2960                         pl330_terminate_all(&pch->chan);
2961                         pl330_free_chan_resources(&pch->chan);
2962                 }
2963         }
2964 probe_err2:
2965         pl330_del(pl330);
2966
2967         return ret;
2968 }
2969
2970 static int pl330_remove(struct amba_device *adev)
2971 {
2972         struct pl330_dmac *pl330 = amba_get_drvdata(adev);
2973         struct dma_pl330_chan *pch, *_p;
2974
2975         pm_runtime_get_noresume(pl330->ddma.dev);
2976
2977         if (adev->dev.of_node)
2978                 of_dma_controller_free(adev->dev.of_node);
2979
2980         dma_async_device_unregister(&pl330->ddma);
2981
2982         /* Idle the DMAC */
2983         list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2984                         chan.device_node) {
2985
2986                 /* Remove the channel */
2987                 list_del(&pch->chan.device_node);
2988
2989                 /* Flush the channel */
2990                 if (pch->thread) {
2991                         pl330_terminate_all(&pch->chan);
2992                         pl330_free_chan_resources(&pch->chan);
2993                 }
2994         }
2995
2996         pl330_del(pl330);
2997
2998         return 0;
2999 }
3000
3001 static struct amba_id pl330_ids[] = {
3002         {
3003                 .id     = 0x00041330,
3004                 .mask   = 0x000fffff,
3005         },
3006         { 0, 0 },
3007 };
3008
3009 MODULE_DEVICE_TABLE(amba, pl330_ids);
3010
3011 static struct amba_driver pl330_driver = {
3012         .drv = {
3013                 .owner = THIS_MODULE,
3014                 .name = "dma-pl330",
3015                 .pm = &pl330_pm,
3016         },
3017         .id_table = pl330_ids,
3018         .probe = pl330_probe,
3019         .remove = pl330_remove,
3020 };
3021
3022 module_amba_driver(pl330_driver);
3023
3024 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3025 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3026 MODULE_LICENSE("GPL");