kernel/drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called COPYING.
  16  */
  17 #ifndef _IOAT_HW_H_
  18 #define _IOAT_HW_H_
  19
  20 /* PCI Configuration Space Values */
  21 #define IOAT_MMIO_BAR           0
  22
  23 /* CB device ID's */
  24 #define IOAT_PCI_DID_5000       0x1A38
  25 #define IOAT_PCI_DID_CNB        0x360B
  26 #define IOAT_PCI_DID_SCNB       0x65FF
  27 #define IOAT_PCI_DID_SNB        0x402F
  28
  29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  34 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  35 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  36 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  37 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  38 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  39
  40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  45 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  46 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  47 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  48 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  49 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  50
  51 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  52 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  53 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  54 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  55
  56 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  57 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  58 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  59 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  60
  61 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  62 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  63 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  64 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  65 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  66
  67
  68 int system_has_dca_enabled(struct pci_dev *pdev);
  69
  70 struct ioat_dma_descriptor {
  71         uint32_t        size;
  72         union {
  73                 uint32_t ctl;
  74                 struct {
  75                         unsigned int int_en:1;
  76                         unsigned int src_snoop_dis:1;
  77                         unsigned int dest_snoop_dis:1;
  78                         unsigned int compl_write:1;
  79                         unsigned int fence:1;
  80                         unsigned int null:1;
  81                         unsigned int src_brk:1;
  82                         unsigned int dest_brk:1;
  83                         unsigned int bundle:1;
  84                         unsigned int dest_dca:1;
  85                         unsigned int hint:1;
  86                         unsigned int rsvd2:13;
  87                         #define IOAT_OP_COPY 0x00
  88                         unsigned int op:8;
  89                 } ctl_f;
  90         };
  91         uint64_t        src_addr;
  92         uint64_t        dst_addr;
  93         uint64_t        next;
  94         uint64_t        rsv1;
  95         uint64_t        rsv2;
  96         /* store some driver data in an unused portion of the descriptor */
  97         union {
  98                 uint64_t        user1;
  99                 uint64_t        tx_cnt;
 100         };
 101         uint64_t        user2;
 102 };
 103
 104 struct ioat_xor_descriptor {
 105         uint32_t        size;
 106         union {
 107                 uint32_t ctl;
 108                 struct {
 109                         unsigned int int_en:1;
 110                         unsigned int src_snoop_dis:1;
 111                         unsigned int dest_snoop_dis:1;
 112                         unsigned int compl_write:1;
 113                         unsigned int fence:1;
 114                         unsigned int src_cnt:3;
 115                         unsigned int bundle:1;
 116                         unsigned int dest_dca:1;
 117                         unsigned int hint:1;
 118                         unsigned int rsvd:13;
 119                         #define IOAT_OP_XOR 0x87
 120                         #define IOAT_OP_XOR_VAL 0x88
 121                         unsigned int op:8;
 122                 } ctl_f;
 123         };
 124         uint64_t        src_addr;
 125         uint64_t        dst_addr;
 126         uint64_t        next;
 127         uint64_t        src_addr2;
 128         uint64_t        src_addr3;
 129         uint64_t        src_addr4;
 130         uint64_t        src_addr5;
 131 };
 132
 133 struct ioat_xor_ext_descriptor {
 134         uint64_t        src_addr6;
 135         uint64_t        src_addr7;
 136         uint64_t        src_addr8;
 137         uint64_t        next;
 138         uint64_t        rsvd[4];
 139 };
 140
 141 struct ioat_pq_descriptor {
 142         union {
 143                 uint32_t        size;
 144                 uint32_t        dwbes;
 145                 struct {
 146                         unsigned int rsvd:25;
 147                         unsigned int p_val_err:1;
 148                         unsigned int q_val_err:1;
 149                         unsigned int rsvd1:4;
 150                         unsigned int wbes:1;
 151                 } dwbes_f;
 152         };
 153         union {
 154                 uint32_t ctl;
 155                 struct {
 156                         unsigned int int_en:1;
 157                         unsigned int src_snoop_dis:1;
 158                         unsigned int dest_snoop_dis:1;
 159                         unsigned int compl_write:1;
 160                         unsigned int fence:1;
 161                         unsigned int src_cnt:3;
 162                         unsigned int bundle:1;
 163                         unsigned int dest_dca:1;
 164                         unsigned int hint:1;
 165                         unsigned int p_disable:1;
 166                         unsigned int q_disable:1;
 167                         unsigned int rsvd2:2;
 168                         unsigned int wb_en:1;
 169                         unsigned int prl_en:1;
 170                         unsigned int rsvd3:7;
 171                         #define IOAT_OP_PQ 0x89
 172                         #define IOAT_OP_PQ_VAL 0x8a
 173                         #define IOAT_OP_PQ_16S 0xa0
 174                         #define IOAT_OP_PQ_VAL_16S 0xa1
 175                         unsigned int op:8;
 176                 } ctl_f;
 177         };
 178         uint64_t        src_addr;
 179         uint64_t        p_addr;
 180         uint64_t        next;
 181         uint64_t        src_addr2;
 182         union {
 183                 uint64_t        src_addr3;
 184                 uint64_t        sed_addr;
 185         };
 186         uint8_t         coef[8];
 187         uint64_t        q_addr;
 188 };
 189
 190 struct ioat_pq_ext_descriptor {
 191         uint64_t        src_addr4;
 192         uint64_t        src_addr5;
 193         uint64_t        src_addr6;
 194         uint64_t        next;
 195         uint64_t        src_addr7;
 196         uint64_t        src_addr8;
 197         uint64_t        rsvd[2];
 198 };
 199
 200 struct ioat_pq_update_descriptor {
 201         uint32_t        size;
 202         union {
 203                 uint32_t ctl;
 204                 struct {
 205                         unsigned int int_en:1;
 206                         unsigned int src_snoop_dis:1;
 207                         unsigned int dest_snoop_dis:1;
 208                         unsigned int compl_write:1;
 209                         unsigned int fence:1;
 210                         unsigned int src_cnt:3;
 211                         unsigned int bundle:1;
 212                         unsigned int dest_dca:1;
 213                         unsigned int hint:1;
 214                         unsigned int p_disable:1;
 215                         unsigned int q_disable:1;
 216                         unsigned int rsvd:3;
 217                         unsigned int coef:8;
 218                         #define IOAT_OP_PQ_UP 0x8b
 219                         unsigned int op:8;
 220                 } ctl_f;
 221         };
 222         uint64_t        src_addr;
 223         uint64_t        p_addr;
 224         uint64_t        next;
 225         uint64_t        src_addr2;
 226         uint64_t        p_src;
 227         uint64_t        q_src;
 228         uint64_t        q_addr;
 229 };
 230
 231 struct ioat_raw_descriptor {
 232         uint64_t        field[8];
 233 };
 234
 235 struct ioat_pq16a_descriptor {
 236         uint8_t coef[8];
 237         uint64_t src_addr3;
 238         uint64_t src_addr4;
 239         uint64_t src_addr5;
 240         uint64_t src_addr6;
 241         uint64_t src_addr7;
 242         uint64_t src_addr8;
 243         uint64_t src_addr9;
 244 };
 245
 246 struct ioat_pq16b_descriptor {
 247         uint64_t src_addr10;
 248         uint64_t src_addr11;
 249         uint64_t src_addr12;
 250         uint64_t src_addr13;
 251         uint64_t src_addr14;
 252         uint64_t src_addr15;
 253         uint64_t src_addr16;
 254         uint64_t rsvd;
 255 };
 256
 257 union ioat_sed_pq_descriptor {
 258         struct ioat_pq16a_descriptor a;
 259         struct ioat_pq16b_descriptor b;
 260 };
 261
 262 #define SED_SIZE        64
 263
 264 struct ioat_sed_raw_descriptor {
 265         uint64_t        a[8];
 266         uint64_t        b[8];
 267         uint64_t        c[8];
 268 };
 269
 270 #endif