kernel/drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/bitops.h>
  24 #include <linux/mm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/semaphore.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/device.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/firmware.h>
  34 #include <linux/slab.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_dma.h>
  40
  41 #include <asm/irq.h>
  42 #include <linux/platform_data/dma-imx-sdma.h>
  43 #include <linux/platform_data/dma-imx.h>
  44
  45 #include "dmaengine.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  * Mode/Count of data node descriptors - IPCv2
 128  */
 129 struct sdma_mode_count {
 130         u32 count   : 16; /* size of the buffer pointed by this BD */
 131         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 132         u32 command :  8; /* command mostlky used for channel 0 */
 133 };
 134
 135 /*
 136  * Buffer descriptor
 137  */
 138 struct sdma_buffer_descriptor {
 139         struct sdma_mode_count  mode;
 140         u32 buffer_addr;        /* address of the buffer described */
 141         u32 ext_buffer_addr;    /* extended buffer address */
 142 } __attribute__ ((packed));
 143
 144 /**
 145  * struct sdma_channel_control - Channel control Block
 146  *
 147  * @current_bd_ptr      current buffer descriptor processed
 148  * @base_bd_ptr         first element of buffer descriptor array
 149  * @unused              padding. The SDMA engine expects an array of 128 byte
 150  *                      control blocks
 151  */
 152 struct sdma_channel_control {
 153         u32 current_bd_ptr;
 154         u32 base_bd_ptr;
 155         u32 unused[2];
 156 } __attribute__ ((packed));
 157
 158 /**
 159  * struct sdma_state_registers - SDMA context for a channel
 160  *
 161  * @pc:         program counter
 162  * @t:          test bit: status of arithmetic & test instruction
 163  * @rpc:        return program counter
 164  * @sf:         source fault while loading data
 165  * @spc:        loop start program counter
 166  * @df:         destination fault while storing data
 167  * @epc:        loop end program counter
 168  * @lm:         loop mode
 169  */
 170 struct sdma_state_registers {
 171         u32 pc     :14;
 172         u32 unused1: 1;
 173         u32 t      : 1;
 174         u32 rpc    :14;
 175         u32 unused0: 1;
 176         u32 sf     : 1;
 177         u32 spc    :14;
 178         u32 unused2: 1;
 179         u32 df     : 1;
 180         u32 epc    :14;
 181         u32 lm     : 2;
 182 } __attribute__ ((packed));
 183
 184 /**
 185  * struct sdma_context_data - sdma context specific to a channel
 186  *
 187  * @channel_state:      channel state bits
 188  * @gReg:               general registers
 189  * @mda:                burst dma destination address register
 190  * @msa:                burst dma source address register
 191  * @ms:                 burst dma status register
 192  * @md:                 burst dma data register
 193  * @pda:                peripheral dma destination address register
 194  * @psa:                peripheral dma source address register
 195  * @ps:                 peripheral dma status register
 196  * @pd:                 peripheral dma data register
 197  * @ca:                 CRC polynomial register
 198  * @cs:                 CRC accumulator register
 199  * @dda:                dedicated core destination address register
 200  * @dsa:                dedicated core source address register
 201  * @ds:                 dedicated core status register
 202  * @dd:                 dedicated core data register
 203  */
 204 struct sdma_context_data {
 205         struct sdma_state_registers  channel_state;
 206         u32  gReg[8];
 207         u32  mda;
 208         u32  msa;
 209         u32  ms;
 210         u32  md;
 211         u32  pda;
 212         u32  psa;
 213         u32  ps;
 214         u32  pd;
 215         u32  ca;
 216         u32  cs;
 217         u32  dda;
 218         u32  dsa;
 219         u32  ds;
 220         u32  dd;
 221         u32  scratch0;
 222         u32  scratch1;
 223         u32  scratch2;
 224         u32  scratch3;
 225         u32  scratch4;
 226         u32  scratch5;
 227         u32  scratch6;
 228         u32  scratch7;
 229 } __attribute__ ((packed));
 230
 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 232
 233 struct sdma_engine;
 234
 235 /**
 236  * struct sdma_channel - housekeeping for a SDMA channel
 237  *
 238  * @sdma                pointer to the SDMA engine for this channel
 239  * @channel             the channel number, matches dmaengine chan_id + 1
 240  * @direction           transfer type. Needed for setting SDMA script
 241  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 242  * @event_id0           aka dma request line
 243  * @event_id1           for channels that use 2 events
 244  * @word_size           peripheral access size
 245  * @buf_tail            ID of the buffer that was processed
 246  * @num_bd              max NUM_BD. number of descriptors currently handling
 247  */
 248 struct sdma_channel {
 249         struct sdma_engine              *sdma;
 250         unsigned int                    channel;
 251         enum dma_transfer_direction             direction;
 252         enum sdma_peripheral_type       peripheral_type;
 253         unsigned int                    event_id0;
 254         unsigned int                    event_id1;
 255         enum dma_slave_buswidth         word_size;
 256         unsigned int                    buf_tail;
 257         unsigned int                    num_bd;
 258         unsigned int                    period_len;
 259         struct sdma_buffer_descriptor   *bd;
 260         dma_addr_t                      bd_phys;
 261         unsigned int                    pc_from_device, pc_to_device;
 262         unsigned long                   flags;
 263         dma_addr_t                      per_address;
 264         unsigned long                   event_mask[2];
 265         unsigned long                   watermark_level;
 266         u32                             shp_addr, per_addr;
 267         struct dma_chan                 chan;
 268         spinlock_t                      lock;
 269         struct dma_async_tx_descriptor  desc;
 270         enum dma_status                 status;
 271         unsigned int                    chn_count;
 272         unsigned int                    chn_real_count;
 273         struct tasklet_struct           tasklet;
 274         struct imx_dma_data             data;
 275 };
 276
 277 #define IMX_DMA_SG_LOOP         BIT(0)
 278
 279 #define MAX_DMA_CHANNELS 32
 280 #define MXC_SDMA_DEFAULT_PRIORITY 1
 281 #define MXC_SDMA_MIN_PRIORITY 1
 282 #define MXC_SDMA_MAX_PRIORITY 7
 283
 284 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 285
 286 /**
 287  * struct sdma_firmware_header - Layout of the firmware image
 288  *
 289  * @magic               "SDMA"
 290  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 291  *                      changes.
 292  * @version_minor       firmware minor version (for binary compatible changes)
 293  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 294  * @num_script_addrs    Number of script addresses in this image
 295  * @ram_code_start      offset of SDMA ram image in this firmware image
 296  * @ram_code_size       size of SDMA ram image
 297  * @script_addrs        Stores the start address of the SDMA scripts
 298  *                      (in SDMA memory space)
 299  */
 300 struct sdma_firmware_header {
 301         u32     magic;
 302         u32     version_major;
 303         u32     version_minor;
 304         u32     script_addrs_start;
 305         u32     num_script_addrs;
 306         u32     ram_code_start;
 307         u32     ram_code_size;
 308 };
 309
 310 struct sdma_driver_data {
 311         int chnenbl0;
 312         int num_events;
 313         struct sdma_script_start_addrs  *script_addrs;
 314 };
 315
 316 struct sdma_engine {
 317         struct device                   *dev;
 318         struct device_dma_parameters    dma_parms;
 319         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 320         struct sdma_channel_control     *channel_control;
 321         void __iomem                    *regs;
 322         struct sdma_context_data        *context;
 323         dma_addr_t                      context_phys;
 324         struct dma_device               dma_device;
 325         struct clk                      *clk_ipg;
 326         struct clk                      *clk_ahb;
 327         spinlock_t                      channel_0_lock;
 328         u32                             script_number;
 329         struct sdma_script_start_addrs  *script_addrs;
 330         const struct sdma_driver_data   *drvdata;
 331 };
 332
 333 static struct sdma_driver_data sdma_imx31 = {
 334         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 335         .num_events = 32,
 336 };
 337
 338 static struct sdma_script_start_addrs sdma_script_imx25 = {
 339         .ap_2_ap_addr = 729,
 340         .uart_2_mcu_addr = 904,
 341         .per_2_app_addr = 1255,
 342         .mcu_2_app_addr = 834,
 343         .uartsh_2_mcu_addr = 1120,
 344         .per_2_shp_addr = 1329,
 345         .mcu_2_shp_addr = 1048,
 346         .ata_2_mcu_addr = 1560,
 347         .mcu_2_ata_addr = 1479,
 348         .app_2_per_addr = 1189,
 349         .app_2_mcu_addr = 770,
 350         .shp_2_per_addr = 1407,
 351         .shp_2_mcu_addr = 979,
 352 };
 353
 354 static struct sdma_driver_data sdma_imx25 = {
 355         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 356         .num_events = 48,
 357         .script_addrs = &sdma_script_imx25,
 358 };
 359
 360 static struct sdma_driver_data sdma_imx35 = {
 361         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 362         .num_events = 48,
 363 };
 364
 365 static struct sdma_script_start_addrs sdma_script_imx51 = {
 366         .ap_2_ap_addr = 642,
 367         .uart_2_mcu_addr = 817,
 368         .mcu_2_app_addr = 747,
 369         .mcu_2_shp_addr = 961,
 370         .ata_2_mcu_addr = 1473,
 371         .mcu_2_ata_addr = 1392,
 372         .app_2_per_addr = 1033,
 373         .app_2_mcu_addr = 683,
 374         .shp_2_per_addr = 1251,
 375         .shp_2_mcu_addr = 892,
 376 };
 377
 378 static struct sdma_driver_data sdma_imx51 = {
 379         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 380         .num_events = 48,
 381         .script_addrs = &sdma_script_imx51,
 382 };
 383
 384 static struct sdma_script_start_addrs sdma_script_imx53 = {
 385         .ap_2_ap_addr = 642,
 386         .app_2_mcu_addr = 683,
 387         .mcu_2_app_addr = 747,
 388         .uart_2_mcu_addr = 817,
 389         .shp_2_mcu_addr = 891,
 390         .mcu_2_shp_addr = 960,
 391         .uartsh_2_mcu_addr = 1032,
 392         .spdif_2_mcu_addr = 1100,
 393         .mcu_2_spdif_addr = 1134,
 394         .firi_2_mcu_addr = 1193,
 395         .mcu_2_firi_addr = 1290,
 396 };
 397
 398 static struct sdma_driver_data sdma_imx53 = {
 399         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 400         .num_events = 48,
 401         .script_addrs = &sdma_script_imx53,
 402 };
 403
 404 static struct sdma_script_start_addrs sdma_script_imx6q = {
 405         .ap_2_ap_addr = 642,
 406         .uart_2_mcu_addr = 817,
 407         .mcu_2_app_addr = 747,
 408         .per_2_per_addr = 6331,
 409         .uartsh_2_mcu_addr = 1032,
 410         .mcu_2_shp_addr = 960,
 411         .app_2_mcu_addr = 683,
 412         .shp_2_mcu_addr = 891,
 413         .spdif_2_mcu_addr = 1100,
 414         .mcu_2_spdif_addr = 1134,
 415 };
 416
 417 static struct sdma_driver_data sdma_imx6q = {
 418         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 419         .num_events = 48,
 420         .script_addrs = &sdma_script_imx6q,
 421 };
 422
 423 static struct platform_device_id sdma_devtypes[] = {
 424         {
 425                 .name = "imx25-sdma",
 426                 .driver_data = (unsigned long)&sdma_imx25,
 427         }, {
 428                 .name = "imx31-sdma",
 429                 .driver_data = (unsigned long)&sdma_imx31,
 430         }, {
 431                 .name = "imx35-sdma",
 432                 .driver_data = (unsigned long)&sdma_imx35,
 433         }, {
 434                 .name = "imx51-sdma",
 435                 .driver_data = (unsigned long)&sdma_imx51,
 436         }, {
 437                 .name = "imx53-sdma",
 438                 .driver_data = (unsigned long)&sdma_imx53,
 439         }, {
 440                 .name = "imx6q-sdma",
 441                 .driver_data = (unsigned long)&sdma_imx6q,
 442         }, {
 443                 /* sentinel */
 444         }
 445 };
 446 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 447
 448 static const struct of_device_id sdma_dt_ids[] = {
 449         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 450         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 451         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 452         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 453         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 454         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 455         { /* sentinel */ }
 456 };
 457 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 458
 459 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 460 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 461 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 462 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 463
 464 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 465 {
 466         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 467         return chnenbl0 + event * 4;
 468 }
 469
 470 static int sdma_config_ownership(struct sdma_channel *sdmac,
 471                 bool event_override, bool mcu_override, bool dsp_override)
 472 {
 473         struct sdma_engine *sdma = sdmac->sdma;
 474         int channel = sdmac->channel;
 475         unsigned long evt, mcu, dsp;
 476
 477         if (event_override && mcu_override && dsp_override)
 478                 return -EINVAL;
 479
 480         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 481         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 482         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 483
 484         if (dsp_override)
 485                 __clear_bit(channel, &dsp);
 486         else
 487                 __set_bit(channel, &dsp);
 488
 489         if (event_override)
 490                 __clear_bit(channel, &evt);
 491         else
 492                 __set_bit(channel, &evt);
 493
 494         if (mcu_override)
 495                 __clear_bit(channel, &mcu);
 496         else
 497                 __set_bit(channel, &mcu);
 498
 499         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 500         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 501         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 502
 503         return 0;
 504 }
 505
 506 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 507 {
 508         writel(BIT(channel), sdma->regs + SDMA_H_START);
 509 }
 510
 511 /*
 512  * sdma_run_channel0 - run a channel and wait till it's done
 513  */
 514 static int sdma_run_channel0(struct sdma_engine *sdma)
 515 {
 516         int ret;
 517         unsigned long timeout = 500;
 518
 519         sdma_enable_channel(sdma, 0);
 520
 521         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
 522                 if (timeout-- <= 0)
 523                         break;
 524                 udelay(1);
 525         }
 526
 527         if (ret) {
 528                 /* Clear the interrupt status */
 529                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
 530         } else {
 531                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 532         }
 533
 534         /* Set bits of CONFIG register with dynamic context switching */
 535         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 536                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 537
 538         return ret ? 0 : -ETIMEDOUT;
 539 }
 540
 541 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 542                 u32 address)
 543 {
 544         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 545         void *buf_virt;
 546         dma_addr_t buf_phys;
 547         int ret;
 548         unsigned long flags;
 549
 550         buf_virt = dma_alloc_coherent(NULL,
 551                         size,
 552                         &buf_phys, GFP_KERNEL);
 553         if (!buf_virt) {
 554                 return -ENOMEM;
 555         }
 556
 557         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 558
 559         bd0->mode.command = C0_SETPM;
 560         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 561         bd0->mode.count = size / 2;
 562         bd0->buffer_addr = buf_phys;
 563         bd0->ext_buffer_addr = address;
 564
 565         memcpy(buf_virt, buf, size);
 566
 567         ret = sdma_run_channel0(sdma);
 568
 569         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 570
 571         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 572
 573         return ret;
 574 }
 575
 576 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 577 {
 578         struct sdma_engine *sdma = sdmac->sdma;
 579         int channel = sdmac->channel;
 580         unsigned long val;
 581         u32 chnenbl = chnenbl_ofs(sdma, event);
 582
 583         val = readl_relaxed(sdma->regs + chnenbl);
 584         __set_bit(channel, &val);
 585         writel_relaxed(val, sdma->regs + chnenbl);
 586 }
 587
 588 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 589 {
 590         struct sdma_engine *sdma = sdmac->sdma;
 591         int channel = sdmac->channel;
 592         u32 chnenbl = chnenbl_ofs(sdma, event);
 593         unsigned long val;
 594
 595         val = readl_relaxed(sdma->regs + chnenbl);
 596         __clear_bit(channel, &val);
 597         writel_relaxed(val, sdma->regs + chnenbl);
 598 }
 599
 600 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 601 {
 602         if (sdmac->desc.callback)
 603                 sdmac->desc.callback(sdmac->desc.callback_param);
 604 }
 605
 606 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 607 {
 608         struct sdma_buffer_descriptor *bd;
 609
 610         /*
 611          * loop mode. Iterate over descriptors, re-setup them and
 612          * call callback function.
 613          */
 614         while (1) {
 615                 bd = &sdmac->bd[sdmac->buf_tail];
 616
 617                 if (bd->mode.status & BD_DONE)
 618                         break;
 619
 620                 if (bd->mode.status & BD_RROR)
 621                         sdmac->status = DMA_ERROR;
 622
 623                 bd->mode.status |= BD_DONE;
 624                 sdmac->buf_tail++;
 625                 sdmac->buf_tail %= sdmac->num_bd;
 626         }
 627 }
 628
 629 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 630 {
 631         struct sdma_buffer_descriptor *bd;
 632         int i, error = 0;
 633
 634         sdmac->chn_real_count = 0;
 635         /*
 636          * non loop mode. Iterate over all descriptors, collect
 637          * errors and call callback function
 638          */
 639         for (i = 0; i < sdmac->num_bd; i++) {
 640                 bd = &sdmac->bd[i];
 641
 642                  if (bd->mode.status & (BD_DONE | BD_RROR))
 643                         error = -EIO;
 644                  sdmac->chn_real_count += bd->mode.count;
 645         }
 646
 647         if (error)
 648                 sdmac->status = DMA_ERROR;
 649         else
 650                 sdmac->status = DMA_COMPLETE;
 651
 652         dma_cookie_complete(&sdmac->desc);
 653         if (sdmac->desc.callback)
 654                 sdmac->desc.callback(sdmac->desc.callback_param);
 655 }
 656
 657 static void sdma_tasklet(unsigned long data)
 658 {
 659         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 660
 661         if (sdmac->flags & IMX_DMA_SG_LOOP)
 662                 sdma_handle_channel_loop(sdmac);
 663         else
 664                 mxc_sdma_handle_channel_normal(sdmac);
 665 }
 666
 667 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 668 {
 669         struct sdma_engine *sdma = dev_id;
 670         unsigned long stat;
 671
 672         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 673         /* not interested in channel 0 interrupts */
 674         stat &= ~1;
 675         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 676
 677         while (stat) {
 678                 int channel = fls(stat) - 1;
 679                 struct sdma_channel *sdmac = &sdma->channel[channel];
 680
 681                 if (sdmac->flags & IMX_DMA_SG_LOOP)
 682                         sdma_update_channel_loop(sdmac);
 683
 684                 tasklet_schedule(&sdmac->tasklet);
 685
 686                 __clear_bit(channel, &stat);
 687         }
 688
 689         return IRQ_HANDLED;
 690 }
 691
 692 /*
 693  * sets the pc of SDMA script according to the peripheral type
 694  */
 695 static void sdma_get_pc(struct sdma_channel *sdmac,
 696                 enum sdma_peripheral_type peripheral_type)
 697 {
 698         struct sdma_engine *sdma = sdmac->sdma;
 699         int per_2_emi = 0, emi_2_per = 0;
 700         /*
 701          * These are needed once we start to support transfers between
 702          * two peripherals or memory-to-memory transfers
 703          */
 704         int per_2_per = 0, emi_2_emi = 0;
 705
 706         sdmac->pc_from_device = 0;
 707         sdmac->pc_to_device = 0;
 708
 709         switch (peripheral_type) {
 710         case IMX_DMATYPE_MEMORY:
 711                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 712                 break;
 713         case IMX_DMATYPE_DSP:
 714                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 715                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 716                 break;
 717         case IMX_DMATYPE_FIRI:
 718                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 719                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 720                 break;
 721         case IMX_DMATYPE_UART:
 722                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 723                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 724                 break;
 725         case IMX_DMATYPE_UART_SP:
 726                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 727                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 728                 break;
 729         case IMX_DMATYPE_ATA:
 730                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 731                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 732                 break;
 733         case IMX_DMATYPE_CSPI:
 734         case IMX_DMATYPE_EXT:
 735         case IMX_DMATYPE_SSI:
 736         case IMX_DMATYPE_SAI:
 737                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 738                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 739                 break;
 740         case IMX_DMATYPE_SSI_DUAL:
 741                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 742                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 743                 break;
 744         case IMX_DMATYPE_SSI_SP:
 745         case IMX_DMATYPE_MMC:
 746         case IMX_DMATYPE_SDHC:
 747         case IMX_DMATYPE_CSPI_SP:
 748         case IMX_DMATYPE_ESAI:
 749         case IMX_DMATYPE_MSHC_SP:
 750                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 751                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 752                 break;
 753         case IMX_DMATYPE_ASRC:
 754                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 755                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 756                 per_2_per = sdma->script_addrs->per_2_per_addr;
 757                 break;
 758         case IMX_DMATYPE_ASRC_SP:
 759                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 760                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 761                 per_2_per = sdma->script_addrs->per_2_per_addr;
 762                 break;
 763         case IMX_DMATYPE_MSHC:
 764                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 765                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 766                 break;
 767         case IMX_DMATYPE_CCM:
 768                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 769                 break;
 770         case IMX_DMATYPE_SPDIF:
 771                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 772                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 773                 break;
 774         case IMX_DMATYPE_IPU_MEMORY:
 775                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 776                 break;
 777         default:
 778                 break;
 779         }
 780
 781         sdmac->pc_from_device = per_2_emi;
 782         sdmac->pc_to_device = emi_2_per;
 783 }
 784
 785 static int sdma_load_context(struct sdma_channel *sdmac)
 786 {
 787         struct sdma_engine *sdma = sdmac->sdma;
 788         int channel = sdmac->channel;
 789         int load_address;
 790         struct sdma_context_data *context = sdma->context;
 791         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 792         int ret;
 793         unsigned long flags;
 794
 795         if (sdmac->direction == DMA_DEV_TO_MEM) {
 796                 load_address = sdmac->pc_from_device;
 797         } else {
 798                 load_address = sdmac->pc_to_device;
 799         }
 800
 801         if (load_address < 0)
 802                 return load_address;
 803
 804         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 805         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 806         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 807         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 808         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 809         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 810
 811         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 812
 813         memset(context, 0, sizeof(*context));
 814         context->channel_state.pc = load_address;
 815
 816         /* Send by context the event mask,base address for peripheral
 817          * and watermark level
 818          */
 819         context->gReg[0] = sdmac->event_mask[1];
 820         context->gReg[1] = sdmac->event_mask[0];
 821         context->gReg[2] = sdmac->per_addr;
 822         context->gReg[6] = sdmac->shp_addr;
 823         context->gReg[7] = sdmac->watermark_level;
 824
 825         bd0->mode.command = C0_SETDM;
 826         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 827         bd0->mode.count = sizeof(*context) / 4;
 828         bd0->buffer_addr = sdma->context_phys;
 829         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 830         ret = sdma_run_channel0(sdma);
 831
 832         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 833
 834         return ret;
 835 }
 836
 837 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 838 {
 839         return container_of(chan, struct sdma_channel, chan);
 840 }
 841
 842 static int sdma_disable_channel(struct dma_chan *chan)
 843 {
 844         struct sdma_channel *sdmac = to_sdma_chan(chan);
 845         struct sdma_engine *sdma = sdmac->sdma;
 846         int channel = sdmac->channel;
 847
 848         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 849         sdmac->status = DMA_ERROR;
 850
 851         return 0;
 852 }
 853
 854 static int sdma_config_channel(struct dma_chan *chan)
 855 {
 856         struct sdma_channel *sdmac = to_sdma_chan(chan);
 857         int ret;
 858
 859         sdma_disable_channel(chan);
 860
 861         sdmac->event_mask[0] = 0;
 862         sdmac->event_mask[1] = 0;
 863         sdmac->shp_addr = 0;
 864         sdmac->per_addr = 0;
 865
 866         if (sdmac->event_id0) {
 867                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 868                         return -EINVAL;
 869                 sdma_event_enable(sdmac, sdmac->event_id0);
 870         }
 871
 872         switch (sdmac->peripheral_type) {
 873         case IMX_DMATYPE_DSP:
 874                 sdma_config_ownership(sdmac, false, true, true);
 875                 break;
 876         case IMX_DMATYPE_MEMORY:
 877                 sdma_config_ownership(sdmac, false, true, false);
 878                 break;
 879         default:
 880                 sdma_config_ownership(sdmac, true, true, false);
 881                 break;
 882         }
 883
 884         sdma_get_pc(sdmac, sdmac->peripheral_type);
 885
 886         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 887                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 888                 /* Handle multiple event channels differently */
 889                 if (sdmac->event_id1) {
 890                         sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
 891                         if (sdmac->event_id1 > 31)
 892                                 __set_bit(31, &sdmac->watermark_level);
 893                         sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
 894                         if (sdmac->event_id0 > 31)
 895                                 __set_bit(30, &sdmac->watermark_level);
 896                 } else {
 897                         __set_bit(sdmac->event_id0, sdmac->event_mask);
 898                 }
 899                 /* Watermark Level */
 900                 sdmac->watermark_level |= sdmac->watermark_level;
 901                 /* Address */
 902                 sdmac->shp_addr = sdmac->per_address;
 903         } else {
 904                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 905         }
 906
 907         ret = sdma_load_context(sdmac);
 908
 909         return ret;
 910 }
 911
 912 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 913                 unsigned int priority)
 914 {
 915         struct sdma_engine *sdma = sdmac->sdma;
 916         int channel = sdmac->channel;
 917
 918         if (priority < MXC_SDMA_MIN_PRIORITY
 919             || priority > MXC_SDMA_MAX_PRIORITY) {
 920                 return -EINVAL;
 921         }
 922
 923         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 924
 925         return 0;
 926 }
 927
 928 static int sdma_request_channel(struct sdma_channel *sdmac)
 929 {
 930         struct sdma_engine *sdma = sdmac->sdma;
 931         int channel = sdmac->channel;
 932         int ret = -EBUSY;
 933
 934         sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
 935                                         GFP_KERNEL);
 936         if (!sdmac->bd) {
 937                 ret = -ENOMEM;
 938                 goto out;
 939         }
 940
 941         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 942         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 943
 944         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 945         return 0;
 946 out:
 947
 948         return ret;
 949 }
 950
 951 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 952 {
 953         unsigned long flags;
 954         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 955         dma_cookie_t cookie;
 956
 957         spin_lock_irqsave(&sdmac->lock, flags);
 958
 959         cookie = dma_cookie_assign(tx);
 960
 961         spin_unlock_irqrestore(&sdmac->lock, flags);
 962
 963         return cookie;
 964 }
 965
 966 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 967 {
 968         struct sdma_channel *sdmac = to_sdma_chan(chan);
 969         struct imx_dma_data *data = chan->private;
 970         int prio, ret;
 971
 972         if (!data)
 973                 return -EINVAL;
 974
 975         switch (data->priority) {
 976         case DMA_PRIO_HIGH:
 977                 prio = 3;
 978                 break;
 979         case DMA_PRIO_MEDIUM:
 980                 prio = 2;
 981                 break;
 982         case DMA_PRIO_LOW:
 983         default:
 984                 prio = 1;
 985                 break;
 986         }
 987
 988         sdmac->peripheral_type = data->peripheral_type;
 989         sdmac->event_id0 = data->dma_request;
 990
 991         clk_enable(sdmac->sdma->clk_ipg);
 992         clk_enable(sdmac->sdma->clk_ahb);
 993
 994         ret = sdma_request_channel(sdmac);
 995         if (ret)
 996                 return ret;
 997
 998         ret = sdma_set_channel_priority(sdmac, prio);
 999         if (ret)
1000                 return ret;
1001
1002         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1003         sdmac->desc.tx_submit = sdma_tx_submit;
1004         /* txd.flags will be overwritten in prep funcs */
1005         sdmac->desc.flags = DMA_CTRL_ACK;
1006
1007         return 0;
1008 }
1009
1010 static void sdma_free_chan_resources(struct dma_chan *chan)
1011 {
1012         struct sdma_channel *sdmac = to_sdma_chan(chan);
1013         struct sdma_engine *sdma = sdmac->sdma;
1014
1015         sdma_disable_channel(chan);
1016
1017         if (sdmac->event_id0)
1018                 sdma_event_disable(sdmac, sdmac->event_id0);
1019         if (sdmac->event_id1)
1020                 sdma_event_disable(sdmac, sdmac->event_id1);
1021
1022         sdmac->event_id0 = 0;
1023         sdmac->event_id1 = 0;
1024
1025         sdma_set_channel_priority(sdmac, 0);
1026
1027         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1028
1029         clk_disable(sdma->clk_ipg);
1030         clk_disable(sdma->clk_ahb);
1031 }
1032
1033 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1034                 struct dma_chan *chan, struct scatterlist *sgl,
1035                 unsigned int sg_len, enum dma_transfer_direction direction,
1036                 unsigned long flags, void *context)
1037 {
1038         struct sdma_channel *sdmac = to_sdma_chan(chan);
1039         struct sdma_engine *sdma = sdmac->sdma;
1040         int ret, i, count;
1041         int channel = sdmac->channel;
1042         struct scatterlist *sg;
1043
1044         if (sdmac->status == DMA_IN_PROGRESS)
1045                 return NULL;
1046         sdmac->status = DMA_IN_PROGRESS;
1047
1048         sdmac->flags = 0;
1049
1050         sdmac->buf_tail = 0;
1051
1052         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1053                         sg_len, channel);
1054
1055         sdmac->direction = direction;
1056         ret = sdma_load_context(sdmac);
1057         if (ret)
1058                 goto err_out;
1059
1060         if (sg_len > NUM_BD) {
1061                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1062                                 channel, sg_len, NUM_BD);
1063                 ret = -EINVAL;
1064                 goto err_out;
1065         }
1066
1067         sdmac->chn_count = 0;
1068         for_each_sg(sgl, sg, sg_len, i) {
1069                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1070                 int param;
1071
1072                 bd->buffer_addr = sg->dma_address;
1073
1074                 count = sg_dma_len(sg);
1075
1076                 if (count > 0xffff) {
1077                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1078                                         channel, count, 0xffff);
1079                         ret = -EINVAL;
1080                         goto err_out;
1081                 }
1082
1083                 bd->mode.count = count;
1084                 sdmac->chn_count += count;
1085
1086                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1087                         ret =  -EINVAL;
1088                         goto err_out;
1089                 }
1090
1091                 switch (sdmac->word_size) {
1092                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1093                         bd->mode.command = 0;
1094                         if (count & 3 || sg->dma_address & 3)
1095                                 return NULL;
1096                         break;
1097                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1098                         bd->mode.command = 2;
1099                         if (count & 1 || sg->dma_address & 1)
1100                                 return NULL;
1101                         break;
1102                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1103                         bd->mode.command = 1;
1104                         break;
1105                 default:
1106                         return NULL;
1107                 }
1108
1109                 param = BD_DONE | BD_EXTD | BD_CONT;
1110
1111                 if (i + 1 == sg_len) {
1112                         param |= BD_INTR;
1113                         param |= BD_LAST;
1114                         param &= ~BD_CONT;
1115                 }
1116
1117                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1118                                 i, count, (u64)sg->dma_address,
1119                                 param & BD_WRAP ? "wrap" : "",
1120                                 param & BD_INTR ? " intr" : "");
1121
1122                 bd->mode.status = param;
1123         }
1124
1125         sdmac->num_bd = sg_len;
1126         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1127
1128         return &sdmac->desc;
1129 err_out:
1130         sdmac->status = DMA_ERROR;
1131         return NULL;
1132 }
1133
1134 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1135                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1136                 size_t period_len, enum dma_transfer_direction direction,
1137                 unsigned long flags)
1138 {
1139         struct sdma_channel *sdmac = to_sdma_chan(chan);
1140         struct sdma_engine *sdma = sdmac->sdma;
1141         int num_periods = buf_len / period_len;
1142         int channel = sdmac->channel;
1143         int ret, i = 0, buf = 0;
1144
1145         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1146
1147         if (sdmac->status == DMA_IN_PROGRESS)
1148                 return NULL;
1149
1150         sdmac->status = DMA_IN_PROGRESS;
1151
1152         sdmac->buf_tail = 0;
1153         sdmac->period_len = period_len;
1154
1155         sdmac->flags |= IMX_DMA_SG_LOOP;
1156         sdmac->direction = direction;
1157         ret = sdma_load_context(sdmac);
1158         if (ret)
1159                 goto err_out;
1160
1161         if (num_periods > NUM_BD) {
1162                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1163                                 channel, num_periods, NUM_BD);
1164                 goto err_out;
1165         }
1166
1167         if (period_len > 0xffff) {
1168                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1169                                 channel, period_len, 0xffff);
1170                 goto err_out;
1171         }
1172
1173         while (buf < buf_len) {
1174                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1175                 int param;
1176
1177                 bd->buffer_addr = dma_addr;
1178
1179                 bd->mode.count = period_len;
1180
1181                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1182                         goto err_out;
1183                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1184                         bd->mode.command = 0;
1185                 else
1186                         bd->mode.command = sdmac->word_size;
1187
1188                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1189                 if (i + 1 == num_periods)
1190                         param |= BD_WRAP;
1191
1192                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1193                                 i, period_len, (u64)dma_addr,
1194                                 param & BD_WRAP ? "wrap" : "",
1195                                 param & BD_INTR ? " intr" : "");
1196
1197                 bd->mode.status = param;
1198
1199                 dma_addr += period_len;
1200                 buf += period_len;
1201
1202                 i++;
1203         }
1204
1205         sdmac->num_bd = num_periods;
1206         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1207
1208         return &sdmac->desc;
1209 err_out:
1210         sdmac->status = DMA_ERROR;
1211         return NULL;
1212 }
1213
1214 static int sdma_config(struct dma_chan *chan,
1215                        struct dma_slave_config *dmaengine_cfg)
1216 {
1217         struct sdma_channel *sdmac = to_sdma_chan(chan);
1218
1219         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1220                 sdmac->per_address = dmaengine_cfg->src_addr;
1221                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1222                         dmaengine_cfg->src_addr_width;
1223                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1224         } else {
1225                 sdmac->per_address = dmaengine_cfg->dst_addr;
1226                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1227                         dmaengine_cfg->dst_addr_width;
1228                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1229         }
1230         sdmac->direction = dmaengine_cfg->direction;
1231         return sdma_config_channel(chan);
1232 }
1233
1234 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1235                                       dma_cookie_t cookie,
1236                                       struct dma_tx_state *txstate)
1237 {
1238         struct sdma_channel *sdmac = to_sdma_chan(chan);
1239         u32 residue;
1240
1241         if (sdmac->flags & IMX_DMA_SG_LOOP)
1242                 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1243         else
1244                 residue = sdmac->chn_count - sdmac->chn_real_count;
1245
1246         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1247                          residue);
1248
1249         return sdmac->status;
1250 }
1251
1252 static void sdma_issue_pending(struct dma_chan *chan)
1253 {
1254         struct sdma_channel *sdmac = to_sdma_chan(chan);
1255         struct sdma_engine *sdma = sdmac->sdma;
1256
1257         if (sdmac->status == DMA_IN_PROGRESS)
1258                 sdma_enable_channel(sdma, sdmac->channel);
1259 }
1260
1261 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1262 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1263 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1264
1265 static void sdma_add_scripts(struct sdma_engine *sdma,
1266                 const struct sdma_script_start_addrs *addr)
1267 {
1268         s32 *addr_arr = (u32 *)addr;
1269         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1270         int i;
1271
1272         /* use the default firmware in ROM if missing external firmware */
1273         if (!sdma->script_number)
1274                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1275
1276         for (i = 0; i < sdma->script_number; i++)
1277                 if (addr_arr[i] > 0)
1278                         saddr_arr[i] = addr_arr[i];
1279 }
1280
1281 static void sdma_load_firmware(const struct firmware *fw, void *context)
1282 {
1283         struct sdma_engine *sdma = context;
1284         const struct sdma_firmware_header *header;
1285         const struct sdma_script_start_addrs *addr;
1286         unsigned short *ram_code;
1287
1288         if (!fw) {
1289                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1290                 /* In this case we just use the ROM firmware. */
1291                 return;
1292         }
1293
1294         if (fw->size < sizeof(*header))
1295                 goto err_firmware;
1296
1297         header = (struct sdma_firmware_header *)fw->data;
1298
1299         if (header->magic != SDMA_FIRMWARE_MAGIC)
1300                 goto err_firmware;
1301         if (header->ram_code_start + header->ram_code_size > fw->size)
1302                 goto err_firmware;
1303         switch (header->version_major) {
1304         case 1:
1305                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1306                 break;
1307         case 2:
1308                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1309                 break;
1310         case 3:
1311                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1312                 break;
1313         default:
1314                 dev_err(sdma->dev, "unknown firmware version\n");
1315                 goto err_firmware;
1316         }
1317
1318         addr = (void *)header + header->script_addrs_start;
1319         ram_code = (void *)header + header->ram_code_start;
1320
1321         clk_enable(sdma->clk_ipg);
1322         clk_enable(sdma->clk_ahb);
1323         /* download the RAM image for SDMA */
1324         sdma_load_script(sdma, ram_code,
1325                         header->ram_code_size,
1326                         addr->ram_code_start_addr);
1327         clk_disable(sdma->clk_ipg);
1328         clk_disable(sdma->clk_ahb);
1329
1330         sdma_add_scripts(sdma, addr);
1331
1332         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1333                         header->version_major,
1334                         header->version_minor);
1335
1336 err_firmware:
1337         release_firmware(fw);
1338 }
1339
1340 static int sdma_get_firmware(struct sdma_engine *sdma,
1341                 const char *fw_name)
1342 {
1343         int ret;
1344
1345         ret = request_firmware_nowait(THIS_MODULE,
1346                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1347                         GFP_KERNEL, sdma, sdma_load_firmware);
1348
1349         return ret;
1350 }
1351
1352 static int sdma_init(struct sdma_engine *sdma)
1353 {
1354         int i, ret;
1355         dma_addr_t ccb_phys;
1356
1357         clk_enable(sdma->clk_ipg);
1358         clk_enable(sdma->clk_ahb);
1359
1360         /* Be sure SDMA has not started yet */
1361         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1362
1363         sdma->channel_control = dma_alloc_coherent(NULL,
1364                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1365                         sizeof(struct sdma_context_data),
1366                         &ccb_phys, GFP_KERNEL);
1367
1368         if (!sdma->channel_control) {
1369                 ret = -ENOMEM;
1370                 goto err_dma_alloc;
1371         }
1372
1373         sdma->context = (void *)sdma->channel_control +
1374                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1375         sdma->context_phys = ccb_phys +
1376                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1377
1378         /* Zero-out the CCB structures array just allocated */
1379         memset(sdma->channel_control, 0,
1380                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1381
1382         /* disable all channels */
1383         for (i = 0; i < sdma->drvdata->num_events; i++)
1384                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1385
1386         /* All channels have priority 0 */
1387         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1388                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1389
1390         ret = sdma_request_channel(&sdma->channel[0]);
1391         if (ret)
1392                 goto err_dma_alloc;
1393
1394         sdma_config_ownership(&sdma->channel[0], false, true, false);
1395
1396         /* Set Command Channel (Channel Zero) */
1397         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1398
1399         /* Set bits of CONFIG register but with static context switching */
1400         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1401         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1402
1403         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1404
1405         /* Initializes channel's priorities */
1406         sdma_set_channel_priority(&sdma->channel[0], 7);
1407
1408         clk_disable(sdma->clk_ipg);
1409         clk_disable(sdma->clk_ahb);
1410
1411         return 0;
1412
1413 err_dma_alloc:
1414         clk_disable(sdma->clk_ipg);
1415         clk_disable(sdma->clk_ahb);
1416         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1417         return ret;
1418 }
1419
1420 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1421 {
1422         struct sdma_channel *sdmac = to_sdma_chan(chan);
1423         struct imx_dma_data *data = fn_param;
1424
1425         if (!imx_dma_is_general_purpose(chan))
1426                 return false;
1427
1428         sdmac->data = *data;
1429         chan->private = &sdmac->data;
1430
1431         return true;
1432 }
1433
1434 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1435                                    struct of_dma *ofdma)
1436 {
1437         struct sdma_engine *sdma = ofdma->of_dma_data;
1438         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1439         struct imx_dma_data data;
1440
1441         if (dma_spec->args_count != 3)
1442                 return NULL;
1443
1444         data.dma_request = dma_spec->args[0];
1445         data.peripheral_type = dma_spec->args[1];
1446         data.priority = dma_spec->args[2];
1447
1448         return dma_request_channel(mask, sdma_filter_fn, &data);
1449 }
1450
1451 static int sdma_probe(struct platform_device *pdev)
1452 {
1453         const struct of_device_id *of_id =
1454                         of_match_device(sdma_dt_ids, &pdev->dev);
1455         struct device_node *np = pdev->dev.of_node;
1456         const char *fw_name;
1457         int ret;
1458         int irq;
1459         struct resource *iores;
1460         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1461         int i;
1462         struct sdma_engine *sdma;
1463         s32 *saddr_arr;
1464         const struct sdma_driver_data *drvdata = NULL;
1465
1466         if (of_id)
1467                 drvdata = of_id->data;
1468         else if (pdev->id_entry)
1469                 drvdata = (void *)pdev->id_entry->driver_data;
1470
1471         if (!drvdata) {
1472                 dev_err(&pdev->dev, "unable to find driver data\n");
1473                 return -EINVAL;
1474         }
1475
1476         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1477         if (ret)
1478                 return ret;
1479
1480         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1481         if (!sdma)
1482                 return -ENOMEM;
1483
1484         spin_lock_init(&sdma->channel_0_lock);
1485
1486         sdma->dev = &pdev->dev;
1487         sdma->drvdata = drvdata;
1488
1489         irq = platform_get_irq(pdev, 0);
1490         if (irq < 0)
1491                 return irq;
1492
1493         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1495         if (IS_ERR(sdma->regs))
1496                 return PTR_ERR(sdma->regs);
1497
1498         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1499         if (IS_ERR(sdma->clk_ipg))
1500                 return PTR_ERR(sdma->clk_ipg);
1501
1502         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1503         if (IS_ERR(sdma->clk_ahb))
1504                 return PTR_ERR(sdma->clk_ahb);
1505
1506         clk_prepare(sdma->clk_ipg);
1507         clk_prepare(sdma->clk_ahb);
1508
1509         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1510                                sdma);
1511         if (ret)
1512                 return ret;
1513
1514         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1515         if (!sdma->script_addrs)
1516                 return -ENOMEM;
1517
1518         /* initially no scripts available */
1519         saddr_arr = (s32 *)sdma->script_addrs;
1520         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1521                 saddr_arr[i] = -EINVAL;
1522
1523         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1524         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1525
1526         INIT_LIST_HEAD(&sdma->dma_device.channels);
1527         /* Initialize channel parameters */
1528         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1529                 struct sdma_channel *sdmac = &sdma->channel[i];
1530
1531                 sdmac->sdma = sdma;
1532                 spin_lock_init(&sdmac->lock);
1533
1534                 sdmac->chan.device = &sdma->dma_device;
1535                 dma_cookie_init(&sdmac->chan);
1536                 sdmac->channel = i;
1537
1538                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1539                              (unsigned long) sdmac);
1540                 /*
1541                  * Add the channel to the DMAC list. Do not add channel 0 though
1542                  * because we need it internally in the SDMA driver. This also means
1543                  * that channel 0 in dmaengine counting matches sdma channel 1.
1544                  */
1545                 if (i)
1546                         list_add_tail(&sdmac->chan.device_node,
1547                                         &sdma->dma_device.channels);
1548         }
1549
1550         ret = sdma_init(sdma);
1551         if (ret)
1552                 goto err_init;
1553
1554         if (sdma->drvdata->script_addrs)
1555                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1556         if (pdata && pdata->script_addrs)
1557                 sdma_add_scripts(sdma, pdata->script_addrs);
1558
1559         if (pdata) {
1560                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1561                 if (ret)
1562                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1563         } else {
1564                 /*
1565                  * Because that device tree does not encode ROM script address,
1566                  * the RAM script in firmware is mandatory for device tree
1567                  * probe, otherwise it fails.
1568                  */
1569                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1570                                               &fw_name);
1571                 if (ret)
1572                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1573                 else {
1574                         ret = sdma_get_firmware(sdma, fw_name);
1575                         if (ret)
1576                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1577                 }
1578         }
1579
1580         sdma->dma_device.dev = &pdev->dev;
1581
1582         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1583         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1584         sdma->dma_device.device_tx_status = sdma_tx_status;
1585         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1586         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1587         sdma->dma_device.device_config = sdma_config;
1588         sdma->dma_device.device_terminate_all = sdma_disable_channel;
1589         sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1590         sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1591         sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1592         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1593         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1594         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1595         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1596
1597         platform_set_drvdata(pdev, sdma);
1598
1599         ret = dma_async_device_register(&sdma->dma_device);
1600         if (ret) {
1601                 dev_err(&pdev->dev, "unable to register\n");
1602                 goto err_init;
1603         }
1604
1605         if (np) {
1606                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1607                 if (ret) {
1608                         dev_err(&pdev->dev, "failed to register controller\n");
1609                         goto err_register;
1610                 }
1611         }
1612
1613         dev_info(sdma->dev, "initialized\n");
1614
1615         return 0;
1616
1617 err_register:
1618         dma_async_device_unregister(&sdma->dma_device);
1619 err_init:
1620         kfree(sdma->script_addrs);
1621         return ret;
1622 }
1623
1624 static int sdma_remove(struct platform_device *pdev)
1625 {
1626         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1627         int i;
1628
1629         dma_async_device_unregister(&sdma->dma_device);
1630         kfree(sdma->script_addrs);
1631         /* Kill the tasklet */
1632         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1633                 struct sdma_channel *sdmac = &sdma->channel[i];
1634
1635                 tasklet_kill(&sdmac->tasklet);
1636         }
1637
1638         platform_set_drvdata(pdev, NULL);
1639         dev_info(&pdev->dev, "Removed...\n");
1640         return 0;
1641 }
1642
1643 static struct platform_driver sdma_driver = {
1644         .driver         = {
1645                 .name   = "imx-sdma",
1646                 .of_match_table = sdma_dt_ids,
1647         },
1648         .id_table       = sdma_devtypes,
1649         .remove         = sdma_remove,
1650         .probe          = sdma_probe,
1651 };
1652
1653 module_platform_driver(sdma_driver);
1654
1655 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1656 MODULE_DESCRIPTION("i.MX SDMA driver");
1657 MODULE_LICENSE("GPL");