kernel/drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /* The set of bus widths supported by the DMA controller */
  65 #define DW_DMA_BUSWIDTHS                          \
  66         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  67         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  68         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  69         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  70
  71 /*----------------------------------------------------------------------*/
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77
  78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  79 {
  80         return to_dw_desc(dwc->active_list.next);
  81 }
  82
  83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  84 {
  85         struct dw_desc *desc, *_desc;
  86         struct dw_desc *ret = NULL;
  87         unsigned int i = 0;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dwc->lock, flags);
  91         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  92                 i++;
  93                 if (async_tx_test_ack(&desc->txd)) {
  94                         list_del(&desc->desc_node);
  95                         ret = desc;
  96                         break;
  97                 }
  98                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  99         }
 100         spin_unlock_irqrestore(&dwc->lock, flags);
 101
 102         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 103
 104         return ret;
 105 }
 106
 107 /*
 108  * Move a descriptor, including any children, to the free list.
 109  * `desc' must not be on any lists.
 110  */
 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 112 {
 113         unsigned long flags;
 114
 115         if (desc) {
 116                 struct dw_desc *child;
 117
 118                 spin_lock_irqsave(&dwc->lock, flags);
 119                 list_for_each_entry(child, &desc->tx_list, desc_node)
 120                         dev_vdbg(chan2dev(&dwc->chan),
 121                                         "moving child desc %p to freelist\n",
 122                                         child);
 123                 list_splice_init(&desc->tx_list, &dwc->free_list);
 124                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 125                 list_add(&desc->desc_node, &dwc->free_list);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127         }
 128 }
 129
 130 static void dwc_initialize(struct dw_dma_chan *dwc)
 131 {
 132         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 133         struct dw_dma_slave *dws = dwc->chan.private;
 134         u32 cfghi = DWC_CFGH_FIFO_MODE;
 135         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 136
 137         if (dwc->initialized == true)
 138                 return;
 139
 140         if (dws) {
 141                 /*
 142                  * We need controller-specific data to set up slave
 143                  * transfers.
 144                  */
 145                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 146
 147                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 148                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 149         } else {
 150                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 151                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 152         }
 153
 154         channel_writel(dwc, CFG_LO, cfglo);
 155         channel_writel(dwc, CFG_HI, cfghi);
 156
 157         /* Enable interrupts */
 158         channel_set_bit(dw, MASK.XFER, dwc->mask);
 159         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 160
 161         dwc->initialized = true;
 162 }
 163
 164 /*----------------------------------------------------------------------*/
 165
 166 static inline unsigned int dwc_fast_ffs(unsigned long long v)
 167 {
 168         /*
 169          * We can be a lot more clever here, but this should take care
 170          * of the most common optimization.
 171          */
 172         if (!(v & 7))
 173                 return 3;
 174         else if (!(v & 3))
 175                 return 2;
 176         else if (!(v & 1))
 177                 return 1;
 178         return 0;
 179 }
 180
 181 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 182 {
 183         dev_err(chan2dev(&dwc->chan),
 184                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 185                 channel_readl(dwc, SAR),
 186                 channel_readl(dwc, DAR),
 187                 channel_readl(dwc, LLP),
 188                 channel_readl(dwc, CTL_HI),
 189                 channel_readl(dwc, CTL_LO));
 190 }
 191
 192 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 193 {
 194         channel_clear_bit(dw, CH_EN, dwc->mask);
 195         while (dma_readl(dw, CH_EN) & dwc->mask)
 196                 cpu_relax();
 197 }
 198
 199 /*----------------------------------------------------------------------*/
 200
 201 /* Perform single block transfer */
 202 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 203                                        struct dw_desc *desc)
 204 {
 205         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 206         u32             ctllo;
 207
 208         /*
 209          * Software emulation of LLP mode relies on interrupts to continue
 210          * multi block transfer.
 211          */
 212         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 213
 214         channel_writel(dwc, SAR, desc->lli.sar);
 215         channel_writel(dwc, DAR, desc->lli.dar);
 216         channel_writel(dwc, CTL_LO, ctllo);
 217         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 218         channel_set_bit(dw, CH_EN, dwc->mask);
 219
 220         /* Move pointer to next descriptor */
 221         dwc->tx_node_active = dwc->tx_node_active->next;
 222 }
 223
 224 /* Called with dwc->lock held and bh disabled */
 225 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 226 {
 227         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 228         unsigned long   was_soft_llp;
 229
 230         /* ASSERT:  channel is idle */
 231         if (dma_readl(dw, CH_EN) & dwc->mask) {
 232                 dev_err(chan2dev(&dwc->chan),
 233                         "%s: BUG: Attempted to start non-idle channel\n",
 234                         __func__);
 235                 dwc_dump_chan_regs(dwc);
 236
 237                 /* The tasklet will hopefully advance the queue... */
 238                 return;
 239         }
 240
 241         if (dwc->nollp) {
 242                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 243                                                 &dwc->flags);
 244                 if (was_soft_llp) {
 245                         dev_err(chan2dev(&dwc->chan),
 246                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 247                         return;
 248                 }
 249
 250                 dwc_initialize(dwc);
 251
 252                 dwc->residue = first->total_len;
 253                 dwc->tx_node_active = &first->tx_list;
 254
 255                 /* Submit first block */
 256                 dwc_do_single_block(dwc, first);
 257
 258                 return;
 259         }
 260
 261         dwc_initialize(dwc);
 262
 263         channel_writel(dwc, LLP, first->txd.phys);
 264         channel_writel(dwc, CTL_LO,
 265                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 266         channel_writel(dwc, CTL_HI, 0);
 267         channel_set_bit(dw, CH_EN, dwc->mask);
 268 }
 269
 270 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 271 {
 272         struct dw_desc *desc;
 273
 274         if (list_empty(&dwc->queue))
 275                 return;
 276
 277         list_move(dwc->queue.next, &dwc->active_list);
 278         desc = dwc_first_active(dwc);
 279         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 280         dwc_dostart(dwc, desc);
 281 }
 282
 283 /*----------------------------------------------------------------------*/
 284
 285 static void
 286 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 287                 bool callback_required)
 288 {
 289         dma_async_tx_callback           callback = NULL;
 290         void                            *param = NULL;
 291         struct dma_async_tx_descriptor  *txd = &desc->txd;
 292         struct dw_desc                  *child;
 293         unsigned long                   flags;
 294
 295         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 296
 297         spin_lock_irqsave(&dwc->lock, flags);
 298         dma_cookie_complete(txd);
 299         if (callback_required) {
 300                 callback = txd->callback;
 301                 param = txd->callback_param;
 302         }
 303
 304         /* async_tx_ack */
 305         list_for_each_entry(child, &desc->tx_list, desc_node)
 306                 async_tx_ack(&child->txd);
 307         async_tx_ack(&desc->txd);
 308
 309         list_splice_init(&desc->tx_list, &dwc->free_list);
 310         list_move(&desc->desc_node, &dwc->free_list);
 311
 312         dma_descriptor_unmap(txd);
 313         spin_unlock_irqrestore(&dwc->lock, flags);
 314
 315         if (callback)
 316                 callback(param);
 317 }
 318
 319 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 320 {
 321         struct dw_desc *desc, *_desc;
 322         LIST_HEAD(list);
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&dwc->lock, flags);
 326         if (dma_readl(dw, CH_EN) & dwc->mask) {
 327                 dev_err(chan2dev(&dwc->chan),
 328                         "BUG: XFER bit set, but channel not idle!\n");
 329
 330                 /* Try to continue after resetting the channel... */
 331                 dwc_chan_disable(dw, dwc);
 332         }
 333
 334         /*
 335          * Submit queued descriptors ASAP, i.e. before we go through
 336          * the completed ones.
 337          */
 338         list_splice_init(&dwc->active_list, &list);
 339         dwc_dostart_first_queued(dwc);
 340
 341         spin_unlock_irqrestore(&dwc->lock, flags);
 342
 343         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 344                 dwc_descriptor_complete(dwc, desc, true);
 345 }
 346
 347 /* Returns how many bytes were already received from source */
 348 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 349 {
 350         u32 ctlhi = channel_readl(dwc, CTL_HI);
 351         u32 ctllo = channel_readl(dwc, CTL_LO);
 352
 353         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 354 }
 355
 356 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 357 {
 358         dma_addr_t llp;
 359         struct dw_desc *desc, *_desc;
 360         struct dw_desc *child;
 361         u32 status_xfer;
 362         unsigned long flags;
 363
 364         spin_lock_irqsave(&dwc->lock, flags);
 365         llp = channel_readl(dwc, LLP);
 366         status_xfer = dma_readl(dw, RAW.XFER);
 367
 368         if (status_xfer & dwc->mask) {
 369                 /* Everything we've submitted is done */
 370                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 371
 372                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 373                         struct list_head *head, *active = dwc->tx_node_active;
 374
 375                         /*
 376                          * We are inside first active descriptor.
 377                          * Otherwise something is really wrong.
 378                          */
 379                         desc = dwc_first_active(dwc);
 380
 381                         head = &desc->tx_list;
 382                         if (active != head) {
 383                                 /* Update desc to reflect last sent one */
 384                                 if (active != head->next)
 385                                         desc = to_dw_desc(active->prev);
 386
 387                                 dwc->residue -= desc->len;
 388
 389                                 child = to_dw_desc(active);
 390
 391                                 /* Submit next block */
 392                                 dwc_do_single_block(dwc, child);
 393
 394                                 spin_unlock_irqrestore(&dwc->lock, flags);
 395                                 return;
 396                         }
 397
 398                         /* We are done here */
 399                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 400                 }
 401
 402                 dwc->residue = 0;
 403
 404                 spin_unlock_irqrestore(&dwc->lock, flags);
 405
 406                 dwc_complete_all(dw, dwc);
 407                 return;
 408         }
 409
 410         if (list_empty(&dwc->active_list)) {
 411                 dwc->residue = 0;
 412                 spin_unlock_irqrestore(&dwc->lock, flags);
 413                 return;
 414         }
 415
 416         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 417                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 418                 spin_unlock_irqrestore(&dwc->lock, flags);
 419                 return;
 420         }
 421
 422         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 423
 424         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 425                 /* Initial residue value */
 426                 dwc->residue = desc->total_len;
 427
 428                 /* Check first descriptors addr */
 429                 if (desc->txd.phys == llp) {
 430                         spin_unlock_irqrestore(&dwc->lock, flags);
 431                         return;
 432                 }
 433
 434                 /* Check first descriptors llp */
 435                 if (desc->lli.llp == llp) {
 436                         /* This one is currently in progress */
 437                         dwc->residue -= dwc_get_sent(dwc);
 438                         spin_unlock_irqrestore(&dwc->lock, flags);
 439                         return;
 440                 }
 441
 442                 dwc->residue -= desc->len;
 443                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 444                         if (child->lli.llp == llp) {
 445                                 /* Currently in progress */
 446                                 dwc->residue -= dwc_get_sent(dwc);
 447                                 spin_unlock_irqrestore(&dwc->lock, flags);
 448                                 return;
 449                         }
 450                         dwc->residue -= child->len;
 451                 }
 452
 453                 /*
 454                  * No descriptors so far seem to be in progress, i.e.
 455                  * this one must be done.
 456                  */
 457                 spin_unlock_irqrestore(&dwc->lock, flags);
 458                 dwc_descriptor_complete(dwc, desc, true);
 459                 spin_lock_irqsave(&dwc->lock, flags);
 460         }
 461
 462         dev_err(chan2dev(&dwc->chan),
 463                 "BUG: All descriptors done, but channel not idle!\n");
 464
 465         /* Try to continue after resetting the channel... */
 466         dwc_chan_disable(dw, dwc);
 467
 468         dwc_dostart_first_queued(dwc);
 469         spin_unlock_irqrestore(&dwc->lock, flags);
 470 }
 471
 472 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 473 {
 474         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 475                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 476 }
 477
 478 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 479 {
 480         struct dw_desc *bad_desc;
 481         struct dw_desc *child;
 482         unsigned long flags;
 483
 484         dwc_scan_descriptors(dw, dwc);
 485
 486         spin_lock_irqsave(&dwc->lock, flags);
 487
 488         /*
 489          * The descriptor currently at the head of the active list is
 490          * borked. Since we don't have any way to report errors, we'll
 491          * just have to scream loudly and try to carry on.
 492          */
 493         bad_desc = dwc_first_active(dwc);
 494         list_del_init(&bad_desc->desc_node);
 495         list_move(dwc->queue.next, dwc->active_list.prev);
 496
 497         /* Clear the error flag and try to restart the controller */
 498         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 499         if (!list_empty(&dwc->active_list))
 500                 dwc_dostart(dwc, dwc_first_active(dwc));
 501
 502         /*
 503          * WARN may seem harsh, but since this only happens
 504          * when someone submits a bad physical address in a
 505          * descriptor, we should consider ourselves lucky that the
 506          * controller flagged an error instead of scribbling over
 507          * random memory locations.
 508          */
 509         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 510                                        "  cookie: %d\n", bad_desc->txd.cookie);
 511         dwc_dump_lli(dwc, &bad_desc->lli);
 512         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 513                 dwc_dump_lli(dwc, &child->lli);
 514
 515         spin_unlock_irqrestore(&dwc->lock, flags);
 516
 517         /* Pretend the descriptor completed successfully */
 518         dwc_descriptor_complete(dwc, bad_desc, true);
 519 }
 520
 521 /* --------------------- Cyclic DMA API extensions -------------------- */
 522
 523 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 524 {
 525         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 526         return channel_readl(dwc, SAR);
 527 }
 528 EXPORT_SYMBOL(dw_dma_get_src_addr);
 529
 530 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 531 {
 532         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 533         return channel_readl(dwc, DAR);
 534 }
 535 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 536
 537 /* Called with dwc->lock held and all DMAC interrupts disabled */
 538 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 539                 u32 status_block, u32 status_err, u32 status_xfer)
 540 {
 541         unsigned long flags;
 542
 543         if (status_block & dwc->mask) {
 544                 void (*callback)(void *param);
 545                 void *callback_param;
 546
 547                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 548                                 channel_readl(dwc, LLP));
 549                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 550
 551                 callback = dwc->cdesc->period_callback;
 552                 callback_param = dwc->cdesc->period_callback_param;
 553
 554                 if (callback)
 555                         callback(callback_param);
 556         }
 557
 558         /*
 559          * Error and transfer complete are highly unlikely, and will most
 560          * likely be due to a configuration error by the user.
 561          */
 562         if (unlikely(status_err & dwc->mask) ||
 563                         unlikely(status_xfer & dwc->mask)) {
 564                 int i;
 565
 566                 dev_err(chan2dev(&dwc->chan),
 567                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 568                         status_xfer ? "xfer" : "error");
 569
 570                 spin_lock_irqsave(&dwc->lock, flags);
 571
 572                 dwc_dump_chan_regs(dwc);
 573
 574                 dwc_chan_disable(dw, dwc);
 575
 576                 /* Make sure DMA does not restart by loading a new list */
 577                 channel_writel(dwc, LLP, 0);
 578                 channel_writel(dwc, CTL_LO, 0);
 579                 channel_writel(dwc, CTL_HI, 0);
 580
 581                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 582                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 583                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 584
 585                 for (i = 0; i < dwc->cdesc->periods; i++)
 586                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 587
 588                 spin_unlock_irqrestore(&dwc->lock, flags);
 589         }
 590
 591         /* Re-enable interrupts */
 592         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 593 }
 594
 595 /* ------------------------------------------------------------------------- */
 596
 597 static void dw_dma_tasklet(unsigned long data)
 598 {
 599         struct dw_dma *dw = (struct dw_dma *)data;
 600         struct dw_dma_chan *dwc;
 601         u32 status_block;
 602         u32 status_xfer;
 603         u32 status_err;
 604         int i;
 605
 606         status_block = dma_readl(dw, RAW.BLOCK);
 607         status_xfer = dma_readl(dw, RAW.XFER);
 608         status_err = dma_readl(dw, RAW.ERROR);
 609
 610         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 611
 612         for (i = 0; i < dw->dma.chancnt; i++) {
 613                 dwc = &dw->chan[i];
 614                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 615                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 616                                         status_xfer);
 617                 else if (status_err & (1 << i))
 618                         dwc_handle_error(dw, dwc);
 619                 else if (status_xfer & (1 << i))
 620                         dwc_scan_descriptors(dw, dwc);
 621         }
 622
 623         /* Re-enable interrupts */
 624         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 625         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 626 }
 627
 628 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 629 {
 630         struct dw_dma *dw = dev_id;
 631         u32 status = dma_readl(dw, STATUS_INT);
 632
 633         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 634
 635         /* Check if we have any interrupt from the DMAC */
 636         if (!status || !dw->in_use)
 637                 return IRQ_NONE;
 638
 639         /*
 640          * Just disable the interrupts. We'll turn them back on in the
 641          * softirq handler.
 642          */
 643         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 644         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 645         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 646
 647         status = dma_readl(dw, STATUS_INT);
 648         if (status) {
 649                 dev_err(dw->dma.dev,
 650                         "BUG: Unexpected interrupts pending: 0x%x\n",
 651                         status);
 652
 653                 /* Try to recover */
 654                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 655                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 657                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 658                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 659         }
 660
 661         tasklet_schedule(&dw->tasklet);
 662
 663         return IRQ_HANDLED;
 664 }
 665
 666 /*----------------------------------------------------------------------*/
 667
 668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 669 {
 670         struct dw_desc          *desc = txd_to_dw_desc(tx);
 671         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 672         dma_cookie_t            cookie;
 673         unsigned long           flags;
 674
 675         spin_lock_irqsave(&dwc->lock, flags);
 676         cookie = dma_cookie_assign(tx);
 677
 678         /*
 679          * REVISIT: We should attempt to chain as many descriptors as
 680          * possible, perhaps even appending to those already submitted
 681          * for DMA. But this is hard to do in a race-free manner.
 682          */
 683
 684         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 685         list_add_tail(&desc->desc_node, &dwc->queue);
 686
 687         spin_unlock_irqrestore(&dwc->lock, flags);
 688
 689         return cookie;
 690 }
 691
 692 static struct dma_async_tx_descriptor *
 693 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 694                 size_t len, unsigned long flags)
 695 {
 696         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 697         struct dw_dma           *dw = to_dw_dma(chan->device);
 698         struct dw_desc          *desc;
 699         struct dw_desc          *first;
 700         struct dw_desc          *prev;
 701         size_t                  xfer_count;
 702         size_t                  offset;
 703         unsigned int            src_width;
 704         unsigned int            dst_width;
 705         unsigned int            data_width;
 706         u32                     ctllo;
 707
 708         dev_vdbg(chan2dev(chan),
 709                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 710                         &dest, &src, len, flags);
 711
 712         if (unlikely(!len)) {
 713                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 714                 return NULL;
 715         }
 716
 717         dwc->direction = DMA_MEM_TO_MEM;
 718
 719         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 720                            dw->data_width[dwc->dst_master]);
 721
 722         src_width = dst_width = min_t(unsigned int, data_width,
 723                                       dwc_fast_ffs(src | dest | len));
 724
 725         ctllo = DWC_DEFAULT_CTLLO(chan)
 726                         | DWC_CTLL_DST_WIDTH(dst_width)
 727                         | DWC_CTLL_SRC_WIDTH(src_width)
 728                         | DWC_CTLL_DST_INC
 729                         | DWC_CTLL_SRC_INC
 730                         | DWC_CTLL_FC_M2M;
 731         prev = first = NULL;
 732
 733         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 734                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 735                                            dwc->block_size);
 736
 737                 desc = dwc_desc_get(dwc);
 738                 if (!desc)
 739                         goto err_desc_get;
 740
 741                 desc->lli.sar = src + offset;
 742                 desc->lli.dar = dest + offset;
 743                 desc->lli.ctllo = ctllo;
 744                 desc->lli.ctlhi = xfer_count;
 745                 desc->len = xfer_count << src_width;
 746
 747                 if (!first) {
 748                         first = desc;
 749                 } else {
 750                         prev->lli.llp = desc->txd.phys;
 751                         list_add_tail(&desc->desc_node,
 752                                         &first->tx_list);
 753                 }
 754                 prev = desc;
 755         }
 756
 757         if (flags & DMA_PREP_INTERRUPT)
 758                 /* Trigger interrupt after last block */
 759                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 760
 761         prev->lli.llp = 0;
 762         first->txd.flags = flags;
 763         first->total_len = len;
 764
 765         return &first->txd;
 766
 767 err_desc_get:
 768         dwc_desc_put(dwc, first);
 769         return NULL;
 770 }
 771
 772 static struct dma_async_tx_descriptor *
 773 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 774                 unsigned int sg_len, enum dma_transfer_direction direction,
 775                 unsigned long flags, void *context)
 776 {
 777         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 778         struct dw_dma           *dw = to_dw_dma(chan->device);
 779         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 780         struct dw_desc          *prev;
 781         struct dw_desc          *first;
 782         u32                     ctllo;
 783         dma_addr_t              reg;
 784         unsigned int            reg_width;
 785         unsigned int            mem_width;
 786         unsigned int            data_width;
 787         unsigned int            i;
 788         struct scatterlist      *sg;
 789         size_t                  total_len = 0;
 790
 791         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 792
 793         if (unlikely(!is_slave_direction(direction) || !sg_len))
 794                 return NULL;
 795
 796         dwc->direction = direction;
 797
 798         prev = first = NULL;
 799
 800         switch (direction) {
 801         case DMA_MEM_TO_DEV:
 802                 reg_width = __ffs(sconfig->dst_addr_width);
 803                 reg = sconfig->dst_addr;
 804                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 805                                 | DWC_CTLL_DST_WIDTH(reg_width)
 806                                 | DWC_CTLL_DST_FIX
 807                                 | DWC_CTLL_SRC_INC);
 808
 809                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 810                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 811
 812                 data_width = dw->data_width[dwc->src_master];
 813
 814                 for_each_sg(sgl, sg, sg_len, i) {
 815                         struct dw_desc  *desc;
 816                         u32             len, dlen, mem;
 817
 818                         mem = sg_dma_address(sg);
 819                         len = sg_dma_len(sg);
 820
 821                         mem_width = min_t(unsigned int,
 822                                           data_width, dwc_fast_ffs(mem | len));
 823
 824 slave_sg_todev_fill_desc:
 825                         desc = dwc_desc_get(dwc);
 826                         if (!desc)
 827                                 goto err_desc_get;
 828
 829                         desc->lli.sar = mem;
 830                         desc->lli.dar = reg;
 831                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 832                         if ((len >> mem_width) > dwc->block_size) {
 833                                 dlen = dwc->block_size << mem_width;
 834                                 mem += dlen;
 835                                 len -= dlen;
 836                         } else {
 837                                 dlen = len;
 838                                 len = 0;
 839                         }
 840
 841                         desc->lli.ctlhi = dlen >> mem_width;
 842                         desc->len = dlen;
 843
 844                         if (!first) {
 845                                 first = desc;
 846                         } else {
 847                                 prev->lli.llp = desc->txd.phys;
 848                                 list_add_tail(&desc->desc_node,
 849                                                 &first->tx_list);
 850                         }
 851                         prev = desc;
 852                         total_len += dlen;
 853
 854                         if (len)
 855                                 goto slave_sg_todev_fill_desc;
 856                 }
 857                 break;
 858         case DMA_DEV_TO_MEM:
 859                 reg_width = __ffs(sconfig->src_addr_width);
 860                 reg = sconfig->src_addr;
 861                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 862                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 863                                 | DWC_CTLL_DST_INC
 864                                 | DWC_CTLL_SRC_FIX);
 865
 866                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 867                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 868
 869                 data_width = dw->data_width[dwc->dst_master];
 870
 871                 for_each_sg(sgl, sg, sg_len, i) {
 872                         struct dw_desc  *desc;
 873                         u32             len, dlen, mem;
 874
 875                         mem = sg_dma_address(sg);
 876                         len = sg_dma_len(sg);
 877
 878                         mem_width = min_t(unsigned int,
 879                                           data_width, dwc_fast_ffs(mem | len));
 880
 881 slave_sg_fromdev_fill_desc:
 882                         desc = dwc_desc_get(dwc);
 883                         if (!desc)
 884                                 goto err_desc_get;
 885
 886                         desc->lli.sar = reg;
 887                         desc->lli.dar = mem;
 888                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 889                         if ((len >> reg_width) > dwc->block_size) {
 890                                 dlen = dwc->block_size << reg_width;
 891                                 mem += dlen;
 892                                 len -= dlen;
 893                         } else {
 894                                 dlen = len;
 895                                 len = 0;
 896                         }
 897                         desc->lli.ctlhi = dlen >> reg_width;
 898                         desc->len = dlen;
 899
 900                         if (!first) {
 901                                 first = desc;
 902                         } else {
 903                                 prev->lli.llp = desc->txd.phys;
 904                                 list_add_tail(&desc->desc_node,
 905                                                 &first->tx_list);
 906                         }
 907                         prev = desc;
 908                         total_len += dlen;
 909
 910                         if (len)
 911                                 goto slave_sg_fromdev_fill_desc;
 912                 }
 913                 break;
 914         default:
 915                 return NULL;
 916         }
 917
 918         if (flags & DMA_PREP_INTERRUPT)
 919                 /* Trigger interrupt after last block */
 920                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 921
 922         prev->lli.llp = 0;
 923         first->total_len = total_len;
 924
 925         return &first->txd;
 926
 927 err_desc_get:
 928         dev_err(chan2dev(chan),
 929                 "not enough descriptors available. Direction %d\n", direction);
 930         dwc_desc_put(dwc, first);
 931         return NULL;
 932 }
 933
 934 bool dw_dma_filter(struct dma_chan *chan, void *param)
 935 {
 936         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 937         struct dw_dma_slave *dws = param;
 938
 939         if (!dws || dws->dma_dev != chan->device->dev)
 940                 return false;
 941
 942         /* We have to copy data since dws can be temporary storage */
 943
 944         dwc->src_id = dws->src_id;
 945         dwc->dst_id = dws->dst_id;
 946
 947         dwc->src_master = dws->src_master;
 948         dwc->dst_master = dws->dst_master;
 949
 950         return true;
 951 }
 952 EXPORT_SYMBOL_GPL(dw_dma_filter);
 953
 954 /*
 955  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 956  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 957  *
 958  * NOTE: burst size 2 is not supported by controller.
 959  *
 960  * This can be done by finding least significant bit set: n & (n - 1)
 961  */
 962 static inline void convert_burst(u32 *maxburst)
 963 {
 964         if (*maxburst > 1)
 965                 *maxburst = fls(*maxburst) - 2;
 966         else
 967                 *maxburst = 0;
 968 }
 969
 970 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 971 {
 972         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 973
 974         /* Check if chan will be configured for slave transfers */
 975         if (!is_slave_direction(sconfig->direction))
 976                 return -EINVAL;
 977
 978         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 979         dwc->direction = sconfig->direction;
 980
 981         convert_burst(&dwc->dma_sconfig.src_maxburst);
 982         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 983
 984         return 0;
 985 }
 986
 987 static int dwc_pause(struct dma_chan *chan)
 988 {
 989         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 990         unsigned long           flags;
 991         unsigned int            count = 20;     /* timeout iterations */
 992         u32                     cfglo;
 993
 994         spin_lock_irqsave(&dwc->lock, flags);
 995
 996         cfglo = channel_readl(dwc, CFG_LO);
 997         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 998         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 999                 udelay(2);
1000
1001         dwc->paused = true;
1002
1003         spin_unlock_irqrestore(&dwc->lock, flags);
1004
1005         return 0;
1006 }
1007
1008 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1009 {
1010         u32 cfglo = channel_readl(dwc, CFG_LO);
1011
1012         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1013
1014         dwc->paused = false;
1015 }
1016
1017 static int dwc_resume(struct dma_chan *chan)
1018 {
1019         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1020         unsigned long           flags;
1021
1022         if (!dwc->paused)
1023                 return 0;
1024
1025         spin_lock_irqsave(&dwc->lock, flags);
1026
1027         dwc_chan_resume(dwc);
1028
1029         spin_unlock_irqrestore(&dwc->lock, flags);
1030
1031         return 0;
1032 }
1033
1034 static int dwc_terminate_all(struct dma_chan *chan)
1035 {
1036         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1037         struct dw_dma           *dw = to_dw_dma(chan->device);
1038         struct dw_desc          *desc, *_desc;
1039         unsigned long           flags;
1040         LIST_HEAD(list);
1041
1042         spin_lock_irqsave(&dwc->lock, flags);
1043
1044         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1045
1046         dwc_chan_disable(dw, dwc);
1047
1048         dwc_chan_resume(dwc);
1049
1050         /* active_list entries will end up before queued entries */
1051         list_splice_init(&dwc->queue, &list);
1052         list_splice_init(&dwc->active_list, &list);
1053
1054         spin_unlock_irqrestore(&dwc->lock, flags);
1055
1056         /* Flush all pending and queued descriptors */
1057         list_for_each_entry_safe(desc, _desc, &list, desc_node)
1058                 dwc_descriptor_complete(dwc, desc, false);
1059
1060         return 0;
1061 }
1062
1063 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1064 {
1065         unsigned long flags;
1066         u32 residue;
1067
1068         spin_lock_irqsave(&dwc->lock, flags);
1069
1070         residue = dwc->residue;
1071         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1072                 residue -= dwc_get_sent(dwc);
1073
1074         spin_unlock_irqrestore(&dwc->lock, flags);
1075         return residue;
1076 }
1077
1078 static enum dma_status
1079 dwc_tx_status(struct dma_chan *chan,
1080               dma_cookie_t cookie,
1081               struct dma_tx_state *txstate)
1082 {
1083         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1084         enum dma_status         ret;
1085
1086         ret = dma_cookie_status(chan, cookie, txstate);
1087         if (ret == DMA_COMPLETE)
1088                 return ret;
1089
1090         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1091
1092         ret = dma_cookie_status(chan, cookie, txstate);
1093         if (ret != DMA_COMPLETE)
1094                 dma_set_residue(txstate, dwc_get_residue(dwc));
1095
1096         if (dwc->paused && ret == DMA_IN_PROGRESS)
1097                 return DMA_PAUSED;
1098
1099         return ret;
1100 }
1101
1102 static void dwc_issue_pending(struct dma_chan *chan)
1103 {
1104         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1105         unsigned long           flags;
1106
1107         spin_lock_irqsave(&dwc->lock, flags);
1108         if (list_empty(&dwc->active_list))
1109                 dwc_dostart_first_queued(dwc);
1110         spin_unlock_irqrestore(&dwc->lock, flags);
1111 }
1112
1113 /*----------------------------------------------------------------------*/
1114
1115 static void dw_dma_off(struct dw_dma *dw)
1116 {
1117         int i;
1118
1119         dma_writel(dw, CFG, 0);
1120
1121         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1122         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1123         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1124         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1125         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1126
1127         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1128                 cpu_relax();
1129
1130         for (i = 0; i < dw->dma.chancnt; i++)
1131                 dw->chan[i].initialized = false;
1132 }
1133
1134 static void dw_dma_on(struct dw_dma *dw)
1135 {
1136         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1137 }
1138
1139 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1140 {
1141         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1142         struct dw_dma           *dw = to_dw_dma(chan->device);
1143         struct dw_desc          *desc;
1144         int                     i;
1145         unsigned long           flags;
1146
1147         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1148
1149         /* ASSERT:  channel is idle */
1150         if (dma_readl(dw, CH_EN) & dwc->mask) {
1151                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1152                 return -EIO;
1153         }
1154
1155         dma_cookie_init(chan);
1156
1157         /*
1158          * NOTE: some controllers may have additional features that we
1159          * need to initialize here, like "scatter-gather" (which
1160          * doesn't mean what you think it means), and status writeback.
1161          */
1162
1163         /* Enable controller here if needed */
1164         if (!dw->in_use)
1165                 dw_dma_on(dw);
1166         dw->in_use |= dwc->mask;
1167
1168         spin_lock_irqsave(&dwc->lock, flags);
1169         i = dwc->descs_allocated;
1170         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1171                 dma_addr_t phys;
1172
1173                 spin_unlock_irqrestore(&dwc->lock, flags);
1174
1175                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1176                 if (!desc)
1177                         goto err_desc_alloc;
1178
1179                 memset(desc, 0, sizeof(struct dw_desc));
1180
1181                 INIT_LIST_HEAD(&desc->tx_list);
1182                 dma_async_tx_descriptor_init(&desc->txd, chan);
1183                 desc->txd.tx_submit = dwc_tx_submit;
1184                 desc->txd.flags = DMA_CTRL_ACK;
1185                 desc->txd.phys = phys;
1186
1187                 dwc_desc_put(dwc, desc);
1188
1189                 spin_lock_irqsave(&dwc->lock, flags);
1190                 i = ++dwc->descs_allocated;
1191         }
1192
1193         spin_unlock_irqrestore(&dwc->lock, flags);
1194
1195         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1196
1197         return i;
1198
1199 err_desc_alloc:
1200         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1201
1202         return i;
1203 }
1204
1205 static void dwc_free_chan_resources(struct dma_chan *chan)
1206 {
1207         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1208         struct dw_dma           *dw = to_dw_dma(chan->device);
1209         struct dw_desc          *desc, *_desc;
1210         unsigned long           flags;
1211         LIST_HEAD(list);
1212
1213         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1214                         dwc->descs_allocated);
1215
1216         /* ASSERT:  channel is idle */
1217         BUG_ON(!list_empty(&dwc->active_list));
1218         BUG_ON(!list_empty(&dwc->queue));
1219         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1220
1221         spin_lock_irqsave(&dwc->lock, flags);
1222         list_splice_init(&dwc->free_list, &list);
1223         dwc->descs_allocated = 0;
1224         dwc->initialized = false;
1225
1226         /* Disable interrupts */
1227         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1228         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1229         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1230
1231         spin_unlock_irqrestore(&dwc->lock, flags);
1232
1233         /* Disable controller in case it was a last user */
1234         dw->in_use &= ~dwc->mask;
1235         if (!dw->in_use)
1236                 dw_dma_off(dw);
1237
1238         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1239                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1240                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1241         }
1242
1243         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1244 }
1245
1246 /* --------------------- Cyclic DMA API extensions -------------------- */
1247
1248 /**
1249  * dw_dma_cyclic_start - start the cyclic DMA transfer
1250  * @chan: the DMA channel to start
1251  *
1252  * Must be called with soft interrupts disabled. Returns zero on success or
1253  * -errno on failure.
1254  */
1255 int dw_dma_cyclic_start(struct dma_chan *chan)
1256 {
1257         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1258         struct dw_dma           *dw = to_dw_dma(chan->device);
1259         unsigned long           flags;
1260
1261         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1262                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1263                 return -ENODEV;
1264         }
1265
1266         spin_lock_irqsave(&dwc->lock, flags);
1267
1268         /* Enable interrupts to perform cyclic transfer */
1269         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1270
1271         dwc_dostart(dwc, dwc->cdesc->desc[0]);
1272
1273         spin_unlock_irqrestore(&dwc->lock, flags);
1274
1275         return 0;
1276 }
1277 EXPORT_SYMBOL(dw_dma_cyclic_start);
1278
1279 /**
1280  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1281  * @chan: the DMA channel to stop
1282  *
1283  * Must be called with soft interrupts disabled.
1284  */
1285 void dw_dma_cyclic_stop(struct dma_chan *chan)
1286 {
1287         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1288         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1289         unsigned long           flags;
1290
1291         spin_lock_irqsave(&dwc->lock, flags);
1292
1293         dwc_chan_disable(dw, dwc);
1294
1295         spin_unlock_irqrestore(&dwc->lock, flags);
1296 }
1297 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1298
1299 /**
1300  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1301  * @chan: the DMA channel to prepare
1302  * @buf_addr: physical DMA address where the buffer starts
1303  * @buf_len: total number of bytes for the entire buffer
1304  * @period_len: number of bytes for each period
1305  * @direction: transfer direction, to or from device
1306  *
1307  * Must be called before trying to start the transfer. Returns a valid struct
1308  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1309  */
1310 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1311                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1312                 enum dma_transfer_direction direction)
1313 {
1314         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1315         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1316         struct dw_cyclic_desc           *cdesc;
1317         struct dw_cyclic_desc           *retval = NULL;
1318         struct dw_desc                  *desc;
1319         struct dw_desc                  *last = NULL;
1320         unsigned long                   was_cyclic;
1321         unsigned int                    reg_width;
1322         unsigned int                    periods;
1323         unsigned int                    i;
1324         unsigned long                   flags;
1325
1326         spin_lock_irqsave(&dwc->lock, flags);
1327         if (dwc->nollp) {
1328                 spin_unlock_irqrestore(&dwc->lock, flags);
1329                 dev_dbg(chan2dev(&dwc->chan),
1330                                 "channel doesn't support LLP transfers\n");
1331                 return ERR_PTR(-EINVAL);
1332         }
1333
1334         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1335                 spin_unlock_irqrestore(&dwc->lock, flags);
1336                 dev_dbg(chan2dev(&dwc->chan),
1337                                 "queue and/or active list are not empty\n");
1338                 return ERR_PTR(-EBUSY);
1339         }
1340
1341         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1342         spin_unlock_irqrestore(&dwc->lock, flags);
1343         if (was_cyclic) {
1344                 dev_dbg(chan2dev(&dwc->chan),
1345                                 "channel already prepared for cyclic DMA\n");
1346                 return ERR_PTR(-EBUSY);
1347         }
1348
1349         retval = ERR_PTR(-EINVAL);
1350
1351         if (unlikely(!is_slave_direction(direction)))
1352                 goto out_err;
1353
1354         dwc->direction = direction;
1355
1356         if (direction == DMA_MEM_TO_DEV)
1357                 reg_width = __ffs(sconfig->dst_addr_width);
1358         else
1359                 reg_width = __ffs(sconfig->src_addr_width);
1360
1361         periods = buf_len / period_len;
1362
1363         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1364         if (period_len > (dwc->block_size << reg_width))
1365                 goto out_err;
1366         if (unlikely(period_len & ((1 << reg_width) - 1)))
1367                 goto out_err;
1368         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1369                 goto out_err;
1370
1371         retval = ERR_PTR(-ENOMEM);
1372
1373         if (periods > NR_DESCS_PER_CHANNEL)
1374                 goto out_err;
1375
1376         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1377         if (!cdesc)
1378                 goto out_err;
1379
1380         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1381         if (!cdesc->desc)
1382                 goto out_err_alloc;
1383
1384         for (i = 0; i < periods; i++) {
1385                 desc = dwc_desc_get(dwc);
1386                 if (!desc)
1387                         goto out_err_desc_get;
1388
1389                 switch (direction) {
1390                 case DMA_MEM_TO_DEV:
1391                         desc->lli.dar = sconfig->dst_addr;
1392                         desc->lli.sar = buf_addr + (period_len * i);
1393                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1394                                         | DWC_CTLL_DST_WIDTH(reg_width)
1395                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1396                                         | DWC_CTLL_DST_FIX
1397                                         | DWC_CTLL_SRC_INC
1398                                         | DWC_CTLL_INT_EN);
1399
1400                         desc->lli.ctllo |= sconfig->device_fc ?
1401                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1402                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1403
1404                         break;
1405                 case DMA_DEV_TO_MEM:
1406                         desc->lli.dar = buf_addr + (period_len * i);
1407                         desc->lli.sar = sconfig->src_addr;
1408                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1409                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1410                                         | DWC_CTLL_DST_WIDTH(reg_width)
1411                                         | DWC_CTLL_DST_INC
1412                                         | DWC_CTLL_SRC_FIX
1413                                         | DWC_CTLL_INT_EN);
1414
1415                         desc->lli.ctllo |= sconfig->device_fc ?
1416                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1417                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1418
1419                         break;
1420                 default:
1421                         break;
1422                 }
1423
1424                 desc->lli.ctlhi = (period_len >> reg_width);
1425                 cdesc->desc[i] = desc;
1426
1427                 if (last)
1428                         last->lli.llp = desc->txd.phys;
1429
1430                 last = desc;
1431         }
1432
1433         /* Let's make a cyclic list */
1434         last->lli.llp = cdesc->desc[0]->txd.phys;
1435
1436         dev_dbg(chan2dev(&dwc->chan),
1437                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1438                         &buf_addr, buf_len, period_len, periods);
1439
1440         cdesc->periods = periods;
1441         dwc->cdesc = cdesc;
1442
1443         return cdesc;
1444
1445 out_err_desc_get:
1446         while (i--)
1447                 dwc_desc_put(dwc, cdesc->desc[i]);
1448 out_err_alloc:
1449         kfree(cdesc);
1450 out_err:
1451         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1452         return (struct dw_cyclic_desc *)retval;
1453 }
1454 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1455
1456 /**
1457  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1458  * @chan: the DMA channel to free
1459  */
1460 void dw_dma_cyclic_free(struct dma_chan *chan)
1461 {
1462         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1463         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1464         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1465         int                     i;
1466         unsigned long           flags;
1467
1468         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1469
1470         if (!cdesc)
1471                 return;
1472
1473         spin_lock_irqsave(&dwc->lock, flags);
1474
1475         dwc_chan_disable(dw, dwc);
1476
1477         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1478         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1479         dma_writel(dw, CLEAR.XFER, dwc->mask);
1480
1481         spin_unlock_irqrestore(&dwc->lock, flags);
1482
1483         for (i = 0; i < cdesc->periods; i++)
1484                 dwc_desc_put(dwc, cdesc->desc[i]);
1485
1486         kfree(cdesc->desc);
1487         kfree(cdesc);
1488
1489         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1490 }
1491 EXPORT_SYMBOL(dw_dma_cyclic_free);
1492
1493 /*----------------------------------------------------------------------*/
1494
1495 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1496 {
1497         struct dw_dma           *dw;
1498         bool                    autocfg = false;
1499         unsigned int            dw_params;
1500         unsigned int            max_blk_size = 0;
1501         int                     err;
1502         int                     i;
1503
1504         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1505         if (!dw)
1506                 return -ENOMEM;
1507
1508         dw->regs = chip->regs;
1509         chip->dw = dw;
1510
1511         pm_runtime_get_sync(chip->dev);
1512
1513         if (!pdata) {
1514                 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1515                 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1516
1517                 autocfg = dw_params >> DW_PARAMS_EN & 1;
1518                 if (!autocfg) {
1519                         err = -EINVAL;
1520                         goto err_pdata;
1521                 }
1522
1523                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1524                 if (!pdata) {
1525                         err = -ENOMEM;
1526                         goto err_pdata;
1527                 }
1528
1529                 /* Get hardware configuration parameters */
1530                 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1531                 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1532                 for (i = 0; i < pdata->nr_masters; i++) {
1533                         pdata->data_width[i] =
1534                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1535                 }
1536                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1537
1538                 /* Fill platform data with the default values */
1539                 pdata->is_private = true;
1540                 pdata->is_memcpy = true;
1541                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1542                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1543         } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1544                 err = -EINVAL;
1545                 goto err_pdata;
1546         }
1547
1548         dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1549                                 GFP_KERNEL);
1550         if (!dw->chan) {
1551                 err = -ENOMEM;
1552                 goto err_pdata;
1553         }
1554
1555         /* Get hardware configuration parameters */
1556         dw->nr_masters = pdata->nr_masters;
1557         for (i = 0; i < dw->nr_masters; i++)
1558                 dw->data_width[i] = pdata->data_width[i];
1559
1560         /* Calculate all channel mask before DMA setup */
1561         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1562
1563         /* Force dma off, just in case */
1564         dw_dma_off(dw);
1565
1566         /* Create a pool of consistent memory blocks for hardware descriptors */
1567         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1568                                          sizeof(struct dw_desc), 4, 0);
1569         if (!dw->desc_pool) {
1570                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1571                 err = -ENOMEM;
1572                 goto err_pdata;
1573         }
1574
1575         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1576
1577         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1578                           "dw_dmac", dw);
1579         if (err)
1580                 goto err_pdata;
1581
1582         INIT_LIST_HEAD(&dw->dma.channels);
1583         for (i = 0; i < pdata->nr_channels; i++) {
1584                 struct dw_dma_chan      *dwc = &dw->chan[i];
1585
1586                 dwc->chan.device = &dw->dma;
1587                 dma_cookie_init(&dwc->chan);
1588                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1589                         list_add_tail(&dwc->chan.device_node,
1590                                         &dw->dma.channels);
1591                 else
1592                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1593
1594                 /* 7 is highest priority & 0 is lowest. */
1595                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1596                         dwc->priority = pdata->nr_channels - i - 1;
1597                 else
1598                         dwc->priority = i;
1599
1600                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1601                 spin_lock_init(&dwc->lock);
1602                 dwc->mask = 1 << i;
1603
1604                 INIT_LIST_HEAD(&dwc->active_list);
1605                 INIT_LIST_HEAD(&dwc->queue);
1606                 INIT_LIST_HEAD(&dwc->free_list);
1607
1608                 channel_clear_bit(dw, CH_EN, dwc->mask);
1609
1610                 dwc->direction = DMA_TRANS_NONE;
1611
1612                 /* Hardware configuration */
1613                 if (autocfg) {
1614                         unsigned int dwc_params;
1615                         unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1616                         void __iomem *addr = chip->regs + r * sizeof(u32);
1617
1618                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1619
1620                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1621                                            dwc_params);
1622
1623                         /*
1624                          * Decode maximum block size for given channel. The
1625                          * stored 4 bit value represents blocks from 0x00 for 3
1626                          * up to 0x0a for 4095.
1627                          */
1628                         dwc->block_size =
1629                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1630                         dwc->nollp =
1631                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1632                 } else {
1633                         dwc->block_size = pdata->block_size;
1634
1635                         /* Check if channel supports multi block transfer */
1636                         channel_writel(dwc, LLP, 0xfffffffc);
1637                         dwc->nollp =
1638                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1639                         channel_writel(dwc, LLP, 0);
1640                 }
1641         }
1642
1643         /* Clear all interrupts on all channels. */
1644         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1645         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1646         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1647         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1648         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1649
1650         /* Set capabilities */
1651         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1652         if (pdata->is_private)
1653                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1654         if (pdata->is_memcpy)
1655                 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1656
1657         dw->dma.dev = chip->dev;
1658         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1659         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1660
1661         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1662         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1663
1664         dw->dma.device_config = dwc_config;
1665         dw->dma.device_pause = dwc_pause;
1666         dw->dma.device_resume = dwc_resume;
1667         dw->dma.device_terminate_all = dwc_terminate_all;
1668
1669         dw->dma.device_tx_status = dwc_tx_status;
1670         dw->dma.device_issue_pending = dwc_issue_pending;
1671
1672         /* DMA capabilities */
1673         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1674         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1675         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1676                              BIT(DMA_MEM_TO_MEM);
1677         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1678
1679         err = dma_async_device_register(&dw->dma);
1680         if (err)
1681                 goto err_dma_register;
1682
1683         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1684                  pdata->nr_channels);
1685
1686         pm_runtime_put_sync_suspend(chip->dev);
1687
1688         return 0;
1689
1690 err_dma_register:
1691         free_irq(chip->irq, dw);
1692 err_pdata:
1693         pm_runtime_put_sync_suspend(chip->dev);
1694         return err;
1695 }
1696 EXPORT_SYMBOL_GPL(dw_dma_probe);
1697
1698 int dw_dma_remove(struct dw_dma_chip *chip)
1699 {
1700         struct dw_dma           *dw = chip->dw;
1701         struct dw_dma_chan      *dwc, *_dwc;
1702
1703         pm_runtime_get_sync(chip->dev);
1704
1705         dw_dma_off(dw);
1706         dma_async_device_unregister(&dw->dma);
1707
1708         free_irq(chip->irq, dw);
1709         tasklet_kill(&dw->tasklet);
1710
1711         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1712                         chan.device_node) {
1713                 list_del(&dwc->chan.device_node);
1714                 channel_clear_bit(dw, CH_EN, dwc->mask);
1715         }
1716
1717         pm_runtime_put_sync_suspend(chip->dev);
1718         return 0;
1719 }
1720 EXPORT_SYMBOL_GPL(dw_dma_remove);
1721
1722 int dw_dma_disable(struct dw_dma_chip *chip)
1723 {
1724         struct dw_dma *dw = chip->dw;
1725
1726         dw_dma_off(dw);
1727         return 0;
1728 }
1729 EXPORT_SYMBOL_GPL(dw_dma_disable);
1730
1731 int dw_dma_enable(struct dw_dma_chip *chip)
1732 {
1733         struct dw_dma *dw = chip->dw;
1734
1735         dw_dma_on(dw);
1736         return 0;
1737 }
1738 EXPORT_SYMBOL_GPL(dw_dma_enable);
1739
1740 MODULE_LICENSE("GPL v2");
1741 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1742 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1743 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");