2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 #include <adf_accel_devices.h>
48 #include <adf_pf2vf_msg.h>
49 #include <adf_common_drv.h>
50 #include "adf_dh895xcc_hw_data.h"
53 /* Worker thread to service arbiter mappings based on dev SKUs */
54 static const uint32_t thrd_to_arb_map_sku4[] = {
55 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
56 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
57 0x00000000, 0x00000000, 0x00000000, 0x00000000
60 static const uint32_t thrd_to_arb_map_sku6[] = {
61 0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
62 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
63 0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
66 static struct adf_hw_device_class dh895xcc_class = {
67 .name = ADF_DH895XCC_DEVICE_NAME,
72 static uint32_t get_accel_mask(uint32_t fuse)
74 return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
75 ADF_DH895XCC_ACCELERATORS_MASK;
78 static uint32_t get_ae_mask(uint32_t fuse)
80 return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
83 static uint32_t get_num_accels(struct adf_hw_device_data *self)
87 if (!self || !self->accel_mask)
90 for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
91 if (self->accel_mask & (1 << i))
97 static uint32_t get_num_aes(struct adf_hw_device_data *self)
101 if (!self || !self->ae_mask)
104 for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
105 if (self->ae_mask & (1 << i))
111 static uint32_t get_misc_bar_id(struct adf_hw_device_data *self)
113 return ADF_DH895XCC_PMISC_BAR;
116 static uint32_t get_etr_bar_id(struct adf_hw_device_data *self)
118 return ADF_DH895XCC_ETR_BAR;
121 static uint32_t get_sram_bar_id(struct adf_hw_device_data *self)
123 return ADF_DH895XCC_SRAM_BAR;
126 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
128 int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
129 >> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
132 case ADF_DH895XCC_FUSECTL_SKU_1:
134 case ADF_DH895XCC_FUSECTL_SKU_2:
136 case ADF_DH895XCC_FUSECTL_SKU_3:
138 case ADF_DH895XCC_FUSECTL_SKU_4:
141 return DEV_SKU_UNKNOWN;
143 return DEV_SKU_UNKNOWN;
146 void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
147 uint32_t const **arb_map_config)
149 switch (accel_dev->accel_pci_dev.sku) {
151 *arb_map_config = thrd_to_arb_map_sku4;
156 *arb_map_config = thrd_to_arb_map_sku6;
159 dev_err(&GET_DEV(accel_dev),
160 "The configuration doesn't match any SKU");
161 *arb_map_config = NULL;
165 static uint32_t get_pf2vf_offset(uint32_t i)
167 return ADF_DH895XCC_PF2VF_OFFSET(i);
170 static uint32_t get_vintmsk_offset(uint32_t i)
172 return ADF_DH895XCC_VINTMSK_OFFSET(i);
175 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
177 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
178 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
179 void __iomem *csr = misc_bar->virt_addr;
182 /* Enable Accel Engine error detection & correction */
183 for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
184 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
185 val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
186 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
187 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
188 val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
189 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
192 /* Enable shared memory error detection & correction */
193 for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
194 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
195 val |= ADF_DH895XCC_ERRSSMSH_EN;
196 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
197 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
198 val |= ADF_DH895XCC_ERRSSMSH_EN;
199 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
203 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
207 addr = (&GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR])->virt_addr;
209 /* Enable bundle and misc interrupts */
210 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET,
211 accel_dev->pf.vf_info ? 0 :
212 GENMASK_ULL(GET_MAX_BANKS(accel_dev) - 1, 0));
213 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET,
214 ADF_DH895XCC_SMIA1_MASK);
217 static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
222 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
224 hw_data->dev_class = &dh895xcc_class;
225 hw_data->instance_id = dh895xcc_class.instances++;
226 hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
227 hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
228 hw_data->num_logical_accel = 1;
229 hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
230 hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
231 hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
232 hw_data->alloc_irq = adf_isr_resource_alloc;
233 hw_data->free_irq = adf_isr_resource_free;
234 hw_data->enable_error_correction = adf_enable_error_correction;
235 hw_data->get_accel_mask = get_accel_mask;
236 hw_data->get_ae_mask = get_ae_mask;
237 hw_data->get_num_accels = get_num_accels;
238 hw_data->get_num_aes = get_num_aes;
239 hw_data->get_etr_bar_id = get_etr_bar_id;
240 hw_data->get_misc_bar_id = get_misc_bar_id;
241 hw_data->get_pf2vf_offset = get_pf2vf_offset;
242 hw_data->get_vintmsk_offset = get_vintmsk_offset;
243 hw_data->get_sram_bar_id = get_sram_bar_id;
244 hw_data->get_sku = get_sku;
245 hw_data->fw_name = ADF_DH895XCC_FW;
246 hw_data->fw_mmp_name = ADF_DH895XCC_MMP;
247 hw_data->init_admin_comms = adf_init_admin_comms;
248 hw_data->exit_admin_comms = adf_exit_admin_comms;
249 hw_data->disable_iov = adf_disable_sriov;
250 hw_data->send_admin_init = adf_send_admin_init;
251 hw_data->init_arb = adf_init_arb;
252 hw_data->exit_arb = adf_exit_arb;
253 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
254 hw_data->enable_ints = adf_enable_ints;
255 hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
256 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
259 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
261 hw_data->dev_class->instances--;