kernel/drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/omap-dma.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/delay.h>
  39 #include <linux/crypto.h>
  40 #include <linux/cryptohash.h>
  41 #include <crypto/scatterwalk.h>
  42 #include <crypto/algapi.h>
  43 #include <crypto/sha.h>
  44 #include <crypto/hash.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 /* mostly device flags */
 105 #define FLAGS_BUSY              0
 106 #define FLAGS_FINAL             1
 107 #define FLAGS_DMA_ACTIVE        2
 108 #define FLAGS_OUTPUT_READY      3
 109 #define FLAGS_INIT              4
 110 #define FLAGS_CPU               5
 111 #define FLAGS_DMA_READY         6
 112 #define FLAGS_AUTO_XOR          7
 113 #define FLAGS_BE32_SHA1         8
 114 /* context flags */
 115 #define FLAGS_FINUP             16
 116 #define FLAGS_SG                17
 117
 118 #define FLAGS_MODE_SHIFT        18
 119 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 120 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 121 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 126
 127 #define FLAGS_HMAC              21
 128 #define FLAGS_ERROR             22
 129
 130 #define OP_UPDATE               1
 131 #define OP_FINAL                2
 132
 133 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 134 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 135
 136 #define BUFLEN                  PAGE_SIZE
 137
 138 struct omap_sham_dev;
 139
 140 struct omap_sham_reqctx {
 141         struct omap_sham_dev    *dd;
 142         unsigned long           flags;
 143         unsigned long           op;
 144
 145         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 146         size_t                  digcnt;
 147         size_t                  bufcnt;
 148         size_t                  buflen;
 149         dma_addr_t              dma_addr;
 150
 151         /* walk state */
 152         struct scatterlist      *sg;
 153         struct scatterlist      sgl;
 154         unsigned int            offset; /* offset in current sg */
 155         unsigned int            total;  /* total request */
 156
 157         u8                      buffer[0] OMAP_ALIGNED;
 158 };
 159
 160 struct omap_sham_hmac_ctx {
 161         struct crypto_shash     *shash;
 162         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 163         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164 };
 165
 166 struct omap_sham_ctx {
 167         struct omap_sham_dev    *dd;
 168
 169         unsigned long           flags;
 170
 171         /* fallback stuff */
 172         struct crypto_shash     *fallback;
 173
 174         struct omap_sham_hmac_ctx base[0];
 175 };
 176
 177 #define OMAP_SHAM_QUEUE_LENGTH  1
 178
 179 struct omap_sham_algs_info {
 180         struct ahash_alg        *algs_list;
 181         unsigned int            size;
 182         unsigned int            registered;
 183 };
 184
 185 struct omap_sham_pdata {
 186         struct omap_sham_algs_info      *algs_info;
 187         unsigned int    algs_info_size;
 188         unsigned long   flags;
 189         int             digest_size;
 190
 191         void            (*copy_hash)(struct ahash_request *req, int out);
 192         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 193                                       int final, int dma);
 194         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 195         int             (*poll_irq)(struct omap_sham_dev *dd);
 196         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 197
 198         u32             odigest_ofs;
 199         u32             idigest_ofs;
 200         u32             din_ofs;
 201         u32             digcnt_ofs;
 202         u32             rev_ofs;
 203         u32             mask_ofs;
 204         u32             sysstatus_ofs;
 205         u32             mode_ofs;
 206         u32             length_ofs;
 207
 208         u32             major_mask;
 209         u32             major_shift;
 210         u32             minor_mask;
 211         u32             minor_shift;
 212 };
 213
 214 struct omap_sham_dev {
 215         struct list_head        list;
 216         unsigned long           phys_base;
 217         struct device           *dev;
 218         void __iomem            *io_base;
 219         int                     irq;
 220         spinlock_t              lock;
 221         int                     err;
 222         unsigned int            dma;
 223         struct dma_chan         *dma_lch;
 224         struct tasklet_struct   done_task;
 225         u8                      polling_mode;
 226
 227         unsigned long           flags;
 228         struct crypto_queue     queue;
 229         struct ahash_request    *req;
 230
 231         const struct omap_sham_pdata    *pdata;
 232 };
 233
 234 struct omap_sham_drv {
 235         struct list_head        dev_list;
 236         spinlock_t              lock;
 237         unsigned long           flags;
 238 };
 239
 240 static struct omap_sham_drv sham = {
 241         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 242         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243 };
 244
 245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 246 {
 247         return __raw_readl(dd->io_base + offset);
 248 }
 249
 250 static inline void omap_sham_write(struct omap_sham_dev *dd,
 251                                         u32 offset, u32 value)
 252 {
 253         __raw_writel(value, dd->io_base + offset);
 254 }
 255
 256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 257                                         u32 value, u32 mask)
 258 {
 259         u32 val;
 260
 261         val = omap_sham_read(dd, address);
 262         val &= ~mask;
 263         val |= value;
 264         omap_sham_write(dd, address, val);
 265 }
 266
 267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 268 {
 269         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 270
 271         while (!(omap_sham_read(dd, offset) & bit)) {
 272                 if (time_is_before_jiffies(timeout))
 273                         return -ETIMEDOUT;
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 280 {
 281         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 282         struct omap_sham_dev *dd = ctx->dd;
 283         u32 *hash = (u32 *)ctx->digest;
 284         int i;
 285
 286         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 287                 if (out)
 288                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 289                 else
 290                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 291         }
 292 }
 293
 294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 295 {
 296         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 297         struct omap_sham_dev *dd = ctx->dd;
 298         int i;
 299
 300         if (ctx->flags & BIT(FLAGS_HMAC)) {
 301                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 302                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 303                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 304                 u32 *opad = (u32 *)bctx->opad;
 305
 306                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 307                         if (out)
 308                                 opad[i] = omap_sham_read(dd,
 309                                                 SHA_REG_ODIGEST(dd, i));
 310                         else
 311                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 312                                                 opad[i]);
 313                 }
 314         }
 315
 316         omap_sham_copy_hash_omap2(req, out);
 317 }
 318
 319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 320 {
 321         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 322         u32 *in = (u32 *)ctx->digest;
 323         u32 *hash = (u32 *)req->result;
 324         int i, d, big_endian = 0;
 325
 326         if (!hash)
 327                 return;
 328
 329         switch (ctx->flags & FLAGS_MODE_MASK) {
 330         case FLAGS_MODE_MD5:
 331                 d = MD5_DIGEST_SIZE / sizeof(u32);
 332                 break;
 333         case FLAGS_MODE_SHA1:
 334                 /* OMAP2 SHA1 is big endian */
 335                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 336                         big_endian = 1;
 337                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 338                 break;
 339         case FLAGS_MODE_SHA224:
 340                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 341                 break;
 342         case FLAGS_MODE_SHA256:
 343                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA384:
 346                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA512:
 349                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         default:
 352                 d = 0;
 353         }
 354
 355         if (big_endian)
 356                 for (i = 0; i < d; i++)
 357                         hash[i] = be32_to_cpu(in[i]);
 358         else
 359                 for (i = 0; i < d; i++)
 360                         hash[i] = le32_to_cpu(in[i]);
 361 }
 362
 363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 364 {
 365         pm_runtime_get_sync(dd->dev);
 366
 367         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 368                 set_bit(FLAGS_INIT, &dd->flags);
 369                 dd->err = 0;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 376                                  int final, int dma)
 377 {
 378         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 379         u32 val = length << 5, mask;
 380
 381         if (likely(ctx->digcnt))
 382                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 383
 384         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 385                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 386                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 387         /*
 388          * Setting ALGO_CONST only for the first iteration
 389          * and CLOSE_HASH only for the last one.
 390          */
 391         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 392                 val |= SHA_REG_CTRL_ALGO;
 393         if (!ctx->digcnt)
 394                 val |= SHA_REG_CTRL_ALGO_CONST;
 395         if (final)
 396                 val |= SHA_REG_CTRL_CLOSE_HASH;
 397
 398         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 399                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 400
 401         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 402 }
 403
 404 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 405 {
 406 }
 407
 408 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 409 {
 410         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 411 }
 412
 413 static int get_block_size(struct omap_sham_reqctx *ctx)
 414 {
 415         int d;
 416
 417         switch (ctx->flags & FLAGS_MODE_MASK) {
 418         case FLAGS_MODE_MD5:
 419         case FLAGS_MODE_SHA1:
 420                 d = SHA1_BLOCK_SIZE;
 421                 break;
 422         case FLAGS_MODE_SHA224:
 423         case FLAGS_MODE_SHA256:
 424                 d = SHA256_BLOCK_SIZE;
 425                 break;
 426         case FLAGS_MODE_SHA384:
 427         case FLAGS_MODE_SHA512:
 428                 d = SHA512_BLOCK_SIZE;
 429                 break;
 430         default:
 431                 d = 0;
 432         }
 433
 434         return d;
 435 }
 436
 437 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 438                                     u32 *value, int count)
 439 {
 440         for (; count--; value++, offset += 4)
 441                 omap_sham_write(dd, offset, *value);
 442 }
 443
 444 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 445                                  int final, int dma)
 446 {
 447         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 448         u32 val, mask;
 449
 450         /*
 451          * Setting ALGO_CONST only for the first iteration and
 452          * CLOSE_HASH only for the last one. Note that flags mode bits
 453          * correspond to algorithm encoding in mode register.
 454          */
 455         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 456         if (!ctx->digcnt) {
 457                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 458                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 459                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 460                 int bs, nr_dr;
 461
 462                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 463
 464                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 465                         bs = get_block_size(ctx);
 466                         nr_dr = bs / (2 * sizeof(u32));
 467                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 468                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 469                                           (u32 *)bctx->ipad, nr_dr);
 470                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 471                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 472                         ctx->digcnt += bs;
 473                 }
 474         }
 475
 476         if (final) {
 477                 val |= SHA_REG_MODE_CLOSE_HASH;
 478
 479                 if (ctx->flags & BIT(FLAGS_HMAC))
 480                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 481         }
 482
 483         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 484                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 485                SHA_REG_MODE_HMAC_KEY_PROC;
 486
 487         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 488         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 489         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 490         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 491                              SHA_REG_MASK_IT_EN |
 492                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 493                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 494 }
 495
 496 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 497 {
 498         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 499 }
 500
 501 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 502 {
 503         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 504                               SHA_REG_IRQSTATUS_INPUT_RDY);
 505 }
 506
 507 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 508                               size_t length, int final)
 509 {
 510         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 511         int count, len32, bs32, offset = 0;
 512         const u32 *buffer = (const u32 *)buf;
 513
 514         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 515                                                 ctx->digcnt, length, final);
 516
 517         dd->pdata->write_ctrl(dd, length, final, 0);
 518         dd->pdata->trigger(dd, length);
 519
 520         /* should be non-zero before next lines to disable clocks later */
 521         ctx->digcnt += length;
 522
 523         if (final)
 524                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 525
 526         set_bit(FLAGS_CPU, &dd->flags);
 527
 528         len32 = DIV_ROUND_UP(length, sizeof(u32));
 529         bs32 = get_block_size(ctx) / sizeof(u32);
 530
 531         while (len32) {
 532                 if (dd->pdata->poll_irq(dd))
 533                         return -ETIMEDOUT;
 534
 535                 for (count = 0; count < min(len32, bs32); count++, offset++)
 536                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 537                                         buffer[offset]);
 538                 len32 -= min(len32, bs32);
 539         }
 540
 541         return -EINPROGRESS;
 542 }
 543
 544 static void omap_sham_dma_callback(void *param)
 545 {
 546         struct omap_sham_dev *dd = param;
 547
 548         set_bit(FLAGS_DMA_READY, &dd->flags);
 549         tasklet_schedule(&dd->done_task);
 550 }
 551
 552 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 553                               size_t length, int final, int is_sg)
 554 {
 555         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 556         struct dma_async_tx_descriptor *tx;
 557         struct dma_slave_config cfg;
 558         int len32, ret, dma_min = get_block_size(ctx);
 559
 560         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 561                                                 ctx->digcnt, length, final);
 562
 563         memset(&cfg, 0, sizeof(cfg));
 564
 565         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 566         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 567         cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
 568
 569         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 570         if (ret) {
 571                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 572                 return ret;
 573         }
 574
 575         len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
 576
 577         if (is_sg) {
 578                 /*
 579                  * The SG entry passed in may not have the 'length' member
 580                  * set correctly so use a local SG entry (sgl) with the
 581                  * proper value for 'length' instead.  If this is not done,
 582                  * the dmaengine may try to DMA the incorrect amount of data.
 583                  */
 584                 sg_init_table(&ctx->sgl, 1);
 585                 ctx->sgl.page_link = ctx->sg->page_link;
 586                 ctx->sgl.offset = ctx->sg->offset;
 587                 sg_dma_len(&ctx->sgl) = len32;
 588                 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
 589
 590                 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
 591                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 592         } else {
 593                 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
 594                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 595         }
 596
 597         if (!tx) {
 598                 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
 599                 return -EINVAL;
 600         }
 601
 602         tx->callback = omap_sham_dma_callback;
 603         tx->callback_param = dd;
 604
 605         dd->pdata->write_ctrl(dd, length, final, 1);
 606
 607         ctx->digcnt += length;
 608
 609         if (final)
 610                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 611
 612         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 613
 614         dmaengine_submit(tx);
 615         dma_async_issue_pending(dd->dma_lch);
 616
 617         dd->pdata->trigger(dd, length);
 618
 619         return -EINPROGRESS;
 620 }
 621
 622 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 623                                 const u8 *data, size_t length)
 624 {
 625         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 626
 627         count = min(count, ctx->total);
 628         if (count <= 0)
 629                 return 0;
 630         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 631         ctx->bufcnt += count;
 632
 633         return count;
 634 }
 635
 636 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 637 {
 638         size_t count;
 639         const u8 *vaddr;
 640
 641         while (ctx->sg) {
 642                 vaddr = kmap_atomic(sg_page(ctx->sg));
 643                 vaddr += ctx->sg->offset;
 644
 645                 count = omap_sham_append_buffer(ctx,
 646                                 vaddr + ctx->offset,
 647                                 ctx->sg->length - ctx->offset);
 648
 649                 kunmap_atomic((void *)vaddr);
 650
 651                 if (!count)
 652                         break;
 653                 ctx->offset += count;
 654                 ctx->total -= count;
 655                 if (ctx->offset == ctx->sg->length) {
 656                         ctx->sg = sg_next(ctx->sg);
 657                         if (ctx->sg)
 658                                 ctx->offset = 0;
 659                         else
 660                                 ctx->total = 0;
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 668                                         struct omap_sham_reqctx *ctx,
 669                                         size_t length, int final)
 670 {
 671         int ret;
 672
 673         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 674                                        DMA_TO_DEVICE);
 675         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 676                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 677                 return -EINVAL;
 678         }
 679
 680         ctx->flags &= ~BIT(FLAGS_SG);
 681
 682         ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
 683         if (ret != -EINPROGRESS)
 684                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 685                                  DMA_TO_DEVICE);
 686
 687         return ret;
 688 }
 689
 690 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 691 {
 692         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 693         unsigned int final;
 694         size_t count;
 695
 696         omap_sham_append_sg(ctx);
 697
 698         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 699
 700         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 701                                          ctx->bufcnt, ctx->digcnt, final);
 702
 703         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 704                 count = ctx->bufcnt;
 705                 ctx->bufcnt = 0;
 706                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 707         }
 708
 709         return 0;
 710 }
 711
 712 /* Start address alignment */
 713 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 714 /* SHA1 block size alignment */
 715 #define SG_SA(sg, bs)   (IS_ALIGNED(sg->length, bs))
 716
 717 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 718 {
 719         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 720         unsigned int length, final, tail;
 721         struct scatterlist *sg;
 722         int ret, bs;
 723
 724         if (!ctx->total)
 725                 return 0;
 726
 727         if (ctx->bufcnt || ctx->offset)
 728                 return omap_sham_update_dma_slow(dd);
 729
 730         /*
 731          * Don't use the sg interface when the transfer size is less
 732          * than the number of elements in a DMA frame.  Otherwise,
 733          * the dmaengine infrastructure will calculate that it needs
 734          * to transfer 0 frames which ultimately fails.
 735          */
 736         if (ctx->total < get_block_size(ctx))
 737                 return omap_sham_update_dma_slow(dd);
 738
 739         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 740                         ctx->digcnt, ctx->bufcnt, ctx->total);
 741
 742         sg = ctx->sg;
 743         bs = get_block_size(ctx);
 744
 745         if (!SG_AA(sg))
 746                 return omap_sham_update_dma_slow(dd);
 747
 748         if (!sg_is_last(sg) && !SG_SA(sg, bs))
 749                 /* size is not BLOCK_SIZE aligned */
 750                 return omap_sham_update_dma_slow(dd);
 751
 752         length = min(ctx->total, sg->length);
 753
 754         if (sg_is_last(sg)) {
 755                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 756                         /* not last sg must be BLOCK_SIZE aligned */
 757                         tail = length & (bs - 1);
 758                         /* without finup() we need one block to close hash */
 759                         if (!tail)
 760                                 tail = bs;
 761                         length -= tail;
 762                 }
 763         }
 764
 765         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 766                 dev_err(dd->dev, "dma_map_sg  error\n");
 767                 return -EINVAL;
 768         }
 769
 770         ctx->flags |= BIT(FLAGS_SG);
 771
 772         ctx->total -= length;
 773         ctx->offset = length; /* offset where to start slow */
 774
 775         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 776
 777         ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
 778         if (ret != -EINPROGRESS)
 779                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 780
 781         return ret;
 782 }
 783
 784 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 785 {
 786         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 787         int bufcnt, final;
 788
 789         if (!ctx->total)
 790                 return 0;
 791
 792         omap_sham_append_sg(ctx);
 793
 794         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 795
 796         dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
 797                 ctx->bufcnt, ctx->digcnt, final);
 798
 799         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 800                 bufcnt = ctx->bufcnt;
 801                 ctx->bufcnt = 0;
 802                 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 809 {
 810         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 811
 812         dmaengine_terminate_all(dd->dma_lch);
 813
 814         if (ctx->flags & BIT(FLAGS_SG)) {
 815                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 816                 if (ctx->sg->length == ctx->offset) {
 817                         ctx->sg = sg_next(ctx->sg);
 818                         if (ctx->sg)
 819                                 ctx->offset = 0;
 820                 }
 821         } else {
 822                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 823                                  DMA_TO_DEVICE);
 824         }
 825
 826         return 0;
 827 }
 828
 829 static int omap_sham_init(struct ahash_request *req)
 830 {
 831         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 832         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 833         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 834         struct omap_sham_dev *dd = NULL, *tmp;
 835         int bs = 0;
 836
 837         spin_lock_bh(&sham.lock);
 838         if (!tctx->dd) {
 839                 list_for_each_entry(tmp, &sham.dev_list, list) {
 840                         dd = tmp;
 841                         break;
 842                 }
 843                 tctx->dd = dd;
 844         } else {
 845                 dd = tctx->dd;
 846         }
 847         spin_unlock_bh(&sham.lock);
 848
 849         ctx->dd = dd;
 850
 851         ctx->flags = 0;
 852
 853         dev_dbg(dd->dev, "init: digest size: %d\n",
 854                 crypto_ahash_digestsize(tfm));
 855
 856         switch (crypto_ahash_digestsize(tfm)) {
 857         case MD5_DIGEST_SIZE:
 858                 ctx->flags |= FLAGS_MODE_MD5;
 859                 bs = SHA1_BLOCK_SIZE;
 860                 break;
 861         case SHA1_DIGEST_SIZE:
 862                 ctx->flags |= FLAGS_MODE_SHA1;
 863                 bs = SHA1_BLOCK_SIZE;
 864                 break;
 865         case SHA224_DIGEST_SIZE:
 866                 ctx->flags |= FLAGS_MODE_SHA224;
 867                 bs = SHA224_BLOCK_SIZE;
 868                 break;
 869         case SHA256_DIGEST_SIZE:
 870                 ctx->flags |= FLAGS_MODE_SHA256;
 871                 bs = SHA256_BLOCK_SIZE;
 872                 break;
 873         case SHA384_DIGEST_SIZE:
 874                 ctx->flags |= FLAGS_MODE_SHA384;
 875                 bs = SHA384_BLOCK_SIZE;
 876                 break;
 877         case SHA512_DIGEST_SIZE:
 878                 ctx->flags |= FLAGS_MODE_SHA512;
 879                 bs = SHA512_BLOCK_SIZE;
 880                 break;
 881         }
 882
 883         ctx->bufcnt = 0;
 884         ctx->digcnt = 0;
 885         ctx->buflen = BUFLEN;
 886
 887         if (tctx->flags & BIT(FLAGS_HMAC)) {
 888                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 889                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 890
 891                         memcpy(ctx->buffer, bctx->ipad, bs);
 892                         ctx->bufcnt = bs;
 893                 }
 894
 895                 ctx->flags |= BIT(FLAGS_HMAC);
 896         }
 897
 898         return 0;
 899
 900 }
 901
 902 static int omap_sham_update_req(struct omap_sham_dev *dd)
 903 {
 904         struct ahash_request *req = dd->req;
 905         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 906         int err;
 907
 908         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 909                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 910
 911         if (ctx->flags & BIT(FLAGS_CPU))
 912                 err = omap_sham_update_cpu(dd);
 913         else
 914                 err = omap_sham_update_dma_start(dd);
 915
 916         /* wait for dma completion before can take more data */
 917         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 918
 919         return err;
 920 }
 921
 922 static int omap_sham_final_req(struct omap_sham_dev *dd)
 923 {
 924         struct ahash_request *req = dd->req;
 925         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 926         int err = 0, use_dma = 1;
 927
 928         if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
 929                 /*
 930                  * faster to handle last block with cpu or
 931                  * use cpu when dma is not present.
 932                  */
 933                 use_dma = 0;
 934
 935         if (use_dma)
 936                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 937         else
 938                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 939
 940         ctx->bufcnt = 0;
 941
 942         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 943
 944         return err;
 945 }
 946
 947 static int omap_sham_finish_hmac(struct ahash_request *req)
 948 {
 949         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 950         struct omap_sham_hmac_ctx *bctx = tctx->base;
 951         int bs = crypto_shash_blocksize(bctx->shash);
 952         int ds = crypto_shash_digestsize(bctx->shash);
 953         SHASH_DESC_ON_STACK(shash, bctx->shash);
 954
 955         shash->tfm = bctx->shash;
 956         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 957
 958         return crypto_shash_init(shash) ?:
 959                crypto_shash_update(shash, bctx->opad, bs) ?:
 960                crypto_shash_finup(shash, req->result, ds, req->result);
 961 }
 962
 963 static int omap_sham_finish(struct ahash_request *req)
 964 {
 965         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 966         struct omap_sham_dev *dd = ctx->dd;
 967         int err = 0;
 968
 969         if (ctx->digcnt) {
 970                 omap_sham_copy_ready_hash(req);
 971                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
 972                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
 973                         err = omap_sham_finish_hmac(req);
 974         }
 975
 976         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 977
 978         return err;
 979 }
 980
 981 static void omap_sham_finish_req(struct ahash_request *req, int err)
 982 {
 983         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 984         struct omap_sham_dev *dd = ctx->dd;
 985
 986         if (!err) {
 987                 dd->pdata->copy_hash(req, 1);
 988                 if (test_bit(FLAGS_FINAL, &dd->flags))
 989                         err = omap_sham_finish(req);
 990         } else {
 991                 ctx->flags |= BIT(FLAGS_ERROR);
 992         }
 993
 994         /* atomic operation is not needed here */
 995         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
 996                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
 997
 998         pm_runtime_put(dd->dev);
 999
1000         if (req->base.complete)
1001                 req->base.complete(&req->base, err);
1002
1003         /* handle new request */
1004         tasklet_schedule(&dd->done_task);
1005 }
1006
1007 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1008                                   struct ahash_request *req)
1009 {
1010         struct crypto_async_request *async_req, *backlog;
1011         struct omap_sham_reqctx *ctx;
1012         unsigned long flags;
1013         int err = 0, ret = 0;
1014
1015         spin_lock_irqsave(&dd->lock, flags);
1016         if (req)
1017                 ret = ahash_enqueue_request(&dd->queue, req);
1018         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1019                 spin_unlock_irqrestore(&dd->lock, flags);
1020                 return ret;
1021         }
1022         backlog = crypto_get_backlog(&dd->queue);
1023         async_req = crypto_dequeue_request(&dd->queue);
1024         if (async_req)
1025                 set_bit(FLAGS_BUSY, &dd->flags);
1026         spin_unlock_irqrestore(&dd->lock, flags);
1027
1028         if (!async_req)
1029                 return ret;
1030
1031         if (backlog)
1032                 backlog->complete(backlog, -EINPROGRESS);
1033
1034         req = ahash_request_cast(async_req);
1035         dd->req = req;
1036         ctx = ahash_request_ctx(req);
1037
1038         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1039                                                 ctx->op, req->nbytes);
1040
1041         err = omap_sham_hw_init(dd);
1042         if (err)
1043                 goto err1;
1044
1045         if (ctx->digcnt)
1046                 /* request has changed - restore hash */
1047                 dd->pdata->copy_hash(req, 0);
1048
1049         if (ctx->op == OP_UPDATE) {
1050                 err = omap_sham_update_req(dd);
1051                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1052                         /* no final() after finup() */
1053                         err = omap_sham_final_req(dd);
1054         } else if (ctx->op == OP_FINAL) {
1055                 err = omap_sham_final_req(dd);
1056         }
1057 err1:
1058         if (err != -EINPROGRESS)
1059                 /* done_task will not finish it, so do it here */
1060                 omap_sham_finish_req(req, err);
1061
1062         dev_dbg(dd->dev, "exit, err: %d\n", err);
1063
1064         return ret;
1065 }
1066
1067 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1068 {
1069         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1070         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1071         struct omap_sham_dev *dd = tctx->dd;
1072
1073         ctx->op = op;
1074
1075         return omap_sham_handle_queue(dd, req);
1076 }
1077
1078 static int omap_sham_update(struct ahash_request *req)
1079 {
1080         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1081         struct omap_sham_dev *dd = ctx->dd;
1082         int bs = get_block_size(ctx);
1083
1084         if (!req->nbytes)
1085                 return 0;
1086
1087         ctx->total = req->nbytes;
1088         ctx->sg = req->src;
1089         ctx->offset = 0;
1090
1091         if (ctx->flags & BIT(FLAGS_FINUP)) {
1092                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1093                         /*
1094                         * OMAP HW accel works only with buffers >= 9
1095                         * will switch to bypass in final()
1096                         * final has the same request and data
1097                         */
1098                         omap_sham_append_sg(ctx);
1099                         return 0;
1100                 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1101                            dd->polling_mode) {
1102                         /*
1103                          * faster to use CPU for short transfers or
1104                          * use cpu when dma is not present.
1105                          */
1106                         ctx->flags |= BIT(FLAGS_CPU);
1107                 }
1108         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1109                 omap_sham_append_sg(ctx);
1110                 return 0;
1111         }
1112
1113         if (dd->polling_mode)
1114                 ctx->flags |= BIT(FLAGS_CPU);
1115
1116         return omap_sham_enqueue(req, OP_UPDATE);
1117 }
1118
1119 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1120                                   const u8 *data, unsigned int len, u8 *out)
1121 {
1122         SHASH_DESC_ON_STACK(shash, tfm);
1123
1124         shash->tfm = tfm;
1125         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1126
1127         return crypto_shash_digest(shash, data, len, out);
1128 }
1129
1130 static int omap_sham_final_shash(struct ahash_request *req)
1131 {
1132         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1133         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1134
1135         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1136                                       ctx->buffer, ctx->bufcnt, req->result);
1137 }
1138
1139 static int omap_sham_final(struct ahash_request *req)
1140 {
1141         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1142
1143         ctx->flags |= BIT(FLAGS_FINUP);
1144
1145         if (ctx->flags & BIT(FLAGS_ERROR))
1146                 return 0; /* uncompleted hash is not needed */
1147
1148         /* OMAP HW accel works only with buffers >= 9 */
1149         /* HMAC is always >= 9 because ipad == block size */
1150         if ((ctx->digcnt + ctx->bufcnt) < 9)
1151                 return omap_sham_final_shash(req);
1152         else if (ctx->bufcnt)
1153                 return omap_sham_enqueue(req, OP_FINAL);
1154
1155         /* copy ready hash (+ finalize hmac) */
1156         return omap_sham_finish(req);
1157 }
1158
1159 static int omap_sham_finup(struct ahash_request *req)
1160 {
1161         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1162         int err1, err2;
1163
1164         ctx->flags |= BIT(FLAGS_FINUP);
1165
1166         err1 = omap_sham_update(req);
1167         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1168                 return err1;
1169         /*
1170          * final() has to be always called to cleanup resources
1171          * even if udpate() failed, except EINPROGRESS
1172          */
1173         err2 = omap_sham_final(req);
1174
1175         return err1 ?: err2;
1176 }
1177
1178 static int omap_sham_digest(struct ahash_request *req)
1179 {
1180         return omap_sham_init(req) ?: omap_sham_finup(req);
1181 }
1182
1183 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1184                       unsigned int keylen)
1185 {
1186         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1187         struct omap_sham_hmac_ctx *bctx = tctx->base;
1188         int bs = crypto_shash_blocksize(bctx->shash);
1189         int ds = crypto_shash_digestsize(bctx->shash);
1190         struct omap_sham_dev *dd = NULL, *tmp;
1191         int err, i;
1192
1193         spin_lock_bh(&sham.lock);
1194         if (!tctx->dd) {
1195                 list_for_each_entry(tmp, &sham.dev_list, list) {
1196                         dd = tmp;
1197                         break;
1198                 }
1199                 tctx->dd = dd;
1200         } else {
1201                 dd = tctx->dd;
1202         }
1203         spin_unlock_bh(&sham.lock);
1204
1205         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1206         if (err)
1207                 return err;
1208
1209         if (keylen > bs) {
1210                 err = omap_sham_shash_digest(bctx->shash,
1211                                 crypto_shash_get_flags(bctx->shash),
1212                                 key, keylen, bctx->ipad);
1213                 if (err)
1214                         return err;
1215                 keylen = ds;
1216         } else {
1217                 memcpy(bctx->ipad, key, keylen);
1218         }
1219
1220         memset(bctx->ipad + keylen, 0, bs - keylen);
1221
1222         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1223                 memcpy(bctx->opad, bctx->ipad, bs);
1224
1225                 for (i = 0; i < bs; i++) {
1226                         bctx->ipad[i] ^= 0x36;
1227                         bctx->opad[i] ^= 0x5c;
1228                 }
1229         }
1230
1231         return err;
1232 }
1233
1234 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1235 {
1236         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1237         const char *alg_name = crypto_tfm_alg_name(tfm);
1238
1239         /* Allocate a fallback and abort if it failed. */
1240         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1241                                             CRYPTO_ALG_NEED_FALLBACK);
1242         if (IS_ERR(tctx->fallback)) {
1243                 pr_err("omap-sham: fallback driver '%s' "
1244                                 "could not be loaded.\n", alg_name);
1245                 return PTR_ERR(tctx->fallback);
1246         }
1247
1248         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1249                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1250
1251         if (alg_base) {
1252                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1253                 tctx->flags |= BIT(FLAGS_HMAC);
1254                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1255                                                 CRYPTO_ALG_NEED_FALLBACK);
1256                 if (IS_ERR(bctx->shash)) {
1257                         pr_err("omap-sham: base driver '%s' "
1258                                         "could not be loaded.\n", alg_base);
1259                         crypto_free_shash(tctx->fallback);
1260                         return PTR_ERR(bctx->shash);
1261                 }
1262
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1269 {
1270         return omap_sham_cra_init_alg(tfm, NULL);
1271 }
1272
1273 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1274 {
1275         return omap_sham_cra_init_alg(tfm, "sha1");
1276 }
1277
1278 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1279 {
1280         return omap_sham_cra_init_alg(tfm, "sha224");
1281 }
1282
1283 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1284 {
1285         return omap_sham_cra_init_alg(tfm, "sha256");
1286 }
1287
1288 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1289 {
1290         return omap_sham_cra_init_alg(tfm, "md5");
1291 }
1292
1293 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1294 {
1295         return omap_sham_cra_init_alg(tfm, "sha384");
1296 }
1297
1298 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1299 {
1300         return omap_sham_cra_init_alg(tfm, "sha512");
1301 }
1302
1303 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1304 {
1305         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1306
1307         crypto_free_shash(tctx->fallback);
1308         tctx->fallback = NULL;
1309
1310         if (tctx->flags & BIT(FLAGS_HMAC)) {
1311                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1312                 crypto_free_shash(bctx->shash);
1313         }
1314 }
1315
1316 static struct ahash_alg algs_sha1_md5[] = {
1317 {
1318         .init           = omap_sham_init,
1319         .update         = omap_sham_update,
1320         .final          = omap_sham_final,
1321         .finup          = omap_sham_finup,
1322         .digest         = omap_sham_digest,
1323         .halg.digestsize        = SHA1_DIGEST_SIZE,
1324         .halg.base      = {
1325                 .cra_name               = "sha1",
1326                 .cra_driver_name        = "omap-sha1",
1327                 .cra_priority           = 100,
1328                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1329                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1330                                                 CRYPTO_ALG_ASYNC |
1331                                                 CRYPTO_ALG_NEED_FALLBACK,
1332                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1333                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1334                 .cra_alignmask          = 0,
1335                 .cra_module             = THIS_MODULE,
1336                 .cra_init               = omap_sham_cra_init,
1337                 .cra_exit               = omap_sham_cra_exit,
1338         }
1339 },
1340 {
1341         .init           = omap_sham_init,
1342         .update         = omap_sham_update,
1343         .final          = omap_sham_final,
1344         .finup          = omap_sham_finup,
1345         .digest         = omap_sham_digest,
1346         .halg.digestsize        = MD5_DIGEST_SIZE,
1347         .halg.base      = {
1348                 .cra_name               = "md5",
1349                 .cra_driver_name        = "omap-md5",
1350                 .cra_priority           = 100,
1351                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1352                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1353                                                 CRYPTO_ALG_ASYNC |
1354                                                 CRYPTO_ALG_NEED_FALLBACK,
1355                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1356                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1357                 .cra_alignmask          = OMAP_ALIGN_MASK,
1358                 .cra_module             = THIS_MODULE,
1359                 .cra_init               = omap_sham_cra_init,
1360                 .cra_exit               = omap_sham_cra_exit,
1361         }
1362 },
1363 {
1364         .init           = omap_sham_init,
1365         .update         = omap_sham_update,
1366         .final          = omap_sham_final,
1367         .finup          = omap_sham_finup,
1368         .digest         = omap_sham_digest,
1369         .setkey         = omap_sham_setkey,
1370         .halg.digestsize        = SHA1_DIGEST_SIZE,
1371         .halg.base      = {
1372                 .cra_name               = "hmac(sha1)",
1373                 .cra_driver_name        = "omap-hmac-sha1",
1374                 .cra_priority           = 100,
1375                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1376                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1377                                                 CRYPTO_ALG_ASYNC |
1378                                                 CRYPTO_ALG_NEED_FALLBACK,
1379                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1380                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1381                                         sizeof(struct omap_sham_hmac_ctx),
1382                 .cra_alignmask          = OMAP_ALIGN_MASK,
1383                 .cra_module             = THIS_MODULE,
1384                 .cra_init               = omap_sham_cra_sha1_init,
1385                 .cra_exit               = omap_sham_cra_exit,
1386         }
1387 },
1388 {
1389         .init           = omap_sham_init,
1390         .update         = omap_sham_update,
1391         .final          = omap_sham_final,
1392         .finup          = omap_sham_finup,
1393         .digest         = omap_sham_digest,
1394         .setkey         = omap_sham_setkey,
1395         .halg.digestsize        = MD5_DIGEST_SIZE,
1396         .halg.base      = {
1397                 .cra_name               = "hmac(md5)",
1398                 .cra_driver_name        = "omap-hmac-md5",
1399                 .cra_priority           = 100,
1400                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1401                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1402                                                 CRYPTO_ALG_ASYNC |
1403                                                 CRYPTO_ALG_NEED_FALLBACK,
1404                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1405                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1406                                         sizeof(struct omap_sham_hmac_ctx),
1407                 .cra_alignmask          = OMAP_ALIGN_MASK,
1408                 .cra_module             = THIS_MODULE,
1409                 .cra_init               = omap_sham_cra_md5_init,
1410                 .cra_exit               = omap_sham_cra_exit,
1411         }
1412 }
1413 };
1414
1415 /* OMAP4 has some algs in addition to what OMAP2 has */
1416 static struct ahash_alg algs_sha224_sha256[] = {
1417 {
1418         .init           = omap_sham_init,
1419         .update         = omap_sham_update,
1420         .final          = omap_sham_final,
1421         .finup          = omap_sham_finup,
1422         .digest         = omap_sham_digest,
1423         .halg.digestsize        = SHA224_DIGEST_SIZE,
1424         .halg.base      = {
1425                 .cra_name               = "sha224",
1426                 .cra_driver_name        = "omap-sha224",
1427                 .cra_priority           = 100,
1428                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1429                                                 CRYPTO_ALG_ASYNC |
1430                                                 CRYPTO_ALG_NEED_FALLBACK,
1431                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1432                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1433                 .cra_alignmask          = 0,
1434                 .cra_module             = THIS_MODULE,
1435                 .cra_init               = omap_sham_cra_init,
1436                 .cra_exit               = omap_sham_cra_exit,
1437         }
1438 },
1439 {
1440         .init           = omap_sham_init,
1441         .update         = omap_sham_update,
1442         .final          = omap_sham_final,
1443         .finup          = omap_sham_finup,
1444         .digest         = omap_sham_digest,
1445         .halg.digestsize        = SHA256_DIGEST_SIZE,
1446         .halg.base      = {
1447                 .cra_name               = "sha256",
1448                 .cra_driver_name        = "omap-sha256",
1449                 .cra_priority           = 100,
1450                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1451                                                 CRYPTO_ALG_ASYNC |
1452                                                 CRYPTO_ALG_NEED_FALLBACK,
1453                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1454                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1455                 .cra_alignmask          = 0,
1456                 .cra_module             = THIS_MODULE,
1457                 .cra_init               = omap_sham_cra_init,
1458                 .cra_exit               = omap_sham_cra_exit,
1459         }
1460 },
1461 {
1462         .init           = omap_sham_init,
1463         .update         = omap_sham_update,
1464         .final          = omap_sham_final,
1465         .finup          = omap_sham_finup,
1466         .digest         = omap_sham_digest,
1467         .setkey         = omap_sham_setkey,
1468         .halg.digestsize        = SHA224_DIGEST_SIZE,
1469         .halg.base      = {
1470                 .cra_name               = "hmac(sha224)",
1471                 .cra_driver_name        = "omap-hmac-sha224",
1472                 .cra_priority           = 100,
1473                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1474                                                 CRYPTO_ALG_ASYNC |
1475                                                 CRYPTO_ALG_NEED_FALLBACK,
1476                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1477                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1478                                         sizeof(struct omap_sham_hmac_ctx),
1479                 .cra_alignmask          = OMAP_ALIGN_MASK,
1480                 .cra_module             = THIS_MODULE,
1481                 .cra_init               = omap_sham_cra_sha224_init,
1482                 .cra_exit               = omap_sham_cra_exit,
1483         }
1484 },
1485 {
1486         .init           = omap_sham_init,
1487         .update         = omap_sham_update,
1488         .final          = omap_sham_final,
1489         .finup          = omap_sham_finup,
1490         .digest         = omap_sham_digest,
1491         .setkey         = omap_sham_setkey,
1492         .halg.digestsize        = SHA256_DIGEST_SIZE,
1493         .halg.base      = {
1494                 .cra_name               = "hmac(sha256)",
1495                 .cra_driver_name        = "omap-hmac-sha256",
1496                 .cra_priority           = 100,
1497                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1498                                                 CRYPTO_ALG_ASYNC |
1499                                                 CRYPTO_ALG_NEED_FALLBACK,
1500                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1501                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1502                                         sizeof(struct omap_sham_hmac_ctx),
1503                 .cra_alignmask          = OMAP_ALIGN_MASK,
1504                 .cra_module             = THIS_MODULE,
1505                 .cra_init               = omap_sham_cra_sha256_init,
1506                 .cra_exit               = omap_sham_cra_exit,
1507         }
1508 },
1509 };
1510
1511 static struct ahash_alg algs_sha384_sha512[] = {
1512 {
1513         .init           = omap_sham_init,
1514         .update         = omap_sham_update,
1515         .final          = omap_sham_final,
1516         .finup          = omap_sham_finup,
1517         .digest         = omap_sham_digest,
1518         .halg.digestsize        = SHA384_DIGEST_SIZE,
1519         .halg.base      = {
1520                 .cra_name               = "sha384",
1521                 .cra_driver_name        = "omap-sha384",
1522                 .cra_priority           = 100,
1523                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1524                                                 CRYPTO_ALG_ASYNC |
1525                                                 CRYPTO_ALG_NEED_FALLBACK,
1526                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1527                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1528                 .cra_alignmask          = 0,
1529                 .cra_module             = THIS_MODULE,
1530                 .cra_init               = omap_sham_cra_init,
1531                 .cra_exit               = omap_sham_cra_exit,
1532         }
1533 },
1534 {
1535         .init           = omap_sham_init,
1536         .update         = omap_sham_update,
1537         .final          = omap_sham_final,
1538         .finup          = omap_sham_finup,
1539         .digest         = omap_sham_digest,
1540         .halg.digestsize        = SHA512_DIGEST_SIZE,
1541         .halg.base      = {
1542                 .cra_name               = "sha512",
1543                 .cra_driver_name        = "omap-sha512",
1544                 .cra_priority           = 100,
1545                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1546                                                 CRYPTO_ALG_ASYNC |
1547                                                 CRYPTO_ALG_NEED_FALLBACK,
1548                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1549                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1550                 .cra_alignmask          = 0,
1551                 .cra_module             = THIS_MODULE,
1552                 .cra_init               = omap_sham_cra_init,
1553                 .cra_exit               = omap_sham_cra_exit,
1554         }
1555 },
1556 {
1557         .init           = omap_sham_init,
1558         .update         = omap_sham_update,
1559         .final          = omap_sham_final,
1560         .finup          = omap_sham_finup,
1561         .digest         = omap_sham_digest,
1562         .setkey         = omap_sham_setkey,
1563         .halg.digestsize        = SHA384_DIGEST_SIZE,
1564         .halg.base      = {
1565                 .cra_name               = "hmac(sha384)",
1566                 .cra_driver_name        = "omap-hmac-sha384",
1567                 .cra_priority           = 100,
1568                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1569                                                 CRYPTO_ALG_ASYNC |
1570                                                 CRYPTO_ALG_NEED_FALLBACK,
1571                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1572                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1573                                         sizeof(struct omap_sham_hmac_ctx),
1574                 .cra_alignmask          = OMAP_ALIGN_MASK,
1575                 .cra_module             = THIS_MODULE,
1576                 .cra_init               = omap_sham_cra_sha384_init,
1577                 .cra_exit               = omap_sham_cra_exit,
1578         }
1579 },
1580 {
1581         .init           = omap_sham_init,
1582         .update         = omap_sham_update,
1583         .final          = omap_sham_final,
1584         .finup          = omap_sham_finup,
1585         .digest         = omap_sham_digest,
1586         .setkey         = omap_sham_setkey,
1587         .halg.digestsize        = SHA512_DIGEST_SIZE,
1588         .halg.base      = {
1589                 .cra_name               = "hmac(sha512)",
1590                 .cra_driver_name        = "omap-hmac-sha512",
1591                 .cra_priority           = 100,
1592                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1593                                                 CRYPTO_ALG_ASYNC |
1594                                                 CRYPTO_ALG_NEED_FALLBACK,
1595                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1596                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1597                                         sizeof(struct omap_sham_hmac_ctx),
1598                 .cra_alignmask          = OMAP_ALIGN_MASK,
1599                 .cra_module             = THIS_MODULE,
1600                 .cra_init               = omap_sham_cra_sha512_init,
1601                 .cra_exit               = omap_sham_cra_exit,
1602         }
1603 },
1604 };
1605
1606 static void omap_sham_done_task(unsigned long data)
1607 {
1608         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1609         int err = 0;
1610
1611         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1612                 omap_sham_handle_queue(dd, NULL);
1613                 return;
1614         }
1615
1616         if (test_bit(FLAGS_CPU, &dd->flags)) {
1617                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1618                         /* hash or semi-hash ready */
1619                         err = omap_sham_update_cpu(dd);
1620                         if (err != -EINPROGRESS)
1621                                 goto finish;
1622                 }
1623         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1624                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1625                         omap_sham_update_dma_stop(dd);
1626                         if (dd->err) {
1627                                 err = dd->err;
1628                                 goto finish;
1629                         }
1630                 }
1631                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1632                         /* hash or semi-hash ready */
1633                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1634                         err = omap_sham_update_dma_start(dd);
1635                         if (err != -EINPROGRESS)
1636                                 goto finish;
1637                 }
1638         }
1639
1640         return;
1641
1642 finish:
1643         dev_dbg(dd->dev, "update done: err: %d\n", err);
1644         /* finish curent request */
1645         omap_sham_finish_req(dd->req, err);
1646 }
1647
1648 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1649 {
1650         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1651                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1652         } else {
1653                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1654                 tasklet_schedule(&dd->done_task);
1655         }
1656
1657         return IRQ_HANDLED;
1658 }
1659
1660 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1661 {
1662         struct omap_sham_dev *dd = dev_id;
1663
1664         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1665                 /* final -> allow device to go to power-saving mode */
1666                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1667
1668         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1669                                  SHA_REG_CTRL_OUTPUT_READY);
1670         omap_sham_read(dd, SHA_REG_CTRL);
1671
1672         return omap_sham_irq_common(dd);
1673 }
1674
1675 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1676 {
1677         struct omap_sham_dev *dd = dev_id;
1678
1679         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1680
1681         return omap_sham_irq_common(dd);
1682 }
1683
1684 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1685         {
1686                 .algs_list      = algs_sha1_md5,
1687                 .size           = ARRAY_SIZE(algs_sha1_md5),
1688         },
1689 };
1690
1691 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1692         .algs_info      = omap_sham_algs_info_omap2,
1693         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1694         .flags          = BIT(FLAGS_BE32_SHA1),
1695         .digest_size    = SHA1_DIGEST_SIZE,
1696         .copy_hash      = omap_sham_copy_hash_omap2,
1697         .write_ctrl     = omap_sham_write_ctrl_omap2,
1698         .trigger        = omap_sham_trigger_omap2,
1699         .poll_irq       = omap_sham_poll_irq_omap2,
1700         .intr_hdlr      = omap_sham_irq_omap2,
1701         .idigest_ofs    = 0x00,
1702         .din_ofs        = 0x1c,
1703         .digcnt_ofs     = 0x14,
1704         .rev_ofs        = 0x5c,
1705         .mask_ofs       = 0x60,
1706         .sysstatus_ofs  = 0x64,
1707         .major_mask     = 0xf0,
1708         .major_shift    = 4,
1709         .minor_mask     = 0x0f,
1710         .minor_shift    = 0,
1711 };
1712
1713 #ifdef CONFIG_OF
1714 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1715         {
1716                 .algs_list      = algs_sha1_md5,
1717                 .size           = ARRAY_SIZE(algs_sha1_md5),
1718         },
1719         {
1720                 .algs_list      = algs_sha224_sha256,
1721                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1722         },
1723 };
1724
1725 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1726         .algs_info      = omap_sham_algs_info_omap4,
1727         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1728         .flags          = BIT(FLAGS_AUTO_XOR),
1729         .digest_size    = SHA256_DIGEST_SIZE,
1730         .copy_hash      = omap_sham_copy_hash_omap4,
1731         .write_ctrl     = omap_sham_write_ctrl_omap4,
1732         .trigger        = omap_sham_trigger_omap4,
1733         .poll_irq       = omap_sham_poll_irq_omap4,
1734         .intr_hdlr      = omap_sham_irq_omap4,
1735         .idigest_ofs    = 0x020,
1736         .odigest_ofs    = 0x0,
1737         .din_ofs        = 0x080,
1738         .digcnt_ofs     = 0x040,
1739         .rev_ofs        = 0x100,
1740         .mask_ofs       = 0x110,
1741         .sysstatus_ofs  = 0x114,
1742         .mode_ofs       = 0x44,
1743         .length_ofs     = 0x48,
1744         .major_mask     = 0x0700,
1745         .major_shift    = 8,
1746         .minor_mask     = 0x003f,
1747         .minor_shift    = 0,
1748 };
1749
1750 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1751         {
1752                 .algs_list      = algs_sha1_md5,
1753                 .size           = ARRAY_SIZE(algs_sha1_md5),
1754         },
1755         {
1756                 .algs_list      = algs_sha224_sha256,
1757                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1758         },
1759         {
1760                 .algs_list      = algs_sha384_sha512,
1761                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1762         },
1763 };
1764
1765 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1766         .algs_info      = omap_sham_algs_info_omap5,
1767         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1768         .flags          = BIT(FLAGS_AUTO_XOR),
1769         .digest_size    = SHA512_DIGEST_SIZE,
1770         .copy_hash      = omap_sham_copy_hash_omap4,
1771         .write_ctrl     = omap_sham_write_ctrl_omap4,
1772         .trigger        = omap_sham_trigger_omap4,
1773         .poll_irq       = omap_sham_poll_irq_omap4,
1774         .intr_hdlr      = omap_sham_irq_omap4,
1775         .idigest_ofs    = 0x240,
1776         .odigest_ofs    = 0x200,
1777         .din_ofs        = 0x080,
1778         .digcnt_ofs     = 0x280,
1779         .rev_ofs        = 0x100,
1780         .mask_ofs       = 0x110,
1781         .sysstatus_ofs  = 0x114,
1782         .mode_ofs       = 0x284,
1783         .length_ofs     = 0x288,
1784         .major_mask     = 0x0700,
1785         .major_shift    = 8,
1786         .minor_mask     = 0x003f,
1787         .minor_shift    = 0,
1788 };
1789
1790 static const struct of_device_id omap_sham_of_match[] = {
1791         {
1792                 .compatible     = "ti,omap2-sham",
1793                 .data           = &omap_sham_pdata_omap2,
1794         },
1795         {
1796                 .compatible     = "ti,omap4-sham",
1797                 .data           = &omap_sham_pdata_omap4,
1798         },
1799         {
1800                 .compatible     = "ti,omap5-sham",
1801                 .data           = &omap_sham_pdata_omap5,
1802         },
1803         {},
1804 };
1805 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1806
1807 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1808                 struct device *dev, struct resource *res)
1809 {
1810         struct device_node *node = dev->of_node;
1811         const struct of_device_id *match;
1812         int err = 0;
1813
1814         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1815         if (!match) {
1816                 dev_err(dev, "no compatible OF match\n");
1817                 err = -EINVAL;
1818                 goto err;
1819         }
1820
1821         err = of_address_to_resource(node, 0, res);
1822         if (err < 0) {
1823                 dev_err(dev, "can't translate OF node address\n");
1824                 err = -EINVAL;
1825                 goto err;
1826         }
1827
1828         dd->irq = irq_of_parse_and_map(node, 0);
1829         if (!dd->irq) {
1830                 dev_err(dev, "can't translate OF irq value\n");
1831                 err = -EINVAL;
1832                 goto err;
1833         }
1834
1835         dd->dma = -1; /* Dummy value that's unused */
1836         dd->pdata = match->data;
1837
1838 err:
1839         return err;
1840 }
1841 #else
1842 static const struct of_device_id omap_sham_of_match[] = {
1843         {},
1844 };
1845
1846 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1847                 struct device *dev, struct resource *res)
1848 {
1849         return -EINVAL;
1850 }
1851 #endif
1852
1853 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1854                 struct platform_device *pdev, struct resource *res)
1855 {
1856         struct device *dev = &pdev->dev;
1857         struct resource *r;
1858         int err = 0;
1859
1860         /* Get the base address */
1861         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862         if (!r) {
1863                 dev_err(dev, "no MEM resource info\n");
1864                 err = -ENODEV;
1865                 goto err;
1866         }
1867         memcpy(res, r, sizeof(*res));
1868
1869         /* Get the IRQ */
1870         dd->irq = platform_get_irq(pdev, 0);
1871         if (dd->irq < 0) {
1872                 dev_err(dev, "no IRQ resource info\n");
1873                 err = dd->irq;
1874                 goto err;
1875         }
1876
1877         /* Get the DMA */
1878         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1879         if (!r) {
1880                 dev_err(dev, "no DMA resource info\n");
1881                 err = -ENODEV;
1882                 goto err;
1883         }
1884         dd->dma = r->start;
1885
1886         /* Only OMAP2/3 can be non-DT */
1887         dd->pdata = &omap_sham_pdata_omap2;
1888
1889 err:
1890         return err;
1891 }
1892
1893 static int omap_sham_probe(struct platform_device *pdev)
1894 {
1895         struct omap_sham_dev *dd;
1896         struct device *dev = &pdev->dev;
1897         struct resource res;
1898         dma_cap_mask_t mask;
1899         int err, i, j;
1900         u32 rev;
1901
1902         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1903         if (dd == NULL) {
1904                 dev_err(dev, "unable to alloc data struct.\n");
1905                 err = -ENOMEM;
1906                 goto data_err;
1907         }
1908         dd->dev = dev;
1909         platform_set_drvdata(pdev, dd);
1910
1911         INIT_LIST_HEAD(&dd->list);
1912         spin_lock_init(&dd->lock);
1913         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1914         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1915
1916         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1917                                omap_sham_get_res_pdev(dd, pdev, &res);
1918         if (err)
1919                 goto data_err;
1920
1921         dd->io_base = devm_ioremap_resource(dev, &res);
1922         if (IS_ERR(dd->io_base)) {
1923                 err = PTR_ERR(dd->io_base);
1924                 goto data_err;
1925         }
1926         dd->phys_base = res.start;
1927
1928         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1929                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
1930         if (err) {
1931                 dev_err(dev, "unable to request irq %d, err = %d\n",
1932                         dd->irq, err);
1933                 goto data_err;
1934         }
1935
1936         dma_cap_zero(mask);
1937         dma_cap_set(DMA_SLAVE, mask);
1938
1939         dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1940                                                        &dd->dma, dev, "rx");
1941         if (!dd->dma_lch) {
1942                 dd->polling_mode = 1;
1943                 dev_dbg(dev, "using polling mode instead of dma\n");
1944         }
1945
1946         dd->flags |= dd->pdata->flags;
1947
1948         pm_runtime_enable(dev);
1949         pm_runtime_irq_safe(dev);
1950         pm_runtime_get_sync(dev);
1951         rev = omap_sham_read(dd, SHA_REG_REV(dd));
1952         pm_runtime_put_sync(&pdev->dev);
1953
1954         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1955                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1956                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1957
1958         spin_lock(&sham.lock);
1959         list_add_tail(&dd->list, &sham.dev_list);
1960         spin_unlock(&sham.lock);
1961
1962         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1963                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1964                         err = crypto_register_ahash(
1965                                         &dd->pdata->algs_info[i].algs_list[j]);
1966                         if (err)
1967                                 goto err_algs;
1968
1969                         dd->pdata->algs_info[i].registered++;
1970                 }
1971         }
1972
1973         return 0;
1974
1975 err_algs:
1976         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1977                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1978                         crypto_unregister_ahash(
1979                                         &dd->pdata->algs_info[i].algs_list[j]);
1980         pm_runtime_disable(dev);
1981         if (dd->dma_lch)
1982                 dma_release_channel(dd->dma_lch);
1983 data_err:
1984         dev_err(dev, "initialization failed.\n");
1985
1986         return err;
1987 }
1988
1989 static int omap_sham_remove(struct platform_device *pdev)
1990 {
1991         static struct omap_sham_dev *dd;
1992         int i, j;
1993
1994         dd = platform_get_drvdata(pdev);
1995         if (!dd)
1996                 return -ENODEV;
1997         spin_lock(&sham.lock);
1998         list_del(&dd->list);
1999         spin_unlock(&sham.lock);
2000         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2001                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2002                         crypto_unregister_ahash(
2003                                         &dd->pdata->algs_info[i].algs_list[j]);
2004         tasklet_kill(&dd->done_task);
2005         pm_runtime_disable(&pdev->dev);
2006
2007         if (dd->dma_lch)
2008                 dma_release_channel(dd->dma_lch);
2009
2010         return 0;
2011 }
2012
2013 #ifdef CONFIG_PM_SLEEP
2014 static int omap_sham_suspend(struct device *dev)
2015 {
2016         pm_runtime_put_sync(dev);
2017         return 0;
2018 }
2019
2020 static int omap_sham_resume(struct device *dev)
2021 {
2022         pm_runtime_get_sync(dev);
2023         return 0;
2024 }
2025 #endif
2026
2027 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2028
2029 static struct platform_driver omap_sham_driver = {
2030         .probe  = omap_sham_probe,
2031         .remove = omap_sham_remove,
2032         .driver = {
2033                 .name   = "omap-sham",
2034                 .pm     = &omap_sham_pm_ops,
2035                 .of_match_table = omap_sham_of_match,
2036         },
2037 };
2038
2039 module_platform_driver(omap_sham_driver);
2040
2041 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2042 MODULE_LICENSE("GPL v2");
2043 MODULE_AUTHOR("Dmitry Kasatkin");
2044 MODULE_ALIAS("platform:omap-sham");