kernel/drivers/clocksource/tcb_clksrc.c

   1 #include <linux/init.h>
   2 #include <linux/clocksource.h>
   3 #include <linux/clockchips.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6
   7 #include <linux/clk.h>
   8 #include <linux/err.h>
   9 #include <linux/ioport.h>
  10 #include <linux/io.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/atmel_tc.h>
  13
  14
  15 /*
  16  * We're configured to use a specific TC block, one that's not hooked
  17  * up to external hardware, to provide a time solution:
  18  *
  19  *   - Two channels combine to create a free-running 32 bit counter
  20  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  21  *     resolution better than 200 nsec).
  22  *   - Some chips support 32 bit counter. A single channel is used for
  23  *     this 32 bit free-running counter. the second channel is not used.
  24  *
  25  *   - The third channel may be used to provide a 16-bit clockevent
  26  *     source, used in either periodic or oneshot mode.
  27  *
  28  * A boot clocksource and clockevent source are also currently needed,
  29  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  30  * this code can be used when init_timers() is called, well before most
  31  * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  32  * have only the timers in one TC block... they currently don't support
  33  * the tclib code, because of that initialization issue.)
  34  *
  35  * REVISIT behavior during system suspend states... we should disable
  36  * all clocks and save the power.  Easily done for clockevent devices,
  37  * but clocksources won't necessarily get the needed notifications.
  38  * For deeper system sleep states, this will be mandatory...
  39  */
  40
  41 static void __iomem *tcaddr;
  42
  43 static cycle_t tc_get_cycles(struct clocksource *cs)
  44 {
  45         unsigned long   flags;
  46         u32             lower, upper;
  47
  48         raw_local_irq_save(flags);
  49         do {
  50                 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
  51                 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  52         } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
  53
  54         raw_local_irq_restore(flags);
  55         return (upper << 16) | lower;
  56 }
  57
  58 static cycle_t tc_get_cycles32(struct clocksource *cs)
  59 {
  60         return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  61 }
  62
  63 static struct clocksource clksrc = {
  64         .name           = "tcb_clksrc",
  65         .rating         = 200,
  66         .read           = tc_get_cycles,
  67         .mask           = CLOCKSOURCE_MASK(32),
  68         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  69 };
  70
  71 #ifdef CONFIG_GENERIC_CLOCKEVENTS
  72
  73 struct tc_clkevt_device {
  74         struct clock_event_device       clkevt;
  75         struct clk                      *clk;
  76         bool                            clk_enabled;
  77         u32                             freq;
  78         void __iomem                    *regs;
  79 };
  80
  81 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
  82 {
  83         return container_of(clkevt, struct tc_clkevt_device, clkevt);
  84 }
  85
  86 static u32 timer_clock;
  87
  88 static void tc_clk_disable(struct clock_event_device *d)
  89 {
  90         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
  91
  92         clk_disable(tcd->clk);
  93         tcd->clk_enabled = false;
  94 }
  95
  96 static void tc_clk_enable(struct clock_event_device *d)
  97 {
  98         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
  99
 100         if (tcd->clk_enabled)
 101                 return;
 102         clk_enable(tcd->clk);
 103         tcd->clk_enabled = true;
 104 }
 105
 106 static int tc_shutdown(struct clock_event_device *d)
 107 {
 108         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 109         void __iomem            *regs = tcd->regs;
 110
 111         __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 112         __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 113         return 0;
 114 }
 115
 116 static int tc_shutdown_clk_off(struct clock_event_device *d)
 117 {
 118         tc_shutdown(d);
 119         if (!clockevent_state_detached(d))
 120                 tc_clk_disable(d);
 121
 122         return 0;
 123 }
 124
 125 static int tc_set_oneshot(struct clock_event_device *d)
 126 {
 127         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 128         void __iomem            *regs = tcd->regs;
 129
 130         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 131                 tc_shutdown(d);
 132
 133         tc_clk_enable(d);
 134
 135         /* count up to RC, then irq and stop */
 136         __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
 137                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
 138         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 139
 140         /* set_next_event() configures and starts the timer */
 141         return 0;
 142 }
 143
 144 static int tc_set_periodic(struct clock_event_device *d)
 145 {
 146         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 147         void __iomem            *regs = tcd->regs;
 148
 149         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 150                 tc_shutdown(d);
 151
 152         /* By not making the gentime core emulate periodic mode on top
 153          * of oneshot, we get lower overhead and improved accuracy.
 154          */
 155         tc_clk_enable(d);
 156
 157         /* count up to RC, then irq and restart */
 158         __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 159                      regs + ATMEL_TC_REG(2, CMR));
 160         __raw_writel((tcd->freq + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 161
 162         /* Enable clock and interrupts on RC compare */
 163         __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 164
 165         /* go go gadget! */
 166         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
 167                      ATMEL_TC_REG(2, CCR));
 168         return 0;
 169 }
 170
 171 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 172 {
 173         __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 174
 175         /* go go gadget! */
 176         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 177                         tcaddr + ATMEL_TC_REG(2, CCR));
 178         return 0;
 179 }
 180
 181 static struct tc_clkevt_device clkevt = {
 182         .clkevt = {
 183                 .name                   = "tc_clkevt",
 184                 .features               = CLOCK_EVT_FEAT_PERIODIC |
 185                                           CLOCK_EVT_FEAT_ONESHOT,
 186                 /* Should be lower than at91rm9200's system timer */
 187 #ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
 188                 .rating                 = 125,
 189 #else
 190                 .rating                 = 200,
 191 #endif
 192                 .set_next_event         = tc_next_event,
 193                 .set_state_shutdown     = tc_shutdown_clk_off,
 194                 .set_state_periodic     = tc_set_periodic,
 195                 .set_state_oneshot      = tc_set_oneshot,
 196         },
 197 };
 198
 199 static irqreturn_t ch2_irq(int irq, void *handle)
 200 {
 201         struct tc_clkevt_device *dev = handle;
 202         unsigned int            sr;
 203
 204         sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
 205         if (sr & ATMEL_TC_CPCS) {
 206                 dev->clkevt.event_handler(&dev->clkevt);
 207                 return IRQ_HANDLED;
 208         }
 209
 210         return IRQ_NONE;
 211 }
 212
 213 static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
 214 {
 215         unsigned divisor = atmel_tc_divisors[divisor_idx];
 216         int ret;
 217         struct clk *t2_clk = tc->clk[2];
 218         int irq = tc->irq[2];
 219
 220         ret = clk_prepare_enable(tc->slow_clk);
 221         if (ret)
 222                 return ret;
 223
 224         /* try to enable t2 clk to avoid future errors in mode change */
 225         ret = clk_prepare_enable(t2_clk);
 226         if (ret) {
 227                 clk_disable_unprepare(tc->slow_clk);
 228                 return ret;
 229         }
 230
 231         clk_disable(t2_clk);
 232
 233         clkevt.regs = tc->regs;
 234         clkevt.clk = t2_clk;
 235
 236         timer_clock = divisor_idx;
 237         if (!divisor)
 238                 clkevt.freq = 32768;
 239         else
 240                 clkevt.freq = clk_get_rate(t2_clk) / divisor;
 241
 242         clkevt.clkevt.cpumask = cpumask_of(0);
 243
 244         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 245         if (ret) {
 246                 clk_unprepare(t2_clk);
 247                 clk_disable_unprepare(tc->slow_clk);
 248                 return ret;
 249         }
 250
 251         clockevents_config_and_register(&clkevt.clkevt, clkevt.freq, 1, 0xffff);
 252
 253         return ret;
 254 }
 255
 256 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 257
 258 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 259 {
 260         /* NOTHING */
 261         return 0;
 262 }
 263
 264 #endif
 265
 266 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 267 {
 268         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 269         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 270                         | ATMEL_TC_WAVE
 271                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 272                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 273                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 274                         tcaddr + ATMEL_TC_REG(0, CMR));
 275         __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 276         __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 277         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 278         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 279
 280         /* channel 1:  waveform mode, input TIOA0 */
 281         __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
 282                         | ATMEL_TC_WAVE
 283                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 284                         tcaddr + ATMEL_TC_REG(1, CMR));
 285         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
 286         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 287
 288         /* chain channel 0 to channel 1*/
 289         __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 290         /* then reset all the timers */
 291         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 292 }
 293
 294 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 295 {
 296         /* channel 0:  waveform mode, input mclk/8 */
 297         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 298                         | ATMEL_TC_WAVE
 299                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 300                         tcaddr + ATMEL_TC_REG(0, CMR));
 301         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 302         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 303
 304         /* then reset all the timers */
 305         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 306 }
 307
 308 static int __init tcb_clksrc_init(void)
 309 {
 310         static char bootinfo[] __initdata
 311                 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 312
 313         struct platform_device *pdev;
 314         struct atmel_tc *tc;
 315         struct clk *t0_clk;
 316         u32 rate, divided_rate = 0;
 317         int best_divisor_idx = -1;
 318         int clk32k_divisor_idx = -1;
 319         int i;
 320         int ret;
 321
 322         tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
 323         if (!tc) {
 324                 pr_debug("can't alloc TC for clocksource\n");
 325                 return -ENODEV;
 326         }
 327         tcaddr = tc->regs;
 328         pdev = tc->pdev;
 329
 330         t0_clk = tc->clk[0];
 331         ret = clk_prepare_enable(t0_clk);
 332         if (ret) {
 333                 pr_debug("can't enable T0 clk\n");
 334                 goto err_free_tc;
 335         }
 336
 337         /* How fast will we be counting?  Pick something over 5 MHz.  */
 338         rate = (u32) clk_get_rate(t0_clk);
 339         for (i = 0; i < 5; i++) {
 340                 unsigned divisor = atmel_tc_divisors[i];
 341                 unsigned tmp;
 342
 343                 /* remember 32 KiHz clock for later */
 344                 if (!divisor) {
 345                         clk32k_divisor_idx = i;
 346                         continue;
 347                 }
 348
 349                 tmp = rate / divisor;
 350                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 351                 if (best_divisor_idx > 0) {
 352                         if (tmp < 5 * 1000 * 1000)
 353                                 continue;
 354                 }
 355                 divided_rate = tmp;
 356                 best_divisor_idx = i;
 357         }
 358
 359
 360         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 361                         divided_rate / 1000000,
 362                         ((divided_rate + 500000) % 1000000) / 1000);
 363
 364         if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 365                 /* use apropriate function to read 32 bit counter */
 366                 clksrc.read = tc_get_cycles32;
 367                 /* setup ony channel 0 */
 368                 tcb_setup_single_chan(tc, best_divisor_idx);
 369         } else {
 370                 /* tclib will give us three clocks no matter what the
 371                  * underlying platform supports.
 372                  */
 373                 ret = clk_prepare_enable(tc->clk[1]);
 374                 if (ret) {
 375                         pr_debug("can't enable T1 clk\n");
 376                         goto err_disable_t0;
 377                 }
 378                 /* setup both channel 0 & 1 */
 379                 tcb_setup_dual_chan(tc, best_divisor_idx);
 380         }
 381
 382         /* and away we go! */
 383         ret = clocksource_register_hz(&clksrc, divided_rate);
 384         if (ret)
 385                 goto err_disable_t1;
 386
 387         /* channel 2:  periodic and oneshot timer support */
 388 #ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
 389         ret = setup_clkevents(tc, clk32k_divisor_idx);
 390 #else
 391         ret = setup_clkevents(tc, best_divisor_idx);
 392 #endif
 393         if (ret)
 394                 goto err_unregister_clksrc;
 395
 396         return 0;
 397
 398 err_unregister_clksrc:
 399         clocksource_unregister(&clksrc);
 400
 401 err_disable_t1:
 402         if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
 403                 clk_disable_unprepare(tc->clk[1]);
 404
 405 err_disable_t0:
 406         clk_disable_unprepare(t0_clk);
 407
 408 err_free_tc:
 409         atmel_tc_free(tc);
 410         return ret;
 411 }
 412 arch_initcall(tcb_clksrc_init);