kernel/drivers/clocksource/tcb_clksrc.c

   1 #include <linux/init.h>
   2 #include <linux/clocksource.h>
   3 #include <linux/clockchips.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6
   7 #include <linux/clk.h>
   8 #include <linux/err.h>
   9 #include <linux/ioport.h>
  10 #include <linux/io.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/atmel_tc.h>
  13
  14
  15 /*
  16  * We're configured to use a specific TC block, one that's not hooked
  17  * up to external hardware, to provide a time solution:
  18  *
  19  *   - Two channels combine to create a free-running 32 bit counter
  20  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  21  *     resolution better than 200 nsec).
  22  *   - Some chips support 32 bit counter. A single channel is used for
  23  *     this 32 bit free-running counter. the second channel is not used.
  24  *
  25  *   - The third channel may be used to provide a 16-bit clockevent
  26  *     source, used in either periodic or oneshot mode.
  27  *
  28  * A boot clocksource and clockevent source are also currently needed,
  29  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  30  * this code can be used when init_timers() is called, well before most
  31  * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  32  * have only the timers in one TC block... they currently don't support
  33  * the tclib code, because of that initialization issue.)
  34  *
  35  * REVISIT behavior during system suspend states... we should disable
  36  * all clocks and save the power.  Easily done for clockevent devices,
  37  * but clocksources won't necessarily get the needed notifications.
  38  * For deeper system sleep states, this will be mandatory...
  39  */
  40
  41 static void __iomem *tcaddr;
  42
  43 static cycle_t tc_get_cycles(struct clocksource *cs)
  44 {
  45         unsigned long   flags;
  46         u32             lower, upper;
  47
  48         raw_local_irq_save(flags);
  49         do {
  50                 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
  51                 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  52         } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
  53
  54         raw_local_irq_restore(flags);
  55         return (upper << 16) | lower;
  56 }
  57
  58 static cycle_t tc_get_cycles32(struct clocksource *cs)
  59 {
  60         return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  61 }
  62
  63 static struct clocksource clksrc = {
  64         .name           = "tcb_clksrc",
  65         .rating         = 200,
  66         .read           = tc_get_cycles,
  67         .mask           = CLOCKSOURCE_MASK(32),
  68         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  69 };
  70
  71 #ifdef CONFIG_GENERIC_CLOCKEVENTS
  72
  73 struct tc_clkevt_device {
  74         struct clock_event_device       clkevt;
  75         struct clk                      *clk;
  76         u32                             freq;
  77         void __iomem                    *regs;
  78 };
  79
  80 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
  81 {
  82         return container_of(clkevt, struct tc_clkevt_device, clkevt);
  83 }
  84
  85 static u32 timer_clock;
  86
  87 static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  88 {
  89         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
  90         void __iomem            *regs = tcd->regs;
  91
  92         if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
  93                         || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
  94                 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
  95                 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
  96                 clk_disable(tcd->clk);
  97         }
  98
  99         switch (m) {
 100
 101         /* By not making the gentime core emulate periodic mode on top
 102          * of oneshot, we get lower overhead and improved accuracy.
 103          */
 104         case CLOCK_EVT_MODE_PERIODIC:
 105                 clk_enable(tcd->clk);
 106
 107                 /* count up to RC, then irq and restart */
 108                 __raw_writel(timer_clock
 109                                 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 110                                 regs + ATMEL_TC_REG(2, CMR));
 111                 __raw_writel((tcd->freq + HZ / 2) / HZ,
 112                              tcaddr + ATMEL_TC_REG(2, RC));
 113
 114                 /* Enable clock and interrupts on RC compare */
 115                 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 116
 117                 /* go go gadget! */
 118                 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 119                                 regs + ATMEL_TC_REG(2, CCR));
 120                 break;
 121
 122         case CLOCK_EVT_MODE_ONESHOT:
 123                 clk_enable(tcd->clk);
 124
 125                 /* count up to RC, then irq and stop */
 126                 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
 127                                 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 128                                 regs + ATMEL_TC_REG(2, CMR));
 129                 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 130
 131                 /* set_next_event() configures and starts the timer */
 132                 break;
 133
 134         default:
 135                 break;
 136         }
 137 }
 138
 139 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 140 {
 141         __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 142
 143         /* go go gadget! */
 144         __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 145                         tcaddr + ATMEL_TC_REG(2, CCR));
 146         return 0;
 147 }
 148
 149 static struct tc_clkevt_device clkevt = {
 150         .clkevt = {
 151                 .name           = "tc_clkevt",
 152                 .features       = CLOCK_EVT_FEAT_PERIODIC
 153                                         | CLOCK_EVT_FEAT_ONESHOT,
 154 #ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
 155                 /* Should be lower than at91rm9200's system timer */
 156                 .rating         = 125,
 157 #else
 158                 .rating         = 200,
 159 #endif
 160                 .set_next_event = tc_next_event,
 161                 .set_mode       = tc_mode,
 162         },
 163 };
 164
 165 static irqreturn_t ch2_irq(int irq, void *handle)
 166 {
 167         struct tc_clkevt_device *dev = handle;
 168         unsigned int            sr;
 169
 170         sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
 171         if (sr & ATMEL_TC_CPCS) {
 172                 dev->clkevt.event_handler(&dev->clkevt);
 173                 return IRQ_HANDLED;
 174         }
 175
 176         return IRQ_NONE;
 177 }
 178
 179 static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
 180 {
 181         unsigned divisor = atmel_tc_divisors[divisor_idx];
 182         int ret;
 183         struct clk *t2_clk = tc->clk[2];
 184         int irq = tc->irq[2];
 185
 186         /* try to enable t2 clk to avoid future errors in mode change */
 187         ret = clk_prepare_enable(t2_clk);
 188         if (ret)
 189                 return ret;
 190         clk_disable(t2_clk);
 191
 192         clkevt.regs = tc->regs;
 193         clkevt.clk = t2_clk;
 194
 195         timer_clock = divisor_idx;
 196         if (!divisor)
 197                 clkevt.freq = 32768;
 198         else
 199                 clkevt.freq = clk_get_rate(t2_clk) / divisor;
 200
 201         clkevt.clkevt.cpumask = cpumask_of(0);
 202
 203         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 204         if (ret) {
 205                 clk_disable_unprepare(t2_clk);
 206                 return ret;
 207         }
 208
 209         clockevents_config_and_register(&clkevt.clkevt, clkevt.freq, 1, 0xffff);
 210
 211         return ret;
 212 }
 213
 214 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 215
 216 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 217 {
 218         /* NOTHING */
 219         return 0;
 220 }
 221
 222 #endif
 223
 224 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 225 {
 226         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 227         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 228                         | ATMEL_TC_WAVE
 229                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 230                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 231                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 232                         tcaddr + ATMEL_TC_REG(0, CMR));
 233         __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 234         __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 235         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 236         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 237
 238         /* channel 1:  waveform mode, input TIOA0 */
 239         __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
 240                         | ATMEL_TC_WAVE
 241                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 242                         tcaddr + ATMEL_TC_REG(1, CMR));
 243         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
 244         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 245
 246         /* chain channel 0 to channel 1*/
 247         __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 248         /* then reset all the timers */
 249         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 250 }
 251
 252 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 253 {
 254         /* channel 0:  waveform mode, input mclk/8 */
 255         __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 256                         | ATMEL_TC_WAVE
 257                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 258                         tcaddr + ATMEL_TC_REG(0, CMR));
 259         __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 260         __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 261
 262         /* then reset all the timers */
 263         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 264 }
 265
 266 static int __init tcb_clksrc_init(void)
 267 {
 268         static char bootinfo[] __initdata
 269                 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 270
 271         struct platform_device *pdev;
 272         struct atmel_tc *tc;
 273         struct clk *t0_clk;
 274         u32 rate, divided_rate = 0;
 275         int best_divisor_idx = -1;
 276         int clk32k_divisor_idx = -1;
 277         int i;
 278         int ret;
 279
 280         tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
 281         if (!tc) {
 282                 pr_debug("can't alloc TC for clocksource\n");
 283                 return -ENODEV;
 284         }
 285         tcaddr = tc->regs;
 286         pdev = tc->pdev;
 287
 288         t0_clk = tc->clk[0];
 289         ret = clk_prepare_enable(t0_clk);
 290         if (ret) {
 291                 pr_debug("can't enable T0 clk\n");
 292                 goto err_free_tc;
 293         }
 294
 295         /* How fast will we be counting?  Pick something over 5 MHz.  */
 296         rate = (u32) clk_get_rate(t0_clk);
 297         for (i = 0; i < 5; i++) {
 298                 unsigned divisor = atmel_tc_divisors[i];
 299                 unsigned tmp;
 300
 301                 /* remember 32 KiHz clock for later */
 302                 if (!divisor) {
 303                         clk32k_divisor_idx = i;
 304                         continue;
 305                 }
 306
 307                 tmp = rate / divisor;
 308                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 309                 if (best_divisor_idx > 0) {
 310                         if (tmp < 5 * 1000 * 1000)
 311                                 continue;
 312                 }
 313                 divided_rate = tmp;
 314                 best_divisor_idx = i;
 315         }
 316
 317
 318         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 319                         divided_rate / 1000000,
 320                         ((divided_rate + 500000) % 1000000) / 1000);
 321
 322         if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 323                 /* use apropriate function to read 32 bit counter */
 324                 clksrc.read = tc_get_cycles32;
 325                 /* setup ony channel 0 */
 326                 tcb_setup_single_chan(tc, best_divisor_idx);
 327         } else {
 328                 /* tclib will give us three clocks no matter what the
 329                  * underlying platform supports.
 330                  */
 331                 ret = clk_prepare_enable(tc->clk[1]);
 332                 if (ret) {
 333                         pr_debug("can't enable T1 clk\n");
 334                         goto err_disable_t0;
 335                 }
 336                 /* setup both channel 0 & 1 */
 337                 tcb_setup_dual_chan(tc, best_divisor_idx);
 338         }
 339
 340         /* and away we go! */
 341         ret = clocksource_register_hz(&clksrc, divided_rate);
 342         if (ret)
 343                 goto err_disable_t1;
 344
 345         /* channel 2:  periodic and oneshot timer support */
 346 #ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
 347         ret = setup_clkevents(tc, clk32k_divisor_idx);
 348 #else
 349         ret = setup_clkevents(tc, best_divisor_idx);
 350 #endif
 351         if (ret)
 352                 goto err_unregister_clksrc;
 353
 354         return 0;
 355
 356 err_unregister_clksrc:
 357         clocksource_unregister(&clksrc);
 358
 359 err_disable_t1:
 360         if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
 361                 clk_disable_unprepare(tc->clk[1]);
 362
 363 err_disable_t0:
 364         clk_disable_unprepare(t0_clk);
 365
 366 err_free_tc:
 367         atmel_tc_free(tc);
 368         return ret;
 369 }
 370 arch_initcall(tcb_clksrc_init);