kernel/drivers/clk/ux500/u8540_clk.c

   1 /*
   2  * Clock definitions for u8540 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/mfd/dbx500-prcmu.h>
  14 #include <linux/platform_data/clk-ux500.h>
  15 #include "clk.h"
  16
  17 void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
  18                     u32 clkrst5_base, u32 clkrst6_base)
  19 {
  20         struct clk *clk;
  21
  22         /* Clock sources. */
  23         /* Fixed ClockGen */
  24         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  25                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  26         clk_register_clkdev(clk, "soc0_pll", NULL);
  27
  28         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  29                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  30         clk_register_clkdev(clk, "soc1_pll", NULL);
  31
  32         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  33                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  34         clk_register_clkdev(clk, "ddr_pll", NULL);
  35
  36         clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
  37                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
  38                                 32768);
  39         clk_register_clkdev(clk, "clk32k", NULL);
  40         clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
  41
  42         clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
  43                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
  44                                 38400000);
  45
  46         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
  47         clk_register_clkdev(clk, NULL, "UART");
  48
  49         /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
  50         clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
  51                         PRCMU_MSP02CLK, 0);
  52         clk_register_clkdev(clk, NULL, "MSP02");
  53
  54         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
  55         clk_register_clkdev(clk, NULL, "MSP1");
  56
  57         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
  58         clk_register_clkdev(clk, NULL, "I2C");
  59
  60         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
  61         clk_register_clkdev(clk, NULL, "slim");
  62
  63         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
  64         clk_register_clkdev(clk, NULL, "PERIPH1");
  65
  66         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
  67         clk_register_clkdev(clk, NULL, "PERIPH2");
  68
  69         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
  70         clk_register_clkdev(clk, NULL, "PERIPH3");
  71
  72         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
  73         clk_register_clkdev(clk, NULL, "PERIPH5");
  74
  75         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
  76         clk_register_clkdev(clk, NULL, "PERIPH6");
  77
  78         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
  79         clk_register_clkdev(clk, NULL, "PERIPH7");
  80
  81         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
  82                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
  83         clk_register_clkdev(clk, NULL, "lcd");
  84         clk_register_clkdev(clk, "lcd", "mcde");
  85
  86         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK,
  87                                 CLK_IS_ROOT);
  88         clk_register_clkdev(clk, NULL, "bml");
  89
  90         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
  91                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
  92
  93         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
  94                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
  95
  96         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
  97                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
  98         clk_register_clkdev(clk, NULL, "hdmi");
  99         clk_register_clkdev(clk, "hdmi", "mcde");
 100
 101         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
 102         clk_register_clkdev(clk, NULL, "apeat");
 103
 104         clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
 105                                 CLK_IS_ROOT);
 106         clk_register_clkdev(clk, NULL, "apetrace");
 107
 108         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 109         clk_register_clkdev(clk, NULL, "mcde");
 110         clk_register_clkdev(clk, "mcde", "mcde");
 111         clk_register_clkdev(clk, NULL, "dsilink.0");
 112         clk_register_clkdev(clk, NULL, "dsilink.1");
 113         clk_register_clkdev(clk, NULL, "dsilink.2");
 114
 115         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 116                                 CLK_IS_ROOT);
 117         clk_register_clkdev(clk, NULL, "ipi2");
 118
 119         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 120                                 CLK_IS_ROOT);
 121         clk_register_clkdev(clk, NULL, "dsialt");
 122
 123         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 124         clk_register_clkdev(clk, NULL, "dma40.0");
 125
 126         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 127         clk_register_clkdev(clk, NULL, "b2r2");
 128         clk_register_clkdev(clk, NULL, "b2r2_core");
 129         clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
 130         clk_register_clkdev(clk, NULL, "b2r2_1_core");
 131
 132         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 133                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 134         clk_register_clkdev(clk, NULL, "tv");
 135         clk_register_clkdev(clk, "tv", "mcde");
 136
 137         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 138         clk_register_clkdev(clk, NULL, "SSP");
 139
 140         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 141         clk_register_clkdev(clk, NULL, "rngclk");
 142
 143         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 144         clk_register_clkdev(clk, NULL, "uicc");
 145
 146         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 147         clk_register_clkdev(clk, NULL, "mtu0");
 148         clk_register_clkdev(clk, NULL, "mtu1");
 149
 150         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
 151                                         PRCMU_SDMMCCLK, 100000000,
 152                                         CLK_IS_ROOT|CLK_SET_RATE_GATE);
 153         clk_register_clkdev(clk, NULL, "sdmmc");
 154
 155         clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
 156                                         PRCMU_SDMMCHCLK, 400000000,
 157                                         CLK_IS_ROOT|CLK_SET_RATE_GATE);
 158         clk_register_clkdev(clk, NULL, "sdmmchclk");
 159
 160         clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT);
 161         clk_register_clkdev(clk, NULL, "hva");
 162
 163         clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT);
 164         clk_register_clkdev(clk, NULL, "g1");
 165
 166         clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
 167                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 168         clk_register_clkdev(clk, "dsilcd", "mcde");
 169
 170         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 171                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 172         clk_register_clkdev(clk, "dsihs2", "mcde");
 173         clk_register_clkdev(clk, "hs_clk", "dsilink.2");
 174
 175         clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk",
 176                                 PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);
 177         clk_register_clkdev(clk, "dsilcd_pll", "mcde");
 178
 179         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 180                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 181         clk_register_clkdev(clk, "dsihs0", "mcde");
 182
 183         clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll",
 184                                 PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);
 185         clk_register_clkdev(clk, "dsihs0", "mcde");
 186         clk_register_clkdev(clk, "hs_clk", "dsilink.0");
 187
 188         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 189                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 190         clk_register_clkdev(clk, "dsihs1", "mcde");
 191
 192         clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll",
 193                                 PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);
 194         clk_register_clkdev(clk, "dsihs1", "mcde");
 195         clk_register_clkdev(clk, "hs_clk", "dsilink.1");
 196
 197         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 198                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 199         clk_register_clkdev(clk, "lp_clk", "dsilink.0");
 200         clk_register_clkdev(clk, "dsilp0", "mcde");
 201
 202         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 203                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 204         clk_register_clkdev(clk, "lp_clk", "dsilink.1");
 205         clk_register_clkdev(clk, "dsilp1", "mcde");
 206
 207         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 208                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 209         clk_register_clkdev(clk, "lp_clk", "dsilink.2");
 210         clk_register_clkdev(clk, "dsilp2", "mcde");
 211
 212         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 213                                 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 214         clk_register_clkdev(clk, "armss", NULL);
 215
 216         clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 217                                 CLK_IGNORE_UNUSED, 1, 2);
 218         clk_register_clkdev(clk, NULL, "smp_twd");
 219
 220         /* PRCC P-clocks */
 221         /* Peripheral 1 : PRCC P-clocks */
 222         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
 223                                 BIT(0), 0);
 224         clk_register_clkdev(clk, "apb_pclk", "uart0");
 225
 226         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
 227                                 BIT(1), 0);
 228         clk_register_clkdev(clk, "apb_pclk", "uart1");
 229
 230         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
 231                                 BIT(2), 0);
 232         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
 233
 234         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
 235                                 BIT(3), 0);
 236         clk_register_clkdev(clk, "apb_pclk", "msp0");
 237         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0");
 238
 239         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
 240                                 BIT(4), 0);
 241         clk_register_clkdev(clk, "apb_pclk", "msp1");
 242         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1");
 243
 244         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
 245                                 BIT(5), 0);
 246         clk_register_clkdev(clk, "apb_pclk", "sdi0");
 247
 248         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
 249                                 BIT(6), 0);
 250         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
 251
 252         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
 253                                 BIT(7), 0);
 254         clk_register_clkdev(clk, NULL, "spi3");
 255
 256         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
 257                                 BIT(8), 0);
 258         clk_register_clkdev(clk, "apb_pclk", "slimbus0");
 259
 260         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
 261                                 BIT(9), 0);
 262         clk_register_clkdev(clk, NULL, "gpio.0");
 263         clk_register_clkdev(clk, NULL, "gpio.1");
 264         clk_register_clkdev(clk, NULL, "gpioblock0");
 265         clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0");
 266
 267         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
 268                                 BIT(10), 0);
 269         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
 270
 271         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
 272                                 BIT(11), 0);
 273         clk_register_clkdev(clk, "apb_pclk", "msp3");
 274         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3");
 275
 276         /* Peripheral 2 : PRCC P-clocks */
 277         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
 278                                 BIT(0), 0);
 279         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
 280
 281         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
 282                                 BIT(1), 0);
 283         clk_register_clkdev(clk, NULL, "spi2");
 284
 285         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
 286                                 BIT(2), 0);
 287         clk_register_clkdev(clk, NULL, "spi1");
 288
 289         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
 290                                 BIT(3), 0);
 291         clk_register_clkdev(clk, NULL, "pwl");
 292
 293         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
 294                                 BIT(4), 0);
 295         clk_register_clkdev(clk, "apb_pclk", "sdi4");
 296
 297         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
 298                                 BIT(5), 0);
 299         clk_register_clkdev(clk, "apb_pclk", "msp2");
 300         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2");
 301
 302         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
 303                                 BIT(6), 0);
 304         clk_register_clkdev(clk, "apb_pclk", "sdi1");
 305
 306         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
 307                                 BIT(7), 0);
 308         clk_register_clkdev(clk, "apb_pclk", "sdi3");
 309
 310         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
 311                                 BIT(8), 0);
 312         clk_register_clkdev(clk, NULL, "spi0");
 313
 314         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
 315                                 BIT(9), 0);
 316         clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
 317
 318         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
 319                                 BIT(10), 0);
 320         clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
 321
 322         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
 323                                 BIT(11), 0);
 324         clk_register_clkdev(clk, NULL, "gpio.6");
 325         clk_register_clkdev(clk, NULL, "gpio.7");
 326         clk_register_clkdev(clk, NULL, "gpioblock1");
 327
 328         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
 329                                 BIT(12), 0);
 330         clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0");
 331
 332         /* Peripheral 3 : PRCC P-clocks */
 333         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
 334                                 BIT(0), 0);
 335         clk_register_clkdev(clk, NULL, "fsmc");
 336
 337         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
 338                                 BIT(1), 0);
 339         clk_register_clkdev(clk, "apb_pclk", "ssp0");
 340
 341         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
 342                                 BIT(2), 0);
 343         clk_register_clkdev(clk, "apb_pclk", "ssp1");
 344
 345         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
 346                                 BIT(3), 0);
 347         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
 348
 349         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
 350                                 BIT(4), 0);
 351         clk_register_clkdev(clk, "apb_pclk", "sdi2");
 352
 353         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
 354                                 BIT(5), 0);
 355         clk_register_clkdev(clk, "apb_pclk", "ske");
 356         clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
 357
 358         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
 359                                 BIT(6), 0);
 360         clk_register_clkdev(clk, "apb_pclk", "uart2");
 361
 362         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
 363                                 BIT(7), 0);
 364         clk_register_clkdev(clk, "apb_pclk", "sdi5");
 365
 366         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
 367                                 BIT(8), 0);
 368         clk_register_clkdev(clk, NULL, "gpio.2");
 369         clk_register_clkdev(clk, NULL, "gpio.3");
 370         clk_register_clkdev(clk, NULL, "gpio.4");
 371         clk_register_clkdev(clk, NULL, "gpio.5");
 372         clk_register_clkdev(clk, NULL, "gpioblock2");
 373
 374         clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", clkrst3_base,
 375                                 BIT(9), 0);
 376         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5");
 377
 378         clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", clkrst3_base,
 379                                 BIT(10), 0);
 380         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6");
 381
 382         clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", clkrst3_base,
 383                                 BIT(11), 0);
 384         clk_register_clkdev(clk, "apb_pclk", "uart3");
 385
 386         clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", clkrst3_base,
 387                                 BIT(12), 0);
 388         clk_register_clkdev(clk, "apb_pclk", "uart4");
 389
 390         /* Peripheral 5 : PRCC P-clocks */
 391         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
 392                                 BIT(0), 0);
 393         clk_register_clkdev(clk, "usb", "musb-ux500.0");
 394         clk_register_clkdev(clk, "usbclk", "ab-iddet.0");
 395
 396         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
 397                                 BIT(1), 0);
 398         clk_register_clkdev(clk, NULL, "gpio.8");
 399         clk_register_clkdev(clk, NULL, "gpioblock3");
 400
 401         /* Peripheral 6 : PRCC P-clocks */
 402         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
 403                                 BIT(0), 0);
 404         clk_register_clkdev(clk, "apb_pclk", "rng");
 405
 406         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
 407                                 BIT(1), 0);
 408         clk_register_clkdev(clk, NULL, "cryp0");
 409         clk_register_clkdev(clk, NULL, "cryp1");
 410
 411         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
 412                                 BIT(2), 0);
 413         clk_register_clkdev(clk, NULL, "hash0");
 414
 415         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
 416                                 BIT(3), 0);
 417         clk_register_clkdev(clk, NULL, "pka");
 418
 419         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
 420                                 BIT(4), 0);
 421         clk_register_clkdev(clk, NULL, "db8540-hash1");
 422
 423         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
 424                                 BIT(5), 0);
 425         clk_register_clkdev(clk, NULL, "cfgreg");
 426
 427         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
 428                                 BIT(6), 0);
 429         clk_register_clkdev(clk, "apb_pclk", "mtu0");
 430
 431         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
 432                                 BIT(7), 0);
 433         clk_register_clkdev(clk, "apb_pclk", "mtu1");
 434
 435         /*
 436          * PRCC K-clocks  ==> see table PRCC_PCKEN/PRCC_KCKEN
 437          * This differs from the internal implementation:
 438          * We don't use the PERPIH[n| clock as parent, since those _should_
 439          * only be used as parents for the P-clocks.
 440          * TODO: "parentjoin" with corresponding P-clocks for all K-clocks.
 441          */
 442
 443         /* Peripheral 1 : PRCC K-clocks */
 444         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 445                         clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
 446         clk_register_clkdev(clk, NULL, "uart0");
 447
 448         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 449                         clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
 450         clk_register_clkdev(clk, NULL, "uart1");
 451
 452         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 453                         clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
 454         clk_register_clkdev(clk, NULL, "nmk-i2c.1");
 455
 456         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 457                         clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
 458         clk_register_clkdev(clk, NULL, "msp0");
 459         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0");
 460
 461         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 462                         clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
 463         clk_register_clkdev(clk, NULL, "msp1");
 464         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1");
 465
 466         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk",
 467                         clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
 468         clk_register_clkdev(clk, NULL, "sdi0");
 469
 470         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 471                         clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
 472         clk_register_clkdev(clk, NULL, "nmk-i2c.2");
 473
 474         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 475                         clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
 476         clk_register_clkdev(clk, NULL, "slimbus0");
 477
 478         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 479                         clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
 480         clk_register_clkdev(clk, NULL, "nmk-i2c.4");
 481
 482         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 483                         clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
 484         clk_register_clkdev(clk, NULL, "msp3");
 485         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3");
 486
 487         /* Peripheral 2 : PRCC K-clocks */
 488         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 489                         clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
 490         clk_register_clkdev(clk, NULL, "nmk-i2c.3");
 491
 492         clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k",
 493                         clkrst2_base, BIT(1), CLK_SET_RATE_GATE);
 494         clk_register_clkdev(clk, NULL, "pwl");
 495
 496         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk",
 497                         clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
 498         clk_register_clkdev(clk, NULL, "sdi4");
 499
 500         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 501                         clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
 502         clk_register_clkdev(clk, NULL, "msp2");
 503         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2");
 504
 505         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk",
 506                         clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
 507         clk_register_clkdev(clk, NULL, "sdi1");
 508
 509         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 510                         clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
 511         clk_register_clkdev(clk, NULL, "sdi3");
 512
 513         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 514                         clkrst2_base, BIT(6),
 515                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 516         clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0");
 517
 518         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 519                         clkrst2_base, BIT(7),
 520                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 521         clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0");
 522
 523         /* Should only be 9540, but might be added for 85xx as well */
 524         clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk",
 525                         clkrst2_base, BIT(9), CLK_SET_RATE_GATE);
 526         clk_register_clkdev(clk, NULL, "msp4");
 527         clk_register_clkdev(clk, "msp4", "ab85xx-codec.0");
 528
 529         /* Peripheral 3 : PRCC K-clocks */
 530         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 531                         clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
 532         clk_register_clkdev(clk, NULL, "ssp0");
 533
 534         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 535                         clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
 536         clk_register_clkdev(clk, NULL, "ssp1");
 537
 538         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 539                         clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
 540         clk_register_clkdev(clk, NULL, "nmk-i2c.0");
 541
 542         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk",
 543                         clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
 544         clk_register_clkdev(clk, NULL, "sdi2");
 545
 546         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 547                         clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
 548         clk_register_clkdev(clk, NULL, "ske");
 549         clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
 550
 551         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 552                         clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
 553         clk_register_clkdev(clk, NULL, "uart2");
 554
 555         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 556                         clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
 557         clk_register_clkdev(clk, NULL, "sdi5");
 558
 559         clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk",
 560                         clkrst3_base, BIT(8), CLK_SET_RATE_GATE);
 561         clk_register_clkdev(clk, NULL, "nmk-i2c.5");
 562
 563         clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk",
 564                         clkrst3_base, BIT(9), CLK_SET_RATE_GATE);
 565         clk_register_clkdev(clk, NULL, "nmk-i2c.6");
 566
 567         clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk",
 568                         clkrst3_base, BIT(10), CLK_SET_RATE_GATE);
 569         clk_register_clkdev(clk, NULL, "uart3");
 570
 571         clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk",
 572                         clkrst3_base, BIT(11), CLK_SET_RATE_GATE);
 573         clk_register_clkdev(clk, NULL, "uart4");
 574
 575         /* Peripheral 6 : PRCC K-clocks */
 576         clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk",
 577                         clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
 578         clk_register_clkdev(clk, NULL, "rng");
 579 }