kernel/drivers/clk/ux500/abx500-clk.c

   1 /*
   2  * abx500 clock implementation for ux500 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/module.h>
  12 #include <linux/device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/mfd/abx500/ab8500.h>
  15 #include <linux/mfd/abx500/ab8500-sysctrl.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/mfd/dbx500-prcmu.h>
  19 #include "clk.h"
  20
  21 /* Clock definitions for ab8500 */
  22 static int ab8500_reg_clks(struct device *dev)
  23 {
  24         int ret;
  25         struct clk *clk;
  26
  27         const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
  28         u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
  29         u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
  30         u8 intclk_reg_bits[] = {
  31                 0 ,
  32                 (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
  33         };
  34
  35         dev_info(dev, "register clocks for ab850x\n");
  36
  37         /* Enable SWAT */
  38         ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
  39         if (ret)
  40                 return ret;
  41
  42         /* ab8500_sysclk */
  43         clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK,
  44                                 CLK_IS_ROOT);
  45         clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
  46         clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
  47         clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
  48         clk_register_clkdev(clk, "sysclk", "shrm_bus");
  49
  50         /* ab8500_sysclk2 */
  51         clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
  52                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
  53                 AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
  54         clk_register_clkdev(clk, "sysclk", "0-0070");
  55
  56         /* ab8500_sysclk3 */
  57         clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
  58                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
  59                 AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
  60         clk_register_clkdev(clk, "sysclk", "cg1960_core.0");
  61
  62         /* ab8500_sysclk4 */
  63         clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
  64                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
  65                 AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
  66
  67         /* ab_ulpclk */
  68         clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
  69                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
  70                 AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
  71                 38400000, 9000, CLK_IS_ROOT);
  72         clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0");
  73
  74         /* ab8500_intclk */
  75         clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
  76                 intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
  77         clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0");
  78         clk_register_clkdev(clk, NULL, "ab8500-pwm.1");
  79
  80         /* ab8500_audioclk */
  81         clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
  82                 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
  83                 AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
  84         clk_register_clkdev(clk, "audioclk", "ab8500-codec.0");
  85
  86         return 0;
  87 }
  88
  89 /* Clock definitions for ab8540 */
  90 static int ab8540_reg_clks(struct device *dev)
  91 {
  92         return 0;
  93 }
  94
  95 /* Clock definitions for ab9540 */
  96 static int ab9540_reg_clks(struct device *dev)
  97 {
  98         return 0;
  99 }
 100
 101 static int abx500_clk_probe(struct platform_device *pdev)
 102 {
 103         struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
 104         int ret;
 105
 106         if (is_ab8500(parent) || is_ab8505(parent)) {
 107                 ret = ab8500_reg_clks(&pdev->dev);
 108         } else if (is_ab8540(parent)) {
 109                 ret = ab8540_reg_clks(&pdev->dev);
 110         } else if (is_ab9540(parent)) {
 111                 ret = ab9540_reg_clks(&pdev->dev);
 112         } else {
 113                 dev_err(&pdev->dev, "non supported plf id\n");
 114                 return -ENODEV;
 115         }
 116
 117         return ret;
 118 }
 119
 120 static struct platform_driver abx500_clk_driver = {
 121         .driver = {
 122                 .name = "abx500-clk",
 123         },
 124         .probe  = abx500_clk_probe,
 125 };
 126
 127 static int __init abx500_clk_init(void)
 128 {
 129         return platform_driver_register(&abx500_clk_driver);
 130 }
 131
 132 arch_initcall(abx500_clk_init);
 133
 134 MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
 135 MODULE_DESCRIPTION("ABX500 clk driver");
 136 MODULE_LICENSE("GPL v2");