kernel/drivers/clk/tegra/clk-tegra-fixed.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/clk/tegra.h>
  25
  26 #include "clk.h"
  27 #include "clk-id.h"
  28
  29 #define OSC_CTRL                        0x50
  30 #define OSC_CTRL_OSC_FREQ_SHIFT         28
  31 #define OSC_CTRL_PLL_REF_DIV_SHIFT      26
  32
  33 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
  34                               unsigned long *input_freqs, unsigned int num,
  35                               unsigned int clk_m_div, unsigned long *osc_freq,
  36                               unsigned long *pll_ref_freq)
  37 {
  38         struct clk *clk, *osc;
  39         struct clk **dt_clk;
  40         u32 val, pll_ref_div;
  41         unsigned osc_idx;
  42
  43         val = readl_relaxed(clk_base + OSC_CTRL);
  44         osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
  45
  46         if (osc_idx < num)
  47                 *osc_freq = input_freqs[osc_idx];
  48         else
  49                 *osc_freq = 0;
  50
  51         if (!*osc_freq) {
  52                 WARN_ON(1);
  53                 return -EINVAL;
  54         }
  55
  56         osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
  57                                       *osc_freq);
  58
  59         dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
  60         if (!dt_clk)
  61                 return 0;
  62
  63         clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
  64                                         0, 1, clk_m_div);
  65         *dt_clk = clk;
  66
  67         /* pll_ref */
  68         val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
  69         pll_ref_div = 1 << val;
  70         dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
  71         if (!dt_clk)
  72                 return 0;
  73
  74         clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
  75                                         0, 1, pll_ref_div);
  76         *dt_clk = clk;
  77
  78         if (pll_ref_freq)
  79                 *pll_ref_freq = *osc_freq / pll_ref_div;
  80
  81         return 0;
  82 }
  83
  84 void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
  85 {
  86         struct clk *clk;
  87         struct clk **dt_clk;
  88
  89         /* clk_32k */
  90         dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
  91         if (dt_clk) {
  92                 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
  93                                         CLK_IS_ROOT, 32768);
  94                 *dt_clk = clk;
  95         }
  96
  97         /* clk_m_div2 */
  98         dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
  99         if (dt_clk) {
 100                 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
 101                                         CLK_SET_RATE_PARENT, 1, 2);
 102                 *dt_clk = clk;
 103         }
 104
 105         /* clk_m_div4 */
 106         dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
 107         if (dt_clk) {
 108                 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
 109                                         CLK_SET_RATE_PARENT, 1, 4);
 110                 *dt_clk = clk;
 111         }
 112 }
 113