kernel/drivers/clk/samsung/clk-s3c64xx.c

   1 /*
   2  * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for all S3C64xx SoCs.
   9 */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
  19
  20 #include "clk.h"
  21 #include "clk-pll.h"
  22
  23 /* S3C64xx clock controller register offsets. */
  24 #define APLL_LOCK               0x000
  25 #define MPLL_LOCK               0x004
  26 #define EPLL_LOCK               0x008
  27 #define APLL_CON                0x00c
  28 #define MPLL_CON                0x010
  29 #define EPLL_CON0               0x014
  30 #define EPLL_CON1               0x018
  31 #define CLK_SRC                 0x01c
  32 #define CLK_DIV0                0x020
  33 #define CLK_DIV1                0x024
  34 #define CLK_DIV2                0x028
  35 #define HCLK_GATE               0x030
  36 #define PCLK_GATE               0x034
  37 #define SCLK_GATE               0x038
  38 #define MEM0_GATE               0x03c
  39 #define CLK_SRC2                0x10c
  40 #define OTHERS                  0x900
  41
  42 /* Helper macros to define clock arrays. */
  43 #define FIXED_RATE_CLOCKS(name) \
  44                 static struct samsung_fixed_rate_clock name[]
  45 #define MUX_CLOCKS(name)        \
  46                 static struct samsung_mux_clock name[]
  47 #define DIV_CLOCKS(name)        \
  48                 static struct samsung_div_clock name[]
  49 #define GATE_CLOCKS(name)       \
  50                 static struct samsung_gate_clock name[]
  51
  52 /* Helper macros for gate types present on S3C64xx. */
  53 #define GATE_BUS(_id, cname, pname, o, b) \
  54                 GATE(_id, cname, pname, o, b, 0, 0)
  55 #define GATE_SCLK(_id, cname, pname, o, b) \
  56                 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
  57 #define GATE_ON(_id, cname, pname, o, b) \
  58                 GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
  59
  60 /* list of PLLs to be registered */
  61 enum s3c64xx_plls {
  62         apll, mpll, epll,
  63 };
  64
  65 static void __iomem *reg_base;
  66 static bool is_s3c6400;
  67
  68 #ifdef CONFIG_PM_SLEEP
  69 static struct samsung_clk_reg_dump *s3c64xx_save_common;
  70 static struct samsung_clk_reg_dump *s3c64xx_save_soc;
  71
  72 /*
  73  * List of controller registers to be saved and restored during
  74  * a suspend/resume cycle.
  75  */
  76 static unsigned long s3c64xx_clk_regs[] __initdata = {
  77         APLL_LOCK,
  78         MPLL_LOCK,
  79         EPLL_LOCK,
  80         APLL_CON,
  81         MPLL_CON,
  82         EPLL_CON0,
  83         EPLL_CON1,
  84         CLK_SRC,
  85         CLK_DIV0,
  86         CLK_DIV1,
  87         CLK_DIV2,
  88         HCLK_GATE,
  89         PCLK_GATE,
  90         SCLK_GATE,
  91 };
  92
  93 static unsigned long s3c6410_clk_regs[] __initdata = {
  94         CLK_SRC2,
  95         MEM0_GATE,
  96 };
  97
  98 static int s3c64xx_clk_suspend(void)
  99 {
 100         samsung_clk_save(reg_base, s3c64xx_save_common,
 101                                 ARRAY_SIZE(s3c64xx_clk_regs));
 102
 103         if (!is_s3c6400)
 104                 samsung_clk_save(reg_base, s3c64xx_save_soc,
 105                                         ARRAY_SIZE(s3c6410_clk_regs));
 106
 107         return 0;
 108 }
 109
 110 static void s3c64xx_clk_resume(void)
 111 {
 112         samsung_clk_restore(reg_base, s3c64xx_save_common,
 113                                 ARRAY_SIZE(s3c64xx_clk_regs));
 114
 115         if (!is_s3c6400)
 116                 samsung_clk_restore(reg_base, s3c64xx_save_soc,
 117                                         ARRAY_SIZE(s3c6410_clk_regs));
 118 }
 119
 120 static struct syscore_ops s3c64xx_clk_syscore_ops = {
 121         .suspend = s3c64xx_clk_suspend,
 122         .resume = s3c64xx_clk_resume,
 123 };
 124
 125 static void s3c64xx_clk_sleep_init(void)
 126 {
 127         s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
 128                                                 ARRAY_SIZE(s3c64xx_clk_regs));
 129         if (!s3c64xx_save_common)
 130                 goto err_warn;
 131
 132         if (!is_s3c6400) {
 133                 s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
 134                                                 ARRAY_SIZE(s3c6410_clk_regs));
 135                 if (!s3c64xx_save_soc)
 136                         goto err_soc;
 137         }
 138
 139         register_syscore_ops(&s3c64xx_clk_syscore_ops);
 140         return;
 141
 142 err_soc:
 143         kfree(s3c64xx_save_common);
 144 err_warn:
 145         pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
 146                 __func__);
 147 }
 148 #else
 149 static void s3c64xx_clk_sleep_init(void) {}
 150 #endif
 151
 152 /* List of parent clocks common for all S3C64xx SoCs. */
 153 PNAME(spi_mmc_p)        = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
 154 PNAME(uart_p)           = { "mout_epll", "dout_mpll" };
 155 PNAME(audio0_p)         = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
 156                                 "pcmcdclk0", "none", "none", "none" };
 157 PNAME(audio1_p)         = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
 158                                 "pcmcdclk0", "none", "none", "none" };
 159 PNAME(mfc_p)            = { "hclkx2", "mout_epll" };
 160 PNAME(apll_p)           = { "fin_pll", "fout_apll" };
 161 PNAME(mpll_p)           = { "fin_pll", "fout_mpll" };
 162 PNAME(epll_p)           = { "fin_pll", "fout_epll" };
 163 PNAME(hclkx2_p)         = { "mout_mpll", "mout_apll" };
 164
 165 /* S3C6400-specific parent clocks. */
 166 PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
 167 PNAME(irda_p6400)       = { "mout_epll", "dout_mpll", "none", "clk48m" };
 168 PNAME(uhost_p6400)      = { "clk48m", "mout_epll", "dout_mpll", "none" };
 169
 170 /* S3C6410-specific parent clocks. */
 171 PNAME(clk27_p6410)      = { "clk27m", "fin_pll" };
 172 PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
 173 PNAME(irda_p6410)       = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
 174 PNAME(uhost_p6410)      = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
 175 PNAME(audio2_p6410)     = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
 176                                 "pcmcdclk1", "none", "none", "none" };
 177
 178 /* Fixed rate clocks generated outside the SoC. */
 179 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
 180         FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0),
 181         FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0),
 182 };
 183
 184 /* Fixed rate clocks generated inside the SoC. */
 185 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
 186         FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000),
 187         FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000),
 188 };
 189
 190 /* List of clock muxes present on all S3C64xx SoCs. */
 191 MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
 192         MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
 193         MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
 194         MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
 195         MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
 196         MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
 197         MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
 198         MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
 199         MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
 200         MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
 201         MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
 202         MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
 203         MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
 204         MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
 205 };
 206
 207 /* List of clock muxes present on S3C6400. */
 208 MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
 209         MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
 210         MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
 211         MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
 212         MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
 213 };
 214
 215 /* List of clock muxes present on S3C6410. */
 216 MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
 217         MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
 218         MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
 219         MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
 220         MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
 221         MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
 222         MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
 223         MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
 224 };
 225
 226 /* List of clock dividers present on all S3C64xx SoCs. */
 227 DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
 228         DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
 229         DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
 230         DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
 231         DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
 232         DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
 233         DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
 234         DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
 235         DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
 236         DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
 237         DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
 238         DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
 239         DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
 240         DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
 241         DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
 242         DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
 243         DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
 244         DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
 245         DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
 246         DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
 247         DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
 248 };
 249
 250 /* List of clock dividers present on S3C6400. */
 251 DIV_CLOCKS(s3c6400_div_clks) __initdata = {
 252         DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
 253 };
 254
 255 /* List of clock dividers present on S3C6410. */
 256 DIV_CLOCKS(s3c6410_div_clks) __initdata = {
 257         DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
 258         DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
 259         DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
 260 };
 261
 262 /* List of clock gates present on all S3C64xx SoCs. */
 263 GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
 264         GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
 265         GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
 266         GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
 267         GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
 268         GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
 269         GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
 270         GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
 271         GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
 272         GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
 273         GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
 274         GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
 275         GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
 276         GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
 277         GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
 278         GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
 279         GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
 280         GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
 281         GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
 282         GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
 283         GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
 284         GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
 285         GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
 286         GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
 287         GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
 288         GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
 289         GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
 290         GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
 291         GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
 292         GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
 293         GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
 294         GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
 295         GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
 296         GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
 297         GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
 298         GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
 299         GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
 300         GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
 301         GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
 302         GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
 303         GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
 304         GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
 305         GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
 306         GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
 307         GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
 308         GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
 309         GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
 310         GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
 311         GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
 312         GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
 313         GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
 314         GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
 315         GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
 316         GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
 317         GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
 318         GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
 319         GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
 320         GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
 321         GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
 322         GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
 323         GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
 324         GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
 325         GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
 326         GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
 327         GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
 328         GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
 329         GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
 330         GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
 331         GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
 332         GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
 333         GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
 334         GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
 335         GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
 336         GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
 337         GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
 338         GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
 339         GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
 340 };
 341
 342 /* List of clock gates present on S3C6400. */
 343 GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
 344         GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
 345         GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
 346 };
 347
 348 /* List of clock gates present on S3C6410. */
 349 GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
 350         GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
 351         GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
 352         GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
 353         GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
 354         GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
 355         GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
 356         GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
 357         GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
 358         GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
 359         GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
 360         GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
 361         GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
 362         GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
 363         GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
 364 };
 365
 366 /* List of PLL clocks. */
 367 static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
 368         [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
 369                                                 APLL_LOCK, APLL_CON, NULL),
 370         [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
 371                                                 MPLL_LOCK, MPLL_CON, NULL),
 372         [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
 373                                                 EPLL_LOCK, EPLL_CON0, NULL),
 374 };
 375
 376 /* Aliases for common s3c64xx clocks. */
 377 static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
 378         ALIAS(FOUT_APLL, NULL, "fout_apll"),
 379         ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
 380         ALIAS(FOUT_EPLL, NULL, "fout_epll"),
 381         ALIAS(MOUT_EPLL, NULL, "mout_epll"),
 382         ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
 383         ALIAS(HCLKX2, NULL, "hclk2"),
 384         ALIAS(HCLK, NULL, "hclk"),
 385         ALIAS(PCLK, NULL, "pclk"),
 386         ALIAS(PCLK, NULL, "clk_uart_baud2"),
 387         ALIAS(ARMCLK, NULL, "armclk"),
 388         ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
 389         ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
 390         ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
 391         ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
 392         ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
 393         ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
 394         ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
 395         ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
 396         ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
 397         ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
 398         ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
 399         ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
 400         ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
 401         ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
 402         ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
 403         ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
 404         ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
 405         ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
 406         ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
 407         ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
 408         ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
 409         ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
 410         ALIAS(PCLK_PWM, NULL, "timers"),
 411         ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
 412         ALIAS(PCLK_WDT, NULL, "watchdog"),
 413         ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
 414         ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
 415         ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
 416         ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
 417         ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
 418         ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
 419         ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
 420         ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
 421         ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
 422         ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
 423         ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
 424         ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
 425         ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
 426         ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
 427         ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
 428         ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
 429         ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
 430         ALIAS(SCLK_CAM, "s3c-camif", "camera"),
 431 };
 432
 433 /* Aliases for s3c6400-specific clocks. */
 434 static struct samsung_clock_alias s3c6400_clock_aliases[] = {
 435         /* Nothing to place here yet. */
 436 };
 437
 438 /* Aliases for s3c6410-specific clocks. */
 439 static struct samsung_clock_alias s3c6410_clock_aliases[] = {
 440         ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
 441         ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
 442         ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
 443         ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
 444         ALIAS(MEM0_SROM, NULL, "srom"),
 445 };
 446
 447 static void __init s3c64xx_clk_register_fixed_ext(
 448                                 struct samsung_clk_provider *ctx,
 449                                 unsigned long fin_pll_f,
 450                                 unsigned long xusbxti_f)
 451 {
 452         s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
 453         s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
 454         samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
 455                                 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
 456 }
 457
 458 /* Register s3c64xx clocks. */
 459 void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
 460                              unsigned long xusbxti_f, bool s3c6400,
 461                              void __iomem *base)
 462 {
 463         struct samsung_clk_provider *ctx;
 464
 465         reg_base = base;
 466         is_s3c6400 = s3c6400;
 467
 468         if (np) {
 469                 reg_base = of_iomap(np, 0);
 470                 if (!reg_base)
 471                         panic("%s: failed to map registers\n", __func__);
 472         }
 473
 474         ctx = samsung_clk_init(np, reg_base, NR_CLKS);
 475         if (!ctx)
 476                 panic("%s: unable to allocate context.\n", __func__);
 477
 478         /* Register external clocks. */
 479         if (!np)
 480                 s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
 481
 482         /* Register PLLs. */
 483         samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
 484                                 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
 485
 486         /* Register common internal clocks. */
 487         samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
 488                                         ARRAY_SIZE(s3c64xx_fixed_rate_clks));
 489         samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
 490                                         ARRAY_SIZE(s3c64xx_mux_clks));
 491         samsung_clk_register_div(ctx, s3c64xx_div_clks,
 492                                         ARRAY_SIZE(s3c64xx_div_clks));
 493         samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
 494                                         ARRAY_SIZE(s3c64xx_gate_clks));
 495
 496         /* Register SoC-specific clocks. */
 497         if (is_s3c6400) {
 498                 samsung_clk_register_mux(ctx, s3c6400_mux_clks,
 499                                         ARRAY_SIZE(s3c6400_mux_clks));
 500                 samsung_clk_register_div(ctx, s3c6400_div_clks,
 501                                         ARRAY_SIZE(s3c6400_div_clks));
 502                 samsung_clk_register_gate(ctx, s3c6400_gate_clks,
 503                                         ARRAY_SIZE(s3c6400_gate_clks));
 504                 samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
 505                                         ARRAY_SIZE(s3c6400_clock_aliases));
 506         } else {
 507                 samsung_clk_register_mux(ctx, s3c6410_mux_clks,
 508                                         ARRAY_SIZE(s3c6410_mux_clks));
 509                 samsung_clk_register_div(ctx, s3c6410_div_clks,
 510                                         ARRAY_SIZE(s3c6410_div_clks));
 511                 samsung_clk_register_gate(ctx, s3c6410_gate_clks,
 512                                         ARRAY_SIZE(s3c6410_gate_clks));
 513                 samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
 514                                         ARRAY_SIZE(s3c6410_clock_aliases));
 515         }
 516
 517         samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
 518                                         ARRAY_SIZE(s3c64xx_clock_aliases));
 519         s3c64xx_clk_sleep_init();
 520
 521         samsung_clk_of_add_provider(np, ctx);
 522
 523         pr_info("%s clocks: apll = %lu, mpll = %lu\n"
 524                 "\tepll = %lu, arm_clk = %lu\n",
 525                 is_s3c6400 ? "S3C6400" : "S3C6410",
 526                 _get_rate("fout_apll"), _get_rate("fout_mpll"),
 527                 _get_rate("fout_epll"), _get_rate("armclk"));
 528 }
 529
 530 static void __init s3c6400_clk_init(struct device_node *np)
 531 {
 532         s3c64xx_clk_init(np, 0, 0, true, NULL);
 533 }
 534 CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
 535
 536 static void __init s3c6410_clk_init(struct device_node *np)
 537 {
 538         s3c64xx_clk_init(np, 0, 0, false, NULL);
 539 }
 540 CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);