kernel/drivers/clk/samsung/clk-exynos7.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9 */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/of.h>
  15
  16 #include "clk.h"
  17 #include <dt-bindings/clock/exynos7-clk.h>
  18
  19 /* Register Offset definitions for CMU_TOPC (0x10570000) */
  20 #define CC_PLL_LOCK             0x0000
  21 #define BUS0_PLL_LOCK           0x0004
  22 #define BUS1_DPLL_LOCK          0x0008
  23 #define MFC_PLL_LOCK            0x000C
  24 #define AUD_PLL_LOCK            0x0010
  25 #define CC_PLL_CON0             0x0100
  26 #define BUS0_PLL_CON0           0x0110
  27 #define BUS1_DPLL_CON0          0x0120
  28 #define MFC_PLL_CON0            0x0130
  29 #define AUD_PLL_CON0            0x0140
  30 #define MUX_SEL_TOPC0           0x0200
  31 #define MUX_SEL_TOPC1           0x0204
  32 #define MUX_SEL_TOPC2           0x0208
  33 #define MUX_SEL_TOPC3           0x020C
  34 #define DIV_TOPC0               0x0600
  35 #define DIV_TOPC1               0x0604
  36 #define DIV_TOPC3               0x060C
  37 #define ENABLE_ACLK_TOPC1       0x0804
  38
  39 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
  40         FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
  41         FFACTOR(0, "ffac_topc_bus0_pll_div4",
  42                 "ffac_topc_bus0_pll_div2", 1, 2, 0),
  43         FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
  44         FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
  45         FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
  46 };
  47
  48 /* List of parent clocks for Muxes in CMU_TOPC */
  49 PNAME(mout_aud_pll_ctrl_p)      = { "fin_pll", "fout_aud_pll" };
  50 PNAME(mout_bus0_pll_ctrl_p)     = { "fin_pll", "fout_bus0_pll" };
  51 PNAME(mout_bus1_pll_ctrl_p)     = { "fin_pll", "fout_bus1_pll" };
  52 PNAME(mout_cc_pll_ctrl_p)       = { "fin_pll", "fout_cc_pll" };
  53 PNAME(mout_mfc_pll_ctrl_p)      = { "fin_pll", "fout_mfc_pll" };
  54
  55 PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
  56         "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
  57         "mout_sclk_mfc_pll_cmuc" };
  58
  59 PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
  60         "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
  61 PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
  62         "ffac_topc_bus1_pll_div2"};
  63 PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
  64         "ffac_topc_cc_pll_div2"};
  65 PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
  66         "ffac_topc_mfc_pll_div2"};
  67
  68
  69 PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
  70         "ffac_topc_bus0_pll_div2"};
  71
  72 static unsigned long topc_clk_regs[] __initdata = {
  73         CC_PLL_LOCK,
  74         BUS0_PLL_LOCK,
  75         BUS1_DPLL_LOCK,
  76         MFC_PLL_LOCK,
  77         AUD_PLL_LOCK,
  78         CC_PLL_CON0,
  79         BUS0_PLL_CON0,
  80         BUS1_DPLL_CON0,
  81         MFC_PLL_CON0,
  82         AUD_PLL_CON0,
  83         MUX_SEL_TOPC0,
  84         MUX_SEL_TOPC1,
  85         MUX_SEL_TOPC2,
  86         MUX_SEL_TOPC3,
  87         DIV_TOPC0,
  88         DIV_TOPC1,
  89         DIV_TOPC3,
  90 };
  91
  92 static struct samsung_mux_clock topc_mux_clks[] __initdata = {
  93         MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
  94         MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
  95         MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
  96         MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
  97
  98         MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
  99                 MUX_SEL_TOPC0, 16, 2),
 100         MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
 101                 MUX_SEL_TOPC0, 20, 1),
 102         MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
 103                 MUX_SEL_TOPC0, 24, 1),
 104         MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
 105                 MUX_SEL_TOPC0, 28, 1),
 106
 107         MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
 108                 MUX_SEL_TOPC1, 16, 1),
 109         MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
 110
 111         MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
 112
 113         MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
 114         MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
 115 };
 116
 117 static struct samsung_div_clock topc_div_clks[] __initdata = {
 118         DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
 119                 DIV_TOPC0, 4, 4),
 120
 121         DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
 122                 DIV_TOPC1, 20, 4),
 123         DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
 124                 DIV_TOPC1, 24, 4),
 125
 126         DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
 127                 DIV_TOPC3, 0, 3),
 128         DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
 129                 DIV_TOPC3, 8, 3),
 130         DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
 131                 DIV_TOPC3, 12, 3),
 132         DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
 133                 DIV_TOPC3, 16, 3),
 134         DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
 135                 DIV_TOPC3, 28, 3),
 136 };
 137
 138 static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
 139         PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
 140         {},
 141 };
 142
 143 static struct samsung_gate_clock topc_gate_clks[] __initdata = {
 144         GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
 145                 ENABLE_ACLK_TOPC1, 20, 0, 0),
 146 };
 147
 148 static struct samsung_pll_clock topc_pll_clks[] __initdata = {
 149         PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
 150                 BUS0_PLL_CON0, NULL),
 151         PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
 152                 CC_PLL_CON0, NULL),
 153         PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
 154                 BUS1_DPLL_CON0, NULL),
 155         PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
 156                 MFC_PLL_CON0, NULL),
 157         PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
 158                 AUD_PLL_CON0, pll1460x_24mhz_tbl),
 159 };
 160
 161 static struct samsung_cmu_info topc_cmu_info __initdata = {
 162         .pll_clks               = topc_pll_clks,
 163         .nr_pll_clks            = ARRAY_SIZE(topc_pll_clks),
 164         .mux_clks               = topc_mux_clks,
 165         .nr_mux_clks            = ARRAY_SIZE(topc_mux_clks),
 166         .div_clks               = topc_div_clks,
 167         .nr_div_clks            = ARRAY_SIZE(topc_div_clks),
 168         .gate_clks              = topc_gate_clks,
 169         .nr_gate_clks           = ARRAY_SIZE(topc_gate_clks),
 170         .fixed_factor_clks      = topc_fixed_factor_clks,
 171         .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
 172         .nr_clk_ids             = TOPC_NR_CLK,
 173         .clk_regs               = topc_clk_regs,
 174         .nr_clk_regs            = ARRAY_SIZE(topc_clk_regs),
 175 };
 176
 177 static void __init exynos7_clk_topc_init(struct device_node *np)
 178 {
 179         samsung_cmu_register_one(np, &topc_cmu_info);
 180 }
 181
 182 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
 183         exynos7_clk_topc_init);
 184
 185 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
 186 #define MUX_SEL_TOP00                   0x0200
 187 #define MUX_SEL_TOP01                   0x0204
 188 #define MUX_SEL_TOP03                   0x020C
 189 #define MUX_SEL_TOP0_PERIC0             0x0230
 190 #define MUX_SEL_TOP0_PERIC1             0x0234
 191 #define MUX_SEL_TOP0_PERIC2             0x0238
 192 #define MUX_SEL_TOP0_PERIC3             0x023C
 193 #define DIV_TOP03                       0x060C
 194 #define DIV_TOP0_PERIC0                 0x0630
 195 #define DIV_TOP0_PERIC1                 0x0634
 196 #define DIV_TOP0_PERIC2                 0x0638
 197 #define DIV_TOP0_PERIC3                 0x063C
 198 #define ENABLE_SCLK_TOP0_PERIC0         0x0A30
 199 #define ENABLE_SCLK_TOP0_PERIC1         0x0A34
 200 #define ENABLE_SCLK_TOP0_PERIC2         0x0A38
 201 #define ENABLE_SCLK_TOP0_PERIC3         0x0A3C
 202
 203 /* List of parent clocks for Muxes in CMU_TOP0 */
 204 PNAME(mout_bus0_pll_p)  = { "fin_pll", "dout_sclk_bus0_pll" };
 205 PNAME(mout_bus1_pll_p)  = { "fin_pll", "dout_sclk_bus1_pll" };
 206 PNAME(mout_cc_pll_p)    = { "fin_pll", "dout_sclk_cc_pll" };
 207 PNAME(mout_mfc_pll_p)   = { "fin_pll", "dout_sclk_mfc_pll" };
 208 PNAME(mout_aud_pll_p)   = { "fin_pll", "dout_sclk_aud_pll" };
 209
 210 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
 211         "ffac_top0_bus0_pll_div2"};
 212 PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
 213         "ffac_top0_bus1_pll_div2"};
 214 PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
 215         "ffac_top0_cc_pll_div2"};
 216 PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
 217         "ffac_top0_mfc_pll_div2"};
 218
 219 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
 220         "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
 221         "mout_top0_half_mfc_pll"};
 222 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
 223         "ioclk_audiocdclk1", "ioclk_spdif_extclk",
 224         "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
 225         "mout_top0_half_bus1_pll"};
 226 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
 227         "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
 228
 229 static unsigned long top0_clk_regs[] __initdata = {
 230         MUX_SEL_TOP00,
 231         MUX_SEL_TOP01,
 232         MUX_SEL_TOP03,
 233         MUX_SEL_TOP0_PERIC0,
 234         MUX_SEL_TOP0_PERIC1,
 235         MUX_SEL_TOP0_PERIC2,
 236         MUX_SEL_TOP0_PERIC3,
 237         DIV_TOP03,
 238         DIV_TOP0_PERIC0,
 239         DIV_TOP0_PERIC1,
 240         DIV_TOP0_PERIC2,
 241         DIV_TOP0_PERIC3,
 242         ENABLE_SCLK_TOP0_PERIC0,
 243         ENABLE_SCLK_TOP0_PERIC1,
 244         ENABLE_SCLK_TOP0_PERIC2,
 245         ENABLE_SCLK_TOP0_PERIC3,
 246 };
 247
 248 static struct samsung_mux_clock top0_mux_clks[] __initdata = {
 249         MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
 250         MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
 251         MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
 252         MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
 253         MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
 254
 255         MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
 256                 MUX_SEL_TOP01, 4, 1),
 257         MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
 258                 MUX_SEL_TOP01, 8, 1),
 259         MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
 260                 MUX_SEL_TOP01, 12, 1),
 261         MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
 262                 MUX_SEL_TOP01, 16, 1),
 263
 264         MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
 265         MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
 266
 267         MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
 268         MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
 269         MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
 270
 271         MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
 272         MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
 273
 274         MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
 275         MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
 276         MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
 277         MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
 278         MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
 279         MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
 280         MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
 281 };
 282
 283 static struct samsung_div_clock top0_div_clks[] __initdata = {
 284         DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
 285                 DIV_TOP03, 12, 6),
 286         DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
 287                 DIV_TOP03, 20, 6),
 288
 289         DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
 290         DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
 291         DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
 292
 293         DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
 294         DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
 295
 296         DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
 297         DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
 298
 299         DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
 300         DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
 301         DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
 302         DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
 303         DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
 304 };
 305
 306 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
 307         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
 308                 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
 309         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
 310                 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
 311         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
 312                 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
 313
 314         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
 315                 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
 316         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
 317                 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
 318
 319         GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
 320                 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
 321         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
 322                 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
 323         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
 324                 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
 325         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
 326                 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
 327         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
 328                 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
 329         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
 330                 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
 331         GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
 332                 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
 333 };
 334
 335 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
 336         FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
 337         FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
 338         FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
 339         FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
 340 };
 341
 342 static struct samsung_cmu_info top0_cmu_info __initdata = {
 343         .mux_clks               = top0_mux_clks,
 344         .nr_mux_clks            = ARRAY_SIZE(top0_mux_clks),
 345         .div_clks               = top0_div_clks,
 346         .nr_div_clks            = ARRAY_SIZE(top0_div_clks),
 347         .gate_clks              = top0_gate_clks,
 348         .nr_gate_clks           = ARRAY_SIZE(top0_gate_clks),
 349         .fixed_factor_clks      = top0_fixed_factor_clks,
 350         .nr_fixed_factor_clks   = ARRAY_SIZE(top0_fixed_factor_clks),
 351         .nr_clk_ids             = TOP0_NR_CLK,
 352         .clk_regs               = top0_clk_regs,
 353         .nr_clk_regs            = ARRAY_SIZE(top0_clk_regs),
 354 };
 355
 356 static void __init exynos7_clk_top0_init(struct device_node *np)
 357 {
 358         samsung_cmu_register_one(np, &top0_cmu_info);
 359 }
 360
 361 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
 362         exynos7_clk_top0_init);
 363
 364 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
 365 #define MUX_SEL_TOP10                   0x0200
 366 #define MUX_SEL_TOP11                   0x0204
 367 #define MUX_SEL_TOP13                   0x020C
 368 #define MUX_SEL_TOP1_FSYS0              0x0224
 369 #define MUX_SEL_TOP1_FSYS1              0x0228
 370 #define DIV_TOP13                       0x060C
 371 #define DIV_TOP1_FSYS0                  0x0624
 372 #define DIV_TOP1_FSYS1                  0x0628
 373 #define ENABLE_ACLK_TOP13               0x080C
 374 #define ENABLE_SCLK_TOP1_FSYS0          0x0A24
 375 #define ENABLE_SCLK_TOP1_FSYS1          0x0A28
 376
 377 /* List of parent clocks for Muxes in CMU_TOP1 */
 378 PNAME(mout_top1_bus0_pll_p)     = { "fin_pll", "dout_sclk_bus0_pll" };
 379 PNAME(mout_top1_bus1_pll_p)     = { "fin_pll", "dout_sclk_bus1_pll_b" };
 380 PNAME(mout_top1_cc_pll_p)       = { "fin_pll", "dout_sclk_cc_pll_b" };
 381 PNAME(mout_top1_mfc_pll_p)      = { "fin_pll", "dout_sclk_mfc_pll_b" };
 382
 383 PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
 384         "ffac_top1_bus0_pll_div2"};
 385 PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
 386         "ffac_top1_bus1_pll_div2"};
 387 PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
 388         "ffac_top1_cc_pll_div2"};
 389 PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
 390         "ffac_top1_mfc_pll_div2"};
 391
 392 PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
 393         "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
 394         "mout_top1_half_mfc_pll"};
 395
 396 static unsigned long top1_clk_regs[] __initdata = {
 397         MUX_SEL_TOP10,
 398         MUX_SEL_TOP11,
 399         MUX_SEL_TOP13,
 400         MUX_SEL_TOP1_FSYS0,
 401         MUX_SEL_TOP1_FSYS1,
 402         DIV_TOP13,
 403         DIV_TOP1_FSYS0,
 404         DIV_TOP1_FSYS1,
 405         ENABLE_ACLK_TOP13,
 406         ENABLE_SCLK_TOP1_FSYS0,
 407         ENABLE_SCLK_TOP1_FSYS1,
 408 };
 409
 410 static struct samsung_mux_clock top1_mux_clks[] __initdata = {
 411         MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
 412         MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
 413         MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
 414                 MUX_SEL_TOP10, 12, 1),
 415         MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
 416                 MUX_SEL_TOP10, 16, 1),
 417
 418         MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
 419                 MUX_SEL_TOP11, 4, 1),
 420         MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
 421                 MUX_SEL_TOP11, 8, 1),
 422         MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
 423                 MUX_SEL_TOP11, 12, 1),
 424         MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
 425                 MUX_SEL_TOP11, 16, 1),
 426
 427         MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
 428         MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 429
 430         MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
 431         MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
 432                 MUX_SEL_TOP1_FSYS0, 28, 2),
 433
 434         MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
 435         MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
 436 };
 437
 438 static struct samsung_div_clock top1_div_clks[] __initdata = {
 439         DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
 440                 DIV_TOP13, 24, 4),
 441         DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
 442                 DIV_TOP13, 28, 4),
 443
 444         DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
 445                 DIV_TOP1_FSYS0, 24, 4),
 446         DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
 447                 DIV_TOP1_FSYS0, 28, 4),
 448
 449         DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
 450                 DIV_TOP1_FSYS1, 24, 4),
 451         DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
 452                 DIV_TOP1_FSYS1, 28, 4),
 453 };
 454
 455 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 456         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
 457                 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
 458         GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
 459                 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 460
 461         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
 462                 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
 463         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
 464                 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
 465 };
 466
 467 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
 468         FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
 469         FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
 470         FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
 471         FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
 472 };
 473
 474 static struct samsung_cmu_info top1_cmu_info __initdata = {
 475         .mux_clks               = top1_mux_clks,
 476         .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
 477         .div_clks               = top1_div_clks,
 478         .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
 479         .gate_clks              = top1_gate_clks,
 480         .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
 481         .fixed_factor_clks      = top1_fixed_factor_clks,
 482         .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
 483         .nr_clk_ids             = TOP1_NR_CLK,
 484         .clk_regs               = top1_clk_regs,
 485         .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
 486 };
 487
 488 static void __init exynos7_clk_top1_init(struct device_node *np)
 489 {
 490         samsung_cmu_register_one(np, &top1_cmu_info);
 491 }
 492
 493 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
 494         exynos7_clk_top1_init);
 495
 496 /* Register Offset definitions for CMU_CCORE (0x105B0000) */
 497 #define MUX_SEL_CCORE                   0x0200
 498 #define DIV_CCORE                       0x0600
 499 #define ENABLE_ACLK_CCORE0              0x0800
 500 #define ENABLE_ACLK_CCORE1              0x0804
 501 #define ENABLE_PCLK_CCORE               0x0900
 502
 503 /*
 504  * List of parent clocks for Muxes in CMU_CCORE
 505  */
 506 PNAME(mout_aclk_ccore_133_p)    = { "fin_pll", "dout_aclk_ccore_133" };
 507
 508 static unsigned long ccore_clk_regs[] __initdata = {
 509         MUX_SEL_CCORE,
 510         ENABLE_PCLK_CCORE,
 511 };
 512
 513 static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
 514         MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
 515                 MUX_SEL_CCORE, 1, 1),
 516 };
 517
 518 static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
 519         GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
 520                 ENABLE_PCLK_CCORE, 8, 0, 0),
 521 };
 522
 523 static struct samsung_cmu_info ccore_cmu_info __initdata = {
 524         .mux_clks               = ccore_mux_clks,
 525         .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
 526         .gate_clks              = ccore_gate_clks,
 527         .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
 528         .nr_clk_ids             = CCORE_NR_CLK,
 529         .clk_regs               = ccore_clk_regs,
 530         .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
 531 };
 532
 533 static void __init exynos7_clk_ccore_init(struct device_node *np)
 534 {
 535         samsung_cmu_register_one(np, &ccore_cmu_info);
 536 }
 537
 538 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
 539         exynos7_clk_ccore_init);
 540
 541 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
 542 #define MUX_SEL_PERIC0                  0x0200
 543 #define ENABLE_PCLK_PERIC0              0x0900
 544 #define ENABLE_SCLK_PERIC0              0x0A00
 545
 546 /* List of parent clocks for Muxes in CMU_PERIC0 */
 547 PNAME(mout_aclk_peric0_66_p)    = { "fin_pll", "dout_aclk_peric0_66" };
 548 PNAME(mout_sclk_uart0_p)        = { "fin_pll", "sclk_uart0" };
 549
 550 static unsigned long peric0_clk_regs[] __initdata = {
 551         MUX_SEL_PERIC0,
 552         ENABLE_PCLK_PERIC0,
 553         ENABLE_SCLK_PERIC0,
 554 };
 555
 556 static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
 557         MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
 558                 MUX_SEL_PERIC0, 0, 1),
 559         MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
 560                 MUX_SEL_PERIC0, 16, 1),
 561 };
 562
 563 static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
 564         GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
 565                 ENABLE_PCLK_PERIC0, 8, 0, 0),
 566         GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
 567                 ENABLE_PCLK_PERIC0, 9, 0, 0),
 568         GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
 569                 ENABLE_PCLK_PERIC0, 10, 0, 0),
 570         GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
 571                 ENABLE_PCLK_PERIC0, 11, 0, 0),
 572         GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
 573                 ENABLE_PCLK_PERIC0, 12, 0, 0),
 574         GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
 575                 ENABLE_PCLK_PERIC0, 13, 0, 0),
 576         GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
 577                 ENABLE_PCLK_PERIC0, 14, 0, 0),
 578         GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
 579                 ENABLE_PCLK_PERIC0, 16, 0, 0),
 580         GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
 581                 ENABLE_PCLK_PERIC0, 20, 0, 0),
 582         GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
 583                 ENABLE_PCLK_PERIC0, 21, 0, 0),
 584
 585         GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
 586                 ENABLE_SCLK_PERIC0, 16, 0, 0),
 587         GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
 588 };
 589
 590 static struct samsung_cmu_info peric0_cmu_info __initdata = {
 591         .mux_clks               = peric0_mux_clks,
 592         .nr_mux_clks            = ARRAY_SIZE(peric0_mux_clks),
 593         .gate_clks              = peric0_gate_clks,
 594         .nr_gate_clks           = ARRAY_SIZE(peric0_gate_clks),
 595         .nr_clk_ids             = PERIC0_NR_CLK,
 596         .clk_regs               = peric0_clk_regs,
 597         .nr_clk_regs            = ARRAY_SIZE(peric0_clk_regs),
 598 };
 599
 600 static void __init exynos7_clk_peric0_init(struct device_node *np)
 601 {
 602         samsung_cmu_register_one(np, &peric0_cmu_info);
 603 }
 604
 605 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
 606 #define MUX_SEL_PERIC10                 0x0200
 607 #define MUX_SEL_PERIC11                 0x0204
 608 #define MUX_SEL_PERIC12                 0x0208
 609 #define ENABLE_PCLK_PERIC1              0x0900
 610 #define ENABLE_SCLK_PERIC10             0x0A00
 611
 612 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
 613         exynos7_clk_peric0_init);
 614
 615 /* List of parent clocks for Muxes in CMU_PERIC1 */
 616 PNAME(mout_aclk_peric1_66_p)    = { "fin_pll", "dout_aclk_peric1_66" };
 617 PNAME(mout_sclk_uart1_p)        = { "fin_pll", "sclk_uart1" };
 618 PNAME(mout_sclk_uart2_p)        = { "fin_pll", "sclk_uart2" };
 619 PNAME(mout_sclk_uart3_p)        = { "fin_pll", "sclk_uart3" };
 620 PNAME(mout_sclk_spi0_p)         = { "fin_pll", "sclk_spi0" };
 621 PNAME(mout_sclk_spi1_p)         = { "fin_pll", "sclk_spi1" };
 622 PNAME(mout_sclk_spi2_p)         = { "fin_pll", "sclk_spi2" };
 623 PNAME(mout_sclk_spi3_p)         = { "fin_pll", "sclk_spi3" };
 624 PNAME(mout_sclk_spi4_p)         = { "fin_pll", "sclk_spi4" };
 625
 626 static unsigned long peric1_clk_regs[] __initdata = {
 627         MUX_SEL_PERIC10,
 628         MUX_SEL_PERIC11,
 629         MUX_SEL_PERIC12,
 630         ENABLE_PCLK_PERIC1,
 631         ENABLE_SCLK_PERIC10,
 632 };
 633
 634 static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
 635         MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
 636                 MUX_SEL_PERIC10, 0, 1),
 637
 638         MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
 639                 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
 640         MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
 641                 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
 642         MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
 643                 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
 644         MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
 645                 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
 646         MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
 647                 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
 648         MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
 649                 MUX_SEL_PERIC11, 20, 1),
 650         MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
 651                 MUX_SEL_PERIC11, 24, 1),
 652         MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
 653                 MUX_SEL_PERIC11, 28, 1),
 654 };
 655
 656 static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
 657         GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
 658                 ENABLE_PCLK_PERIC1, 4, 0, 0),
 659         GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
 660                 ENABLE_PCLK_PERIC1, 5, 0, 0),
 661         GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
 662                 ENABLE_PCLK_PERIC1, 6, 0, 0),
 663         GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
 664                 ENABLE_PCLK_PERIC1, 7, 0, 0),
 665         GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
 666                 ENABLE_PCLK_PERIC1, 8, 0, 0),
 667         GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
 668                 ENABLE_PCLK_PERIC1, 9, 0, 0),
 669         GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
 670                 ENABLE_PCLK_PERIC1, 10, 0, 0),
 671         GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
 672                 ENABLE_PCLK_PERIC1, 11, 0, 0),
 673         GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
 674                 ENABLE_PCLK_PERIC1, 12, 0, 0),
 675         GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
 676                 ENABLE_PCLK_PERIC1, 13, 0, 0),
 677         GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
 678                 ENABLE_PCLK_PERIC1, 14, 0, 0),
 679         GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
 680                 ENABLE_PCLK_PERIC1, 15, 0, 0),
 681         GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
 682                 ENABLE_PCLK_PERIC1, 16, 0, 0),
 683         GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
 684                 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
 685         GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
 686                 ENABLE_PCLK_PERIC1, 18, 0, 0),
 687         GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
 688                 ENABLE_PCLK_PERIC1, 19, 0, 0),
 689
 690         GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
 691                 ENABLE_SCLK_PERIC10, 9, 0, 0),
 692         GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
 693                 ENABLE_SCLK_PERIC10, 10, 0, 0),
 694         GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
 695                 ENABLE_SCLK_PERIC10, 11, 0, 0),
 696         GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
 697                 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
 698         GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
 699                 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
 700         GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
 701                 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
 702         GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
 703                 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
 704         GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
 705                 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
 706         GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
 707                 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
 708         GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
 709                 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
 710         GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
 711                 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
 712 };
 713
 714 static struct samsung_cmu_info peric1_cmu_info __initdata = {
 715         .mux_clks               = peric1_mux_clks,
 716         .nr_mux_clks            = ARRAY_SIZE(peric1_mux_clks),
 717         .gate_clks              = peric1_gate_clks,
 718         .nr_gate_clks           = ARRAY_SIZE(peric1_gate_clks),
 719         .nr_clk_ids             = PERIC1_NR_CLK,
 720         .clk_regs               = peric1_clk_regs,
 721         .nr_clk_regs            = ARRAY_SIZE(peric1_clk_regs),
 722 };
 723
 724 static void __init exynos7_clk_peric1_init(struct device_node *np)
 725 {
 726         samsung_cmu_register_one(np, &peric1_cmu_info);
 727 }
 728
 729 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
 730         exynos7_clk_peric1_init);
 731
 732 /* Register Offset definitions for CMU_PERIS (0x10040000) */
 733 #define MUX_SEL_PERIS                   0x0200
 734 #define ENABLE_PCLK_PERIS               0x0900
 735 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
 736 #define ENABLE_SCLK_PERIS               0x0A00
 737 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
 738
 739 /* List of parent clocks for Muxes in CMU_PERIS */
 740 PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
 741
 742 static unsigned long peris_clk_regs[] __initdata = {
 743         MUX_SEL_PERIS,
 744         ENABLE_PCLK_PERIS,
 745         ENABLE_PCLK_PERIS_SECURE_CHIPID,
 746         ENABLE_SCLK_PERIS,
 747         ENABLE_SCLK_PERIS_SECURE_CHIPID,
 748 };
 749
 750 static struct samsung_mux_clock peris_mux_clks[] __initdata = {
 751         MUX(0, "mout_aclk_peris_66_user",
 752                 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
 753 };
 754
 755 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
 756         GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
 757                 ENABLE_PCLK_PERIS, 6, 0, 0),
 758         GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
 759                 ENABLE_PCLK_PERIS, 10, 0, 0),
 760
 761         GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
 762                 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
 763         GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
 764                 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
 765
 766         GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
 767 };
 768
 769 static struct samsung_cmu_info peris_cmu_info __initdata = {
 770         .mux_clks               = peris_mux_clks,
 771         .nr_mux_clks            = ARRAY_SIZE(peris_mux_clks),
 772         .gate_clks              = peris_gate_clks,
 773         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
 774         .nr_clk_ids             = PERIS_NR_CLK,
 775         .clk_regs               = peris_clk_regs,
 776         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
 777 };
 778
 779 static void __init exynos7_clk_peris_init(struct device_node *np)
 780 {
 781         samsung_cmu_register_one(np, &peris_cmu_info);
 782 }
 783
 784 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 785         exynos7_clk_peris_init);
 786
 787 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
 788 #define MUX_SEL_FSYS00                  0x0200
 789 #define MUX_SEL_FSYS01                  0x0204
 790 #define MUX_SEL_FSYS02                  0x0208
 791 #define ENABLE_ACLK_FSYS00              0x0800
 792 #define ENABLE_ACLK_FSYS01              0x0804
 793 #define ENABLE_SCLK_FSYS01              0x0A04
 794 #define ENABLE_SCLK_FSYS02              0x0A08
 795 #define ENABLE_SCLK_FSYS04              0x0A10
 796
 797 /*
 798  * List of parent clocks for Muxes in CMU_FSYS0
 799  */
 800 PNAME(mout_aclk_fsys0_200_p)    = { "fin_pll", "dout_aclk_fsys0_200" };
 801 PNAME(mout_sclk_mmc2_p)         = { "fin_pll", "sclk_mmc2" };
 802
 803 PNAME(mout_sclk_usbdrd300_p)    = { "fin_pll", "sclk_usbdrd300" };
 804 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)    = { "fin_pll",
 805                                 "phyclk_usbdrd300_udrd30_phyclock" };
 806 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
 807                                 "phyclk_usbdrd300_udrd30_pipe_pclk" };
 808
 809 /* fixed rate clocks used in the FSYS0 block */
 810 struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
 811         FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
 812                 CLK_IS_ROOT, 60000000),
 813         FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
 814                 CLK_IS_ROOT, 125000000),
 815 };
 816
 817 static unsigned long fsys0_clk_regs[] __initdata = {
 818         MUX_SEL_FSYS00,
 819         MUX_SEL_FSYS01,
 820         MUX_SEL_FSYS02,
 821         ENABLE_ACLK_FSYS00,
 822         ENABLE_ACLK_FSYS01,
 823         ENABLE_SCLK_FSYS01,
 824         ENABLE_SCLK_FSYS02,
 825         ENABLE_SCLK_FSYS04,
 826 };
 827
 828 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
 829         MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
 830                 MUX_SEL_FSYS00, 24, 1),
 831
 832         MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
 833         MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
 834                 MUX_SEL_FSYS01, 28, 1),
 835
 836         MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
 837                 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
 838                 MUX_SEL_FSYS02, 24, 1),
 839         MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
 840                 mout_phyclk_usbdrd300_udrd30_phyclk_p,
 841                 MUX_SEL_FSYS02, 28, 1),
 842 };
 843
 844 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
 845         GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
 846                 "mout_aclk_fsys0_200_user",
 847                 ENABLE_ACLK_FSYS00, 19, 0, 0),
 848         GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
 849                         ENABLE_ACLK_FSYS00, 3, 0, 0),
 850         GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
 851                         ENABLE_ACLK_FSYS00, 4, 0, 0),
 852
 853         GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
 854                 ENABLE_ACLK_FSYS01, 29, 0, 0),
 855         GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
 856                 ENABLE_ACLK_FSYS01, 31, 0, 0),
 857
 858         GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
 859                 "mout_sclk_usbdrd300_user",
 860                 ENABLE_SCLK_FSYS01, 4, 0, 0),
 861         GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
 862                 ENABLE_SCLK_FSYS01, 8, 0, 0),
 863
 864         GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
 865                 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
 866                 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
 867                 ENABLE_SCLK_FSYS02, 24, 0, 0),
 868         GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
 869                 "phyclk_usbdrd300_udrd30_phyclk_user",
 870                 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
 871                 ENABLE_SCLK_FSYS02, 28, 0, 0),
 872
 873         GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
 874                 "fin_pll",
 875                 ENABLE_SCLK_FSYS04, 28, 0, 0),
 876 };
 877
 878 static struct samsung_cmu_info fsys0_cmu_info __initdata = {
 879         .mux_clks               = fsys0_mux_clks,
 880         .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
 881         .gate_clks              = fsys0_gate_clks,
 882         .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
 883         .nr_clk_ids             = TOP1_NR_CLK,
 884         .clk_regs               = fsys0_clk_regs,
 885         .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
 886 };
 887
 888 static void __init exynos7_clk_fsys0_init(struct device_node *np)
 889 {
 890         samsung_cmu_register_one(np, &fsys0_cmu_info);
 891 }
 892
 893 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
 894         exynos7_clk_fsys0_init);
 895
 896 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
 897 #define MUX_SEL_FSYS10                  0x0200
 898 #define MUX_SEL_FSYS11                  0x0204
 899 #define ENABLE_ACLK_FSYS1               0x0800
 900
 901 /*
 902  * List of parent clocks for Muxes in CMU_FSYS1
 903  */
 904 PNAME(mout_aclk_fsys1_200_p)    = { "fin_pll",  "dout_aclk_fsys1_200" };
 905 PNAME(mout_sclk_mmc0_p)         = { "fin_pll", "sclk_mmc0" };
 906 PNAME(mout_sclk_mmc1_p)         = { "fin_pll", "sclk_mmc1" };
 907
 908 static unsigned long fsys1_clk_regs[] __initdata = {
 909         MUX_SEL_FSYS10,
 910         MUX_SEL_FSYS11,
 911         ENABLE_ACLK_FSYS1,
 912 };
 913
 914 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
 915         MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
 916                 MUX_SEL_FSYS10, 28, 1),
 917
 918         MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
 919         MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
 920 };
 921
 922 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
 923         GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
 924                 ENABLE_ACLK_FSYS1, 29, 0, 0),
 925         GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
 926                 ENABLE_ACLK_FSYS1, 30, 0, 0),
 927 };
 928
 929 static struct samsung_cmu_info fsys1_cmu_info __initdata = {
 930         .mux_clks               = fsys1_mux_clks,
 931         .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
 932         .gate_clks              = fsys1_gate_clks,
 933         .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
 934         .nr_clk_ids             = TOP1_NR_CLK,
 935         .clk_regs               = fsys1_clk_regs,
 936         .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
 937 };
 938
 939 static void __init exynos7_clk_fsys1_init(struct device_node *np)
 940 {
 941         samsung_cmu_register_one(np, &fsys1_cmu_info);
 942 }
 943
 944 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
 945         exynos7_clk_fsys1_init);
 946
 947 #define MUX_SEL_MSCL                    0x0200
 948 #define DIV_MSCL                        0x0600
 949 #define ENABLE_ACLK_MSCL                0x0800
 950 #define ENABLE_PCLK_MSCL                0x0900
 951
 952 /* List of parent clocks for Muxes in CMU_MSCL */
 953 PNAME(mout_aclk_mscl_532_user_p)        = { "fin_pll", "aclk_mscl_532" };
 954
 955 static unsigned long mscl_clk_regs[] __initdata = {
 956         MUX_SEL_MSCL,
 957         DIV_MSCL,
 958         ENABLE_ACLK_MSCL,
 959         ENABLE_PCLK_MSCL,
 960 };
 961
 962 static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
 963         MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
 964                 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
 965 };
 966 static struct samsung_div_clock mscl_div_clks[] __initdata = {
 967         DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
 968                         DIV_MSCL, 0, 3),
 969 };
 970 static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
 971
 972         GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
 973                         ENABLE_ACLK_MSCL, 31, 0, 0),
 974         GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
 975                         ENABLE_ACLK_MSCL, 30, 0, 0),
 976         GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
 977                         ENABLE_ACLK_MSCL, 29, 0, 0),
 978         GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
 979                         ENABLE_ACLK_MSCL, 28, 0, 0),
 980         GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
 981                         "usermux_aclk_mscl_532",
 982                         ENABLE_ACLK_MSCL, 27, 0, 0),
 983         GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
 984                         "usermux_aclk_mscl_532",
 985                         ENABLE_ACLK_MSCL, 26, 0, 0),
 986         GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
 987                         ENABLE_ACLK_MSCL, 25, 0, 0),
 988         GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
 989                         ENABLE_ACLK_MSCL, 24, 0, 0),
 990         GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
 991                         "usermux_aclk_mscl_532",
 992                         ENABLE_ACLK_MSCL, 23, 0, 0),
 993         GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
 994                         ENABLE_ACLK_MSCL, 22, 0, 0),
 995         GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
 996                         ENABLE_ACLK_MSCL, 21, 0, 0),
 997         GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
 998                         ENABLE_ACLK_MSCL, 20, 0, 0),
 999         GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
1000                         ENABLE_ACLK_MSCL, 19, 0, 0),
1001         GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1002                         ENABLE_ACLK_MSCL, 18, 0, 0),
1003         GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1004                         ENABLE_ACLK_MSCL, 17, 0, 0),
1005         GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1006                         ENABLE_ACLK_MSCL, 16, 0, 0),
1007         GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1008                         "usermux_aclk_mscl_532",
1009                         ENABLE_ACLK_MSCL, 15, 0, 0),
1010         GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1011                         "usermux_aclk_mscl_532",
1012                         ENABLE_ACLK_MSCL, 14, 0, 0),
1013
1014         GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1015                         ENABLE_PCLK_MSCL, 31, 0, 0),
1016         GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1017                         ENABLE_PCLK_MSCL, 30, 0, 0),
1018         GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1019                         ENABLE_PCLK_MSCL, 29, 0, 0),
1020         GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1021                         ENABLE_PCLK_MSCL, 28, 0, 0),
1022         GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1023                         ENABLE_PCLK_MSCL, 27, 0, 0),
1024         GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1025                         ENABLE_PCLK_MSCL, 26, 0, 0),
1026         GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1027                         ENABLE_PCLK_MSCL, 25, 0, 0),
1028         GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1029                         ENABLE_PCLK_MSCL, 24, 0, 0),
1030         GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1031                         ENABLE_PCLK_MSCL, 23, 0, 0),
1032         GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1033                         ENABLE_PCLK_MSCL, 22, 0, 0),
1034         GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1035                         ENABLE_PCLK_MSCL, 21, 0, 0),
1036         GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1037                         ENABLE_PCLK_MSCL, 20, 0, 0),
1038 };
1039
1040 static struct samsung_cmu_info mscl_cmu_info __initdata = {
1041         .mux_clks               = mscl_mux_clks,
1042         .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
1043         .div_clks               = mscl_div_clks,
1044         .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
1045         .gate_clks              = mscl_gate_clks,
1046         .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
1047         .nr_clk_ids             = MSCL_NR_CLK,
1048         .clk_regs               = mscl_clk_regs,
1049         .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
1050 };
1051
1052 static void __init exynos7_clk_mscl_init(struct device_node *np)
1053 {
1054         samsung_cmu_register_one(np, &mscl_cmu_info);
1055 }
1056
1057 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1058                 exynos7_clk_mscl_init);
1059
1060 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1061 #define MUX_SEL_AUD                     0x0200
1062 #define DIV_AUD0                        0x0600
1063 #define DIV_AUD1                        0x0604
1064 #define ENABLE_ACLK_AUD                 0x0800
1065 #define ENABLE_PCLK_AUD                 0x0900
1066 #define ENABLE_SCLK_AUD                 0x0A00
1067
1068 /*
1069  * List of parent clocks for Muxes in CMU_AUD
1070  */
1071 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1072 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1073
1074 static unsigned long aud_clk_regs[] __initdata = {
1075         MUX_SEL_AUD,
1076         DIV_AUD0,
1077         DIV_AUD1,
1078         ENABLE_ACLK_AUD,
1079         ENABLE_PCLK_AUD,
1080         ENABLE_SCLK_AUD,
1081 };
1082
1083 static struct samsung_mux_clock aud_mux_clks[] __initdata = {
1084         MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1085         MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1086         MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1087 };
1088
1089 static struct samsung_div_clock aud_div_clks[] __initdata = {
1090         DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1091         DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1092         DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1093
1094         DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1095         DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1096         DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1097         DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1098         DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1099 };
1100
1101 static struct samsung_gate_clock aud_gate_clks[] __initdata = {
1102         GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1103                         ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1104         GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1105                         ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1106         GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1107         GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1108                         ENABLE_SCLK_AUD, 30, 0, 0),
1109
1110         GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1111         GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1112         GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1113         GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1114         GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1115         GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1116         GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1117                         ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1118         GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1119                         ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1120         GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1121         GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1122
1123         GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1124         GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1125                          ENABLE_ACLK_AUD, 28, 0, 0),
1126         GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1127 };
1128
1129 static struct samsung_cmu_info aud_cmu_info __initdata = {
1130         .mux_clks               = aud_mux_clks,
1131         .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
1132         .div_clks               = aud_div_clks,
1133         .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
1134         .gate_clks              = aud_gate_clks,
1135         .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
1136         .nr_clk_ids             = AUD_NR_CLK,
1137         .clk_regs               = aud_clk_regs,
1138         .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
1139 };
1140
1141 static void __init exynos7_clk_aud_init(struct device_node *np)
1142 {
1143         samsung_cmu_register_one(np, &aud_cmu_info);
1144 }
1145
1146 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1147                 exynos7_clk_aud_init);