kernel/drivers/clk/samsung/clk-exynos5420.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
   4  *          Chander Kashyap <k.chander@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Common Clock Framework support for Exynos5420 SoC.
  11 */
  12
  13 #include <dt-bindings/clock/exynos5420.h>
  14 #include <linux/slab.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include "clk.h"
  21
  22 #define APLL_LOCK               0x0
  23 #define APLL_CON0               0x100
  24 #define SRC_CPU                 0x200
  25 #define DIV_CPU0                0x500
  26 #define DIV_CPU1                0x504
  27 #define GATE_BUS_CPU            0x700
  28 #define GATE_SCLK_CPU           0x800
  29 #define CLKOUT_CMU_CPU          0xa00
  30 #define SRC_MASK_CPERI          0x4300
  31 #define GATE_IP_G2D             0x8800
  32 #define CPLL_LOCK               0x10020
  33 #define DPLL_LOCK               0x10030
  34 #define EPLL_LOCK               0x10040
  35 #define RPLL_LOCK               0x10050
  36 #define IPLL_LOCK               0x10060
  37 #define SPLL_LOCK               0x10070
  38 #define VPLL_LOCK               0x10080
  39 #define MPLL_LOCK               0x10090
  40 #define CPLL_CON0               0x10120
  41 #define DPLL_CON0               0x10128
  42 #define EPLL_CON0               0x10130
  43 #define EPLL_CON1               0x10134
  44 #define EPLL_CON2               0x10138
  45 #define RPLL_CON0               0x10140
  46 #define RPLL_CON1               0x10144
  47 #define RPLL_CON2               0x10148
  48 #define IPLL_CON0               0x10150
  49 #define SPLL_CON0               0x10160
  50 #define VPLL_CON0               0x10170
  51 #define MPLL_CON0               0x10180
  52 #define SRC_TOP0                0x10200
  53 #define SRC_TOP1                0x10204
  54 #define SRC_TOP2                0x10208
  55 #define SRC_TOP3                0x1020c
  56 #define SRC_TOP4                0x10210
  57 #define SRC_TOP5                0x10214
  58 #define SRC_TOP6                0x10218
  59 #define SRC_TOP7                0x1021c
  60 #define SRC_TOP8                0x10220 /* 5800 specific */
  61 #define SRC_TOP9                0x10224 /* 5800 specific */
  62 #define SRC_DISP10              0x1022c
  63 #define SRC_MAU                 0x10240
  64 #define SRC_FSYS                0x10244
  65 #define SRC_PERIC0              0x10250
  66 #define SRC_PERIC1              0x10254
  67 #define SRC_ISP                 0x10270
  68 #define SRC_CAM                 0x10274 /* 5800 specific */
  69 #define SRC_TOP10               0x10280
  70 #define SRC_TOP11               0x10284
  71 #define SRC_TOP12               0x10288
  72 #define SRC_TOP13               0x1028c /* 5800 specific */
  73 #define SRC_MASK_TOP0           0x10300
  74 #define SRC_MASK_TOP1           0x10304
  75 #define SRC_MASK_TOP2           0x10308
  76 #define SRC_MASK_TOP7           0x1031c
  77 #define SRC_MASK_DISP10         0x1032c
  78 #define SRC_MASK_MAU            0x10334
  79 #define SRC_MASK_FSYS           0x10340
  80 #define SRC_MASK_PERIC0         0x10350
  81 #define SRC_MASK_PERIC1         0x10354
  82 #define SRC_MASK_ISP            0x10370
  83 #define DIV_TOP0                0x10500
  84 #define DIV_TOP1                0x10504
  85 #define DIV_TOP2                0x10508
  86 #define DIV_TOP8                0x10520 /* 5800 specific */
  87 #define DIV_TOP9                0x10524 /* 5800 specific */
  88 #define DIV_DISP10              0x1052c
  89 #define DIV_MAU                 0x10544
  90 #define DIV_FSYS0               0x10548
  91 #define DIV_FSYS1               0x1054c
  92 #define DIV_FSYS2               0x10550
  93 #define DIV_PERIC0              0x10558
  94 #define DIV_PERIC1              0x1055c
  95 #define DIV_PERIC2              0x10560
  96 #define DIV_PERIC3              0x10564
  97 #define DIV_PERIC4              0x10568
  98 #define DIV_CAM                 0x10574 /* 5800 specific */
  99 #define SCLK_DIV_ISP0           0x10580
 100 #define SCLK_DIV_ISP1           0x10584
 101 #define DIV2_RATIO0             0x10590
 102 #define DIV4_RATIO              0x105a0
 103 #define GATE_BUS_TOP            0x10700
 104 #define GATE_BUS_DISP1          0x10728
 105 #define GATE_BUS_GEN            0x1073c
 106 #define GATE_BUS_FSYS0          0x10740
 107 #define GATE_BUS_FSYS2          0x10748
 108 #define GATE_BUS_PERIC          0x10750
 109 #define GATE_BUS_PERIC1         0x10754
 110 #define GATE_BUS_PERIS0         0x10760
 111 #define GATE_BUS_PERIS1         0x10764
 112 #define GATE_BUS_NOC            0x10770
 113 #define GATE_TOP_SCLK_ISP       0x10870
 114 #define GATE_IP_GSCL0           0x10910
 115 #define GATE_IP_GSCL1           0x10920
 116 #define GATE_IP_CAM             0x10924 /* 5800 specific */
 117 #define GATE_IP_MFC             0x1092c
 118 #define GATE_IP_DISP1           0x10928
 119 #define GATE_IP_G3D             0x10930
 120 #define GATE_IP_GEN             0x10934
 121 #define GATE_IP_FSYS            0x10944
 122 #define GATE_IP_PERIC           0x10950
 123 #define GATE_IP_PERIS           0x10960
 124 #define GATE_IP_MSCL            0x10970
 125 #define GATE_TOP_SCLK_GSCL      0x10820
 126 #define GATE_TOP_SCLK_DISP1     0x10828
 127 #define GATE_TOP_SCLK_MAU       0x1083c
 128 #define GATE_TOP_SCLK_FSYS      0x10840
 129 #define GATE_TOP_SCLK_PERIC     0x10850
 130 #define TOP_SPARE2              0x10b08
 131 #define BPLL_LOCK               0x20010
 132 #define BPLL_CON0               0x20110
 133 #define KPLL_LOCK               0x28000
 134 #define KPLL_CON0               0x28100
 135 #define SRC_KFC                 0x28200
 136 #define DIV_KFC0                0x28500
 137
 138 /* Exynos5x SoC type */
 139 enum exynos5x_soc {
 140         EXYNOS5420,
 141         EXYNOS5800,
 142 };
 143
 144 /* list of PLLs */
 145 enum exynos5x_plls {
 146         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
 147         bpll, kpll,
 148         nr_plls                 /* number of PLLs */
 149 };
 150
 151 static void __iomem *reg_base;
 152 static enum exynos5x_soc exynos5x_soc;
 153
 154 #ifdef CONFIG_PM_SLEEP
 155 static struct samsung_clk_reg_dump *exynos5x_save;
 156 static struct samsung_clk_reg_dump *exynos5800_save;
 157
 158 /*
 159  * list of controller registers to be saved and restored during a
 160  * suspend/resume cycle.
 161  */
 162 static unsigned long exynos5x_clk_regs[] __initdata = {
 163         SRC_CPU,
 164         DIV_CPU0,
 165         DIV_CPU1,
 166         GATE_BUS_CPU,
 167         GATE_SCLK_CPU,
 168         CLKOUT_CMU_CPU,
 169         EPLL_CON0,
 170         EPLL_CON1,
 171         EPLL_CON2,
 172         RPLL_CON0,
 173         RPLL_CON1,
 174         RPLL_CON2,
 175         SRC_TOP0,
 176         SRC_TOP1,
 177         SRC_TOP2,
 178         SRC_TOP3,
 179         SRC_TOP4,
 180         SRC_TOP5,
 181         SRC_TOP6,
 182         SRC_TOP7,
 183         SRC_DISP10,
 184         SRC_MAU,
 185         SRC_FSYS,
 186         SRC_PERIC0,
 187         SRC_PERIC1,
 188         SRC_TOP10,
 189         SRC_TOP11,
 190         SRC_TOP12,
 191         SRC_MASK_TOP2,
 192         SRC_MASK_TOP7,
 193         SRC_MASK_DISP10,
 194         SRC_MASK_FSYS,
 195         SRC_MASK_PERIC0,
 196         SRC_MASK_PERIC1,
 197         SRC_MASK_TOP0,
 198         SRC_MASK_TOP1,
 199         SRC_MASK_MAU,
 200         SRC_MASK_ISP,
 201         SRC_ISP,
 202         DIV_TOP0,
 203         DIV_TOP1,
 204         DIV_TOP2,
 205         DIV_DISP10,
 206         DIV_MAU,
 207         DIV_FSYS0,
 208         DIV_FSYS1,
 209         DIV_FSYS2,
 210         DIV_PERIC0,
 211         DIV_PERIC1,
 212         DIV_PERIC2,
 213         DIV_PERIC3,
 214         DIV_PERIC4,
 215         SCLK_DIV_ISP0,
 216         SCLK_DIV_ISP1,
 217         DIV2_RATIO0,
 218         DIV4_RATIO,
 219         GATE_BUS_DISP1,
 220         GATE_BUS_TOP,
 221         GATE_BUS_GEN,
 222         GATE_BUS_FSYS0,
 223         GATE_BUS_FSYS2,
 224         GATE_BUS_PERIC,
 225         GATE_BUS_PERIC1,
 226         GATE_BUS_PERIS0,
 227         GATE_BUS_PERIS1,
 228         GATE_BUS_NOC,
 229         GATE_TOP_SCLK_ISP,
 230         GATE_IP_GSCL0,
 231         GATE_IP_GSCL1,
 232         GATE_IP_MFC,
 233         GATE_IP_DISP1,
 234         GATE_IP_G3D,
 235         GATE_IP_GEN,
 236         GATE_IP_FSYS,
 237         GATE_IP_PERIC,
 238         GATE_IP_PERIS,
 239         GATE_IP_MSCL,
 240         GATE_TOP_SCLK_GSCL,
 241         GATE_TOP_SCLK_DISP1,
 242         GATE_TOP_SCLK_MAU,
 243         GATE_TOP_SCLK_FSYS,
 244         GATE_TOP_SCLK_PERIC,
 245         TOP_SPARE2,
 246         SRC_KFC,
 247         DIV_KFC0,
 248 };
 249
 250 static unsigned long exynos5800_clk_regs[] __initdata = {
 251         SRC_TOP8,
 252         SRC_TOP9,
 253         SRC_CAM,
 254         SRC_TOP1,
 255         DIV_TOP8,
 256         DIV_TOP9,
 257         DIV_CAM,
 258         GATE_IP_CAM,
 259 };
 260
 261 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
 262         { .offset = SRC_MASK_CPERI,             .value = 0xffffffff, },
 263         { .offset = SRC_MASK_TOP0,              .value = 0x11111111, },
 264         { .offset = SRC_MASK_TOP1,              .value = 0x11101111, },
 265         { .offset = SRC_MASK_TOP2,              .value = 0x11111110, },
 266         { .offset = SRC_MASK_TOP7,              .value = 0x00111100, },
 267         { .offset = SRC_MASK_DISP10,            .value = 0x11111110, },
 268         { .offset = SRC_MASK_MAU,               .value = 0x10000000, },
 269         { .offset = SRC_MASK_FSYS,              .value = 0x11111110, },
 270         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
 271         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
 272         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
 273         { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
 274         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
 275         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
 276 };
 277
 278 static int exynos5420_clk_suspend(void)
 279 {
 280         samsung_clk_save(reg_base, exynos5x_save,
 281                                 ARRAY_SIZE(exynos5x_clk_regs));
 282
 283         if (exynos5x_soc == EXYNOS5800)
 284                 samsung_clk_save(reg_base, exynos5800_save,
 285                                 ARRAY_SIZE(exynos5800_clk_regs));
 286
 287         samsung_clk_restore(reg_base, exynos5420_set_clksrc,
 288                                 ARRAY_SIZE(exynos5420_set_clksrc));
 289
 290         return 0;
 291 }
 292
 293 static void exynos5420_clk_resume(void)
 294 {
 295         samsung_clk_restore(reg_base, exynos5x_save,
 296                                 ARRAY_SIZE(exynos5x_clk_regs));
 297
 298         if (exynos5x_soc == EXYNOS5800)
 299                 samsung_clk_restore(reg_base, exynos5800_save,
 300                                 ARRAY_SIZE(exynos5800_clk_regs));
 301 }
 302
 303 static struct syscore_ops exynos5420_clk_syscore_ops = {
 304         .suspend = exynos5420_clk_suspend,
 305         .resume = exynos5420_clk_resume,
 306 };
 307
 308 static void exynos5420_clk_sleep_init(void)
 309 {
 310         exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
 311                                         ARRAY_SIZE(exynos5x_clk_regs));
 312         if (!exynos5x_save) {
 313                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
 314                         __func__);
 315                 return;
 316         }
 317
 318         if (exynos5x_soc == EXYNOS5800) {
 319                 exynos5800_save =
 320                         samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
 321                                         ARRAY_SIZE(exynos5800_clk_regs));
 322                 if (!exynos5800_save)
 323                         goto err_soc;
 324         }
 325
 326         register_syscore_ops(&exynos5420_clk_syscore_ops);
 327         return;
 328 err_soc:
 329         kfree(exynos5x_save);
 330         pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
 331                 __func__);
 332         return;
 333 }
 334 #else
 335 static void exynos5420_clk_sleep_init(void) {}
 336 #endif
 337
 338 /* list of all parent clocks */
 339 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 340                                 "mout_sclk_mpll", "mout_sclk_spll"};
 341 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
 342 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
 343 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
 344 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
 345 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
 346 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
 347 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
 348 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
 349 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
 350 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
 351 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
 352 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
 353 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
 354
 355 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 356                                         "mout_sclk_mpll"};
 357 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
 358                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
 359                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
 360 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 361 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 362 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 363
 364 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
 365 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
 366 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
 367 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
 368
 369 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
 370 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
 371 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
 372 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
 373
 374 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 375 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 376 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
 377 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
 378
 379 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
 380 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
 381 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
 382
 383 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
 384 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
 385
 386 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
 387                                         "mout_sclk_spll"};
 388 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
 389
 390 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
 391 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
 392
 393 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 394 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 395
 396 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
 397 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
 398
 399 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
 400 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
 401
 402 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
 403 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 404
 405 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 406 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
 407 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 408
 409 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 410 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
 411
 412 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 413 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
 414
 415 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
 416 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
 417 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
 418 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
 419
 420 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 421 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
 422
 423 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
 424 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
 425
 426 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
 427 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
 428
 429 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
 430 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
 431
 432 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
 433                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 434                         "mout_sclk_epll", "mout_sclk_rpll"};
 435 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
 436                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 437                         "mout_sclk_epll", "mout_sclk_rpll"};
 438 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
 439                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 440                         "mout_sclk_epll", "mout_sclk_rpll"};
 441 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
 442                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
 443                         "mout_sclk_epll", "mout_sclk_rpll"};
 444 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 445 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 446                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 447                          "mout_sclk_epll", "mout_sclk_rpll"};
 448 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
 449                                 "mout_sclk_mpll", "mout_sclk_spll"};
 450 /* List of parents specific to exynos5800 */
 451 PNAME(mout_epll2_5800_p)        = { "mout_sclk_epll", "ff_dout_epll2" };
 452 PNAME(mout_group1_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 453                                 "mout_sclk_mpll", "ff_dout_spll2" };
 454 PNAME(mout_group2_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 455                                         "mout_sclk_mpll", "ff_dout_spll2",
 456                                         "mout_epll2", "mout_sclk_ipll" };
 457 PNAME(mout_group3_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 458                                         "mout_sclk_mpll", "ff_dout_spll2",
 459                                         "mout_epll2" };
 460 PNAME(mout_group5_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 461                                         "mout_sclk_mpll", "mout_sclk_spll" };
 462 PNAME(mout_group6_5800_p)       = { "mout_sclk_ipll", "mout_sclk_dpll",
 463                                 "mout_sclk_mpll", "ff_dout_spll2" };
 464 PNAME(mout_group7_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 465                                         "mout_sclk_mpll", "mout_sclk_spll",
 466                                         "mout_epll2", "mout_sclk_ipll" };
 467 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
 468                                         "mout_sclk_mpll",
 469                                         "ff_dout_spll2" };
 470 PNAME(mout_group8_5800_p)       = { "dout_aclk432_scaler", "dout_sclk_sw" };
 471 PNAME(mout_group9_5800_p)       = { "dout_osc_div", "mout_sw_aclk432_scaler" };
 472 PNAME(mout_group10_5800_p)      = { "dout_aclk432_cam", "dout_sclk_sw" };
 473 PNAME(mout_group11_5800_p)      = { "dout_osc_div", "mout_sw_aclk432_cam" };
 474 PNAME(mout_group12_5800_p)      = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
 475 PNAME(mout_group13_5800_p)      = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 476 PNAME(mout_group14_5800_p)      = { "dout_aclk550_cam", "dout_sclk_sw" };
 477 PNAME(mout_group15_5800_p)      = { "dout_osc_div", "mout_sw_aclk550_cam" };
 478
 479 /* fixed rate clocks generated outside the soc */
 480 static struct samsung_fixed_rate_clock
 481                 exynos5x_fixed_rate_ext_clks[] __initdata = {
 482         FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
 483 };
 484
 485 /* fixed rate clocks generated inside the soc */
 486 static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
 487         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 488         FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
 489         FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
 490         FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
 491         FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
 492 };
 493
 494 static struct samsung_fixed_factor_clock
 495                 exynos5x_fixed_factor_clks[] __initdata = {
 496         FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
 497         FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 498 };
 499
 500 static struct samsung_fixed_factor_clock
 501                 exynos5800_fixed_factor_clks[] __initdata = {
 502         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
 503         FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 504 };
 505
 506 static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
 507         MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
 508         MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
 509         MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
 510         MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
 511
 512         MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 513         MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
 514         MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
 515         MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
 516         MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
 517
 518         MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
 519         MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
 520         MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
 521         MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
 522         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 523         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 524
 525         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
 526                         20, 2),
 527         MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 528         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 529
 530         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
 531         MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
 532         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
 533         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
 534
 535         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
 536                                                         SRC_TOP9, 16, 1),
 537         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
 538                                                         SRC_TOP9, 20, 1),
 539         MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
 540                                                         SRC_TOP9, 24, 1),
 541         MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
 542                                                         SRC_TOP9, 28, 1),
 543
 544         MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
 545         MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
 546                                                         SRC_TOP13, 20, 1),
 547         MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
 548                                                         SRC_TOP13, 24, 1),
 549         MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
 550                                                         SRC_TOP13, 28, 1),
 551
 552         MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
 553 };
 554
 555 static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
 556         DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
 557
 558         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
 559                                 DIV_TOP8, 16, 3),
 560         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
 561                                 DIV_TOP8, 20, 3),
 562         DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
 563                                 DIV_TOP8, 24, 3),
 564         DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
 565                                 DIV_TOP8, 28, 3),
 566
 567         DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
 568         DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
 569 };
 570
 571 static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
 572         GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
 573                                 GATE_BUS_TOP, 24, 0, 0),
 574         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
 575                                 GATE_BUS_TOP, 27, 0, 0),
 576 };
 577
 578 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 579         MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
 580         MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
 581                                 TOP_SPARE2, 4, 1),
 582
 583         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 584         MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
 585                                 SRC_TOP0, 4, 2, "aclk400_mscl"),
 586         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 587         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 588
 589         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 590         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 591                                 SRC_TOP1, 4, 2),
 592         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
 593         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 594         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 595
 596         MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
 597         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
 598         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
 599         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 600         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 601         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 602
 603         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
 604
 605         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 606 };
 607
 608 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 609         DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
 610                         DIV_TOP0, 16, 3),
 611 };
 612
 613 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 614         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
 615                         SRC_TOP7, 4, 1),
 616         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 617         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 618
 619         MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
 620         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 621         MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
 622         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 623
 624         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 625         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 626         MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
 627         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 628
 629         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 630         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 631
 632         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
 633
 634         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
 635                         SRC_TOP3, 0, 1),
 636         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 637                         SRC_TOP3, 4, 1),
 638         MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
 639                         mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
 640         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 641                         SRC_TOP3, 12, 1),
 642         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
 643                         SRC_TOP3, 16, 1),
 644         MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
 645                         SRC_TOP3, 20, 1),
 646         MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
 647                         SRC_TOP3, 24, 1),
 648         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 649                         SRC_TOP3, 28, 1),
 650
 651         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
 652                         SRC_TOP4, 0, 1),
 653         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
 654                         SRC_TOP4, 4, 1),
 655         MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
 656                         SRC_TOP4, 8, 1),
 657         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 658                         SRC_TOP4, 12, 1),
 659         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
 660                         SRC_TOP4, 16, 1),
 661         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 662         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 663         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
 664                         SRC_TOP4, 28, 1),
 665
 666         MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
 667                         mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
 668         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
 669                         SRC_TOP5, 4, 1),
 670         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
 671                         SRC_TOP5, 8, 1),
 672         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
 673                         SRC_TOP5, 12, 1),
 674         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
 675                         SRC_TOP5, 16, 1),
 676         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 677                         SRC_TOP5, 20, 1),
 678         MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
 679                         mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
 680         MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
 681                         SRC_TOP5, 28, 1),
 682
 683         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 684         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
 685         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 686         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 687         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 688         MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
 689         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 690         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 691
 692         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 693                         SRC_TOP10, 0, 1),
 694         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 695                         SRC_TOP10, 4, 1),
 696         MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
 697                         SRC_TOP10, 8, 1),
 698         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 699                         SRC_TOP10, 12, 1),
 700         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
 701                         SRC_TOP10, 16, 1),
 702         MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 703                         SRC_TOP10, 20, 1),
 704         MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
 705                         SRC_TOP10, 24, 1),
 706         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 707                         SRC_TOP10, 28, 1),
 708
 709         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
 710                         SRC_TOP11, 0, 1),
 711         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
 712                         SRC_TOP11, 4, 1),
 713         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
 714         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
 715                         SRC_TOP11, 12, 1),
 716         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
 717         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
 718         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
 719                         SRC_TOP11, 28, 1),
 720
 721         MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
 722                         mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
 723         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 724                         SRC_TOP12, 8, 1),
 725         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
 726                         SRC_TOP12, 12, 1),
 727         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
 728         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 729                         SRC_TOP12, 20, 1),
 730         MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
 731                         mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
 732         MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
 733                         SRC_TOP12, 28, 1),
 734
 735         /* DISP1 Block */
 736         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
 737         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 738         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 739         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 740         MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
 741
 742         MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
 743
 744         /* MAU Block */
 745         MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 746
 747         /* FSYS Block */
 748         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
 749         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 750         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 751         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 752         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 753         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 754         MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 755
 756         /* PERIC Block */
 757         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
 758         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 759         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 760         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 761         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 762         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 763         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 764         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
 765         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
 766         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 767         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 768         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 769
 770         /* ISP Block */
 771         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
 772         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
 773         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
 774         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
 775         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 776 };
 777
 778 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
 779         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 780         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
 781         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
 782         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 783         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 784
 785         DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
 786         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
 787         DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
 788         DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
 789         DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
 790         DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
 791         DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
 792
 793         DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
 794                         DIV_TOP1, 0, 3),
 795         DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
 796                         DIV_TOP1, 4, 3),
 797         DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
 798         DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
 799                         DIV_TOP1, 16, 3),
 800         DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
 801         DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
 802         DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
 803
 804         DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
 805         DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
 806         DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
 807         DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
 808         DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
 809         DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
 810
 811         /* DISP1 Block */
 812         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
 813         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 814         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 815         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 816         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
 817         DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
 818
 819         /* Audio Block */
 820         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 821         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 822
 823         /* USB3.0 */
 824         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
 825         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
 826         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
 827         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
 828
 829         /* MMC */
 830         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 831         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
 832         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 833
 834         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
 835         DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 836
 837         /* UART and PWM */
 838         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
 839         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
 840         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
 841         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
 842         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
 843
 844         /* SPI */
 845         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
 846         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
 847         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 848
 849         /* Mfc Block */
 850         DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
 851
 852         /* PCM */
 853         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
 854         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
 855
 856         /* Audio - I2S */
 857         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
 858         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
 859         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
 860         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
 861         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 862
 863         /* SPI Pre-Ratio */
 864         DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
 865         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
 866         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
 867
 868         /* GSCL Block */
 869         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
 870                         DIV2_RATIO0, 4, 2),
 871         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 872
 873         /* MSCL Block */
 874         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
 875
 876         /* PSGEN */
 877         DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
 878         DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
 879
 880         /* ISP Block */
 881         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
 882         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
 883         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 884         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
 885         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
 886         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
 887         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
 888         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
 889                         CLK_SET_RATE_PARENT, 0),
 890         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
 891                         CLK_SET_RATE_PARENT, 0),
 892 };
 893
 894 static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
 895         /* G2D */
 896         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
 897         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 898         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
 899         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
 900         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 901
 902         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 903                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
 904         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
 905                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
 906
 907         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
 908                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
 909         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
 910                         GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
 911         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
 912                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
 913         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
 914                         GATE_BUS_TOP, 5, 0, 0),
 915         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
 916                         GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
 917         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
 918                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
 919         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
 920                         GATE_BUS_TOP, 8, 0, 0),
 921         GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
 922                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 923         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
 924                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 925         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
 926                         GATE_BUS_TOP, 13, 0, 0),
 927         GATE(0, "aclk166", "mout_user_aclk166",
 928                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
 929         GATE(0, "aclk333", "mout_aclk333",
 930                         GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
 931         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
 932                         GATE_BUS_TOP, 16, 0, 0),
 933         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
 934                         GATE_BUS_TOP, 17, 0, 0),
 935         GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
 936                         GATE_BUS_TOP, 18, 0, 0),
 937         GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
 938                         GATE_BUS_TOP, 28, 0, 0),
 939         GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
 940                         GATE_BUS_TOP, 29, 0, 0),
 941
 942         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
 943                         SRC_MASK_TOP2, 24, 0, 0),
 944
 945         GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
 946                         SRC_MASK_TOP7, 20, 0, 0),
 947
 948         /* sclk */
 949         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
 950                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 951         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
 952                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 953         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
 954                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 955         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 956                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 957         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
 958                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 959         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
 960                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 961         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
 962                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 963         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 964                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 965         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
 966                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 967         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
 968                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
 969         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
 970                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
 971         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
 972                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
 973         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
 974                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
 975
 976         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
 977                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 978         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
 979                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 980         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
 981                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 982         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
 983                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
 984         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
 985                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 986         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
 987                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 988         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
 989                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
 990
 991         /* Display */
 992         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
 993                         GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
 994         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
 995                         GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
 996         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
 997                         GATE_TOP_SCLK_DISP1, 9, 0, 0),
 998         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
 999                         GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1000         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1001                         GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1002
1003         /* Maudio Block */
1004         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1005                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1006         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1007                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1008
1009         /* FSYS Block */
1010         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1011         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1012         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1013         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1014         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1015         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1016         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1017         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1018         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1019                         GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1020         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1021         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1022         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1023         GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1024                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1025
1026         /* PERIC Block */
1027         GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1028                         GATE_IP_PERIC, 0, 0, 0),
1029         GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1030                         GATE_IP_PERIC, 1, 0, 0),
1031         GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1032                         GATE_IP_PERIC, 2, 0, 0),
1033         GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1034                         GATE_IP_PERIC, 3, 0, 0),
1035         GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1036                         GATE_IP_PERIC, 6, 0, 0),
1037         GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1038                         GATE_IP_PERIC, 7, 0, 0),
1039         GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1040                         GATE_IP_PERIC, 8, 0, 0),
1041         GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1042                         GATE_IP_PERIC, 9, 0, 0),
1043         GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1044                         GATE_IP_PERIC, 10, 0, 0),
1045         GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1046                         GATE_IP_PERIC, 11, 0, 0),
1047         GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1048                         GATE_IP_PERIC, 12, 0, 0),
1049         GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1050                         GATE_IP_PERIC, 13, 0, 0),
1051         GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1052                         GATE_IP_PERIC, 14, 0, 0),
1053         GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1054                         GATE_IP_PERIC, 15, 0, 0),
1055         GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1056                         GATE_IP_PERIC, 16, 0, 0),
1057         GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1058                         GATE_IP_PERIC, 17, 0, 0),
1059         GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1060                         GATE_IP_PERIC, 18, 0, 0),
1061         GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1062                         GATE_IP_PERIC, 20, 0, 0),
1063         GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1064                         GATE_IP_PERIC, 21, 0, 0),
1065         GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1066                         GATE_IP_PERIC, 22, 0, 0),
1067         GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1068                         GATE_IP_PERIC, 23, 0, 0),
1069         GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1070                         GATE_IP_PERIC, 24, 0, 0),
1071         GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1072                         GATE_IP_PERIC, 26, 0, 0),
1073         GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1074                         GATE_IP_PERIC, 28, 0, 0),
1075         GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1076                         GATE_IP_PERIC, 30, 0, 0),
1077         GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1078                         GATE_IP_PERIC, 31, 0, 0),
1079
1080         GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1081                         GATE_BUS_PERIC, 22, 0, 0),
1082
1083         /* PERIS Block */
1084         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1085                         GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1086         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1087                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1088         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1089         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1090         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1091         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1092         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1093         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1094         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1095         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1096         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1097         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1098         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1099         GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1100         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1101         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1102         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1103         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1104
1105         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
1106
1107         /* GEN Block */
1108         GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1109         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1110         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1111         GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1112         GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1113         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1114                         GATE_IP_GEN, 6, 0, 0),
1115         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1116         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1117                         GATE_IP_GEN, 9, 0, 0),
1118
1119         /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1120         GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1121                         GATE_BUS_GEN, 28, 0, 0),
1122         GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1123
1124         /* GSCL Block */
1125         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1126                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
1127         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1128                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
1129
1130         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1131         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1132         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1133                         GATE_IP_GSCL0, 4, 0, 0),
1134         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1135                         GATE_IP_GSCL0, 5, 0, 0),
1136         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1137                         GATE_IP_GSCL0, 6, 0, 0),
1138
1139         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1140                         GATE_IP_GSCL1, 2, 0, 0),
1141         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1142                         GATE_IP_GSCL1, 3, 0, 0),
1143         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1144                         GATE_IP_GSCL1, 4, 0, 0),
1145         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1146                         GATE_IP_GSCL1, 6, 0, 0),
1147         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1148                         GATE_IP_GSCL1, 7, 0, 0),
1149         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1150         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1151         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1152                         GATE_IP_GSCL1, 16, 0, 0),
1153         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1154                         GATE_IP_GSCL1, 17, 0, 0),
1155
1156         /* MSCL Block */
1157         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1158         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1159         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1160         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1161                         GATE_IP_MSCL, 8, 0, 0),
1162         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1163                         GATE_IP_MSCL, 9, 0, 0),
1164         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1165                         GATE_IP_MSCL, 10, 0, 0),
1166
1167         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1168         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1169         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1170         GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1171         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1172         GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1173                         GATE_IP_DISP1, 7, 0, 0),
1174         GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1175                         GATE_IP_DISP1, 8, 0, 0),
1176         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1177                         GATE_IP_DISP1, 9, 0, 0),
1178
1179         /* ISP */
1180         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1181                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1182         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1183                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1184         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1185                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1186         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1187                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1188         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1189                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1190         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1191                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1192         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1193                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1194
1195         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1196         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1197         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1198
1199         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1200 };
1201
1202 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
1203         PLL_35XX_RATE(2000000000, 250, 3, 0),
1204         PLL_35XX_RATE(1900000000, 475, 6, 0),
1205         PLL_35XX_RATE(1800000000, 225, 3, 0),
1206         PLL_35XX_RATE(1700000000, 425, 6, 0),
1207         PLL_35XX_RATE(1600000000, 200, 3, 0),
1208         PLL_35XX_RATE(1500000000, 250, 4, 0),
1209         PLL_35XX_RATE(1400000000, 175, 3, 0),
1210         PLL_35XX_RATE(1300000000, 325, 6, 0),
1211         PLL_35XX_RATE(1200000000, 200, 2, 1),
1212         PLL_35XX_RATE(1100000000, 275, 3, 1),
1213         PLL_35XX_RATE(1000000000, 250, 3, 1),
1214         PLL_35XX_RATE(900000000,  150, 2, 1),
1215         PLL_35XX_RATE(800000000,  200, 3, 1),
1216         PLL_35XX_RATE(700000000,  175, 3, 1),
1217         PLL_35XX_RATE(600000000,  200, 2, 2),
1218         PLL_35XX_RATE(500000000,  250, 3, 2),
1219         PLL_35XX_RATE(400000000,  200, 3, 2),
1220         PLL_35XX_RATE(300000000,  200, 2, 3),
1221         PLL_35XX_RATE(200000000,  200, 3, 3),
1222 };
1223
1224 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1225         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1226                 APLL_CON0, NULL),
1227         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1228                 CPLL_CON0, NULL),
1229         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1230                 DPLL_CON0, NULL),
1231         [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1232                 EPLL_CON0, NULL),
1233         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1234                 RPLL_CON0, NULL),
1235         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1236                 IPLL_CON0, NULL),
1237         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1238                 SPLL_CON0, NULL),
1239         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1240                 VPLL_CON0, NULL),
1241         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1242                 MPLL_CON0, NULL),
1243         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1244                 BPLL_CON0, NULL),
1245         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1246                 KPLL_CON0, NULL),
1247 };
1248
1249 static const struct of_device_id ext_clk_match[] __initconst = {
1250         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1251         { },
1252 };
1253
1254 /* register exynos5420 clocks */
1255 static void __init exynos5x_clk_init(struct device_node *np,
1256                 enum exynos5x_soc soc)
1257 {
1258         struct samsung_clk_provider *ctx;
1259
1260         if (np) {
1261                 reg_base = of_iomap(np, 0);
1262                 if (!reg_base)
1263                         panic("%s: failed to map registers\n", __func__);
1264         } else {
1265                 panic("%s: unable to determine soc\n", __func__);
1266         }
1267
1268         exynos5x_soc = soc;
1269
1270         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1271         if (!ctx)
1272                 panic("%s: unable to allocate context.\n", __func__);
1273
1274         samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1275                         ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1276                         ext_clk_match);
1277
1278         if (_get_rate("fin_pll") == 24 * MHZ) {
1279                 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1280                 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1281         }
1282
1283         samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1284                                         reg_base);
1285         samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1286                         ARRAY_SIZE(exynos5x_fixed_rate_clks));
1287         samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1288                         ARRAY_SIZE(exynos5x_fixed_factor_clks));
1289         samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1290                         ARRAY_SIZE(exynos5x_mux_clks));
1291         samsung_clk_register_div(ctx, exynos5x_div_clks,
1292                         ARRAY_SIZE(exynos5x_div_clks));
1293         samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1294                         ARRAY_SIZE(exynos5x_gate_clks));
1295
1296         if (soc == EXYNOS5420) {
1297                 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1298                                 ARRAY_SIZE(exynos5420_mux_clks));
1299                 samsung_clk_register_div(ctx, exynos5420_div_clks,
1300                                 ARRAY_SIZE(exynos5420_div_clks));
1301         } else {
1302                 samsung_clk_register_fixed_factor(
1303                                 ctx, exynos5800_fixed_factor_clks,
1304                                 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1305                 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1306                                 ARRAY_SIZE(exynos5800_mux_clks));
1307                 samsung_clk_register_div(ctx, exynos5800_div_clks,
1308                                 ARRAY_SIZE(exynos5800_div_clks));
1309                 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1310                                 ARRAY_SIZE(exynos5800_gate_clks));
1311         }
1312
1313         exynos5420_clk_sleep_init();
1314
1315         samsung_clk_of_add_provider(np, ctx);
1316 }
1317
1318 static void __init exynos5420_clk_init(struct device_node *np)
1319 {
1320         exynos5x_clk_init(np, EXYNOS5420);
1321 }
1322 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1323
1324 static void __init exynos5800_clk_init(struct device_node *np)
1325 {
1326         exynos5x_clk_init(np, EXYNOS5800);
1327 }
1328 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);