kernel/drivers/clk/rockchip/clk.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * based on
   6  *
   7  * samsung/clk.c
   8  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   9  * Copyright (c) 2013 Linaro Ltd.
  10  * Author: Thomas Abraham <thomas.ab@samsung.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/regmap.h>
  28 #include <linux/reboot.h>
  29 #include "clk.h"
  30
  31 /**
  32  * Register a clock branch.
  33  * Most clock branches have a form like
  34  *
  35  * src1 --|--\
  36  *        |M |--[GATE]-[DIV]-
  37  * src2 --|--/
  38  *
  39  * sometimes without one of those components.
  40  */
  41 static struct clk *rockchip_clk_register_branch(const char *name,
  42                 const char *const *parent_names, u8 num_parents, void __iomem *base,
  43                 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
  44                 u8 div_shift, u8 div_width, u8 div_flags,
  45                 struct clk_div_table *div_table, int gate_offset,
  46                 u8 gate_shift, u8 gate_flags, unsigned long flags,
  47                 spinlock_t *lock)
  48 {
  49         struct clk *clk;
  50         struct clk_mux *mux = NULL;
  51         struct clk_gate *gate = NULL;
  52         struct clk_divider *div = NULL;
  53         const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
  54                              *gate_ops = NULL;
  55
  56         if (num_parents > 1) {
  57                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  58                 if (!mux)
  59                         return ERR_PTR(-ENOMEM);
  60
  61                 mux->reg = base + muxdiv_offset;
  62                 mux->shift = mux_shift;
  63                 mux->mask = BIT(mux_width) - 1;
  64                 mux->flags = mux_flags;
  65                 mux->lock = lock;
  66                 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
  67                                                         : &clk_mux_ops;
  68         }
  69
  70         if (gate_offset >= 0) {
  71                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  72                 if (!gate)
  73                         goto err_gate;
  74
  75                 gate->flags = gate_flags;
  76                 gate->reg = base + gate_offset;
  77                 gate->bit_idx = gate_shift;
  78                 gate->lock = lock;
  79                 gate_ops = &clk_gate_ops;
  80         }
  81
  82         if (div_width > 0) {
  83                 div = kzalloc(sizeof(*div), GFP_KERNEL);
  84                 if (!div)
  85                         goto err_div;
  86
  87                 div->flags = div_flags;
  88                 div->reg = base + muxdiv_offset;
  89                 div->shift = div_shift;
  90                 div->width = div_width;
  91                 div->lock = lock;
  92                 div->table = div_table;
  93                 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
  94                                                 ? &clk_divider_ro_ops
  95                                                 : &clk_divider_ops;
  96         }
  97
  98         clk = clk_register_composite(NULL, name, parent_names, num_parents,
  99                                      mux ? &mux->hw : NULL, mux_ops,
 100                                      div ? &div->hw : NULL, div_ops,
 101                                      gate ? &gate->hw : NULL, gate_ops,
 102                                      flags);
 103
 104         return clk;
 105 err_div:
 106         kfree(gate);
 107 err_gate:
 108         kfree(mux);
 109         return ERR_PTR(-ENOMEM);
 110 }
 111
 112 static struct clk *rockchip_clk_register_frac_branch(const char *name,
 113                 const char *const *parent_names, u8 num_parents,
 114                 void __iomem *base, int muxdiv_offset, u8 div_flags,
 115                 int gate_offset, u8 gate_shift, u8 gate_flags,
 116                 unsigned long flags, spinlock_t *lock)
 117 {
 118         struct clk *clk;
 119         struct clk_gate *gate = NULL;
 120         struct clk_fractional_divider *div = NULL;
 121         const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
 122
 123         if (gate_offset >= 0) {
 124                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 125                 if (!gate)
 126                         return ERR_PTR(-ENOMEM);
 127
 128                 gate->flags = gate_flags;
 129                 gate->reg = base + gate_offset;
 130                 gate->bit_idx = gate_shift;
 131                 gate->lock = lock;
 132                 gate_ops = &clk_gate_ops;
 133         }
 134
 135         if (muxdiv_offset < 0)
 136                 return ERR_PTR(-EINVAL);
 137
 138         div = kzalloc(sizeof(*div), GFP_KERNEL);
 139         if (!div)
 140                 return ERR_PTR(-ENOMEM);
 141
 142         div->flags = div_flags;
 143         div->reg = base + muxdiv_offset;
 144         div->mshift = 16;
 145         div->mwidth = 16;
 146         div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
 147         div->nshift = 0;
 148         div->nwidth = 16;
 149         div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 150         div->lock = lock;
 151         div_ops = &clk_fractional_divider_ops;
 152
 153         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 154                                      NULL, NULL,
 155                                      &div->hw, div_ops,
 156                                      gate ? &gate->hw : NULL, gate_ops,
 157                                      flags);
 158
 159         return clk;
 160 }
 161
 162 static DEFINE_SPINLOCK(clk_lock);
 163 static struct clk **clk_table;
 164 static void __iomem *reg_base;
 165 static struct clk_onecell_data clk_data;
 166 static struct device_node *cru_node;
 167 static struct regmap *grf;
 168
 169 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
 170                               unsigned long nr_clks)
 171 {
 172         reg_base = base;
 173         cru_node = np;
 174         grf = ERR_PTR(-EPROBE_DEFER);
 175
 176         clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
 177         if (!clk_table)
 178                 pr_err("%s: could not allocate clock lookup table\n", __func__);
 179
 180         clk_data.clks = clk_table;
 181         clk_data.clk_num = nr_clks;
 182         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 183 }
 184
 185 struct regmap *rockchip_clk_get_grf(void)
 186 {
 187         if (IS_ERR(grf))
 188                 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
 189         return grf;
 190 }
 191
 192 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
 193 {
 194         if (clk_table && id)
 195                 clk_table[id] = clk;
 196 }
 197
 198 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
 199                                 unsigned int nr_pll, int grf_lock_offset)
 200 {
 201         struct clk *clk;
 202         int idx;
 203
 204         for (idx = 0; idx < nr_pll; idx++, list++) {
 205                 clk = rockchip_clk_register_pll(list->type, list->name,
 206                                 list->parent_names, list->num_parents,
 207                                 reg_base, list->con_offset, grf_lock_offset,
 208                                 list->lock_shift, list->mode_offset,
 209                                 list->mode_shift, list->rate_table,
 210                                 list->pll_flags, &clk_lock);
 211                 if (IS_ERR(clk)) {
 212                         pr_err("%s: failed to register clock %s\n", __func__,
 213                                 list->name);
 214                         continue;
 215                 }
 216
 217                 rockchip_clk_add_lookup(clk, list->id);
 218         }
 219 }
 220
 221 void __init rockchip_clk_register_branches(
 222                                       struct rockchip_clk_branch *list,
 223                                       unsigned int nr_clk)
 224 {
 225         struct clk *clk = NULL;
 226         unsigned int idx;
 227         unsigned long flags;
 228
 229         for (idx = 0; idx < nr_clk; idx++, list++) {
 230                 flags = list->flags;
 231
 232                 /* catch simple muxes */
 233                 switch (list->branch_type) {
 234                 case branch_mux:
 235                         clk = clk_register_mux(NULL, list->name,
 236                                 list->parent_names, list->num_parents,
 237                                 flags, reg_base + list->muxdiv_offset,
 238                                 list->mux_shift, list->mux_width,
 239                                 list->mux_flags, &clk_lock);
 240                         break;
 241                 case branch_divider:
 242                         if (list->div_table)
 243                                 clk = clk_register_divider_table(NULL,
 244                                         list->name, list->parent_names[0],
 245                                         flags, reg_base + list->muxdiv_offset,
 246                                         list->div_shift, list->div_width,
 247                                         list->div_flags, list->div_table,
 248                                         &clk_lock);
 249                         else
 250                                 clk = clk_register_divider(NULL, list->name,
 251                                         list->parent_names[0], flags,
 252                                         reg_base + list->muxdiv_offset,
 253                                         list->div_shift, list->div_width,
 254                                         list->div_flags, &clk_lock);
 255                         break;
 256                 case branch_fraction_divider:
 257                         clk = rockchip_clk_register_frac_branch(list->name,
 258                                 list->parent_names, list->num_parents,
 259                                 reg_base, list->muxdiv_offset, list->div_flags,
 260                                 list->gate_offset, list->gate_shift,
 261                                 list->gate_flags, flags, &clk_lock);
 262                         break;
 263                 case branch_gate:
 264                         flags |= CLK_SET_RATE_PARENT;
 265
 266                         clk = clk_register_gate(NULL, list->name,
 267                                 list->parent_names[0], flags,
 268                                 reg_base + list->gate_offset,
 269                                 list->gate_shift, list->gate_flags, &clk_lock);
 270                         break;
 271                 case branch_composite:
 272                         clk = rockchip_clk_register_branch(list->name,
 273                                 list->parent_names, list->num_parents,
 274                                 reg_base, list->muxdiv_offset, list->mux_shift,
 275                                 list->mux_width, list->mux_flags,
 276                                 list->div_shift, list->div_width,
 277                                 list->div_flags, list->div_table,
 278                                 list->gate_offset, list->gate_shift,
 279                                 list->gate_flags, flags, &clk_lock);
 280                         break;
 281                 case branch_mmc:
 282                         clk = rockchip_clk_register_mmc(
 283                                 list->name,
 284                                 list->parent_names, list->num_parents,
 285                                 reg_base + list->muxdiv_offset,
 286                                 list->div_shift
 287                         );
 288                         break;
 289                 case branch_inverter:
 290                         clk = rockchip_clk_register_inverter(
 291                                 list->name, list->parent_names,
 292                                 list->num_parents,
 293                                 reg_base + list->muxdiv_offset,
 294                                 list->div_shift, list->div_flags, &clk_lock);
 295                         break;
 296                 }
 297
 298                 /* none of the cases above matched */
 299                 if (!clk) {
 300                         pr_err("%s: unknown clock type %d\n",
 301                                __func__, list->branch_type);
 302                         continue;
 303                 }
 304
 305                 if (IS_ERR(clk)) {
 306                         pr_err("%s: failed to register clock %s: %ld\n",
 307                                __func__, list->name, PTR_ERR(clk));
 308                         continue;
 309                 }
 310
 311                 rockchip_clk_add_lookup(clk, list->id);
 312         }
 313 }
 314
 315 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
 316                         const char *name, const char *const *parent_names,
 317                         u8 num_parents,
 318                         const struct rockchip_cpuclk_reg_data *reg_data,
 319                         const struct rockchip_cpuclk_rate_table *rates,
 320                         int nrates)
 321 {
 322         struct clk *clk;
 323
 324         clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
 325                                            reg_data, rates, nrates, reg_base,
 326                                            &clk_lock);
 327         if (IS_ERR(clk)) {
 328                 pr_err("%s: failed to register clock %s: %ld\n",
 329                        __func__, name, PTR_ERR(clk));
 330                 return;
 331         }
 332
 333         rockchip_clk_add_lookup(clk, lookup_id);
 334 }
 335
 336 void __init rockchip_clk_protect_critical(const char *const clocks[],
 337                                           int nclocks)
 338 {
 339         int i;
 340
 341         /* Protect the clocks that needs to stay on */
 342         for (i = 0; i < nclocks; i++) {
 343                 struct clk *clk = __clk_lookup(clocks[i]);
 344
 345                 if (clk)
 346                         clk_prepare_enable(clk);
 347         }
 348 }
 349
 350 static unsigned int reg_restart;
 351 static int rockchip_restart_notify(struct notifier_block *this,
 352                                    unsigned long mode, void *cmd)
 353 {
 354         writel(0xfdb9, reg_base + reg_restart);
 355         return NOTIFY_DONE;
 356 }
 357
 358 static struct notifier_block rockchip_restart_handler = {
 359         .notifier_call = rockchip_restart_notify,
 360         .priority = 128,
 361 };
 362
 363 void __init rockchip_register_restart_notifier(unsigned int reg)
 364 {
 365         int ret;
 366
 367         reg_restart = reg;
 368         ret = register_restart_handler(&rockchip_restart_handler);
 369         if (ret)
 370                 pr_err("%s: cannot register restart handler, %d\n",
 371                        __func__, ret);
 372 }