kernel/drivers/clk/qcom/gcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll3 = {
  36         .l_reg = 0x3164,
  37         .m_reg = 0x3168,
  38         .n_reg = 0x316c,
  39         .config_reg = 0x3174,
  40         .mode_reg = 0x3160,
  41         .status_reg = 0x3178,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll3",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll4_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(4),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll4_vote",
  56                 .parent_names = (const char *[]){ "pll4" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll8 = {
  63         .l_reg = 0x3144,
  64         .m_reg = 0x3148,
  65         .n_reg = 0x314c,
  66         .config_reg = 0x3154,
  67         .mode_reg = 0x3140,
  68         .status_reg = 0x3158,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll8",
  72                 .parent_names = (const char *[]){ "pxo" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_ops,
  75         },
  76 };
  77
  78 static struct clk_regmap pll8_vote = {
  79         .enable_reg = 0x34c0,
  80         .enable_mask = BIT(8),
  81         .hw.init = &(struct clk_init_data){
  82                 .name = "pll8_vote",
  83                 .parent_names = (const char *[]){ "pll8" },
  84                 .num_parents = 1,
  85                 .ops = &clk_pll_vote_ops,
  86         },
  87 };
  88
  89 static struct clk_pll pll14 = {
  90         .l_reg = 0x31c4,
  91         .m_reg = 0x31c8,
  92         .n_reg = 0x31cc,
  93         .config_reg = 0x31d4,
  94         .mode_reg = 0x31c0,
  95         .status_reg = 0x31d8,
  96         .status_bit = 16,
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "pll14",
  99                 .parent_names = (const char *[]){ "pxo" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_ops,
 102         },
 103 };
 104
 105 static struct clk_regmap pll14_vote = {
 106         .enable_reg = 0x34c0,
 107         .enable_mask = BIT(14),
 108         .hw.init = &(struct clk_init_data){
 109                 .name = "pll14_vote",
 110                 .parent_names = (const char *[]){ "pll14" },
 111                 .num_parents = 1,
 112                 .ops = &clk_pll_vote_ops,
 113         },
 114 };
 115
 116 enum {
 117         P_PXO,
 118         P_PLL8,
 119         P_PLL3,
 120         P_CXO,
 121 };
 122
 123 static const struct parent_map gcc_pxo_pll8_map[] = {
 124         { P_PXO, 0 },
 125         { P_PLL8, 3 }
 126 };
 127
 128 static const char *gcc_pxo_pll8[] = {
 129         "pxo",
 130         "pll8_vote",
 131 };
 132
 133 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 134         { P_PXO, 0 },
 135         { P_PLL8, 3 },
 136         { P_CXO, 5 }
 137 };
 138
 139 static const char *gcc_pxo_pll8_cxo[] = {
 140         "pxo",
 141         "pll8_vote",
 142         "cxo",
 143 };
 144
 145 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
 146         { P_PXO, 0 },
 147         { P_PLL8, 3 },
 148         { P_PLL3, 6 }
 149 };
 150
 151 static const char *gcc_pxo_pll8_pll3[] = {
 152         "pxo",
 153         "pll8_vote",
 154         "pll3",
 155 };
 156
 157 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 158         {  1843200, P_PLL8, 2,  6, 625 },
 159         {  3686400, P_PLL8, 2, 12, 625 },
 160         {  7372800, P_PLL8, 2, 24, 625 },
 161         { 14745600, P_PLL8, 2, 48, 625 },
 162         { 16000000, P_PLL8, 4,  1,   6 },
 163         { 24000000, P_PLL8, 4,  1,   4 },
 164         { 32000000, P_PLL8, 4,  1,   3 },
 165         { 40000000, P_PLL8, 1,  5,  48 },
 166         { 46400000, P_PLL8, 1, 29, 240 },
 167         { 48000000, P_PLL8, 4,  1,   2 },
 168         { 51200000, P_PLL8, 1,  2,  15 },
 169         { 56000000, P_PLL8, 1,  7,  48 },
 170         { 58982400, P_PLL8, 1, 96, 625 },
 171         { 64000000, P_PLL8, 2,  1,   3 },
 172         { }
 173 };
 174
 175 static struct clk_rcg gsbi1_uart_src = {
 176         .ns_reg = 0x29d4,
 177         .md_reg = 0x29d0,
 178         .mn = {
 179                 .mnctr_en_bit = 8,
 180                 .mnctr_reset_bit = 7,
 181                 .mnctr_mode_shift = 5,
 182                 .n_val_shift = 16,
 183                 .m_val_shift = 16,
 184                 .width = 16,
 185         },
 186         .p = {
 187                 .pre_div_shift = 3,
 188                 .pre_div_width = 2,
 189         },
 190         .s = {
 191                 .src_sel_shift = 0,
 192                 .parent_map = gcc_pxo_pll8_map,
 193         },
 194         .freq_tbl = clk_tbl_gsbi_uart,
 195         .clkr = {
 196                 .enable_reg = 0x29d4,
 197                 .enable_mask = BIT(11),
 198                 .hw.init = &(struct clk_init_data){
 199                         .name = "gsbi1_uart_src",
 200                         .parent_names = gcc_pxo_pll8,
 201                         .num_parents = 2,
 202                         .ops = &clk_rcg_ops,
 203                         .flags = CLK_SET_PARENT_GATE,
 204                 },
 205         },
 206 };
 207
 208 static struct clk_branch gsbi1_uart_clk = {
 209         .halt_reg = 0x2fcc,
 210         .halt_bit = 10,
 211         .clkr = {
 212                 .enable_reg = 0x29d4,
 213                 .enable_mask = BIT(9),
 214                 .hw.init = &(struct clk_init_data){
 215                         .name = "gsbi1_uart_clk",
 216                         .parent_names = (const char *[]){
 217                                 "gsbi1_uart_src",
 218                         },
 219                         .num_parents = 1,
 220                         .ops = &clk_branch_ops,
 221                         .flags = CLK_SET_RATE_PARENT,
 222                 },
 223         },
 224 };
 225
 226 static struct clk_rcg gsbi2_uart_src = {
 227         .ns_reg = 0x29f4,
 228         .md_reg = 0x29f0,
 229         .mn = {
 230                 .mnctr_en_bit = 8,
 231                 .mnctr_reset_bit = 7,
 232                 .mnctr_mode_shift = 5,
 233                 .n_val_shift = 16,
 234                 .m_val_shift = 16,
 235                 .width = 16,
 236         },
 237         .p = {
 238                 .pre_div_shift = 3,
 239                 .pre_div_width = 2,
 240         },
 241         .s = {
 242                 .src_sel_shift = 0,
 243                 .parent_map = gcc_pxo_pll8_map,
 244         },
 245         .freq_tbl = clk_tbl_gsbi_uart,
 246         .clkr = {
 247                 .enable_reg = 0x29f4,
 248                 .enable_mask = BIT(11),
 249                 .hw.init = &(struct clk_init_data){
 250                         .name = "gsbi2_uart_src",
 251                         .parent_names = gcc_pxo_pll8,
 252                         .num_parents = 2,
 253                         .ops = &clk_rcg_ops,
 254                         .flags = CLK_SET_PARENT_GATE,
 255                 },
 256         },
 257 };
 258
 259 static struct clk_branch gsbi2_uart_clk = {
 260         .halt_reg = 0x2fcc,
 261         .halt_bit = 6,
 262         .clkr = {
 263                 .enable_reg = 0x29f4,
 264                 .enable_mask = BIT(9),
 265                 .hw.init = &(struct clk_init_data){
 266                         .name = "gsbi2_uart_clk",
 267                         .parent_names = (const char *[]){
 268                                 "gsbi2_uart_src",
 269                         },
 270                         .num_parents = 1,
 271                         .ops = &clk_branch_ops,
 272                         .flags = CLK_SET_RATE_PARENT,
 273                 },
 274         },
 275 };
 276
 277 static struct clk_rcg gsbi3_uart_src = {
 278         .ns_reg = 0x2a14,
 279         .md_reg = 0x2a10,
 280         .mn = {
 281                 .mnctr_en_bit = 8,
 282                 .mnctr_reset_bit = 7,
 283                 .mnctr_mode_shift = 5,
 284                 .n_val_shift = 16,
 285                 .m_val_shift = 16,
 286                 .width = 16,
 287         },
 288         .p = {
 289                 .pre_div_shift = 3,
 290                 .pre_div_width = 2,
 291         },
 292         .s = {
 293                 .src_sel_shift = 0,
 294                 .parent_map = gcc_pxo_pll8_map,
 295         },
 296         .freq_tbl = clk_tbl_gsbi_uart,
 297         .clkr = {
 298                 .enable_reg = 0x2a14,
 299                 .enable_mask = BIT(11),
 300                 .hw.init = &(struct clk_init_data){
 301                         .name = "gsbi3_uart_src",
 302                         .parent_names = gcc_pxo_pll8,
 303                         .num_parents = 2,
 304                         .ops = &clk_rcg_ops,
 305                         .flags = CLK_SET_PARENT_GATE,
 306                 },
 307         },
 308 };
 309
 310 static struct clk_branch gsbi3_uart_clk = {
 311         .halt_reg = 0x2fcc,
 312         .halt_bit = 2,
 313         .clkr = {
 314                 .enable_reg = 0x2a14,
 315                 .enable_mask = BIT(9),
 316                 .hw.init = &(struct clk_init_data){
 317                         .name = "gsbi3_uart_clk",
 318                         .parent_names = (const char *[]){
 319                                 "gsbi3_uart_src",
 320                         },
 321                         .num_parents = 1,
 322                         .ops = &clk_branch_ops,
 323                         .flags = CLK_SET_RATE_PARENT,
 324                 },
 325         },
 326 };
 327
 328 static struct clk_rcg gsbi4_uart_src = {
 329         .ns_reg = 0x2a34,
 330         .md_reg = 0x2a30,
 331         .mn = {
 332                 .mnctr_en_bit = 8,
 333                 .mnctr_reset_bit = 7,
 334                 .mnctr_mode_shift = 5,
 335                 .n_val_shift = 16,
 336                 .m_val_shift = 16,
 337                 .width = 16,
 338         },
 339         .p = {
 340                 .pre_div_shift = 3,
 341                 .pre_div_width = 2,
 342         },
 343         .s = {
 344                 .src_sel_shift = 0,
 345                 .parent_map = gcc_pxo_pll8_map,
 346         },
 347         .freq_tbl = clk_tbl_gsbi_uart,
 348         .clkr = {
 349                 .enable_reg = 0x2a34,
 350                 .enable_mask = BIT(11),
 351                 .hw.init = &(struct clk_init_data){
 352                         .name = "gsbi4_uart_src",
 353                         .parent_names = gcc_pxo_pll8,
 354                         .num_parents = 2,
 355                         .ops = &clk_rcg_ops,
 356                         .flags = CLK_SET_PARENT_GATE,
 357                 },
 358         },
 359 };
 360
 361 static struct clk_branch gsbi4_uart_clk = {
 362         .halt_reg = 0x2fd0,
 363         .halt_bit = 26,
 364         .clkr = {
 365                 .enable_reg = 0x2a34,
 366                 .enable_mask = BIT(9),
 367                 .hw.init = &(struct clk_init_data){
 368                         .name = "gsbi4_uart_clk",
 369                         .parent_names = (const char *[]){
 370                                 "gsbi4_uart_src",
 371                         },
 372                         .num_parents = 1,
 373                         .ops = &clk_branch_ops,
 374                         .flags = CLK_SET_RATE_PARENT,
 375                 },
 376         },
 377 };
 378
 379 static struct clk_rcg gsbi5_uart_src = {
 380         .ns_reg = 0x2a54,
 381         .md_reg = 0x2a50,
 382         .mn = {
 383                 .mnctr_en_bit = 8,
 384                 .mnctr_reset_bit = 7,
 385                 .mnctr_mode_shift = 5,
 386                 .n_val_shift = 16,
 387                 .m_val_shift = 16,
 388                 .width = 16,
 389         },
 390         .p = {
 391                 .pre_div_shift = 3,
 392                 .pre_div_width = 2,
 393         },
 394         .s = {
 395                 .src_sel_shift = 0,
 396                 .parent_map = gcc_pxo_pll8_map,
 397         },
 398         .freq_tbl = clk_tbl_gsbi_uart,
 399         .clkr = {
 400                 .enable_reg = 0x2a54,
 401                 .enable_mask = BIT(11),
 402                 .hw.init = &(struct clk_init_data){
 403                         .name = "gsbi5_uart_src",
 404                         .parent_names = gcc_pxo_pll8,
 405                         .num_parents = 2,
 406                         .ops = &clk_rcg_ops,
 407                         .flags = CLK_SET_PARENT_GATE,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_branch gsbi5_uart_clk = {
 413         .halt_reg = 0x2fd0,
 414         .halt_bit = 22,
 415         .clkr = {
 416                 .enable_reg = 0x2a54,
 417                 .enable_mask = BIT(9),
 418                 .hw.init = &(struct clk_init_data){
 419                         .name = "gsbi5_uart_clk",
 420                         .parent_names = (const char *[]){
 421                                 "gsbi5_uart_src",
 422                         },
 423                         .num_parents = 1,
 424                         .ops = &clk_branch_ops,
 425                         .flags = CLK_SET_RATE_PARENT,
 426                 },
 427         },
 428 };
 429
 430 static struct clk_rcg gsbi6_uart_src = {
 431         .ns_reg = 0x2a74,
 432         .md_reg = 0x2a70,
 433         .mn = {
 434                 .mnctr_en_bit = 8,
 435                 .mnctr_reset_bit = 7,
 436                 .mnctr_mode_shift = 5,
 437                 .n_val_shift = 16,
 438                 .m_val_shift = 16,
 439                 .width = 16,
 440         },
 441         .p = {
 442                 .pre_div_shift = 3,
 443                 .pre_div_width = 2,
 444         },
 445         .s = {
 446                 .src_sel_shift = 0,
 447                 .parent_map = gcc_pxo_pll8_map,
 448         },
 449         .freq_tbl = clk_tbl_gsbi_uart,
 450         .clkr = {
 451                 .enable_reg = 0x2a74,
 452                 .enable_mask = BIT(11),
 453                 .hw.init = &(struct clk_init_data){
 454                         .name = "gsbi6_uart_src",
 455                         .parent_names = gcc_pxo_pll8,
 456                         .num_parents = 2,
 457                         .ops = &clk_rcg_ops,
 458                         .flags = CLK_SET_PARENT_GATE,
 459                 },
 460         },
 461 };
 462
 463 static struct clk_branch gsbi6_uart_clk = {
 464         .halt_reg = 0x2fd0,
 465         .halt_bit = 18,
 466         .clkr = {
 467                 .enable_reg = 0x2a74,
 468                 .enable_mask = BIT(9),
 469                 .hw.init = &(struct clk_init_data){
 470                         .name = "gsbi6_uart_clk",
 471                         .parent_names = (const char *[]){
 472                                 "gsbi6_uart_src",
 473                         },
 474                         .num_parents = 1,
 475                         .ops = &clk_branch_ops,
 476                         .flags = CLK_SET_RATE_PARENT,
 477                 },
 478         },
 479 };
 480
 481 static struct clk_rcg gsbi7_uart_src = {
 482         .ns_reg = 0x2a94,
 483         .md_reg = 0x2a90,
 484         .mn = {
 485                 .mnctr_en_bit = 8,
 486                 .mnctr_reset_bit = 7,
 487                 .mnctr_mode_shift = 5,
 488                 .n_val_shift = 16,
 489                 .m_val_shift = 16,
 490                 .width = 16,
 491         },
 492         .p = {
 493                 .pre_div_shift = 3,
 494                 .pre_div_width = 2,
 495         },
 496         .s = {
 497                 .src_sel_shift = 0,
 498                 .parent_map = gcc_pxo_pll8_map,
 499         },
 500         .freq_tbl = clk_tbl_gsbi_uart,
 501         .clkr = {
 502                 .enable_reg = 0x2a94,
 503                 .enable_mask = BIT(11),
 504                 .hw.init = &(struct clk_init_data){
 505                         .name = "gsbi7_uart_src",
 506                         .parent_names = gcc_pxo_pll8,
 507                         .num_parents = 2,
 508                         .ops = &clk_rcg_ops,
 509                         .flags = CLK_SET_PARENT_GATE,
 510                 },
 511         },
 512 };
 513
 514 static struct clk_branch gsbi7_uart_clk = {
 515         .halt_reg = 0x2fd0,
 516         .halt_bit = 14,
 517         .clkr = {
 518                 .enable_reg = 0x2a94,
 519                 .enable_mask = BIT(9),
 520                 .hw.init = &(struct clk_init_data){
 521                         .name = "gsbi7_uart_clk",
 522                         .parent_names = (const char *[]){
 523                                 "gsbi7_uart_src",
 524                         },
 525                         .num_parents = 1,
 526                         .ops = &clk_branch_ops,
 527                         .flags = CLK_SET_RATE_PARENT,
 528                 },
 529         },
 530 };
 531
 532 static struct clk_rcg gsbi8_uart_src = {
 533         .ns_reg = 0x2ab4,
 534         .md_reg = 0x2ab0,
 535         .mn = {
 536                 .mnctr_en_bit = 8,
 537                 .mnctr_reset_bit = 7,
 538                 .mnctr_mode_shift = 5,
 539                 .n_val_shift = 16,
 540                 .m_val_shift = 16,
 541                 .width = 16,
 542         },
 543         .p = {
 544                 .pre_div_shift = 3,
 545                 .pre_div_width = 2,
 546         },
 547         .s = {
 548                 .src_sel_shift = 0,
 549                 .parent_map = gcc_pxo_pll8_map,
 550         },
 551         .freq_tbl = clk_tbl_gsbi_uart,
 552         .clkr = {
 553                 .enable_reg = 0x2ab4,
 554                 .enable_mask = BIT(11),
 555                 .hw.init = &(struct clk_init_data){
 556                         .name = "gsbi8_uart_src",
 557                         .parent_names = gcc_pxo_pll8,
 558                         .num_parents = 2,
 559                         .ops = &clk_rcg_ops,
 560                         .flags = CLK_SET_PARENT_GATE,
 561                 },
 562         },
 563 };
 564
 565 static struct clk_branch gsbi8_uart_clk = {
 566         .halt_reg = 0x2fd0,
 567         .halt_bit = 10,
 568         .clkr = {
 569                 .enable_reg = 0x2ab4,
 570                 .enable_mask = BIT(9),
 571                 .hw.init = &(struct clk_init_data){
 572                         .name = "gsbi8_uart_clk",
 573                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 574                         .num_parents = 1,
 575                         .ops = &clk_branch_ops,
 576                         .flags = CLK_SET_RATE_PARENT,
 577                 },
 578         },
 579 };
 580
 581 static struct clk_rcg gsbi9_uart_src = {
 582         .ns_reg = 0x2ad4,
 583         .md_reg = 0x2ad0,
 584         .mn = {
 585                 .mnctr_en_bit = 8,
 586                 .mnctr_reset_bit = 7,
 587                 .mnctr_mode_shift = 5,
 588                 .n_val_shift = 16,
 589                 .m_val_shift = 16,
 590                 .width = 16,
 591         },
 592         .p = {
 593                 .pre_div_shift = 3,
 594                 .pre_div_width = 2,
 595         },
 596         .s = {
 597                 .src_sel_shift = 0,
 598                 .parent_map = gcc_pxo_pll8_map,
 599         },
 600         .freq_tbl = clk_tbl_gsbi_uart,
 601         .clkr = {
 602                 .enable_reg = 0x2ad4,
 603                 .enable_mask = BIT(11),
 604                 .hw.init = &(struct clk_init_data){
 605                         .name = "gsbi9_uart_src",
 606                         .parent_names = gcc_pxo_pll8,
 607                         .num_parents = 2,
 608                         .ops = &clk_rcg_ops,
 609                         .flags = CLK_SET_PARENT_GATE,
 610                 },
 611         },
 612 };
 613
 614 static struct clk_branch gsbi9_uart_clk = {
 615         .halt_reg = 0x2fd0,
 616         .halt_bit = 6,
 617         .clkr = {
 618                 .enable_reg = 0x2ad4,
 619                 .enable_mask = BIT(9),
 620                 .hw.init = &(struct clk_init_data){
 621                         .name = "gsbi9_uart_clk",
 622                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 623                         .num_parents = 1,
 624                         .ops = &clk_branch_ops,
 625                         .flags = CLK_SET_RATE_PARENT,
 626                 },
 627         },
 628 };
 629
 630 static struct clk_rcg gsbi10_uart_src = {
 631         .ns_reg = 0x2af4,
 632         .md_reg = 0x2af0,
 633         .mn = {
 634                 .mnctr_en_bit = 8,
 635                 .mnctr_reset_bit = 7,
 636                 .mnctr_mode_shift = 5,
 637                 .n_val_shift = 16,
 638                 .m_val_shift = 16,
 639                 .width = 16,
 640         },
 641         .p = {
 642                 .pre_div_shift = 3,
 643                 .pre_div_width = 2,
 644         },
 645         .s = {
 646                 .src_sel_shift = 0,
 647                 .parent_map = gcc_pxo_pll8_map,
 648         },
 649         .freq_tbl = clk_tbl_gsbi_uart,
 650         .clkr = {
 651                 .enable_reg = 0x2af4,
 652                 .enable_mask = BIT(11),
 653                 .hw.init = &(struct clk_init_data){
 654                         .name = "gsbi10_uart_src",
 655                         .parent_names = gcc_pxo_pll8,
 656                         .num_parents = 2,
 657                         .ops = &clk_rcg_ops,
 658                         .flags = CLK_SET_PARENT_GATE,
 659                 },
 660         },
 661 };
 662
 663 static struct clk_branch gsbi10_uart_clk = {
 664         .halt_reg = 0x2fd0,
 665         .halt_bit = 2,
 666         .clkr = {
 667                 .enable_reg = 0x2af4,
 668                 .enable_mask = BIT(9),
 669                 .hw.init = &(struct clk_init_data){
 670                         .name = "gsbi10_uart_clk",
 671                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 672                         .num_parents = 1,
 673                         .ops = &clk_branch_ops,
 674                         .flags = CLK_SET_RATE_PARENT,
 675                 },
 676         },
 677 };
 678
 679 static struct clk_rcg gsbi11_uart_src = {
 680         .ns_reg = 0x2b14,
 681         .md_reg = 0x2b10,
 682         .mn = {
 683                 .mnctr_en_bit = 8,
 684                 .mnctr_reset_bit = 7,
 685                 .mnctr_mode_shift = 5,
 686                 .n_val_shift = 16,
 687                 .m_val_shift = 16,
 688                 .width = 16,
 689         },
 690         .p = {
 691                 .pre_div_shift = 3,
 692                 .pre_div_width = 2,
 693         },
 694         .s = {
 695                 .src_sel_shift = 0,
 696                 .parent_map = gcc_pxo_pll8_map,
 697         },
 698         .freq_tbl = clk_tbl_gsbi_uart,
 699         .clkr = {
 700                 .enable_reg = 0x2b14,
 701                 .enable_mask = BIT(11),
 702                 .hw.init = &(struct clk_init_data){
 703                         .name = "gsbi11_uart_src",
 704                         .parent_names = gcc_pxo_pll8,
 705                         .num_parents = 2,
 706                         .ops = &clk_rcg_ops,
 707                         .flags = CLK_SET_PARENT_GATE,
 708                 },
 709         },
 710 };
 711
 712 static struct clk_branch gsbi11_uart_clk = {
 713         .halt_reg = 0x2fd4,
 714         .halt_bit = 17,
 715         .clkr = {
 716                 .enable_reg = 0x2b14,
 717                 .enable_mask = BIT(9),
 718                 .hw.init = &(struct clk_init_data){
 719                         .name = "gsbi11_uart_clk",
 720                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 721                         .num_parents = 1,
 722                         .ops = &clk_branch_ops,
 723                         .flags = CLK_SET_RATE_PARENT,
 724                 },
 725         },
 726 };
 727
 728 static struct clk_rcg gsbi12_uart_src = {
 729         .ns_reg = 0x2b34,
 730         .md_reg = 0x2b30,
 731         .mn = {
 732                 .mnctr_en_bit = 8,
 733                 .mnctr_reset_bit = 7,
 734                 .mnctr_mode_shift = 5,
 735                 .n_val_shift = 16,
 736                 .m_val_shift = 16,
 737                 .width = 16,
 738         },
 739         .p = {
 740                 .pre_div_shift = 3,
 741                 .pre_div_width = 2,
 742         },
 743         .s = {
 744                 .src_sel_shift = 0,
 745                 .parent_map = gcc_pxo_pll8_map,
 746         },
 747         .freq_tbl = clk_tbl_gsbi_uart,
 748         .clkr = {
 749                 .enable_reg = 0x2b34,
 750                 .enable_mask = BIT(11),
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "gsbi12_uart_src",
 753                         .parent_names = gcc_pxo_pll8,
 754                         .num_parents = 2,
 755                         .ops = &clk_rcg_ops,
 756                         .flags = CLK_SET_PARENT_GATE,
 757                 },
 758         },
 759 };
 760
 761 static struct clk_branch gsbi12_uart_clk = {
 762         .halt_reg = 0x2fd4,
 763         .halt_bit = 13,
 764         .clkr = {
 765                 .enable_reg = 0x2b34,
 766                 .enable_mask = BIT(9),
 767                 .hw.init = &(struct clk_init_data){
 768                         .name = "gsbi12_uart_clk",
 769                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 770                         .num_parents = 1,
 771                         .ops = &clk_branch_ops,
 772                         .flags = CLK_SET_RATE_PARENT,
 773                 },
 774         },
 775 };
 776
 777 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 778         {  1100000, P_PXO,  1, 2, 49 },
 779         {  5400000, P_PXO,  1, 1,  5 },
 780         { 10800000, P_PXO,  1, 2,  5 },
 781         { 15060000, P_PLL8, 1, 2, 51 },
 782         { 24000000, P_PLL8, 4, 1,  4 },
 783         { 25600000, P_PLL8, 1, 1, 15 },
 784         { 27000000, P_PXO,  1, 0,  0 },
 785         { 48000000, P_PLL8, 4, 1,  2 },
 786         { 51200000, P_PLL8, 1, 2, 15 },
 787         { }
 788 };
 789
 790 static struct clk_rcg gsbi1_qup_src = {
 791         .ns_reg = 0x29cc,
 792         .md_reg = 0x29c8,
 793         .mn = {
 794                 .mnctr_en_bit = 8,
 795                 .mnctr_reset_bit = 7,
 796                 .mnctr_mode_shift = 5,
 797                 .n_val_shift = 16,
 798                 .m_val_shift = 16,
 799                 .width = 8,
 800         },
 801         .p = {
 802                 .pre_div_shift = 3,
 803                 .pre_div_width = 2,
 804         },
 805         .s = {
 806                 .src_sel_shift = 0,
 807                 .parent_map = gcc_pxo_pll8_map,
 808         },
 809         .freq_tbl = clk_tbl_gsbi_qup,
 810         .clkr = {
 811                 .enable_reg = 0x29cc,
 812                 .enable_mask = BIT(11),
 813                 .hw.init = &(struct clk_init_data){
 814                         .name = "gsbi1_qup_src",
 815                         .parent_names = gcc_pxo_pll8,
 816                         .num_parents = 2,
 817                         .ops = &clk_rcg_ops,
 818                         .flags = CLK_SET_PARENT_GATE,
 819                 },
 820         },
 821 };
 822
 823 static struct clk_branch gsbi1_qup_clk = {
 824         .halt_reg = 0x2fcc,
 825         .halt_bit = 9,
 826         .clkr = {
 827                 .enable_reg = 0x29cc,
 828                 .enable_mask = BIT(9),
 829                 .hw.init = &(struct clk_init_data){
 830                         .name = "gsbi1_qup_clk",
 831                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 832                         .num_parents = 1,
 833                         .ops = &clk_branch_ops,
 834                         .flags = CLK_SET_RATE_PARENT,
 835                 },
 836         },
 837 };
 838
 839 static struct clk_rcg gsbi2_qup_src = {
 840         .ns_reg = 0x29ec,
 841         .md_reg = 0x29e8,
 842         .mn = {
 843                 .mnctr_en_bit = 8,
 844                 .mnctr_reset_bit = 7,
 845                 .mnctr_mode_shift = 5,
 846                 .n_val_shift = 16,
 847                 .m_val_shift = 16,
 848                 .width = 8,
 849         },
 850         .p = {
 851                 .pre_div_shift = 3,
 852                 .pre_div_width = 2,
 853         },
 854         .s = {
 855                 .src_sel_shift = 0,
 856                 .parent_map = gcc_pxo_pll8_map,
 857         },
 858         .freq_tbl = clk_tbl_gsbi_qup,
 859         .clkr = {
 860                 .enable_reg = 0x29ec,
 861                 .enable_mask = BIT(11),
 862                 .hw.init = &(struct clk_init_data){
 863                         .name = "gsbi2_qup_src",
 864                         .parent_names = gcc_pxo_pll8,
 865                         .num_parents = 2,
 866                         .ops = &clk_rcg_ops,
 867                         .flags = CLK_SET_PARENT_GATE,
 868                 },
 869         },
 870 };
 871
 872 static struct clk_branch gsbi2_qup_clk = {
 873         .halt_reg = 0x2fcc,
 874         .halt_bit = 4,
 875         .clkr = {
 876                 .enable_reg = 0x29ec,
 877                 .enable_mask = BIT(9),
 878                 .hw.init = &(struct clk_init_data){
 879                         .name = "gsbi2_qup_clk",
 880                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 881                         .num_parents = 1,
 882                         .ops = &clk_branch_ops,
 883                         .flags = CLK_SET_RATE_PARENT,
 884                 },
 885         },
 886 };
 887
 888 static struct clk_rcg gsbi3_qup_src = {
 889         .ns_reg = 0x2a0c,
 890         .md_reg = 0x2a08,
 891         .mn = {
 892                 .mnctr_en_bit = 8,
 893                 .mnctr_reset_bit = 7,
 894                 .mnctr_mode_shift = 5,
 895                 .n_val_shift = 16,
 896                 .m_val_shift = 16,
 897                 .width = 8,
 898         },
 899         .p = {
 900                 .pre_div_shift = 3,
 901                 .pre_div_width = 2,
 902         },
 903         .s = {
 904                 .src_sel_shift = 0,
 905                 .parent_map = gcc_pxo_pll8_map,
 906         },
 907         .freq_tbl = clk_tbl_gsbi_qup,
 908         .clkr = {
 909                 .enable_reg = 0x2a0c,
 910                 .enable_mask = BIT(11),
 911                 .hw.init = &(struct clk_init_data){
 912                         .name = "gsbi3_qup_src",
 913                         .parent_names = gcc_pxo_pll8,
 914                         .num_parents = 2,
 915                         .ops = &clk_rcg_ops,
 916                         .flags = CLK_SET_PARENT_GATE,
 917                 },
 918         },
 919 };
 920
 921 static struct clk_branch gsbi3_qup_clk = {
 922         .halt_reg = 0x2fcc,
 923         .halt_bit = 0,
 924         .clkr = {
 925                 .enable_reg = 0x2a0c,
 926                 .enable_mask = BIT(9),
 927                 .hw.init = &(struct clk_init_data){
 928                         .name = "gsbi3_qup_clk",
 929                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 930                         .num_parents = 1,
 931                         .ops = &clk_branch_ops,
 932                         .flags = CLK_SET_RATE_PARENT,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_rcg gsbi4_qup_src = {
 938         .ns_reg = 0x2a2c,
 939         .md_reg = 0x2a28,
 940         .mn = {
 941                 .mnctr_en_bit = 8,
 942                 .mnctr_reset_bit = 7,
 943                 .mnctr_mode_shift = 5,
 944                 .n_val_shift = 16,
 945                 .m_val_shift = 16,
 946                 .width = 8,
 947         },
 948         .p = {
 949                 .pre_div_shift = 3,
 950                 .pre_div_width = 2,
 951         },
 952         .s = {
 953                 .src_sel_shift = 0,
 954                 .parent_map = gcc_pxo_pll8_map,
 955         },
 956         .freq_tbl = clk_tbl_gsbi_qup,
 957         .clkr = {
 958                 .enable_reg = 0x2a2c,
 959                 .enable_mask = BIT(11),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "gsbi4_qup_src",
 962                         .parent_names = gcc_pxo_pll8,
 963                         .num_parents = 2,
 964                         .ops = &clk_rcg_ops,
 965                         .flags = CLK_SET_PARENT_GATE,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_branch gsbi4_qup_clk = {
 971         .halt_reg = 0x2fd0,
 972         .halt_bit = 24,
 973         .clkr = {
 974                 .enable_reg = 0x2a2c,
 975                 .enable_mask = BIT(9),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "gsbi4_qup_clk",
 978                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 979                         .num_parents = 1,
 980                         .ops = &clk_branch_ops,
 981                         .flags = CLK_SET_RATE_PARENT,
 982                 },
 983         },
 984 };
 985
 986 static struct clk_rcg gsbi5_qup_src = {
 987         .ns_reg = 0x2a4c,
 988         .md_reg = 0x2a48,
 989         .mn = {
 990                 .mnctr_en_bit = 8,
 991                 .mnctr_reset_bit = 7,
 992                 .mnctr_mode_shift = 5,
 993                 .n_val_shift = 16,
 994                 .m_val_shift = 16,
 995                 .width = 8,
 996         },
 997         .p = {
 998                 .pre_div_shift = 3,
 999                 .pre_div_width = 2,
1000         },
1001         .s = {
1002                 .src_sel_shift = 0,
1003                 .parent_map = gcc_pxo_pll8_map,
1004         },
1005         .freq_tbl = clk_tbl_gsbi_qup,
1006         .clkr = {
1007                 .enable_reg = 0x2a4c,
1008                 .enable_mask = BIT(11),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "gsbi5_qup_src",
1011                         .parent_names = gcc_pxo_pll8,
1012                         .num_parents = 2,
1013                         .ops = &clk_rcg_ops,
1014                         .flags = CLK_SET_PARENT_GATE,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch gsbi5_qup_clk = {
1020         .halt_reg = 0x2fd0,
1021         .halt_bit = 20,
1022         .clkr = {
1023                 .enable_reg = 0x2a4c,
1024                 .enable_mask = BIT(9),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "gsbi5_qup_clk",
1027                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
1028                         .num_parents = 1,
1029                         .ops = &clk_branch_ops,
1030                         .flags = CLK_SET_RATE_PARENT,
1031                 },
1032         },
1033 };
1034
1035 static struct clk_rcg gsbi6_qup_src = {
1036         .ns_reg = 0x2a6c,
1037         .md_reg = 0x2a68,
1038         .mn = {
1039                 .mnctr_en_bit = 8,
1040                 .mnctr_reset_bit = 7,
1041                 .mnctr_mode_shift = 5,
1042                 .n_val_shift = 16,
1043                 .m_val_shift = 16,
1044                 .width = 8,
1045         },
1046         .p = {
1047                 .pre_div_shift = 3,
1048                 .pre_div_width = 2,
1049         },
1050         .s = {
1051                 .src_sel_shift = 0,
1052                 .parent_map = gcc_pxo_pll8_map,
1053         },
1054         .freq_tbl = clk_tbl_gsbi_qup,
1055         .clkr = {
1056                 .enable_reg = 0x2a6c,
1057                 .enable_mask = BIT(11),
1058                 .hw.init = &(struct clk_init_data){
1059                         .name = "gsbi6_qup_src",
1060                         .parent_names = gcc_pxo_pll8,
1061                         .num_parents = 2,
1062                         .ops = &clk_rcg_ops,
1063                         .flags = CLK_SET_PARENT_GATE,
1064                 },
1065         },
1066 };
1067
1068 static struct clk_branch gsbi6_qup_clk = {
1069         .halt_reg = 0x2fd0,
1070         .halt_bit = 16,
1071         .clkr = {
1072                 .enable_reg = 0x2a6c,
1073                 .enable_mask = BIT(9),
1074                 .hw.init = &(struct clk_init_data){
1075                         .name = "gsbi6_qup_clk",
1076                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1077                         .num_parents = 1,
1078                         .ops = &clk_branch_ops,
1079                         .flags = CLK_SET_RATE_PARENT,
1080                 },
1081         },
1082 };
1083
1084 static struct clk_rcg gsbi7_qup_src = {
1085         .ns_reg = 0x2a8c,
1086         .md_reg = 0x2a88,
1087         .mn = {
1088                 .mnctr_en_bit = 8,
1089                 .mnctr_reset_bit = 7,
1090                 .mnctr_mode_shift = 5,
1091                 .n_val_shift = 16,
1092                 .m_val_shift = 16,
1093                 .width = 8,
1094         },
1095         .p = {
1096                 .pre_div_shift = 3,
1097                 .pre_div_width = 2,
1098         },
1099         .s = {
1100                 .src_sel_shift = 0,
1101                 .parent_map = gcc_pxo_pll8_map,
1102         },
1103         .freq_tbl = clk_tbl_gsbi_qup,
1104         .clkr = {
1105                 .enable_reg = 0x2a8c,
1106                 .enable_mask = BIT(11),
1107                 .hw.init = &(struct clk_init_data){
1108                         .name = "gsbi7_qup_src",
1109                         .parent_names = gcc_pxo_pll8,
1110                         .num_parents = 2,
1111                         .ops = &clk_rcg_ops,
1112                         .flags = CLK_SET_PARENT_GATE,
1113                 },
1114         },
1115 };
1116
1117 static struct clk_branch gsbi7_qup_clk = {
1118         .halt_reg = 0x2fd0,
1119         .halt_bit = 12,
1120         .clkr = {
1121                 .enable_reg = 0x2a8c,
1122                 .enable_mask = BIT(9),
1123                 .hw.init = &(struct clk_init_data){
1124                         .name = "gsbi7_qup_clk",
1125                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1126                         .num_parents = 1,
1127                         .ops = &clk_branch_ops,
1128                         .flags = CLK_SET_RATE_PARENT,
1129                 },
1130         },
1131 };
1132
1133 static struct clk_rcg gsbi8_qup_src = {
1134         .ns_reg = 0x2aac,
1135         .md_reg = 0x2aa8,
1136         .mn = {
1137                 .mnctr_en_bit = 8,
1138                 .mnctr_reset_bit = 7,
1139                 .mnctr_mode_shift = 5,
1140                 .n_val_shift = 16,
1141                 .m_val_shift = 16,
1142                 .width = 8,
1143         },
1144         .p = {
1145                 .pre_div_shift = 3,
1146                 .pre_div_width = 2,
1147         },
1148         .s = {
1149                 .src_sel_shift = 0,
1150                 .parent_map = gcc_pxo_pll8_map,
1151         },
1152         .freq_tbl = clk_tbl_gsbi_qup,
1153         .clkr = {
1154                 .enable_reg = 0x2aac,
1155                 .enable_mask = BIT(11),
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "gsbi8_qup_src",
1158                         .parent_names = gcc_pxo_pll8,
1159                         .num_parents = 2,
1160                         .ops = &clk_rcg_ops,
1161                         .flags = CLK_SET_PARENT_GATE,
1162                 },
1163         },
1164 };
1165
1166 static struct clk_branch gsbi8_qup_clk = {
1167         .halt_reg = 0x2fd0,
1168         .halt_bit = 8,
1169         .clkr = {
1170                 .enable_reg = 0x2aac,
1171                 .enable_mask = BIT(9),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "gsbi8_qup_clk",
1174                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1175                         .num_parents = 1,
1176                         .ops = &clk_branch_ops,
1177                         .flags = CLK_SET_RATE_PARENT,
1178                 },
1179         },
1180 };
1181
1182 static struct clk_rcg gsbi9_qup_src = {
1183         .ns_reg = 0x2acc,
1184         .md_reg = 0x2ac8,
1185         .mn = {
1186                 .mnctr_en_bit = 8,
1187                 .mnctr_reset_bit = 7,
1188                 .mnctr_mode_shift = 5,
1189                 .n_val_shift = 16,
1190                 .m_val_shift = 16,
1191                 .width = 8,
1192         },
1193         .p = {
1194                 .pre_div_shift = 3,
1195                 .pre_div_width = 2,
1196         },
1197         .s = {
1198                 .src_sel_shift = 0,
1199                 .parent_map = gcc_pxo_pll8_map,
1200         },
1201         .freq_tbl = clk_tbl_gsbi_qup,
1202         .clkr = {
1203                 .enable_reg = 0x2acc,
1204                 .enable_mask = BIT(11),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "gsbi9_qup_src",
1207                         .parent_names = gcc_pxo_pll8,
1208                         .num_parents = 2,
1209                         .ops = &clk_rcg_ops,
1210                         .flags = CLK_SET_PARENT_GATE,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gsbi9_qup_clk = {
1216         .halt_reg = 0x2fd0,
1217         .halt_bit = 4,
1218         .clkr = {
1219                 .enable_reg = 0x2acc,
1220                 .enable_mask = BIT(9),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gsbi9_qup_clk",
1223                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1224                         .num_parents = 1,
1225                         .ops = &clk_branch_ops,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                 },
1228         },
1229 };
1230
1231 static struct clk_rcg gsbi10_qup_src = {
1232         .ns_reg = 0x2aec,
1233         .md_reg = 0x2ae8,
1234         .mn = {
1235                 .mnctr_en_bit = 8,
1236                 .mnctr_reset_bit = 7,
1237                 .mnctr_mode_shift = 5,
1238                 .n_val_shift = 16,
1239                 .m_val_shift = 16,
1240                 .width = 8,
1241         },
1242         .p = {
1243                 .pre_div_shift = 3,
1244                 .pre_div_width = 2,
1245         },
1246         .s = {
1247                 .src_sel_shift = 0,
1248                 .parent_map = gcc_pxo_pll8_map,
1249         },
1250         .freq_tbl = clk_tbl_gsbi_qup,
1251         .clkr = {
1252                 .enable_reg = 0x2aec,
1253                 .enable_mask = BIT(11),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gsbi10_qup_src",
1256                         .parent_names = gcc_pxo_pll8,
1257                         .num_parents = 2,
1258                         .ops = &clk_rcg_ops,
1259                         .flags = CLK_SET_PARENT_GATE,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gsbi10_qup_clk = {
1265         .halt_reg = 0x2fd0,
1266         .halt_bit = 0,
1267         .clkr = {
1268                 .enable_reg = 0x2aec,
1269                 .enable_mask = BIT(9),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gsbi10_qup_clk",
1272                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1273                         .num_parents = 1,
1274                         .ops = &clk_branch_ops,
1275                         .flags = CLK_SET_RATE_PARENT,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_rcg gsbi11_qup_src = {
1281         .ns_reg = 0x2b0c,
1282         .md_reg = 0x2b08,
1283         .mn = {
1284                 .mnctr_en_bit = 8,
1285                 .mnctr_reset_bit = 7,
1286                 .mnctr_mode_shift = 5,
1287                 .n_val_shift = 16,
1288                 .m_val_shift = 16,
1289                 .width = 8,
1290         },
1291         .p = {
1292                 .pre_div_shift = 3,
1293                 .pre_div_width = 2,
1294         },
1295         .s = {
1296                 .src_sel_shift = 0,
1297                 .parent_map = gcc_pxo_pll8_map,
1298         },
1299         .freq_tbl = clk_tbl_gsbi_qup,
1300         .clkr = {
1301                 .enable_reg = 0x2b0c,
1302                 .enable_mask = BIT(11),
1303                 .hw.init = &(struct clk_init_data){
1304                         .name = "gsbi11_qup_src",
1305                         .parent_names = gcc_pxo_pll8,
1306                         .num_parents = 2,
1307                         .ops = &clk_rcg_ops,
1308                         .flags = CLK_SET_PARENT_GATE,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch gsbi11_qup_clk = {
1314         .halt_reg = 0x2fd4,
1315         .halt_bit = 15,
1316         .clkr = {
1317                 .enable_reg = 0x2b0c,
1318                 .enable_mask = BIT(9),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gsbi11_qup_clk",
1321                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1322                         .num_parents = 1,
1323                         .ops = &clk_branch_ops,
1324                         .flags = CLK_SET_RATE_PARENT,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_rcg gsbi12_qup_src = {
1330         .ns_reg = 0x2b2c,
1331         .md_reg = 0x2b28,
1332         .mn = {
1333                 .mnctr_en_bit = 8,
1334                 .mnctr_reset_bit = 7,
1335                 .mnctr_mode_shift = 5,
1336                 .n_val_shift = 16,
1337                 .m_val_shift = 16,
1338                 .width = 8,
1339         },
1340         .p = {
1341                 .pre_div_shift = 3,
1342                 .pre_div_width = 2,
1343         },
1344         .s = {
1345                 .src_sel_shift = 0,
1346                 .parent_map = gcc_pxo_pll8_map,
1347         },
1348         .freq_tbl = clk_tbl_gsbi_qup,
1349         .clkr = {
1350                 .enable_reg = 0x2b2c,
1351                 .enable_mask = BIT(11),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "gsbi12_qup_src",
1354                         .parent_names = gcc_pxo_pll8,
1355                         .num_parents = 2,
1356                         .ops = &clk_rcg_ops,
1357                         .flags = CLK_SET_PARENT_GATE,
1358                 },
1359         },
1360 };
1361
1362 static struct clk_branch gsbi12_qup_clk = {
1363         .halt_reg = 0x2fd4,
1364         .halt_bit = 11,
1365         .clkr = {
1366                 .enable_reg = 0x2b2c,
1367                 .enable_mask = BIT(9),
1368                 .hw.init = &(struct clk_init_data){
1369                         .name = "gsbi12_qup_clk",
1370                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1371                         .num_parents = 1,
1372                         .ops = &clk_branch_ops,
1373                         .flags = CLK_SET_RATE_PARENT,
1374                 },
1375         },
1376 };
1377
1378 static const struct freq_tbl clk_tbl_gp[] = {
1379         { 9600000, P_CXO,  2, 0, 0 },
1380         { 13500000, P_PXO,  2, 0, 0 },
1381         { 19200000, P_CXO,  1, 0, 0 },
1382         { 27000000, P_PXO,  1, 0, 0 },
1383         { 64000000, P_PLL8, 2, 1, 3 },
1384         { 76800000, P_PLL8, 1, 1, 5 },
1385         { 96000000, P_PLL8, 4, 0, 0 },
1386         { 128000000, P_PLL8, 3, 0, 0 },
1387         { 192000000, P_PLL8, 2, 0, 0 },
1388         { }
1389 };
1390
1391 static struct clk_rcg gp0_src = {
1392         .ns_reg = 0x2d24,
1393         .md_reg = 0x2d00,
1394         .mn = {
1395                 .mnctr_en_bit = 8,
1396                 .mnctr_reset_bit = 7,
1397                 .mnctr_mode_shift = 5,
1398                 .n_val_shift = 16,
1399                 .m_val_shift = 16,
1400                 .width = 8,
1401         },
1402         .p = {
1403                 .pre_div_shift = 3,
1404                 .pre_div_width = 2,
1405         },
1406         .s = {
1407                 .src_sel_shift = 0,
1408                 .parent_map = gcc_pxo_pll8_cxo_map,
1409         },
1410         .freq_tbl = clk_tbl_gp,
1411         .clkr = {
1412                 .enable_reg = 0x2d24,
1413                 .enable_mask = BIT(11),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gp0_src",
1416                         .parent_names = gcc_pxo_pll8_cxo,
1417                         .num_parents = 3,
1418                         .ops = &clk_rcg_ops,
1419                         .flags = CLK_SET_PARENT_GATE,
1420                 },
1421         }
1422 };
1423
1424 static struct clk_branch gp0_clk = {
1425         .halt_reg = 0x2fd8,
1426         .halt_bit = 7,
1427         .clkr = {
1428                 .enable_reg = 0x2d24,
1429                 .enable_mask = BIT(9),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gp0_clk",
1432                         .parent_names = (const char *[]){ "gp0_src" },
1433                         .num_parents = 1,
1434                         .ops = &clk_branch_ops,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                 },
1437         },
1438 };
1439
1440 static struct clk_rcg gp1_src = {
1441         .ns_reg = 0x2d44,
1442         .md_reg = 0x2d40,
1443         .mn = {
1444                 .mnctr_en_bit = 8,
1445                 .mnctr_reset_bit = 7,
1446                 .mnctr_mode_shift = 5,
1447                 .n_val_shift = 16,
1448                 .m_val_shift = 16,
1449                 .width = 8,
1450         },
1451         .p = {
1452                 .pre_div_shift = 3,
1453                 .pre_div_width = 2,
1454         },
1455         .s = {
1456                 .src_sel_shift = 0,
1457                 .parent_map = gcc_pxo_pll8_cxo_map,
1458         },
1459         .freq_tbl = clk_tbl_gp,
1460         .clkr = {
1461                 .enable_reg = 0x2d44,
1462                 .enable_mask = BIT(11),
1463                 .hw.init = &(struct clk_init_data){
1464                         .name = "gp1_src",
1465                         .parent_names = gcc_pxo_pll8_cxo,
1466                         .num_parents = 3,
1467                         .ops = &clk_rcg_ops,
1468                         .flags = CLK_SET_RATE_GATE,
1469                 },
1470         }
1471 };
1472
1473 static struct clk_branch gp1_clk = {
1474         .halt_reg = 0x2fd8,
1475         .halt_bit = 6,
1476         .clkr = {
1477                 .enable_reg = 0x2d44,
1478                 .enable_mask = BIT(9),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gp1_clk",
1481                         .parent_names = (const char *[]){ "gp1_src" },
1482                         .num_parents = 1,
1483                         .ops = &clk_branch_ops,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_rcg gp2_src = {
1490         .ns_reg = 0x2d64,
1491         .md_reg = 0x2d60,
1492         .mn = {
1493                 .mnctr_en_bit = 8,
1494                 .mnctr_reset_bit = 7,
1495                 .mnctr_mode_shift = 5,
1496                 .n_val_shift = 16,
1497                 .m_val_shift = 16,
1498                 .width = 8,
1499         },
1500         .p = {
1501                 .pre_div_shift = 3,
1502                 .pre_div_width = 2,
1503         },
1504         .s = {
1505                 .src_sel_shift = 0,
1506                 .parent_map = gcc_pxo_pll8_cxo_map,
1507         },
1508         .freq_tbl = clk_tbl_gp,
1509         .clkr = {
1510                 .enable_reg = 0x2d64,
1511                 .enable_mask = BIT(11),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "gp2_src",
1514                         .parent_names = gcc_pxo_pll8_cxo,
1515                         .num_parents = 3,
1516                         .ops = &clk_rcg_ops,
1517                         .flags = CLK_SET_RATE_GATE,
1518                 },
1519         }
1520 };
1521
1522 static struct clk_branch gp2_clk = {
1523         .halt_reg = 0x2fd8,
1524         .halt_bit = 5,
1525         .clkr = {
1526                 .enable_reg = 0x2d64,
1527                 .enable_mask = BIT(9),
1528                 .hw.init = &(struct clk_init_data){
1529                         .name = "gp2_clk",
1530                         .parent_names = (const char *[]){ "gp2_src" },
1531                         .num_parents = 1,
1532                         .ops = &clk_branch_ops,
1533                         .flags = CLK_SET_RATE_PARENT,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch pmem_clk = {
1539         .hwcg_reg = 0x25a0,
1540         .hwcg_bit = 6,
1541         .halt_reg = 0x2fc8,
1542         .halt_bit = 20,
1543         .clkr = {
1544                 .enable_reg = 0x25a0,
1545                 .enable_mask = BIT(4),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "pmem_clk",
1548                         .ops = &clk_branch_ops,
1549                         .flags = CLK_IS_ROOT,
1550                 },
1551         },
1552 };
1553
1554 static struct clk_rcg prng_src = {
1555         .ns_reg = 0x2e80,
1556         .p = {
1557                 .pre_div_shift = 3,
1558                 .pre_div_width = 4,
1559         },
1560         .s = {
1561                 .src_sel_shift = 0,
1562                 .parent_map = gcc_pxo_pll8_map,
1563         },
1564         .clkr = {
1565                 .hw.init = &(struct clk_init_data){
1566                         .name = "prng_src",
1567                         .parent_names = gcc_pxo_pll8,
1568                         .num_parents = 2,
1569                         .ops = &clk_rcg_ops,
1570                 },
1571         },
1572 };
1573
1574 static struct clk_branch prng_clk = {
1575         .halt_reg = 0x2fd8,
1576         .halt_check = BRANCH_HALT_VOTED,
1577         .halt_bit = 10,
1578         .clkr = {
1579                 .enable_reg = 0x3080,
1580                 .enable_mask = BIT(10),
1581                 .hw.init = &(struct clk_init_data){
1582                         .name = "prng_clk",
1583                         .parent_names = (const char *[]){ "prng_src" },
1584                         .num_parents = 1,
1585                         .ops = &clk_branch_ops,
1586                 },
1587         },
1588 };
1589
1590 static const struct freq_tbl clk_tbl_sdc[] = {
1591         {    144000, P_PXO,   3, 2, 125 },
1592         {    400000, P_PLL8,  4, 1, 240 },
1593         {  16000000, P_PLL8,  4, 1,   6 },
1594         {  17070000, P_PLL8,  1, 2,  45 },
1595         {  20210000, P_PLL8,  1, 1,  19 },
1596         {  24000000, P_PLL8,  4, 1,   4 },
1597         {  48000000, P_PLL8,  4, 1,   2 },
1598         {  64000000, P_PLL8,  3, 1,   2 },
1599         {  96000000, P_PLL8,  4, 0,   0 },
1600         { 192000000, P_PLL8,  2, 0,   0 },
1601         { }
1602 };
1603
1604 static struct clk_rcg sdc1_src = {
1605         .ns_reg = 0x282c,
1606         .md_reg = 0x2828,
1607         .mn = {
1608                 .mnctr_en_bit = 8,
1609                 .mnctr_reset_bit = 7,
1610                 .mnctr_mode_shift = 5,
1611                 .n_val_shift = 16,
1612                 .m_val_shift = 16,
1613                 .width = 8,
1614         },
1615         .p = {
1616                 .pre_div_shift = 3,
1617                 .pre_div_width = 2,
1618         },
1619         .s = {
1620                 .src_sel_shift = 0,
1621                 .parent_map = gcc_pxo_pll8_map,
1622         },
1623         .freq_tbl = clk_tbl_sdc,
1624         .clkr = {
1625                 .enable_reg = 0x282c,
1626                 .enable_mask = BIT(11),
1627                 .hw.init = &(struct clk_init_data){
1628                         .name = "sdc1_src",
1629                         .parent_names = gcc_pxo_pll8,
1630                         .num_parents = 2,
1631                         .ops = &clk_rcg_ops,
1632                         .flags = CLK_SET_RATE_GATE,
1633                 },
1634         }
1635 };
1636
1637 static struct clk_branch sdc1_clk = {
1638         .halt_reg = 0x2fc8,
1639         .halt_bit = 6,
1640         .clkr = {
1641                 .enable_reg = 0x282c,
1642                 .enable_mask = BIT(9),
1643                 .hw.init = &(struct clk_init_data){
1644                         .name = "sdc1_clk",
1645                         .parent_names = (const char *[]){ "sdc1_src" },
1646                         .num_parents = 1,
1647                         .ops = &clk_branch_ops,
1648                         .flags = CLK_SET_RATE_PARENT,
1649                 },
1650         },
1651 };
1652
1653 static struct clk_rcg sdc2_src = {
1654         .ns_reg = 0x284c,
1655         .md_reg = 0x2848,
1656         .mn = {
1657                 .mnctr_en_bit = 8,
1658                 .mnctr_reset_bit = 7,
1659                 .mnctr_mode_shift = 5,
1660                 .n_val_shift = 16,
1661                 .m_val_shift = 16,
1662                 .width = 8,
1663         },
1664         .p = {
1665                 .pre_div_shift = 3,
1666                 .pre_div_width = 2,
1667         },
1668         .s = {
1669                 .src_sel_shift = 0,
1670                 .parent_map = gcc_pxo_pll8_map,
1671         },
1672         .freq_tbl = clk_tbl_sdc,
1673         .clkr = {
1674                 .enable_reg = 0x284c,
1675                 .enable_mask = BIT(11),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "sdc2_src",
1678                         .parent_names = gcc_pxo_pll8,
1679                         .num_parents = 2,
1680                         .ops = &clk_rcg_ops,
1681                         .flags = CLK_SET_RATE_GATE,
1682                 },
1683         }
1684 };
1685
1686 static struct clk_branch sdc2_clk = {
1687         .halt_reg = 0x2fc8,
1688         .halt_bit = 5,
1689         .clkr = {
1690                 .enable_reg = 0x284c,
1691                 .enable_mask = BIT(9),
1692                 .hw.init = &(struct clk_init_data){
1693                         .name = "sdc2_clk",
1694                         .parent_names = (const char *[]){ "sdc2_src" },
1695                         .num_parents = 1,
1696                         .ops = &clk_branch_ops,
1697                         .flags = CLK_SET_RATE_PARENT,
1698                 },
1699         },
1700 };
1701
1702 static struct clk_rcg sdc3_src = {
1703         .ns_reg = 0x286c,
1704         .md_reg = 0x2868,
1705         .mn = {
1706                 .mnctr_en_bit = 8,
1707                 .mnctr_reset_bit = 7,
1708                 .mnctr_mode_shift = 5,
1709                 .n_val_shift = 16,
1710                 .m_val_shift = 16,
1711                 .width = 8,
1712         },
1713         .p = {
1714                 .pre_div_shift = 3,
1715                 .pre_div_width = 2,
1716         },
1717         .s = {
1718                 .src_sel_shift = 0,
1719                 .parent_map = gcc_pxo_pll8_map,
1720         },
1721         .freq_tbl = clk_tbl_sdc,
1722         .clkr = {
1723                 .enable_reg = 0x286c,
1724                 .enable_mask = BIT(11),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "sdc3_src",
1727                         .parent_names = gcc_pxo_pll8,
1728                         .num_parents = 2,
1729                         .ops = &clk_rcg_ops,
1730                         .flags = CLK_SET_RATE_GATE,
1731                 },
1732         }
1733 };
1734
1735 static struct clk_branch sdc3_clk = {
1736         .halt_reg = 0x2fc8,
1737         .halt_bit = 4,
1738         .clkr = {
1739                 .enable_reg = 0x286c,
1740                 .enable_mask = BIT(9),
1741                 .hw.init = &(struct clk_init_data){
1742                         .name = "sdc3_clk",
1743                         .parent_names = (const char *[]){ "sdc3_src" },
1744                         .num_parents = 1,
1745                         .ops = &clk_branch_ops,
1746                         .flags = CLK_SET_RATE_PARENT,
1747                 },
1748         },
1749 };
1750
1751 static struct clk_rcg sdc4_src = {
1752         .ns_reg = 0x288c,
1753         .md_reg = 0x2888,
1754         .mn = {
1755                 .mnctr_en_bit = 8,
1756                 .mnctr_reset_bit = 7,
1757                 .mnctr_mode_shift = 5,
1758                 .n_val_shift = 16,
1759                 .m_val_shift = 16,
1760                 .width = 8,
1761         },
1762         .p = {
1763                 .pre_div_shift = 3,
1764                 .pre_div_width = 2,
1765         },
1766         .s = {
1767                 .src_sel_shift = 0,
1768                 .parent_map = gcc_pxo_pll8_map,
1769         },
1770         .freq_tbl = clk_tbl_sdc,
1771         .clkr = {
1772                 .enable_reg = 0x288c,
1773                 .enable_mask = BIT(11),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "sdc4_src",
1776                         .parent_names = gcc_pxo_pll8,
1777                         .num_parents = 2,
1778                         .ops = &clk_rcg_ops,
1779                         .flags = CLK_SET_RATE_GATE,
1780                 },
1781         }
1782 };
1783
1784 static struct clk_branch sdc4_clk = {
1785         .halt_reg = 0x2fc8,
1786         .halt_bit = 3,
1787         .clkr = {
1788                 .enable_reg = 0x288c,
1789                 .enable_mask = BIT(9),
1790                 .hw.init = &(struct clk_init_data){
1791                         .name = "sdc4_clk",
1792                         .parent_names = (const char *[]){ "sdc4_src" },
1793                         .num_parents = 1,
1794                         .ops = &clk_branch_ops,
1795                         .flags = CLK_SET_RATE_PARENT,
1796                 },
1797         },
1798 };
1799
1800 static struct clk_rcg sdc5_src = {
1801         .ns_reg = 0x28ac,
1802         .md_reg = 0x28a8,
1803         .mn = {
1804                 .mnctr_en_bit = 8,
1805                 .mnctr_reset_bit = 7,
1806                 .mnctr_mode_shift = 5,
1807                 .n_val_shift = 16,
1808                 .m_val_shift = 16,
1809                 .width = 8,
1810         },
1811         .p = {
1812                 .pre_div_shift = 3,
1813                 .pre_div_width = 2,
1814         },
1815         .s = {
1816                 .src_sel_shift = 0,
1817                 .parent_map = gcc_pxo_pll8_map,
1818         },
1819         .freq_tbl = clk_tbl_sdc,
1820         .clkr = {
1821                 .enable_reg = 0x28ac,
1822                 .enable_mask = BIT(11),
1823                 .hw.init = &(struct clk_init_data){
1824                         .name = "sdc5_src",
1825                         .parent_names = gcc_pxo_pll8,
1826                         .num_parents = 2,
1827                         .ops = &clk_rcg_ops,
1828                         .flags = CLK_SET_RATE_GATE,
1829                 },
1830         }
1831 };
1832
1833 static struct clk_branch sdc5_clk = {
1834         .halt_reg = 0x2fc8,
1835         .halt_bit = 2,
1836         .clkr = {
1837                 .enable_reg = 0x28ac,
1838                 .enable_mask = BIT(9),
1839                 .hw.init = &(struct clk_init_data){
1840                         .name = "sdc5_clk",
1841                         .parent_names = (const char *[]){ "sdc5_src" },
1842                         .num_parents = 1,
1843                         .ops = &clk_branch_ops,
1844                         .flags = CLK_SET_RATE_PARENT,
1845                 },
1846         },
1847 };
1848
1849 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1850         { 105000, P_PXO,  1, 1, 256 },
1851         { }
1852 };
1853
1854 static struct clk_rcg tsif_ref_src = {
1855         .ns_reg = 0x2710,
1856         .md_reg = 0x270c,
1857         .mn = {
1858                 .mnctr_en_bit = 8,
1859                 .mnctr_reset_bit = 7,
1860                 .mnctr_mode_shift = 5,
1861                 .n_val_shift = 16,
1862                 .m_val_shift = 16,
1863                 .width = 16,
1864         },
1865         .p = {
1866                 .pre_div_shift = 3,
1867                 .pre_div_width = 2,
1868         },
1869         .s = {
1870                 .src_sel_shift = 0,
1871                 .parent_map = gcc_pxo_pll8_map,
1872         },
1873         .freq_tbl = clk_tbl_tsif_ref,
1874         .clkr = {
1875                 .enable_reg = 0x2710,
1876                 .enable_mask = BIT(11),
1877                 .hw.init = &(struct clk_init_data){
1878                         .name = "tsif_ref_src",
1879                         .parent_names = gcc_pxo_pll8,
1880                         .num_parents = 2,
1881                         .ops = &clk_rcg_ops,
1882                         .flags = CLK_SET_RATE_GATE,
1883                 },
1884         }
1885 };
1886
1887 static struct clk_branch tsif_ref_clk = {
1888         .halt_reg = 0x2fd4,
1889         .halt_bit = 5,
1890         .clkr = {
1891                 .enable_reg = 0x2710,
1892                 .enable_mask = BIT(9),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "tsif_ref_clk",
1895                         .parent_names = (const char *[]){ "tsif_ref_src" },
1896                         .num_parents = 1,
1897                         .ops = &clk_branch_ops,
1898                         .flags = CLK_SET_RATE_PARENT,
1899                 },
1900         },
1901 };
1902
1903 static const struct freq_tbl clk_tbl_usb[] = {
1904         { 60000000, P_PLL8, 1, 5, 32 },
1905         { }
1906 };
1907
1908 static struct clk_rcg usb_hs1_xcvr_src = {
1909         .ns_reg = 0x290c,
1910         .md_reg = 0x2908,
1911         .mn = {
1912                 .mnctr_en_bit = 8,
1913                 .mnctr_reset_bit = 7,
1914                 .mnctr_mode_shift = 5,
1915                 .n_val_shift = 16,
1916                 .m_val_shift = 16,
1917                 .width = 8,
1918         },
1919         .p = {
1920                 .pre_div_shift = 3,
1921                 .pre_div_width = 2,
1922         },
1923         .s = {
1924                 .src_sel_shift = 0,
1925                 .parent_map = gcc_pxo_pll8_map,
1926         },
1927         .freq_tbl = clk_tbl_usb,
1928         .clkr = {
1929                 .enable_reg = 0x290c,
1930                 .enable_mask = BIT(11),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "usb_hs1_xcvr_src",
1933                         .parent_names = gcc_pxo_pll8,
1934                         .num_parents = 2,
1935                         .ops = &clk_rcg_ops,
1936                         .flags = CLK_SET_RATE_GATE,
1937                 },
1938         }
1939 };
1940
1941 static struct clk_branch usb_hs1_xcvr_clk = {
1942         .halt_reg = 0x2fc8,
1943         .halt_bit = 0,
1944         .clkr = {
1945                 .enable_reg = 0x290c,
1946                 .enable_mask = BIT(9),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "usb_hs1_xcvr_clk",
1949                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1950                         .num_parents = 1,
1951                         .ops = &clk_branch_ops,
1952                         .flags = CLK_SET_RATE_PARENT,
1953                 },
1954         },
1955 };
1956
1957 static struct clk_rcg usb_hs3_xcvr_src = {
1958         .ns_reg = 0x370c,
1959         .md_reg = 0x3708,
1960         .mn = {
1961                 .mnctr_en_bit = 8,
1962                 .mnctr_reset_bit = 7,
1963                 .mnctr_mode_shift = 5,
1964                 .n_val_shift = 16,
1965                 .m_val_shift = 16,
1966                 .width = 8,
1967         },
1968         .p = {
1969                 .pre_div_shift = 3,
1970                 .pre_div_width = 2,
1971         },
1972         .s = {
1973                 .src_sel_shift = 0,
1974                 .parent_map = gcc_pxo_pll8_map,
1975         },
1976         .freq_tbl = clk_tbl_usb,
1977         .clkr = {
1978                 .enable_reg = 0x370c,
1979                 .enable_mask = BIT(11),
1980                 .hw.init = &(struct clk_init_data){
1981                         .name = "usb_hs3_xcvr_src",
1982                         .parent_names = gcc_pxo_pll8,
1983                         .num_parents = 2,
1984                         .ops = &clk_rcg_ops,
1985                         .flags = CLK_SET_RATE_GATE,
1986                 },
1987         }
1988 };
1989
1990 static struct clk_branch usb_hs3_xcvr_clk = {
1991         .halt_reg = 0x2fc8,
1992         .halt_bit = 30,
1993         .clkr = {
1994                 .enable_reg = 0x370c,
1995                 .enable_mask = BIT(9),
1996                 .hw.init = &(struct clk_init_data){
1997                         .name = "usb_hs3_xcvr_clk",
1998                         .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1999                         .num_parents = 1,
2000                         .ops = &clk_branch_ops,
2001                         .flags = CLK_SET_RATE_PARENT,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_rcg usb_hs4_xcvr_src = {
2007         .ns_reg = 0x372c,
2008         .md_reg = 0x3728,
2009         .mn = {
2010                 .mnctr_en_bit = 8,
2011                 .mnctr_reset_bit = 7,
2012                 .mnctr_mode_shift = 5,
2013                 .n_val_shift = 16,
2014                 .m_val_shift = 16,
2015                 .width = 8,
2016         },
2017         .p = {
2018                 .pre_div_shift = 3,
2019                 .pre_div_width = 2,
2020         },
2021         .s = {
2022                 .src_sel_shift = 0,
2023                 .parent_map = gcc_pxo_pll8_map,
2024         },
2025         .freq_tbl = clk_tbl_usb,
2026         .clkr = {
2027                 .enable_reg = 0x372c,
2028                 .enable_mask = BIT(11),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "usb_hs4_xcvr_src",
2031                         .parent_names = gcc_pxo_pll8,
2032                         .num_parents = 2,
2033                         .ops = &clk_rcg_ops,
2034                         .flags = CLK_SET_RATE_GATE,
2035                 },
2036         }
2037 };
2038
2039 static struct clk_branch usb_hs4_xcvr_clk = {
2040         .halt_reg = 0x2fc8,
2041         .halt_bit = 2,
2042         .clkr = {
2043                 .enable_reg = 0x372c,
2044                 .enable_mask = BIT(9),
2045                 .hw.init = &(struct clk_init_data){
2046                         .name = "usb_hs4_xcvr_clk",
2047                         .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2048                         .num_parents = 1,
2049                         .ops = &clk_branch_ops,
2050                         .flags = CLK_SET_RATE_PARENT,
2051                 },
2052         },
2053 };
2054
2055 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2056         .ns_reg = 0x2928,
2057         .md_reg = 0x2924,
2058         .mn = {
2059                 .mnctr_en_bit = 8,
2060                 .mnctr_reset_bit = 7,
2061                 .mnctr_mode_shift = 5,
2062                 .n_val_shift = 16,
2063                 .m_val_shift = 16,
2064                 .width = 8,
2065         },
2066         .p = {
2067                 .pre_div_shift = 3,
2068                 .pre_div_width = 2,
2069         },
2070         .s = {
2071                 .src_sel_shift = 0,
2072                 .parent_map = gcc_pxo_pll8_map,
2073         },
2074         .freq_tbl = clk_tbl_usb,
2075         .clkr = {
2076                 .enable_reg = 0x2928,
2077                 .enable_mask = BIT(11),
2078                 .hw.init = &(struct clk_init_data){
2079                         .name = "usb_hsic_xcvr_fs_src",
2080                         .parent_names = gcc_pxo_pll8,
2081                         .num_parents = 2,
2082                         .ops = &clk_rcg_ops,
2083                         .flags = CLK_SET_RATE_GATE,
2084                 },
2085         }
2086 };
2087
2088 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2089
2090 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2091         .halt_reg = 0x2fc8,
2092         .halt_bit = 2,
2093         .clkr = {
2094                 .enable_reg = 0x2928,
2095                 .enable_mask = BIT(9),
2096                 .hw.init = &(struct clk_init_data){
2097                         .name = "usb_hsic_xcvr_fs_clk",
2098                         .parent_names = usb_hsic_xcvr_fs_src_p,
2099                         .num_parents = 1,
2100                         .ops = &clk_branch_ops,
2101                         .flags = CLK_SET_RATE_PARENT,
2102                 },
2103         },
2104 };
2105
2106 static struct clk_branch usb_hsic_system_clk = {
2107         .halt_reg = 0x2fcc,
2108         .halt_bit = 24,
2109         .clkr = {
2110                 .enable_reg = 0x292c,
2111                 .enable_mask = BIT(4),
2112                 .hw.init = &(struct clk_init_data){
2113                         .parent_names = usb_hsic_xcvr_fs_src_p,
2114                         .num_parents = 1,
2115                         .name = "usb_hsic_system_clk",
2116                         .ops = &clk_branch_ops,
2117                         .flags = CLK_SET_RATE_PARENT,
2118                 },
2119         },
2120 };
2121
2122 static struct clk_branch usb_hsic_hsic_clk = {
2123         .halt_reg = 0x2fcc,
2124         .halt_bit = 19,
2125         .clkr = {
2126                 .enable_reg = 0x2b44,
2127                 .enable_mask = BIT(0),
2128                 .hw.init = &(struct clk_init_data){
2129                         .parent_names = (const char *[]){ "pll14_vote" },
2130                         .num_parents = 1,
2131                         .name = "usb_hsic_hsic_clk",
2132                         .ops = &clk_branch_ops,
2133                 },
2134         },
2135 };
2136
2137 static struct clk_branch usb_hsic_hsio_cal_clk = {
2138         .halt_reg = 0x2fcc,
2139         .halt_bit = 23,
2140         .clkr = {
2141                 .enable_reg = 0x2b48,
2142                 .enable_mask = BIT(0),
2143                 .hw.init = &(struct clk_init_data){
2144                         .name = "usb_hsic_hsio_cal_clk",
2145                         .ops = &clk_branch_ops,
2146                         .flags = CLK_IS_ROOT,
2147                 },
2148         },
2149 };
2150
2151 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2152         .ns_reg = 0x2968,
2153         .md_reg = 0x2964,
2154         .mn = {
2155                 .mnctr_en_bit = 8,
2156                 .mnctr_reset_bit = 7,
2157                 .mnctr_mode_shift = 5,
2158                 .n_val_shift = 16,
2159                 .m_val_shift = 16,
2160                 .width = 8,
2161         },
2162         .p = {
2163                 .pre_div_shift = 3,
2164                 .pre_div_width = 2,
2165         },
2166         .s = {
2167                 .src_sel_shift = 0,
2168                 .parent_map = gcc_pxo_pll8_map,
2169         },
2170         .freq_tbl = clk_tbl_usb,
2171         .clkr = {
2172                 .enable_reg = 0x2968,
2173                 .enable_mask = BIT(11),
2174                 .hw.init = &(struct clk_init_data){
2175                         .name = "usb_fs1_xcvr_fs_src",
2176                         .parent_names = gcc_pxo_pll8,
2177                         .num_parents = 2,
2178                         .ops = &clk_rcg_ops,
2179                         .flags = CLK_SET_RATE_GATE,
2180                 },
2181         }
2182 };
2183
2184 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2185
2186 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2187         .halt_reg = 0x2fcc,
2188         .halt_bit = 15,
2189         .clkr = {
2190                 .enable_reg = 0x2968,
2191                 .enable_mask = BIT(9),
2192                 .hw.init = &(struct clk_init_data){
2193                         .name = "usb_fs1_xcvr_fs_clk",
2194                         .parent_names = usb_fs1_xcvr_fs_src_p,
2195                         .num_parents = 1,
2196                         .ops = &clk_branch_ops,
2197                         .flags = CLK_SET_RATE_PARENT,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch usb_fs1_system_clk = {
2203         .halt_reg = 0x2fcc,
2204         .halt_bit = 16,
2205         .clkr = {
2206                 .enable_reg = 0x296c,
2207                 .enable_mask = BIT(4),
2208                 .hw.init = &(struct clk_init_data){
2209                         .parent_names = usb_fs1_xcvr_fs_src_p,
2210                         .num_parents = 1,
2211                         .name = "usb_fs1_system_clk",
2212                         .ops = &clk_branch_ops,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2219         .ns_reg = 0x2988,
2220         .md_reg = 0x2984,
2221         .mn = {
2222                 .mnctr_en_bit = 8,
2223                 .mnctr_reset_bit = 7,
2224                 .mnctr_mode_shift = 5,
2225                 .n_val_shift = 16,
2226                 .m_val_shift = 16,
2227                 .width = 8,
2228         },
2229         .p = {
2230                 .pre_div_shift = 3,
2231                 .pre_div_width = 2,
2232         },
2233         .s = {
2234                 .src_sel_shift = 0,
2235                 .parent_map = gcc_pxo_pll8_map,
2236         },
2237         .freq_tbl = clk_tbl_usb,
2238         .clkr = {
2239                 .enable_reg = 0x2988,
2240                 .enable_mask = BIT(11),
2241                 .hw.init = &(struct clk_init_data){
2242                         .name = "usb_fs2_xcvr_fs_src",
2243                         .parent_names = gcc_pxo_pll8,
2244                         .num_parents = 2,
2245                         .ops = &clk_rcg_ops,
2246                         .flags = CLK_SET_RATE_GATE,
2247                 },
2248         }
2249 };
2250
2251 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2252
2253 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2254         .halt_reg = 0x2fcc,
2255         .halt_bit = 12,
2256         .clkr = {
2257                 .enable_reg = 0x2988,
2258                 .enable_mask = BIT(9),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "usb_fs2_xcvr_fs_clk",
2261                         .parent_names = usb_fs2_xcvr_fs_src_p,
2262                         .num_parents = 1,
2263                         .ops = &clk_branch_ops,
2264                         .flags = CLK_SET_RATE_PARENT,
2265                 },
2266         },
2267 };
2268
2269 static struct clk_branch usb_fs2_system_clk = {
2270         .halt_reg = 0x2fcc,
2271         .halt_bit = 13,
2272         .clkr = {
2273                 .enable_reg = 0x298c,
2274                 .enable_mask = BIT(4),
2275                 .hw.init = &(struct clk_init_data){
2276                         .name = "usb_fs2_system_clk",
2277                         .parent_names = usb_fs2_xcvr_fs_src_p,
2278                         .num_parents = 1,
2279                         .ops = &clk_branch_ops,
2280                         .flags = CLK_SET_RATE_PARENT,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch ce1_core_clk = {
2286         .hwcg_reg = 0x2724,
2287         .hwcg_bit = 6,
2288         .halt_reg = 0x2fd4,
2289         .halt_bit = 27,
2290         .clkr = {
2291                 .enable_reg = 0x2724,
2292                 .enable_mask = BIT(4),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "ce1_core_clk",
2295                         .ops = &clk_branch_ops,
2296                         .flags = CLK_IS_ROOT,
2297                 },
2298         },
2299 };
2300
2301 static struct clk_branch ce1_h_clk = {
2302         .halt_reg = 0x2fd4,
2303         .halt_bit = 1,
2304         .clkr = {
2305                 .enable_reg = 0x2720,
2306                 .enable_mask = BIT(4),
2307                 .hw.init = &(struct clk_init_data){
2308                         .name = "ce1_h_clk",
2309                         .ops = &clk_branch_ops,
2310                         .flags = CLK_IS_ROOT,
2311                 },
2312         },
2313 };
2314
2315 static struct clk_branch dma_bam_h_clk = {
2316         .hwcg_reg = 0x25c0,
2317         .hwcg_bit = 6,
2318         .halt_reg = 0x2fc8,
2319         .halt_bit = 12,
2320         .clkr = {
2321                 .enable_reg = 0x25c0,
2322                 .enable_mask = BIT(4),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "dma_bam_h_clk",
2325                         .ops = &clk_branch_ops,
2326                         .flags = CLK_IS_ROOT,
2327                 },
2328         },
2329 };
2330
2331 static struct clk_branch gsbi1_h_clk = {
2332         .hwcg_reg = 0x29c0,
2333         .hwcg_bit = 6,
2334         .halt_reg = 0x2fcc,
2335         .halt_bit = 11,
2336         .clkr = {
2337                 .enable_reg = 0x29c0,
2338                 .enable_mask = BIT(4),
2339                 .hw.init = &(struct clk_init_data){
2340                         .name = "gsbi1_h_clk",
2341                         .ops = &clk_branch_ops,
2342                         .flags = CLK_IS_ROOT,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch gsbi2_h_clk = {
2348         .hwcg_reg = 0x29e0,
2349         .hwcg_bit = 6,
2350         .halt_reg = 0x2fcc,
2351         .halt_bit = 7,
2352         .clkr = {
2353                 .enable_reg = 0x29e0,
2354                 .enable_mask = BIT(4),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gsbi2_h_clk",
2357                         .ops = &clk_branch_ops,
2358                         .flags = CLK_IS_ROOT,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gsbi3_h_clk = {
2364         .hwcg_reg = 0x2a00,
2365         .hwcg_bit = 6,
2366         .halt_reg = 0x2fcc,
2367         .halt_bit = 3,
2368         .clkr = {
2369                 .enable_reg = 0x2a00,
2370                 .enable_mask = BIT(4),
2371                 .hw.init = &(struct clk_init_data){
2372                         .name = "gsbi3_h_clk",
2373                         .ops = &clk_branch_ops,
2374                         .flags = CLK_IS_ROOT,
2375                 },
2376         },
2377 };
2378
2379 static struct clk_branch gsbi4_h_clk = {
2380         .hwcg_reg = 0x2a20,
2381         .hwcg_bit = 6,
2382         .halt_reg = 0x2fd0,
2383         .halt_bit = 27,
2384         .clkr = {
2385                 .enable_reg = 0x2a20,
2386                 .enable_mask = BIT(4),
2387                 .hw.init = &(struct clk_init_data){
2388                         .name = "gsbi4_h_clk",
2389                         .ops = &clk_branch_ops,
2390                         .flags = CLK_IS_ROOT,
2391                 },
2392         },
2393 };
2394
2395 static struct clk_branch gsbi5_h_clk = {
2396         .hwcg_reg = 0x2a40,
2397         .hwcg_bit = 6,
2398         .halt_reg = 0x2fd0,
2399         .halt_bit = 23,
2400         .clkr = {
2401                 .enable_reg = 0x2a40,
2402                 .enable_mask = BIT(4),
2403                 .hw.init = &(struct clk_init_data){
2404                         .name = "gsbi5_h_clk",
2405                         .ops = &clk_branch_ops,
2406                         .flags = CLK_IS_ROOT,
2407                 },
2408         },
2409 };
2410
2411 static struct clk_branch gsbi6_h_clk = {
2412         .hwcg_reg = 0x2a60,
2413         .hwcg_bit = 6,
2414         .halt_reg = 0x2fd0,
2415         .halt_bit = 19,
2416         .clkr = {
2417                 .enable_reg = 0x2a60,
2418                 .enable_mask = BIT(4),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "gsbi6_h_clk",
2421                         .ops = &clk_branch_ops,
2422                         .flags = CLK_IS_ROOT,
2423                 },
2424         },
2425 };
2426
2427 static struct clk_branch gsbi7_h_clk = {
2428         .hwcg_reg = 0x2a80,
2429         .hwcg_bit = 6,
2430         .halt_reg = 0x2fd0,
2431         .halt_bit = 15,
2432         .clkr = {
2433                 .enable_reg = 0x2a80,
2434                 .enable_mask = BIT(4),
2435                 .hw.init = &(struct clk_init_data){
2436                         .name = "gsbi7_h_clk",
2437                         .ops = &clk_branch_ops,
2438                         .flags = CLK_IS_ROOT,
2439                 },
2440         },
2441 };
2442
2443 static struct clk_branch gsbi8_h_clk = {
2444         .hwcg_reg = 0x2aa0,
2445         .hwcg_bit = 6,
2446         .halt_reg = 0x2fd0,
2447         .halt_bit = 11,
2448         .clkr = {
2449                 .enable_reg = 0x2aa0,
2450                 .enable_mask = BIT(4),
2451                 .hw.init = &(struct clk_init_data){
2452                         .name = "gsbi8_h_clk",
2453                         .ops = &clk_branch_ops,
2454                         .flags = CLK_IS_ROOT,
2455                 },
2456         },
2457 };
2458
2459 static struct clk_branch gsbi9_h_clk = {
2460         .hwcg_reg = 0x2ac0,
2461         .hwcg_bit = 6,
2462         .halt_reg = 0x2fd0,
2463         .halt_bit = 7,
2464         .clkr = {
2465                 .enable_reg = 0x2ac0,
2466                 .enable_mask = BIT(4),
2467                 .hw.init = &(struct clk_init_data){
2468                         .name = "gsbi9_h_clk",
2469                         .ops = &clk_branch_ops,
2470                         .flags = CLK_IS_ROOT,
2471                 },
2472         },
2473 };
2474
2475 static struct clk_branch gsbi10_h_clk = {
2476         .hwcg_reg = 0x2ae0,
2477         .hwcg_bit = 6,
2478         .halt_reg = 0x2fd0,
2479         .halt_bit = 3,
2480         .clkr = {
2481                 .enable_reg = 0x2ae0,
2482                 .enable_mask = BIT(4),
2483                 .hw.init = &(struct clk_init_data){
2484                         .name = "gsbi10_h_clk",
2485                         .ops = &clk_branch_ops,
2486                         .flags = CLK_IS_ROOT,
2487                 },
2488         },
2489 };
2490
2491 static struct clk_branch gsbi11_h_clk = {
2492         .hwcg_reg = 0x2b00,
2493         .hwcg_bit = 6,
2494         .halt_reg = 0x2fd4,
2495         .halt_bit = 18,
2496         .clkr = {
2497                 .enable_reg = 0x2b00,
2498                 .enable_mask = BIT(4),
2499                 .hw.init = &(struct clk_init_data){
2500                         .name = "gsbi11_h_clk",
2501                         .ops = &clk_branch_ops,
2502                         .flags = CLK_IS_ROOT,
2503                 },
2504         },
2505 };
2506
2507 static struct clk_branch gsbi12_h_clk = {
2508         .hwcg_reg = 0x2b20,
2509         .hwcg_bit = 6,
2510         .halt_reg = 0x2fd4,
2511         .halt_bit = 14,
2512         .clkr = {
2513                 .enable_reg = 0x2b20,
2514                 .enable_mask = BIT(4),
2515                 .hw.init = &(struct clk_init_data){
2516                         .name = "gsbi12_h_clk",
2517                         .ops = &clk_branch_ops,
2518                         .flags = CLK_IS_ROOT,
2519                 },
2520         },
2521 };
2522
2523 static struct clk_branch tsif_h_clk = {
2524         .hwcg_reg = 0x2700,
2525         .hwcg_bit = 6,
2526         .halt_reg = 0x2fd4,
2527         .halt_bit = 7,
2528         .clkr = {
2529                 .enable_reg = 0x2700,
2530                 .enable_mask = BIT(4),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "tsif_h_clk",
2533                         .ops = &clk_branch_ops,
2534                         .flags = CLK_IS_ROOT,
2535                 },
2536         },
2537 };
2538
2539 static struct clk_branch usb_fs1_h_clk = {
2540         .halt_reg = 0x2fcc,
2541         .halt_bit = 17,
2542         .clkr = {
2543                 .enable_reg = 0x2960,
2544                 .enable_mask = BIT(4),
2545                 .hw.init = &(struct clk_init_data){
2546                         .name = "usb_fs1_h_clk",
2547                         .ops = &clk_branch_ops,
2548                         .flags = CLK_IS_ROOT,
2549                 },
2550         },
2551 };
2552
2553 static struct clk_branch usb_fs2_h_clk = {
2554         .halt_reg = 0x2fcc,
2555         .halt_bit = 14,
2556         .clkr = {
2557                 .enable_reg = 0x2980,
2558                 .enable_mask = BIT(4),
2559                 .hw.init = &(struct clk_init_data){
2560                         .name = "usb_fs2_h_clk",
2561                         .ops = &clk_branch_ops,
2562                         .flags = CLK_IS_ROOT,
2563                 },
2564         },
2565 };
2566
2567 static struct clk_branch usb_hs1_h_clk = {
2568         .hwcg_reg = 0x2900,
2569         .hwcg_bit = 6,
2570         .halt_reg = 0x2fc8,
2571         .halt_bit = 1,
2572         .clkr = {
2573                 .enable_reg = 0x2900,
2574                 .enable_mask = BIT(4),
2575                 .hw.init = &(struct clk_init_data){
2576                         .name = "usb_hs1_h_clk",
2577                         .ops = &clk_branch_ops,
2578                         .flags = CLK_IS_ROOT,
2579                 },
2580         },
2581 };
2582
2583 static struct clk_branch usb_hs3_h_clk = {
2584         .halt_reg = 0x2fc8,
2585         .halt_bit = 31,
2586         .clkr = {
2587                 .enable_reg = 0x3700,
2588                 .enable_mask = BIT(4),
2589                 .hw.init = &(struct clk_init_data){
2590                         .name = "usb_hs3_h_clk",
2591                         .ops = &clk_branch_ops,
2592                         .flags = CLK_IS_ROOT,
2593                 },
2594         },
2595 };
2596
2597 static struct clk_branch usb_hs4_h_clk = {
2598         .halt_reg = 0x2fc8,
2599         .halt_bit = 7,
2600         .clkr = {
2601                 .enable_reg = 0x3720,
2602                 .enable_mask = BIT(4),
2603                 .hw.init = &(struct clk_init_data){
2604                         .name = "usb_hs4_h_clk",
2605                         .ops = &clk_branch_ops,
2606                         .flags = CLK_IS_ROOT,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch usb_hsic_h_clk = {
2612         .halt_reg = 0x2fcc,
2613         .halt_bit = 28,
2614         .clkr = {
2615                 .enable_reg = 0x2920,
2616                 .enable_mask = BIT(4),
2617                 .hw.init = &(struct clk_init_data){
2618                         .name = "usb_hsic_h_clk",
2619                         .ops = &clk_branch_ops,
2620                         .flags = CLK_IS_ROOT,
2621                 },
2622         },
2623 };
2624
2625 static struct clk_branch sdc1_h_clk = {
2626         .hwcg_reg = 0x2820,
2627         .hwcg_bit = 6,
2628         .halt_reg = 0x2fc8,
2629         .halt_bit = 11,
2630         .clkr = {
2631                 .enable_reg = 0x2820,
2632                 .enable_mask = BIT(4),
2633                 .hw.init = &(struct clk_init_data){
2634                         .name = "sdc1_h_clk",
2635                         .ops = &clk_branch_ops,
2636                         .flags = CLK_IS_ROOT,
2637                 },
2638         },
2639 };
2640
2641 static struct clk_branch sdc2_h_clk = {
2642         .hwcg_reg = 0x2840,
2643         .hwcg_bit = 6,
2644         .halt_reg = 0x2fc8,
2645         .halt_bit = 10,
2646         .clkr = {
2647                 .enable_reg = 0x2840,
2648                 .enable_mask = BIT(4),
2649                 .hw.init = &(struct clk_init_data){
2650                         .name = "sdc2_h_clk",
2651                         .ops = &clk_branch_ops,
2652                         .flags = CLK_IS_ROOT,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch sdc3_h_clk = {
2658         .hwcg_reg = 0x2860,
2659         .hwcg_bit = 6,
2660         .halt_reg = 0x2fc8,
2661         .halt_bit = 9,
2662         .clkr = {
2663                 .enable_reg = 0x2860,
2664                 .enable_mask = BIT(4),
2665                 .hw.init = &(struct clk_init_data){
2666                         .name = "sdc3_h_clk",
2667                         .ops = &clk_branch_ops,
2668                         .flags = CLK_IS_ROOT,
2669                 },
2670         },
2671 };
2672
2673 static struct clk_branch sdc4_h_clk = {
2674         .hwcg_reg = 0x2880,
2675         .hwcg_bit = 6,
2676         .halt_reg = 0x2fc8,
2677         .halt_bit = 8,
2678         .clkr = {
2679                 .enable_reg = 0x2880,
2680                 .enable_mask = BIT(4),
2681                 .hw.init = &(struct clk_init_data){
2682                         .name = "sdc4_h_clk",
2683                         .ops = &clk_branch_ops,
2684                         .flags = CLK_IS_ROOT,
2685                 },
2686         },
2687 };
2688
2689 static struct clk_branch sdc5_h_clk = {
2690         .hwcg_reg = 0x28a0,
2691         .hwcg_bit = 6,
2692         .halt_reg = 0x2fc8,
2693         .halt_bit = 7,
2694         .clkr = {
2695                 .enable_reg = 0x28a0,
2696                 .enable_mask = BIT(4),
2697                 .hw.init = &(struct clk_init_data){
2698                         .name = "sdc5_h_clk",
2699                         .ops = &clk_branch_ops,
2700                         .flags = CLK_IS_ROOT,
2701                 },
2702         },
2703 };
2704
2705 static struct clk_branch adm0_clk = {
2706         .halt_reg = 0x2fdc,
2707         .halt_check = BRANCH_HALT_VOTED,
2708         .halt_bit = 14,
2709         .clkr = {
2710                 .enable_reg = 0x3080,
2711                 .enable_mask = BIT(2),
2712                 .hw.init = &(struct clk_init_data){
2713                         .name = "adm0_clk",
2714                         .ops = &clk_branch_ops,
2715                         .flags = CLK_IS_ROOT,
2716                 },
2717         },
2718 };
2719
2720 static struct clk_branch adm0_pbus_clk = {
2721         .hwcg_reg = 0x2208,
2722         .hwcg_bit = 6,
2723         .halt_reg = 0x2fdc,
2724         .halt_check = BRANCH_HALT_VOTED,
2725         .halt_bit = 13,
2726         .clkr = {
2727                 .enable_reg = 0x3080,
2728                 .enable_mask = BIT(3),
2729                 .hw.init = &(struct clk_init_data){
2730                         .name = "adm0_pbus_clk",
2731                         .ops = &clk_branch_ops,
2732                         .flags = CLK_IS_ROOT,
2733                 },
2734         },
2735 };
2736
2737 static struct freq_tbl clk_tbl_ce3[] = {
2738         { 48000000, P_PLL8, 8 },
2739         { 100000000, P_PLL3, 12 },
2740         { 120000000, P_PLL3, 10 },
2741         { }
2742 };
2743
2744 static struct clk_rcg ce3_src = {
2745         .ns_reg = 0x36c0,
2746         .p = {
2747                 .pre_div_shift = 3,
2748                 .pre_div_width = 4,
2749         },
2750         .s = {
2751                 .src_sel_shift = 0,
2752                 .parent_map = gcc_pxo_pll8_pll3_map,
2753         },
2754         .freq_tbl = clk_tbl_ce3,
2755         .clkr = {
2756                 .enable_reg = 0x2c08,
2757                 .enable_mask = BIT(7),
2758                 .hw.init = &(struct clk_init_data){
2759                         .name = "ce3_src",
2760                         .parent_names = gcc_pxo_pll8_pll3,
2761                         .num_parents = 3,
2762                         .ops = &clk_rcg_ops,
2763                         .flags = CLK_SET_RATE_GATE,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch ce3_core_clk = {
2769         .halt_reg = 0x2fdc,
2770         .halt_bit = 5,
2771         .clkr = {
2772                 .enable_reg = 0x36c4,
2773                 .enable_mask = BIT(4),
2774                 .hw.init = &(struct clk_init_data){
2775                         .name = "ce3_core_clk",
2776                         .parent_names = (const char *[]){ "ce3_src" },
2777                         .num_parents = 1,
2778                         .ops = &clk_branch_ops,
2779                         .flags = CLK_SET_RATE_PARENT,
2780                 },
2781         },
2782 };
2783
2784 static struct clk_branch ce3_h_clk = {
2785         .halt_reg = 0x2fc4,
2786         .halt_bit = 16,
2787         .clkr = {
2788                 .enable_reg = 0x36c4,
2789                 .enable_mask = BIT(4),
2790                 .hw.init = &(struct clk_init_data){
2791                         .name = "ce3_h_clk",
2792                         .parent_names = (const char *[]){ "ce3_src" },
2793                         .num_parents = 1,
2794                         .ops = &clk_branch_ops,
2795                         .flags = CLK_SET_RATE_PARENT,
2796                 },
2797         },
2798 };
2799
2800 static const struct freq_tbl clk_tbl_sata_ref[] = {
2801         { 48000000, P_PLL8, 8, 0, 0 },
2802         { 100000000, P_PLL3, 12, 0, 0 },
2803         { }
2804 };
2805
2806 static struct clk_rcg sata_clk_src = {
2807         .ns_reg = 0x2c08,
2808         .p = {
2809                 .pre_div_shift = 3,
2810                 .pre_div_width = 4,
2811         },
2812         .s = {
2813                 .src_sel_shift = 0,
2814                 .parent_map = gcc_pxo_pll8_pll3_map,
2815         },
2816         .freq_tbl = clk_tbl_sata_ref,
2817         .clkr = {
2818                 .enable_reg = 0x2c08,
2819                 .enable_mask = BIT(7),
2820                 .hw.init = &(struct clk_init_data){
2821                         .name = "sata_clk_src",
2822                         .parent_names = gcc_pxo_pll8_pll3,
2823                         .num_parents = 3,
2824                         .ops = &clk_rcg_ops,
2825                         .flags = CLK_SET_RATE_GATE,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch sata_rxoob_clk = {
2831         .halt_reg = 0x2fdc,
2832         .halt_bit = 26,
2833         .clkr = {
2834                 .enable_reg = 0x2c0c,
2835                 .enable_mask = BIT(4),
2836                 .hw.init = &(struct clk_init_data){
2837                         .name = "sata_rxoob_clk",
2838                         .parent_names = (const char *[]){ "sata_clk_src" },
2839                         .num_parents = 1,
2840                         .ops = &clk_branch_ops,
2841                         .flags = CLK_SET_RATE_PARENT,
2842                 },
2843         },
2844 };
2845
2846 static struct clk_branch sata_pmalive_clk = {
2847         .halt_reg = 0x2fdc,
2848         .halt_bit = 25,
2849         .clkr = {
2850                 .enable_reg = 0x2c10,
2851                 .enable_mask = BIT(4),
2852                 .hw.init = &(struct clk_init_data){
2853                         .name = "sata_pmalive_clk",
2854                         .parent_names = (const char *[]){ "sata_clk_src" },
2855                         .num_parents = 1,
2856                         .ops = &clk_branch_ops,
2857                         .flags = CLK_SET_RATE_PARENT,
2858                 },
2859         },
2860 };
2861
2862 static struct clk_branch sata_phy_ref_clk = {
2863         .halt_reg = 0x2fdc,
2864         .halt_bit = 24,
2865         .clkr = {
2866                 .enable_reg = 0x2c14,
2867                 .enable_mask = BIT(4),
2868                 .hw.init = &(struct clk_init_data){
2869                         .name = "sata_phy_ref_clk",
2870                         .parent_names = (const char *[]){ "pxo" },
2871                         .num_parents = 1,
2872                         .ops = &clk_branch_ops,
2873                 },
2874         },
2875 };
2876
2877 static struct clk_branch sata_a_clk = {
2878         .halt_reg = 0x2fc0,
2879         .halt_bit = 12,
2880         .clkr = {
2881                 .enable_reg = 0x2c20,
2882                 .enable_mask = BIT(4),
2883                 .hw.init = &(struct clk_init_data){
2884                         .name = "sata_a_clk",
2885                         .ops = &clk_branch_ops,
2886                         .flags = CLK_IS_ROOT,
2887                 },
2888         },
2889 };
2890
2891 static struct clk_branch sata_h_clk = {
2892         .halt_reg = 0x2fdc,
2893         .halt_bit = 27,
2894         .clkr = {
2895                 .enable_reg = 0x2c00,
2896                 .enable_mask = BIT(4),
2897                 .hw.init = &(struct clk_init_data){
2898                         .name = "sata_h_clk",
2899                         .ops = &clk_branch_ops,
2900                         .flags = CLK_IS_ROOT,
2901                 },
2902         },
2903 };
2904
2905 static struct clk_branch sfab_sata_s_h_clk = {
2906         .halt_reg = 0x2fc4,
2907         .halt_bit = 14,
2908         .clkr = {
2909                 .enable_reg = 0x2480,
2910                 .enable_mask = BIT(4),
2911                 .hw.init = &(struct clk_init_data){
2912                         .name = "sfab_sata_s_h_clk",
2913                         .ops = &clk_branch_ops,
2914                         .flags = CLK_IS_ROOT,
2915                 },
2916         },
2917 };
2918
2919 static struct clk_branch sata_phy_cfg_clk = {
2920         .halt_reg = 0x2fcc,
2921         .halt_bit = 12,
2922         .clkr = {
2923                 .enable_reg = 0x2c40,
2924                 .enable_mask = BIT(4),
2925                 .hw.init = &(struct clk_init_data){
2926                         .name = "sata_phy_cfg_clk",
2927                         .ops = &clk_branch_ops,
2928                         .flags = CLK_IS_ROOT,
2929                 },
2930         },
2931 };
2932
2933 static struct clk_branch pcie_phy_ref_clk = {
2934         .halt_reg = 0x2fdc,
2935         .halt_bit = 29,
2936         .clkr = {
2937                 .enable_reg = 0x22d0,
2938                 .enable_mask = BIT(4),
2939                 .hw.init = &(struct clk_init_data){
2940                         .name = "pcie_phy_ref_clk",
2941                         .ops = &clk_branch_ops,
2942                         .flags = CLK_IS_ROOT,
2943                 },
2944         },
2945 };
2946
2947 static struct clk_branch pcie_h_clk = {
2948         .halt_reg = 0x2fd4,
2949         .halt_bit = 8,
2950         .clkr = {
2951                 .enable_reg = 0x22cc,
2952                 .enable_mask = BIT(4),
2953                 .hw.init = &(struct clk_init_data){
2954                         .name = "pcie_h_clk",
2955                         .ops = &clk_branch_ops,
2956                         .flags = CLK_IS_ROOT,
2957                 },
2958         },
2959 };
2960
2961 static struct clk_branch pcie_a_clk = {
2962         .halt_reg = 0x2fc0,
2963         .halt_bit = 13,
2964         .clkr = {
2965                 .enable_reg = 0x22c0,
2966                 .enable_mask = BIT(4),
2967                 .hw.init = &(struct clk_init_data){
2968                         .name = "pcie_a_clk",
2969                         .ops = &clk_branch_ops,
2970                         .flags = CLK_IS_ROOT,
2971                 },
2972         },
2973 };
2974
2975 static struct clk_branch pmic_arb0_h_clk = {
2976         .halt_reg = 0x2fd8,
2977         .halt_check = BRANCH_HALT_VOTED,
2978         .halt_bit = 22,
2979         .clkr = {
2980                 .enable_reg = 0x3080,
2981                 .enable_mask = BIT(8),
2982                 .hw.init = &(struct clk_init_data){
2983                         .name = "pmic_arb0_h_clk",
2984                         .ops = &clk_branch_ops,
2985                         .flags = CLK_IS_ROOT,
2986                 },
2987         },
2988 };
2989
2990 static struct clk_branch pmic_arb1_h_clk = {
2991         .halt_reg = 0x2fd8,
2992         .halt_check = BRANCH_HALT_VOTED,
2993         .halt_bit = 21,
2994         .clkr = {
2995                 .enable_reg = 0x3080,
2996                 .enable_mask = BIT(9),
2997                 .hw.init = &(struct clk_init_data){
2998                         .name = "pmic_arb1_h_clk",
2999                         .ops = &clk_branch_ops,
3000                         .flags = CLK_IS_ROOT,
3001                 },
3002         },
3003 };
3004
3005 static struct clk_branch pmic_ssbi2_clk = {
3006         .halt_reg = 0x2fd8,
3007         .halt_check = BRANCH_HALT_VOTED,
3008         .halt_bit = 23,
3009         .clkr = {
3010                 .enable_reg = 0x3080,
3011                 .enable_mask = BIT(7),
3012                 .hw.init = &(struct clk_init_data){
3013                         .name = "pmic_ssbi2_clk",
3014                         .ops = &clk_branch_ops,
3015                         .flags = CLK_IS_ROOT,
3016                 },
3017         },
3018 };
3019
3020 static struct clk_branch rpm_msg_ram_h_clk = {
3021         .hwcg_reg = 0x27e0,
3022         .hwcg_bit = 6,
3023         .halt_reg = 0x2fd8,
3024         .halt_check = BRANCH_HALT_VOTED,
3025         .halt_bit = 12,
3026         .clkr = {
3027                 .enable_reg = 0x3080,
3028                 .enable_mask = BIT(6),
3029                 .hw.init = &(struct clk_init_data){
3030                         .name = "rpm_msg_ram_h_clk",
3031                         .ops = &clk_branch_ops,
3032                         .flags = CLK_IS_ROOT,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_regmap *gcc_msm8960_clks[] = {
3038         [PLL3] = &pll3.clkr,
3039         [PLL4_VOTE] = &pll4_vote,
3040         [PLL8] = &pll8.clkr,
3041         [PLL8_VOTE] = &pll8_vote,
3042         [PLL14] = &pll14.clkr,
3043         [PLL14_VOTE] = &pll14_vote,
3044         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3045         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3046         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3047         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3048         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3049         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3050         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3051         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3052         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3053         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3054         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3055         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3056         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3057         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3058         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3059         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3060         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3061         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3062         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3063         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3064         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3065         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3066         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3067         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3068         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3069         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3070         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3071         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3072         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3073         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3074         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3075         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3076         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3077         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3078         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3079         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3080         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3081         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3082         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3083         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3084         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3085         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3086         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3087         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3088         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3089         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3090         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3091         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3092         [GP0_SRC] = &gp0_src.clkr,
3093         [GP0_CLK] = &gp0_clk.clkr,
3094         [GP1_SRC] = &gp1_src.clkr,
3095         [GP1_CLK] = &gp1_clk.clkr,
3096         [GP2_SRC] = &gp2_src.clkr,
3097         [GP2_CLK] = &gp2_clk.clkr,
3098         [PMEM_A_CLK] = &pmem_clk.clkr,
3099         [PRNG_SRC] = &prng_src.clkr,
3100         [PRNG_CLK] = &prng_clk.clkr,
3101         [SDC1_SRC] = &sdc1_src.clkr,
3102         [SDC1_CLK] = &sdc1_clk.clkr,
3103         [SDC2_SRC] = &sdc2_src.clkr,
3104         [SDC2_CLK] = &sdc2_clk.clkr,
3105         [SDC3_SRC] = &sdc3_src.clkr,
3106         [SDC3_CLK] = &sdc3_clk.clkr,
3107         [SDC4_SRC] = &sdc4_src.clkr,
3108         [SDC4_CLK] = &sdc4_clk.clkr,
3109         [SDC5_SRC] = &sdc5_src.clkr,
3110         [SDC5_CLK] = &sdc5_clk.clkr,
3111         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3112         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3113         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3114         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3115         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3116         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3117         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3118         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3119         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3120         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3121         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3122         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3123         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3124         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3125         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3126         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3127         [CE1_H_CLK] = &ce1_h_clk.clkr,
3128         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3129         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3130         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3131         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3132         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3133         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3134         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3135         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3136         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3137         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3138         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3139         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3140         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3141         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3142         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3143         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3144         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3145         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3146         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3147         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3148         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3149         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3150         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3151         [ADM0_CLK] = &adm0_clk.clkr,
3152         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3153         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3154         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3155         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3156         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3157 };
3158
3159 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3160         [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3161         [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3162         [QDSS_STM_RESET] = { 0x2060, 6 },
3163         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3164         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3165         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3166         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3167         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3168         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3169         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3170         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3171         [ADM0_C2_RESET] = { 0x220c, 4},
3172         [ADM0_C1_RESET] = { 0x220c, 3},
3173         [ADM0_C0_RESET] = { 0x220c, 2},
3174         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3175         [ADM0_RESET] = { 0x220c },
3176         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3177         [QDSS_POR_RESET] = { 0x2260, 4 },
3178         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3179         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3180         [QDSS_AXI_RESET] = { 0x2260, 1 },
3181         [QDSS_DBG_RESET] = { 0x2260 },
3182         [PCIE_A_RESET] = { 0x22c0, 7 },
3183         [PCIE_AUX_RESET] = { 0x22c8, 7 },
3184         [PCIE_H_RESET] = { 0x22d0, 7 },
3185         [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3186         [SFAB_PCIE_S_RESET] = { 0x22d4 },
3187         [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3188         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3189         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3190         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3191         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3192         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3193         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3194         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3195         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3196         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3197         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3198         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3199         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3200         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3201         [PPSS_PROC_RESET] = { 0x2594, 1 },
3202         [PPSS_RESET] = { 0x2594},
3203         [DMA_BAM_RESET] = { 0x25c0, 7 },
3204         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3205         [SLIMBUS_H_RESET] = { 0x2620, 7 },
3206         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3207         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3208         [TSIF_H_RESET] = { 0x2700, 7 },
3209         [CE1_H_RESET] = { 0x2720, 7 },
3210         [CE1_CORE_RESET] = { 0x2724, 7 },
3211         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3212         [CE2_H_RESET] = { 0x2740, 7 },
3213         [CE2_CORE_RESET] = { 0x2744, 7 },
3214         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3215         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3216         [RPM_PROC_RESET] = { 0x27c0, 7 },
3217         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3218         [SDC1_RESET] = { 0x2830 },
3219         [SDC2_RESET] = { 0x2850 },
3220         [SDC3_RESET] = { 0x2870 },
3221         [SDC4_RESET] = { 0x2890 },
3222         [SDC5_RESET] = { 0x28b0 },
3223         [DFAB_A2_RESET] = { 0x28c0, 7 },
3224         [USB_HS1_RESET] = { 0x2910 },
3225         [USB_HSIC_RESET] = { 0x2934 },
3226         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3227         [USB_FS1_RESET] = { 0x2974 },
3228         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3229         [USB_FS2_RESET] = { 0x2994 },
3230         [GSBI1_RESET] = { 0x29dc },
3231         [GSBI2_RESET] = { 0x29fc },
3232         [GSBI3_RESET] = { 0x2a1c },
3233         [GSBI4_RESET] = { 0x2a3c },
3234         [GSBI5_RESET] = { 0x2a5c },
3235         [GSBI6_RESET] = { 0x2a7c },
3236         [GSBI7_RESET] = { 0x2a9c },
3237         [GSBI8_RESET] = { 0x2abc },
3238         [GSBI9_RESET] = { 0x2adc },
3239         [GSBI10_RESET] = { 0x2afc },
3240         [GSBI11_RESET] = { 0x2b1c },
3241         [GSBI12_RESET] = { 0x2b3c },
3242         [SPDM_RESET] = { 0x2b6c },
3243         [TLMM_H_RESET] = { 0x2ba0, 7 },
3244         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3245         [MSS_SLP_RESET] = { 0x2c60, 7 },
3246         [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3247         [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3248         [MSS_RESET] = { 0x2c64 },
3249         [SATA_H_RESET] = { 0x2c80, 7 },
3250         [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3251         [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3252         [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3253         [TSSC_RESET] = { 0x2ca0, 7 },
3254         [PDM_RESET] = { 0x2cc0, 12 },
3255         [MPM_H_RESET] = { 0x2da0, 7 },
3256         [MPM_RESET] = { 0x2da4 },
3257         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3258         [PRNG_RESET] = { 0x2e80, 12 },
3259         [RIVA_RESET] = { 0x35e0 },
3260 };
3261
3262 static struct clk_regmap *gcc_apq8064_clks[] = {
3263         [PLL3] = &pll3.clkr,
3264         [PLL4_VOTE] = &pll4_vote,
3265         [PLL8] = &pll8.clkr,
3266         [PLL8_VOTE] = &pll8_vote,
3267         [PLL14] = &pll14.clkr,
3268         [PLL14_VOTE] = &pll14_vote,
3269         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3270         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3271         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3272         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3273         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3274         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3275         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3276         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3277         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3278         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3279         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3280         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3281         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3282         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3283         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3284         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3285         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3286         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3287         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3288         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3289         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3290         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3291         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3292         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3293         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3294         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3295         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3296         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3297         [GP0_SRC] = &gp0_src.clkr,
3298         [GP0_CLK] = &gp0_clk.clkr,
3299         [GP1_SRC] = &gp1_src.clkr,
3300         [GP1_CLK] = &gp1_clk.clkr,
3301         [GP2_SRC] = &gp2_src.clkr,
3302         [GP2_CLK] = &gp2_clk.clkr,
3303         [PMEM_A_CLK] = &pmem_clk.clkr,
3304         [PRNG_SRC] = &prng_src.clkr,
3305         [PRNG_CLK] = &prng_clk.clkr,
3306         [SDC1_SRC] = &sdc1_src.clkr,
3307         [SDC1_CLK] = &sdc1_clk.clkr,
3308         [SDC2_SRC] = &sdc2_src.clkr,
3309         [SDC2_CLK] = &sdc2_clk.clkr,
3310         [SDC3_SRC] = &sdc3_src.clkr,
3311         [SDC3_CLK] = &sdc3_clk.clkr,
3312         [SDC4_SRC] = &sdc4_src.clkr,
3313         [SDC4_CLK] = &sdc4_clk.clkr,
3314         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3315         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3316         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3317         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3318         [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3319         [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3320         [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3321         [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3322         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3323         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3324         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3325         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3326         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3327         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3328         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3329         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3330         [SATA_H_CLK] = &sata_h_clk.clkr,
3331         [SATA_CLK_SRC] = &sata_clk_src.clkr,
3332         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3333         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3334         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3335         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3336         [SATA_A_CLK] = &sata_a_clk.clkr,
3337         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3338         [CE3_SRC] = &ce3_src.clkr,
3339         [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3340         [CE3_H_CLK] = &ce3_h_clk.clkr,
3341         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3342         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3343         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3344         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3345         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3346         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3347         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3348         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3349         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3350         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3351         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3352         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3353         [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3354         [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3355         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3356         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3357         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3358         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3359         [ADM0_CLK] = &adm0_clk.clkr,
3360         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3361         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3362         [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3363         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3364         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3365         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3366         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3367         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3368 };
3369
3370 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3371         [QDSS_STM_RESET] = { 0x2060, 6 },
3372         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3373         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3374         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3375         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3376         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3377         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3378         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3379         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3380         [ADM0_C2_RESET] = { 0x220c, 4},
3381         [ADM0_C1_RESET] = { 0x220c, 3},
3382         [ADM0_C0_RESET] = { 0x220c, 2},
3383         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3384         [ADM0_RESET] = { 0x220c },
3385         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3386         [QDSS_POR_RESET] = { 0x2260, 4 },
3387         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3388         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3389         [QDSS_AXI_RESET] = { 0x2260, 1 },
3390         [QDSS_DBG_RESET] = { 0x2260 },
3391         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3392         [SFAB_PCIE_S_RESET] = { 0x22d8 },
3393         [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3394         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3395         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3396         [PCIE_POR_RESET] = { 0x22dc, 3 },
3397         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3398         [PCIE_ACLK_RESET] = { 0x22dc },
3399         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3400         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3401         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3402         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3403         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3404         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3405         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3406         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3407         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3408         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3409         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3410         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3411         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3412         [PPSS_PROC_RESET] = { 0x2594, 1 },
3413         [PPSS_RESET] = { 0x2594},
3414         [DMA_BAM_RESET] = { 0x25c0, 7 },
3415         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3416         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3417         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3418         [TSIF_H_RESET] = { 0x2700, 7 },
3419         [CE1_H_RESET] = { 0x2720, 7 },
3420         [CE1_CORE_RESET] = { 0x2724, 7 },
3421         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3422         [CE2_H_RESET] = { 0x2740, 7 },
3423         [CE2_CORE_RESET] = { 0x2744, 7 },
3424         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3425         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3426         [RPM_PROC_RESET] = { 0x27c0, 7 },
3427         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3428         [SDC1_RESET] = { 0x2830 },
3429         [SDC2_RESET] = { 0x2850 },
3430         [SDC3_RESET] = { 0x2870 },
3431         [SDC4_RESET] = { 0x2890 },
3432         [USB_HS1_RESET] = { 0x2910 },
3433         [USB_HSIC_RESET] = { 0x2934 },
3434         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3435         [USB_FS1_RESET] = { 0x2974 },
3436         [GSBI1_RESET] = { 0x29dc },
3437         [GSBI2_RESET] = { 0x29fc },
3438         [GSBI3_RESET] = { 0x2a1c },
3439         [GSBI4_RESET] = { 0x2a3c },
3440         [GSBI5_RESET] = { 0x2a5c },
3441         [GSBI6_RESET] = { 0x2a7c },
3442         [GSBI7_RESET] = { 0x2a9c },
3443         [SPDM_RESET] = { 0x2b6c },
3444         [TLMM_H_RESET] = { 0x2ba0, 7 },
3445         [SATA_SFAB_M_RESET] = { 0x2c18 },
3446         [SATA_RESET] = { 0x2c1c },
3447         [GSS_SLP_RESET] = { 0x2c60, 7 },
3448         [GSS_RESET] = { 0x2c64 },
3449         [TSSC_RESET] = { 0x2ca0, 7 },
3450         [PDM_RESET] = { 0x2cc0, 12 },
3451         [MPM_H_RESET] = { 0x2da0, 7 },
3452         [MPM_RESET] = { 0x2da4 },
3453         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3454         [PRNG_RESET] = { 0x2e80, 12 },
3455         [RIVA_RESET] = { 0x35e0 },
3456         [CE3_H_RESET] = { 0x36c4, 7 },
3457         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3458         [SFAB_CE3_S_RESET] = { 0x36c8 },
3459         [CE3_RESET] = { 0x36cc, 7 },
3460         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3461         [USB_HS3_RESET] = { 0x3710 },
3462         [USB_HS4_RESET] = { 0x3730 },
3463 };
3464
3465 static const struct regmap_config gcc_msm8960_regmap_config = {
3466         .reg_bits       = 32,
3467         .reg_stride     = 4,
3468         .val_bits       = 32,
3469         .max_register   = 0x3660,
3470         .fast_io        = true,
3471 };
3472
3473 static const struct regmap_config gcc_apq8064_regmap_config = {
3474         .reg_bits       = 32,
3475         .reg_stride     = 4,
3476         .val_bits       = 32,
3477         .max_register   = 0x3880,
3478         .fast_io        = true,
3479 };
3480
3481 static const struct qcom_cc_desc gcc_msm8960_desc = {
3482         .config = &gcc_msm8960_regmap_config,
3483         .clks = gcc_msm8960_clks,
3484         .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3485         .resets = gcc_msm8960_resets,
3486         .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3487 };
3488
3489 static const struct qcom_cc_desc gcc_apq8064_desc = {
3490         .config = &gcc_apq8064_regmap_config,
3491         .clks = gcc_apq8064_clks,
3492         .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3493         .resets = gcc_apq8064_resets,
3494         .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3495 };
3496
3497 static const struct of_device_id gcc_msm8960_match_table[] = {
3498         { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3499         { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3500         { }
3501 };
3502 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3503
3504 static int gcc_msm8960_probe(struct platform_device *pdev)
3505 {
3506         struct clk *clk;
3507         struct device *dev = &pdev->dev;
3508         const struct of_device_id *match;
3509
3510         match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3511         if (!match)
3512                 return -EINVAL;
3513
3514         /* Temporary until RPM clocks supported */
3515         clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
3516         if (IS_ERR(clk))
3517                 return PTR_ERR(clk);
3518
3519         clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
3520         if (IS_ERR(clk))
3521                 return PTR_ERR(clk);
3522
3523         return qcom_cc_probe(pdev, match->data);
3524 }
3525
3526 static int gcc_msm8960_remove(struct platform_device *pdev)
3527 {
3528         qcom_cc_remove(pdev);
3529         return 0;
3530 }
3531
3532 static struct platform_driver gcc_msm8960_driver = {
3533         .probe          = gcc_msm8960_probe,
3534         .remove         = gcc_msm8960_remove,
3535         .driver         = {
3536                 .name   = "gcc-msm8960",
3537                 .of_match_table = gcc_msm8960_match_table,
3538         },
3539 };
3540
3541 static int __init gcc_msm8960_init(void)
3542 {
3543         return platform_driver_register(&gcc_msm8960_driver);
3544 }
3545 core_initcall(gcc_msm8960_init);
3546
3547 static void __exit gcc_msm8960_exit(void)
3548 {
3549         platform_driver_unregister(&gcc_msm8960_driver);
3550 }
3551 module_exit(gcc_msm8960_exit);
3552
3553 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3554 MODULE_LICENSE("GPL v2");
3555 MODULE_ALIAS("platform:gcc-msm8960");