kernel/drivers/clk/pistachio/clk-pistachio.c

   1 /*
   2  * Pistachio SoC clock controllers
   3  *
   4  * Copyright (C) 2014 Google, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of.h>
  16
  17 #include <dt-bindings/clock/pistachio-clk.h>
  18
  19 #include "clk.h"
  20
  21 static struct pistachio_gate pistachio_gates[] __initdata = {
  22         GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
  23         GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
  24         GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
  25         GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
  26         GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
  27         GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
  28         GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
  29         GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
  30         GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
  31         GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
  32         GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
  33         GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
  34         GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
  35         GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
  36         GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
  37         GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
  38         GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
  39         GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
  40         GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
  41         GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
  42         GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
  43         GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
  44         GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
  45              0x104, 22),
  46         GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
  47         GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
  48         GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
  49         GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
  50         GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
  51         GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
  52 };
  53
  54 static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
  55         FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
  56         FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
  57 };
  58
  59 static struct pistachio_div pistachio_divs[] __initdata = {
  60         DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
  61             0x204, 2),
  62         DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
  63         DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
  64                 0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
  65         DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
  66                 0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
  67         DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
  68                 0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
  69         DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
  70                 0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
  71         DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
  72         DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
  73         DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
  74         DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
  75         DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
  76         DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
  77         DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
  78               0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
  79         DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
  80               CLK_DIVIDER_ROUND_CLOSEST),
  81         DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
  82               0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
  83         DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
  84               CLK_DIVIDER_ROUND_CLOSEST),
  85         DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
  86         DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
  87             0x248, 3),
  88         DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
  89         DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
  90             0x250, 3),
  91         DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
  92         DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
  93             "event_timer_mux", 0x258, 3),
  94         DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
  95             0x25c, 12),
  96         DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
  97             "aux_adc_internal", 0x260, 3),
  98         DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
  99         DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
 100         DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
 101         DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
 102         DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
 103         DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
 104             0x278, 3),
 105         DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
 106 };
 107
 108 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
 109 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
 110 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
 111 PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
 112 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
 113 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
 114 PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
 115 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
 116 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
 117 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
 118 PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
 119                                "rpu_l_pll_mux" };
 120 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
 121 PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
 122 PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
 123 PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
 124 PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
 125
 126 static struct pistachio_mux pistachio_muxes[] __initdata = {
 127         MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
 128             0x200, 0),
 129         MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
 130         MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
 131         MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
 132         MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
 133         MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
 134         MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
 135         MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
 136         MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
 137         MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
 138         MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
 139         MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
 140         MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
 141         MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
 142         MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
 143         MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
 144 };
 145
 146 static struct pistachio_pll pistachio_plls[] __initdata = {
 147         PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
 148         PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
 149                   PLL_GF40LP_FRAC, 0xc),
 150         PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
 151         PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
 152         PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
 153         PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
 154         PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
 155 };
 156
 157 PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
 158                      "rpu_l_pll_mux", "sys_pll_mux",
 159                      "wifi_pll_mux", "bt_pll_mux" };
 160 static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
 161
 162 static unsigned int pistachio_critical_clks_core[] __initdata = {
 163         CLK_MIPS
 164 };
 165
 166 static unsigned int pistachio_critical_clks_sys[] __initdata = {
 167         PERIPH_CLK_SYS,
 168         PERIPH_CLK_SYS_BUS,
 169         PERIPH_CLK_DDR,
 170         PERIPH_CLK_ROM,
 171 };
 172
 173 static void __init pistachio_clk_init(struct device_node *np)
 174 {
 175         struct pistachio_clk_provider *p;
 176         struct clk *debug_clk;
 177
 178         p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
 179         if (!p)
 180                 return;
 181
 182         pistachio_clk_register_pll(p, pistachio_plls,
 183                                    ARRAY_SIZE(pistachio_plls));
 184         pistachio_clk_register_mux(p, pistachio_muxes,
 185                                    ARRAY_SIZE(pistachio_muxes));
 186         pistachio_clk_register_div(p, pistachio_divs,
 187                                    ARRAY_SIZE(pistachio_divs));
 188         pistachio_clk_register_fixed_factor(p, pistachio_ffs,
 189                                             ARRAY_SIZE(pistachio_ffs));
 190         pistachio_clk_register_gate(p, pistachio_gates,
 191                                     ARRAY_SIZE(pistachio_gates));
 192
 193         debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
 194                                            ARRAY_SIZE(mux_debug),
 195                                            CLK_SET_RATE_NO_REPARENT,
 196                                            p->base + 0x200, 18, 0x1f, 0,
 197                                            mux_debug_idx, NULL);
 198         p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
 199
 200         pistachio_clk_register_provider(p);
 201
 202         pistachio_clk_force_enable(p, pistachio_critical_clks_core,
 203                                    ARRAY_SIZE(pistachio_critical_clks_core));
 204 }
 205 CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
 206
 207 static struct pistachio_gate pistachio_periph_gates[] __initdata = {
 208         GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
 209         GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
 210         GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
 211         GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
 212         GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",
 213              0x100, 4),
 214         GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",
 215              0x100, 5),
 216         GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
 217         GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
 218         GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
 219         GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
 220         GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
 221         GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
 222         GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
 223         GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
 224 };
 225
 226 static struct pistachio_div pistachio_periph_divs[] __initdata = {
 227         DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),
 228         DIV(PERIPH_CLK_COUNTER_FAST_DIV, "counter_fast_div", "periph_sys",
 229             0x110, 7),
 230         DIV(PERIPH_CLK_COUNTER_SLOW_PRE_DIV, "counter_slow_pre_div",
 231             "periph_sys", 0x114, 7),
 232         DIV(PERIPH_CLK_COUNTER_SLOW_DIV, "counter_slow_div",
 233             "counter_slow_pre_div", 0x118, 7),
 234         DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
 235               CLK_DIVIDER_ROUND_CLOSEST),
 236         DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
 237               CLK_DIVIDER_ROUND_CLOSEST),
 238         DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,
 239               CLK_DIVIDER_ROUND_CLOSEST),
 240         DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,
 241               CLK_DIVIDER_ROUND_CLOSEST),
 242         DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),
 243         DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),
 244         DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),
 245         DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),
 246         DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),
 247         DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),
 248         DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),
 249         DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),
 250         DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),
 251         DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),
 252         DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),
 253         DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),
 254 };
 255
 256 static void __init pistachio_clk_periph_init(struct device_node *np)
 257 {
 258         struct pistachio_clk_provider *p;
 259
 260         p = pistachio_clk_alloc_provider(np, PERIPH_CLK_NR_CLKS);
 261         if (!p)
 262                 return;
 263
 264         pistachio_clk_register_div(p, pistachio_periph_divs,
 265                                    ARRAY_SIZE(pistachio_periph_divs));
 266         pistachio_clk_register_gate(p, pistachio_periph_gates,
 267                                     ARRAY_SIZE(pistachio_periph_gates));
 268
 269         pistachio_clk_register_provider(p);
 270
 271         pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
 272                                    ARRAY_SIZE(pistachio_critical_clks_sys));
 273 }
 274 CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
 275                pistachio_clk_periph_init);
 276
 277 static struct pistachio_gate pistachio_sys_gates[] __initdata = {
 278         GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
 279         GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
 280         GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
 281         GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
 282         GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
 283         GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
 284         GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
 285         GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
 286         GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
 287         GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
 288         GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
 289         GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
 290         GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
 291         GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
 292         GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
 293         GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
 294         GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
 295         GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
 296         GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
 297         GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
 298         GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
 299         GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
 300         GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
 301 };
 302
 303 static void __init pistachio_cr_periph_init(struct device_node *np)
 304 {
 305         struct pistachio_clk_provider *p;
 306
 307         p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);
 308         if (!p)
 309                 return;
 310
 311         pistachio_clk_register_gate(p, pistachio_sys_gates,
 312                                     ARRAY_SIZE(pistachio_sys_gates));
 313
 314         pistachio_clk_register_provider(p);
 315 }
 316 CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",
 317                pistachio_cr_periph_init);
 318
 319 static struct pistachio_gate pistachio_ext_gates[] __initdata = {
 320         GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
 321         GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)
 322 };
 323
 324 static void __init pistachio_cr_top_init(struct device_node *np)
 325 {
 326         struct pistachio_clk_provider *p;
 327
 328         p = pistachio_clk_alloc_provider(np, EXT_CLK_NR_CLKS);
 329         if (!p)
 330                 return;
 331
 332         pistachio_clk_register_gate(p, pistachio_ext_gates,
 333                                     ARRAY_SIZE(pistachio_ext_gates));
 334
 335         pistachio_clk_register_provider(p);
 336 }
 337 CLK_OF_DECLARE(pistachio_cr_top, "img,pistachio-cr-top",
 338                pistachio_cr_top_init);