2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
58 #define CREATE_TRACE_POINTS
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126 static bool __read_mostly backwards_tsc_observed = false;
128 #define KVM_NR_SHARED_MSRS 16
130 struct kvm_shared_msrs_global {
132 u32 msrs[KVM_NR_SHARED_MSRS];
135 struct kvm_shared_msrs {
136 struct user_return_notifier urn;
138 struct kvm_shared_msr_values {
141 } values[KVM_NR_SHARED_MSRS];
144 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
145 static struct kvm_shared_msrs __percpu *shared_msrs;
147 struct kvm_stats_debugfs_item debugfs_entries[] = {
148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
158 { "halt_exits", VCPU_STAT(halt_exits) },
159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
162 { "hypercalls", VCPU_STAT(hypercalls) },
163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
170 { "irq_injections", VCPU_STAT(irq_injections) },
171 { "nmi_injections", VCPU_STAT(nmi_injections) },
172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
179 { "mmu_unsync", VM_STAT(mmu_unsync) },
180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
181 { "largepages", VM_STAT(lpages) },
185 u64 __read_mostly host_xcr0;
187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
189 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
196 static void kvm_on_user_return(struct user_return_notifier *urn)
199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
201 struct kvm_shared_msr_values *values;
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
214 static void shared_msr_update(unsigned slot, u32 msr)
217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
231 void kvm_define_shared_msr(unsigned slot, u32 msr)
233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
234 shared_msrs_global.msrs[slot] = msr;
235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
238 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
240 static void kvm_shared_msr_cpu_online(void)
244 for (i = 0; i < shared_msrs_global.nr; ++i)
245 shared_msr_update(i, shared_msrs_global.msrs[i]);
248 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
256 smsr->values[slot].curr = value;
257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
268 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
270 static void drop_user_return_notifiers(void)
272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
279 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
281 return vcpu->arch.apic_base;
283 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
285 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 kvm_lapic_set_base(vcpu, msr_info->data);
306 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
308 asmlinkage __visible void kvm_spurious_fault(void)
310 /* Fault while not rebooting. We want the trace. */
313 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
315 #define EXCPT_BENIGN 0
316 #define EXCPT_CONTRIBUTORY 1
319 static int exception_class(int vector)
329 return EXCPT_CONTRIBUTORY;
336 #define EXCPT_FAULT 0
338 #define EXCPT_ABORT 2
339 #define EXCPT_INTERRUPT 3
341 static int exception_type(int vector)
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
357 /* Reserved exceptions will result in fault */
361 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
362 unsigned nr, bool has_error, u32 error_code,
368 kvm_make_request(KVM_REQ_EVENT, vcpu);
370 if (!vcpu->arch.exception.pending) {
372 if (has_error && !is_protmode(vcpu))
374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
378 vcpu->arch.exception.reinject = reinject;
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
405 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
407 kvm_multiple_exception(vcpu, nr, false, 0, false);
409 EXPORT_SYMBOL_GPL(kvm_queue_exception);
411 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
415 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
417 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
420 kvm_inject_gp(vcpu, 0);
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
424 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
426 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
428 ++vcpu->stat.pf_guest;
429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
432 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
434 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
441 return fault->nested_page_fault;
444 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
449 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
451 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
455 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
457 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
461 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
467 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
474 EXPORT_SYMBOL_GPL(kvm_require_cpl);
476 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
481 kvm_queue_exception(vcpu, UD_VECTOR);
484 EXPORT_SYMBOL_GPL(kvm_require_dr);
487 * This function will be used to read from the physical memory of the currently
488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
489 * can read from guest physical or from the guest's guest physical memory.
491 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
495 struct x86_exception exception;
499 ngpa = gfn_to_gpa(ngfn);
500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
501 if (real_gfn == UNMAPPED_GVA)
504 real_gfn = gpa_to_gfn(real_gfn);
506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
508 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
510 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
511 void *data, int offset, int len, u32 access)
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
518 * Load the pae pdptrs. Return true is they are all valid.
520 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
536 if (is_present_gpte(pdpte[i]) &&
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
554 EXPORT_SYMBOL_GPL(load_pdptrs);
556 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
583 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
591 if (cr0 & 0xffffffff00000000UL)
595 cr0 &= ~CR0_RESERVED_BITS;
597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
605 if ((vcpu->arch.efer & EFER_LME)) {
610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
623 kvm_x86_ops->set_cr0(vcpu, cr0);
625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
626 kvm_clear_async_pf_completion_queue(vcpu);
627 kvm_async_pf_hash_reset(vcpu);
630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640 EXPORT_SYMBOL_GPL(kvm_set_cr0);
642 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
646 EXPORT_SYMBOL_GPL(kvm_lmsw);
648 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
658 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
667 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
670 u64 old_xcr0 = vcpu->arch.xcr0;
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
676 if (!(xcr0 & XFEATURE_MASK_FP))
678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
687 if (xcr0 & ~valid_bits)
690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
700 kvm_put_guest_xcr0(vcpu);
701 vcpu->arch.xcr0 = xcr0;
703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
704 kvm_update_cpuid(vcpu);
708 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
712 kvm_inject_gp(vcpu, 0);
717 EXPORT_SYMBOL_GPL(kvm_set_xcr);
719 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
725 if (cr4 & CR4_RESERVED_BITS)
728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
740 if (is_long_mode(vcpu)) {
741 if (!(cr4 & X86_CR4_PAE))
743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
763 kvm_mmu_reset_context(vcpu);
765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
766 kvm_update_cpuid(vcpu);
770 EXPORT_SYMBOL_GPL(kvm_set_cr4);
772 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
775 cr3 &= ~CR3_PCID_INVD;
778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
779 kvm_mmu_sync_roots(vcpu);
780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
784 if (is_long_mode(vcpu)) {
785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
791 vcpu->arch.cr3 = cr3;
792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
793 kvm_mmu_new_cr3(vcpu);
796 EXPORT_SYMBOL_GPL(kvm_set_cr3);
798 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
800 if (cr8 & CR8_RESERVED_BITS)
802 if (lapic_in_kernel(vcpu))
803 kvm_lapic_set_tpr(vcpu, cr8);
805 vcpu->arch.cr8 = cr8;
808 EXPORT_SYMBOL_GPL(kvm_set_cr8);
810 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
812 if (lapic_in_kernel(vcpu))
813 return kvm_lapic_get_cr8(vcpu);
815 return vcpu->arch.cr8;
817 EXPORT_SYMBOL_GPL(kvm_get_cr8);
819 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
830 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
836 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
850 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
852 u64 fixed = DR6_FIXED_1;
854 if (!guest_cpuid_has_rtm(vcpu))
859 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
870 if (val & 0xffffffff00000000ULL)
872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
873 kvm_update_dr6(vcpu);
878 if (val & 0xffffffff00000000ULL)
880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
881 kvm_update_dr7(vcpu);
888 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
890 if (__kvm_set_dr(vcpu, dr, val)) {
891 kvm_inject_gp(vcpu, 0);
896 EXPORT_SYMBOL_GPL(kvm_set_dr);
898 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
902 *val = vcpu->arch.db[dr];
907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
910 *val = kvm_x86_ops->get_dr6(vcpu);
915 *val = vcpu->arch.dr7;
920 EXPORT_SYMBOL_GPL(kvm_get_dr);
922 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
935 EXPORT_SYMBOL_GPL(kvm_rdpmc);
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
941 * This list is modified at module load time to reflect the
942 * capabilities of the host cpu. This capabilities test skips MSRs that are
943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
947 static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
957 static unsigned num_msrs_to_save;
959 static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
968 HV_X64_MSR_VP_RUNTIME,
969 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
973 MSR_IA32_TSCDEADLINE,
974 MSR_IA32_MISC_ENABLE,
980 static unsigned num_emulated_msrs;
982 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
984 if (efer & efer_reserved_bits)
987 if (efer & EFER_FFXSR) {
988 struct kvm_cpuid_entry2 *feat;
990 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
991 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
995 if (efer & EFER_SVME) {
996 struct kvm_cpuid_entry2 *feat;
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
999 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1005 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1007 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1009 u64 old_efer = vcpu->arch.efer;
1011 if (!kvm_valid_efer(vcpu, efer))
1015 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1019 efer |= vcpu->arch.efer & EFER_LMA;
1021 kvm_x86_ops->set_efer(vcpu, efer);
1023 /* Update reserved bits */
1024 if ((efer ^ old_efer) & EFER_NX)
1025 kvm_mmu_reset_context(vcpu);
1030 void kvm_enable_efer_bits(u64 mask)
1032 efer_reserved_bits &= ~mask;
1034 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037 * Writes msr value into into the appropriate "register".
1038 * Returns 0 on success, non-0 otherwise.
1039 * Assumes vcpu_load() was already called.
1041 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1043 switch (msr->index) {
1046 case MSR_KERNEL_GS_BASE:
1049 if (is_noncanonical_address(msr->data))
1052 case MSR_IA32_SYSENTER_EIP:
1053 case MSR_IA32_SYSENTER_ESP:
1055 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1056 * non-canonical address is written on Intel but not on
1057 * AMD (which ignores the top 32-bits, because it does
1058 * not implement 64-bit SYSENTER).
1060 * 64-bit code should hence be able to write a non-canonical
1061 * value on AMD. Making the address canonical ensures that
1062 * vmentry does not fail on Intel after writing a non-canonical
1063 * value, and that something deterministic happens if the guest
1064 * invokes 64-bit SYSENTER.
1066 msr->data = get_canonical(msr->data);
1068 return kvm_x86_ops->set_msr(vcpu, msr);
1070 EXPORT_SYMBOL_GPL(kvm_set_msr);
1073 * Adapt set_msr() to msr_io()'s calling convention
1075 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1077 struct msr_data msr;
1081 msr.host_initiated = true;
1082 r = kvm_get_msr(vcpu, &msr);
1090 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092 struct msr_data msr;
1096 msr.host_initiated = true;
1097 return kvm_set_msr(vcpu, &msr);
1100 #ifdef CONFIG_X86_64
1101 struct pvclock_gtod_data {
1104 struct { /* extract of a clocksource struct */
1116 static struct pvclock_gtod_data pvclock_gtod_data;
1118 static void update_pvclock_gtod(struct timekeeper *tk)
1120 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1123 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1125 write_seqcount_begin(&vdata->seq);
1127 /* copy pvclock gtod data */
1128 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1129 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1130 vdata->clock.mask = tk->tkr_mono.mask;
1131 vdata->clock.mult = tk->tkr_mono.mult;
1132 vdata->clock.shift = tk->tkr_mono.shift;
1134 vdata->boot_ns = boot_ns;
1135 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1137 write_seqcount_end(&vdata->seq);
1141 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1145 * vcpu_enter_guest. This function is only called from
1146 * the physical CPU that is running vcpu.
1148 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1155 struct pvclock_wall_clock wc;
1156 struct timespec boot;
1161 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1166 ++version; /* first time write, random junk */
1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1173 * The guest calculates current wall clock time by adding
1174 * system time (updated by kvm_guest_time_update below) to the
1175 * wall clock specified here. guest system time equals host
1176 * system time for us, thus we must fill in host boot time here.
1180 if (kvm->arch.kvmclock_offset) {
1181 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1182 boot = timespec_sub(boot, ts);
1184 wc.sec = boot.tv_sec;
1185 wc.nsec = boot.tv_nsec;
1186 wc.version = version;
1188 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1191 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1194 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1196 uint32_t quotient, remainder;
1198 /* Don't try to replace with do_div(), this one calculates
1199 * "(dividend << 32) / divisor" */
1201 : "=a" (quotient), "=d" (remainder)
1202 : "0" (0), "1" (dividend), "r" (divisor) );
1206 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1207 s8 *pshift, u32 *pmultiplier)
1214 tps64 = base_khz * 1000LL;
1215 scaled64 = scaled_khz * 1000LL;
1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1221 tps32 = (uint32_t)tps64;
1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1231 *pmultiplier = div_frac(scaled64, tps32);
1233 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1234 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1237 #ifdef CONFIG_X86_64
1238 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1241 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1242 static unsigned long max_tsc_khz;
1244 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
1250 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1252 u64 v = (u64)khz * (1000000 + ppm);
1257 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261 /* Guest TSC same frequency as host TSC? */
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1293 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
1298 /* tsc_khz can be zero if TSC calibration fails */
1299 if (this_tsc_khz == 0) {
1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1305 /* Compute a scale to convert nanoseconds in TSC cycles */
1306 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
1309 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1319 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1323 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1326 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
1331 tsc += vcpu->arch.this_tsc_write;
1335 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1337 #ifdef CONFIG_X86_64
1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1363 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370 * Multiply tsc by a fixed point number represented by ratio.
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1379 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1384 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1394 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1396 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1402 return target_tsc - tsc;
1405 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1409 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1411 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1413 struct kvm *kvm = vcpu->kvm;
1414 u64 offset, ns, elapsed;
1415 unsigned long flags;
1418 bool already_matched;
1419 u64 data = msr->data;
1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1422 offset = kvm_compute_tsc_offset(vcpu, data);
1423 ns = get_kernel_ns();
1424 elapsed = ns - kvm->arch.last_tsc_nsec;
1426 if (vcpu->arch.virtual_tsc_khz) {
1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
1431 #ifdef CONFIG_X86_64
1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1434 /* do_div() only does unsigned */
1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1444 _ASM_EXTABLE(1b, 4b)
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1450 do_div(elapsed, 1000);
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1457 usdiff = USEC_PER_SEC;
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1471 if (usdiff < USEC_PER_SEC &&
1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1473 if (!check_tsc_unstable()) {
1474 offset = kvm->arch.cur_tsc_offset;
1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
1479 offset = kvm_compute_tsc_offset(vcpu, data);
1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
1490 * exact software computation in compute_guest_tsc()
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1500 kvm->arch.cur_tsc_generation, data);
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1511 vcpu->arch.last_guest_tsc = data;
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1525 kvm->arch.nr_vcpus_matched_tsc = 0;
1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1534 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1536 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1542 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1550 #ifdef CONFIG_X86_64
1552 static cycle_t read_tsc(void)
1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
1557 if (likely(ret >= last))
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1572 static inline u64 vgettsc(cycle_t *cycle_now)
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1577 *cycle_now = read_tsc();
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1583 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1591 seq = read_seqcount_begin(>od->seq);
1592 mode = gtod->clock.vclock_mode;
1593 ns = gtod->nsec_base;
1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
1596 ns += gtod->boot_ns;
1597 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1603 /* returns true if host is using tsc clocksource */
1604 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
1619 * CPUs at the next numbered event.
1621 * "timespecX" represents host monotonic time. "tscX" represents
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1639 * - 0 < N - M => M < N
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1655 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1657 #ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1660 bool host_tsc_clocksource, vcpus_matched;
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
1666 * If the host uses TSC clock, then passthrough TSC as stable
1669 host_tsc_clocksource = kvm_get_time_and_clockread(
1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1686 static void kvm_gen_update_masterclock(struct kvm *kvm)
1688 #ifdef CONFIG_X86_64
1690 struct kvm_vcpu *vcpu;
1691 struct kvm_arch *ka = &kvm->arch;
1693 spin_lock(&ka->pvclock_gtod_sync_lock);
1694 kvm_make_mclock_inprogress_request(kvm);
1695 /* no guest entries from this point */
1696 pvclock_update_vm_gtod_copy(kvm);
1698 kvm_for_each_vcpu(i, vcpu, kvm)
1699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1701 /* guest entries allowed */
1702 kvm_for_each_vcpu(i, vcpu, kvm)
1703 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1705 spin_unlock(&ka->pvclock_gtod_sync_lock);
1709 static int kvm_guest_time_update(struct kvm_vcpu *v)
1711 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
1712 struct kvm_vcpu_arch *vcpu = &v->arch;
1713 struct kvm_arch *ka = &v->kvm->arch;
1715 u64 tsc_timestamp, host_tsc;
1716 struct pvclock_vcpu_time_info guest_hv_clock;
1718 bool use_master_clock;
1724 * If the host uses TSC clock, then passthrough TSC as stable
1727 spin_lock(&ka->pvclock_gtod_sync_lock);
1728 use_master_clock = ka->use_master_clock;
1729 if (use_master_clock) {
1730 host_tsc = ka->master_cycle_now;
1731 kernel_ns = ka->master_kernel_ns;
1733 spin_unlock(&ka->pvclock_gtod_sync_lock);
1735 /* Keep irq disabled to prevent changes to the clock */
1736 local_irq_save(flags);
1737 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1738 if (unlikely(this_tsc_khz == 0)) {
1739 local_irq_restore(flags);
1740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1743 if (!use_master_clock) {
1745 kernel_ns = get_kernel_ns();
1748 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1751 * We may have to catch up the TSC to match elapsed wall clock
1752 * time for two reasons, even if kvmclock is used.
1753 * 1) CPU could have been running below the maximum TSC rate
1754 * 2) Broken TSC compensation resets the base at each VCPU
1755 * entry to avoid unknown leaps of TSC even when running
1756 * again on the same CPU. This may cause apparent elapsed
1757 * time to disappear, and the guest to stand still or run
1760 if (vcpu->tsc_catchup) {
1761 u64 tsc = compute_guest_tsc(v, kernel_ns);
1762 if (tsc > tsc_timestamp) {
1763 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1764 tsc_timestamp = tsc;
1768 local_irq_restore(flags);
1770 if (!vcpu->pv_time_enabled)
1773 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1774 tgt_tsc_khz = kvm_has_tsc_control ?
1775 vcpu->virtual_tsc_khz : this_tsc_khz;
1776 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
1777 &vcpu->hv_clock.tsc_shift,
1778 &vcpu->hv_clock.tsc_to_system_mul);
1779 vcpu->hw_tsc_khz = this_tsc_khz;
1782 /* With all the info we got, fill in the values */
1783 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1784 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1785 vcpu->last_guest_tsc = tsc_timestamp;
1787 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1788 &guest_hv_clock, sizeof(guest_hv_clock))))
1791 /* This VCPU is paused, but it's legal for a guest to read another
1792 * VCPU's kvmclock, so we really have to follow the specification where
1793 * it says that version is odd if data is being modified, and even after
1796 * Version field updates must be kept separate. This is because
1797 * kvm_write_guest_cached might use a "rep movs" instruction, and
1798 * writes within a string instruction are weakly ordered. So there
1799 * are three writes overall.
1801 * As a small optimization, only write the version field in the first
1802 * and third write. The vcpu->pv_time cache is still valid, because the
1803 * version field is the first in the struct.
1805 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1807 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1808 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1810 sizeof(vcpu->hv_clock.version));
1814 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1815 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1817 if (vcpu->pvclock_set_guest_stopped_request) {
1818 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1819 vcpu->pvclock_set_guest_stopped_request = false;
1822 /* If the host uses TSC clocksource, then it is stable */
1823 if (use_master_clock)
1824 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1826 vcpu->hv_clock.flags = pvclock_flags;
1828 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1830 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1832 sizeof(vcpu->hv_clock));
1836 vcpu->hv_clock.version++;
1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 sizeof(vcpu->hv_clock.version));
1844 * kvmclock updates which are isolated to a given vcpu, such as
1845 * vcpu->cpu migration, should not allow system_timestamp from
1846 * the rest of the vcpus to remain static. Otherwise ntp frequency
1847 * correction applies to one vcpu's system_timestamp but not
1850 * So in those cases, request a kvmclock update for all vcpus.
1851 * We need to rate-limit these requests though, as they can
1852 * considerably slow guests that have a large number of vcpus.
1853 * The time for a remote vcpu to update its kvmclock is bound
1854 * by the delay we use to rate-limit the updates.
1857 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1859 static void kvmclock_update_fn(struct work_struct *work)
1862 struct delayed_work *dwork = to_delayed_work(work);
1863 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1864 kvmclock_update_work);
1865 struct kvm *kvm = container_of(ka, struct kvm, arch);
1866 struct kvm_vcpu *vcpu;
1868 kvm_for_each_vcpu(i, vcpu, kvm) {
1869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1870 kvm_vcpu_kick(vcpu);
1874 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1876 struct kvm *kvm = v->kvm;
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1879 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1880 KVMCLOCK_UPDATE_DELAY);
1883 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1885 static void kvmclock_sync_fn(struct work_struct *work)
1887 struct delayed_work *dwork = to_delayed_work(work);
1888 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1889 kvmclock_sync_work);
1890 struct kvm *kvm = container_of(ka, struct kvm, arch);
1892 if (!kvmclock_periodic_sync)
1895 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1896 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1897 KVMCLOCK_SYNC_PERIOD);
1900 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1902 u64 mcg_cap = vcpu->arch.mcg_cap;
1903 unsigned bank_num = mcg_cap & 0xff;
1906 case MSR_IA32_MCG_STATUS:
1907 vcpu->arch.mcg_status = data;
1909 case MSR_IA32_MCG_CTL:
1910 if (!(mcg_cap & MCG_CTL_P))
1912 if (data != 0 && data != ~(u64)0)
1914 vcpu->arch.mcg_ctl = data;
1917 if (msr >= MSR_IA32_MC0_CTL &&
1918 msr < MSR_IA32_MCx_CTL(bank_num)) {
1919 u32 offset = msr - MSR_IA32_MC0_CTL;
1920 /* only 0 or all 1s can be written to IA32_MCi_CTL
1921 * some Linux kernels though clear bit 10 in bank 4 to
1922 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1923 * this to avoid an uncatched #GP in the guest
1925 if ((offset & 0x3) == 0 &&
1926 data != 0 && (data | (1 << 10)) != ~(u64)0)
1928 vcpu->arch.mce_banks[offset] = data;
1936 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1938 struct kvm *kvm = vcpu->kvm;
1939 int lm = is_long_mode(vcpu);
1940 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1941 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1942 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1943 : kvm->arch.xen_hvm_config.blob_size_32;
1944 u32 page_num = data & ~PAGE_MASK;
1945 u64 page_addr = data & PAGE_MASK;
1950 if (page_num >= blob_size)
1953 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1958 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1967 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1969 gpa_t gpa = data & ~0x3f;
1971 /* Bits 2:5 are reserved, Should be zero */
1975 vcpu->arch.apf.msr_val = data;
1977 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1978 kvm_clear_async_pf_completion_queue(vcpu);
1979 kvm_async_pf_hash_reset(vcpu);
1983 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1987 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1988 kvm_async_pf_wakeup_all(vcpu);
1992 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1994 vcpu->arch.pv_time_enabled = false;
1997 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2004 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2005 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2006 vcpu->arch.st.accum_steal = delta;
2009 static void record_steal_time(struct kvm_vcpu *vcpu)
2011 accumulate_steal_time(vcpu);
2013 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2016 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2017 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2020 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2021 vcpu->arch.st.steal.version += 2;
2022 vcpu->arch.st.accum_steal = 0;
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2028 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2031 u32 msr = msr_info->index;
2032 u64 data = msr_info->data;
2035 case MSR_AMD64_NB_CFG:
2036 case MSR_IA32_UCODE_REV:
2037 case MSR_IA32_UCODE_WRITE:
2038 case MSR_VM_HSAVE_PA:
2039 case MSR_AMD64_PATCH_LOADER:
2040 case MSR_AMD64_BU_CFG2:
2044 return set_efer(vcpu, data);
2046 data &= ~(u64)0x40; /* ignore flush filter disable */
2047 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2048 data &= ~(u64)0x8; /* ignore TLB cache disable */
2049 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2051 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2056 case MSR_FAM10H_MMIO_CONF_BASE:
2058 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2063 case MSR_IA32_DEBUGCTLMSR:
2065 /* We support the non-activated case already */
2067 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2068 /* Values other than LBR and BTF are vendor-specific,
2069 thus reserved and should throw a #GP */
2072 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2075 case 0x200 ... 0x2ff:
2076 return kvm_mtrr_set_msr(vcpu, msr, data);
2077 case MSR_IA32_APICBASE:
2078 return kvm_set_apic_base(vcpu, msr_info);
2079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2080 return kvm_x2apic_msr_write(vcpu, msr, data);
2081 case MSR_IA32_TSCDEADLINE:
2082 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2084 case MSR_IA32_TSC_ADJUST:
2085 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2086 if (!msr_info->host_initiated) {
2087 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2088 adjust_tsc_offset_guest(vcpu, adj);
2090 vcpu->arch.ia32_tsc_adjust_msr = data;
2093 case MSR_IA32_MISC_ENABLE:
2094 vcpu->arch.ia32_misc_enable_msr = data;
2096 case MSR_IA32_SMBASE:
2097 if (!msr_info->host_initiated)
2099 vcpu->arch.smbase = data;
2101 case MSR_KVM_WALL_CLOCK_NEW:
2102 case MSR_KVM_WALL_CLOCK:
2103 vcpu->kvm->arch.wall_clock = data;
2104 kvm_write_wall_clock(vcpu->kvm, data);
2106 case MSR_KVM_SYSTEM_TIME_NEW:
2107 case MSR_KVM_SYSTEM_TIME: {
2109 struct kvm_arch *ka = &vcpu->kvm->arch;
2111 kvmclock_reset(vcpu);
2113 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2114 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2116 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2117 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2120 ka->boot_vcpu_runs_old_kvmclock = tmp;
2123 vcpu->arch.time = data;
2124 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2126 /* we verify if the enable bit is set... */
2130 gpa_offset = data & ~(PAGE_MASK | 1);
2132 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2133 &vcpu->arch.pv_time, data & ~1ULL,
2134 sizeof(struct pvclock_vcpu_time_info)))
2135 vcpu->arch.pv_time_enabled = false;
2137 vcpu->arch.pv_time_enabled = true;
2141 case MSR_KVM_ASYNC_PF_EN:
2142 if (kvm_pv_enable_async_pf(vcpu, data))
2145 case MSR_KVM_STEAL_TIME:
2147 if (unlikely(!sched_info_on()))
2150 if (data & KVM_STEAL_RESERVED_MASK)
2153 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2154 data & KVM_STEAL_VALID_BITS,
2155 sizeof(struct kvm_steal_time)))
2158 vcpu->arch.st.msr_val = data;
2160 if (!(data & KVM_MSR_ENABLED))
2163 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2166 case MSR_KVM_PV_EOI_EN:
2167 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2171 case MSR_IA32_MCG_CTL:
2172 case MSR_IA32_MCG_STATUS:
2173 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2174 return set_msr_mce(vcpu, msr, data);
2176 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2177 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2178 pr = true; /* fall through */
2179 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2180 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2181 if (kvm_pmu_is_valid_msr(vcpu, msr))
2182 return kvm_pmu_set_msr(vcpu, msr_info);
2184 if (pr || data != 0)
2185 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2186 "0x%x data 0x%llx\n", msr, data);
2188 case MSR_K7_CLK_CTL:
2190 * Ignore all writes to this no longer documented MSR.
2191 * Writes are only relevant for old K7 processors,
2192 * all pre-dating SVM, but a recommended workaround from
2193 * AMD for these chips. It is possible to specify the
2194 * affected processor models on the command line, hence
2195 * the need to ignore the workaround.
2198 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2199 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2200 case HV_X64_MSR_CRASH_CTL:
2201 return kvm_hv_set_msr_common(vcpu, msr, data,
2202 msr_info->host_initiated);
2203 case MSR_IA32_BBL_CR_CTL3:
2204 /* Drop writes to this legacy MSR -- see rdmsr
2205 * counterpart for further detail.
2207 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2209 case MSR_AMD64_OSVW_ID_LENGTH:
2210 if (!guest_cpuid_has_osvw(vcpu))
2212 vcpu->arch.osvw.length = data;
2214 case MSR_AMD64_OSVW_STATUS:
2215 if (!guest_cpuid_has_osvw(vcpu))
2217 vcpu->arch.osvw.status = data;
2220 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2221 return xen_hvm_config(vcpu, data);
2222 if (kvm_pmu_is_valid_msr(vcpu, msr))
2223 return kvm_pmu_set_msr(vcpu, msr_info);
2225 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2229 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2236 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2240 * Reads an msr value (of 'msr_index') into 'pdata'.
2241 * Returns 0 on success, non-0 otherwise.
2242 * Assumes vcpu_load() was already called.
2244 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2246 return kvm_x86_ops->get_msr(vcpu, msr);
2248 EXPORT_SYMBOL_GPL(kvm_get_msr);
2250 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2253 u64 mcg_cap = vcpu->arch.mcg_cap;
2254 unsigned bank_num = mcg_cap & 0xff;
2257 case MSR_IA32_P5_MC_ADDR:
2258 case MSR_IA32_P5_MC_TYPE:
2261 case MSR_IA32_MCG_CAP:
2262 data = vcpu->arch.mcg_cap;
2264 case MSR_IA32_MCG_CTL:
2265 if (!(mcg_cap & MCG_CTL_P))
2267 data = vcpu->arch.mcg_ctl;
2269 case MSR_IA32_MCG_STATUS:
2270 data = vcpu->arch.mcg_status;
2273 if (msr >= MSR_IA32_MC0_CTL &&
2274 msr < MSR_IA32_MCx_CTL(bank_num)) {
2275 u32 offset = msr - MSR_IA32_MC0_CTL;
2276 data = vcpu->arch.mce_banks[offset];
2285 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2287 switch (msr_info->index) {
2288 case MSR_IA32_PLATFORM_ID:
2289 case MSR_IA32_EBL_CR_POWERON:
2290 case MSR_IA32_DEBUGCTLMSR:
2291 case MSR_IA32_LASTBRANCHFROMIP:
2292 case MSR_IA32_LASTBRANCHTOIP:
2293 case MSR_IA32_LASTINTFROMIP:
2294 case MSR_IA32_LASTINTTOIP:
2296 case MSR_K8_TSEG_ADDR:
2297 case MSR_K8_TSEG_MASK:
2299 case MSR_VM_HSAVE_PA:
2300 case MSR_K8_INT_PENDING_MSG:
2301 case MSR_AMD64_NB_CFG:
2302 case MSR_FAM10H_MMIO_CONF_BASE:
2303 case MSR_AMD64_BU_CFG2:
2306 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2307 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2308 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2309 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2310 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2311 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2314 case MSR_IA32_UCODE_REV:
2315 msr_info->data = 0x100000000ULL;
2318 case 0x200 ... 0x2ff:
2319 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2320 case 0xcd: /* fsb frequency */
2324 * MSR_EBC_FREQUENCY_ID
2325 * Conservative value valid for even the basic CPU models.
2326 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2327 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2328 * and 266MHz for model 3, or 4. Set Core Clock
2329 * Frequency to System Bus Frequency Ratio to 1 (bits
2330 * 31:24) even though these are only valid for CPU
2331 * models > 2, however guests may end up dividing or
2332 * multiplying by zero otherwise.
2334 case MSR_EBC_FREQUENCY_ID:
2335 msr_info->data = 1 << 24;
2337 case MSR_IA32_APICBASE:
2338 msr_info->data = kvm_get_apic_base(vcpu);
2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2341 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2343 case MSR_IA32_TSCDEADLINE:
2344 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2346 case MSR_IA32_TSC_ADJUST:
2347 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2349 case MSR_IA32_MISC_ENABLE:
2350 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2352 case MSR_IA32_SMBASE:
2353 if (!msr_info->host_initiated)
2355 msr_info->data = vcpu->arch.smbase;
2357 case MSR_IA32_PERF_STATUS:
2358 /* TSC increment by tick */
2359 msr_info->data = 1000ULL;
2360 /* CPU multiplier */
2361 msr_info->data |= (((uint64_t)4ULL) << 40);
2364 msr_info->data = vcpu->arch.efer;
2366 case MSR_KVM_WALL_CLOCK:
2367 case MSR_KVM_WALL_CLOCK_NEW:
2368 msr_info->data = vcpu->kvm->arch.wall_clock;
2370 case MSR_KVM_SYSTEM_TIME:
2371 case MSR_KVM_SYSTEM_TIME_NEW:
2372 msr_info->data = vcpu->arch.time;
2374 case MSR_KVM_ASYNC_PF_EN:
2375 msr_info->data = vcpu->arch.apf.msr_val;
2377 case MSR_KVM_STEAL_TIME:
2378 msr_info->data = vcpu->arch.st.msr_val;
2380 case MSR_KVM_PV_EOI_EN:
2381 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2383 case MSR_IA32_P5_MC_ADDR:
2384 case MSR_IA32_P5_MC_TYPE:
2385 case MSR_IA32_MCG_CAP:
2386 case MSR_IA32_MCG_CTL:
2387 case MSR_IA32_MCG_STATUS:
2388 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2389 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2390 case MSR_K7_CLK_CTL:
2392 * Provide expected ramp-up count for K7. All other
2393 * are set to zero, indicating minimum divisors for
2396 * This prevents guest kernels on AMD host with CPU
2397 * type 6, model 8 and higher from exploding due to
2398 * the rdmsr failing.
2400 msr_info->data = 0x20000000;
2402 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2403 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2404 case HV_X64_MSR_CRASH_CTL:
2405 return kvm_hv_get_msr_common(vcpu,
2406 msr_info->index, &msr_info->data);
2408 case MSR_IA32_BBL_CR_CTL3:
2409 /* This legacy MSR exists but isn't fully documented in current
2410 * silicon. It is however accessed by winxp in very narrow
2411 * scenarios where it sets bit #19, itself documented as
2412 * a "reserved" bit. Best effort attempt to source coherent
2413 * read data here should the balance of the register be
2414 * interpreted by the guest:
2416 * L2 cache control register 3: 64GB range, 256KB size,
2417 * enabled, latency 0x1, configured
2419 msr_info->data = 0xbe702111;
2421 case MSR_AMD64_OSVW_ID_LENGTH:
2422 if (!guest_cpuid_has_osvw(vcpu))
2424 msr_info->data = vcpu->arch.osvw.length;
2426 case MSR_AMD64_OSVW_STATUS:
2427 if (!guest_cpuid_has_osvw(vcpu))
2429 msr_info->data = vcpu->arch.osvw.status;
2432 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2433 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2435 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2438 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2445 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2448 * Read or write a bunch of msrs. All parameters are kernel addresses.
2450 * @return number of msrs set successfully.
2452 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2453 struct kvm_msr_entry *entries,
2454 int (*do_msr)(struct kvm_vcpu *vcpu,
2455 unsigned index, u64 *data))
2459 idx = srcu_read_lock(&vcpu->kvm->srcu);
2460 for (i = 0; i < msrs->nmsrs; ++i)
2461 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2469 * Read or write a bunch of msrs. Parameters are user addresses.
2471 * @return number of msrs set successfully.
2473 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2474 int (*do_msr)(struct kvm_vcpu *vcpu,
2475 unsigned index, u64 *data),
2478 struct kvm_msrs msrs;
2479 struct kvm_msr_entry *entries;
2484 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2488 if (msrs.nmsrs >= MAX_IO_MSRS)
2491 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2492 entries = memdup_user(user_msrs->entries, size);
2493 if (IS_ERR(entries)) {
2494 r = PTR_ERR(entries);
2498 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2503 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2519 case KVM_CAP_IRQCHIP:
2521 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2522 case KVM_CAP_SET_TSS_ADDR:
2523 case KVM_CAP_EXT_CPUID:
2524 case KVM_CAP_EXT_EMUL_CPUID:
2525 case KVM_CAP_CLOCKSOURCE:
2527 case KVM_CAP_NOP_IO_DELAY:
2528 case KVM_CAP_MP_STATE:
2529 case KVM_CAP_SYNC_MMU:
2530 case KVM_CAP_USER_NMI:
2531 case KVM_CAP_REINJECT_CONTROL:
2532 case KVM_CAP_IRQ_INJECT_STATUS:
2533 case KVM_CAP_IOEVENTFD:
2534 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2536 case KVM_CAP_PIT_STATE2:
2537 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2538 case KVM_CAP_XEN_HVM:
2539 case KVM_CAP_ADJUST_CLOCK:
2540 case KVM_CAP_VCPU_EVENTS:
2541 case KVM_CAP_HYPERV:
2542 case KVM_CAP_HYPERV_VAPIC:
2543 case KVM_CAP_HYPERV_SPIN:
2544 case KVM_CAP_PCI_SEGMENT:
2545 case KVM_CAP_DEBUGREGS:
2546 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2548 case KVM_CAP_ASYNC_PF:
2549 case KVM_CAP_GET_TSC_KHZ:
2550 case KVM_CAP_KVMCLOCK_CTRL:
2551 case KVM_CAP_READONLY_MEM:
2552 case KVM_CAP_HYPERV_TIME:
2553 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2554 case KVM_CAP_TSC_DEADLINE_TIMER:
2555 case KVM_CAP_ENABLE_CAP_VM:
2556 case KVM_CAP_DISABLE_QUIRKS:
2557 case KVM_CAP_SET_BOOT_CPU_ID:
2558 case KVM_CAP_SPLIT_IRQCHIP:
2559 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2560 case KVM_CAP_ASSIGN_DEV_IRQ:
2561 case KVM_CAP_PCI_2_3:
2565 case KVM_CAP_X86_SMM:
2566 /* SMBASE is usually relocated above 1M on modern chipsets,
2567 * and SMM handlers might indeed rely on 4G segment limits,
2568 * so do not report SMM to be available if real mode is
2569 * emulated via vm86 mode. Still, do not go to great lengths
2570 * to avoid userspace's usage of the feature, because it is a
2571 * fringe case that is not enabled except via specific settings
2572 * of the module parameters.
2574 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2576 case KVM_CAP_COALESCED_MMIO:
2577 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2580 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2582 case KVM_CAP_NR_VCPUS:
2583 r = KVM_SOFT_MAX_VCPUS;
2585 case KVM_CAP_MAX_VCPUS:
2588 case KVM_CAP_NR_MEMSLOTS:
2589 r = KVM_USER_MEM_SLOTS;
2591 case KVM_CAP_PV_MMU: /* obsolete */
2594 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2596 r = iommu_present(&pci_bus_type);
2600 r = KVM_MAX_MCE_BANKS;
2605 case KVM_CAP_TSC_CONTROL:
2606 r = kvm_has_tsc_control;
2616 long kvm_arch_dev_ioctl(struct file *filp,
2617 unsigned int ioctl, unsigned long arg)
2619 void __user *argp = (void __user *)arg;
2623 case KVM_GET_MSR_INDEX_LIST: {
2624 struct kvm_msr_list __user *user_msr_list = argp;
2625 struct kvm_msr_list msr_list;
2629 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2632 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2633 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2636 if (n < msr_list.nmsrs)
2639 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2640 num_msrs_to_save * sizeof(u32)))
2642 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2644 num_emulated_msrs * sizeof(u32)))
2649 case KVM_GET_SUPPORTED_CPUID:
2650 case KVM_GET_EMULATED_CPUID: {
2651 struct kvm_cpuid2 __user *cpuid_arg = argp;
2652 struct kvm_cpuid2 cpuid;
2655 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2658 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2664 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2669 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2672 mce_cap = KVM_MCE_CAP_SUPPORTED;
2674 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 static void wbinvd_ipi(void *garbage)
2691 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2693 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2696 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2698 /* Address WBINVD may be executed by guest */
2699 if (need_emulate_wbinvd(vcpu)) {
2700 if (kvm_x86_ops->has_wbinvd_exit())
2701 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2702 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2703 smp_call_function_single(vcpu->cpu,
2704 wbinvd_ipi, NULL, 1);
2707 kvm_x86_ops->vcpu_load(vcpu, cpu);
2709 /* Apply any externally detected TSC adjustments (due to suspend) */
2710 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2711 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2712 vcpu->arch.tsc_offset_adjustment = 0;
2713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2716 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2717 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2718 rdtsc() - vcpu->arch.last_host_tsc;
2720 mark_tsc_unstable("KVM discovered backwards TSC");
2722 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2723 kvm_x86_ops->set_hv_timer(vcpu,
2724 kvm_get_lapic_tscdeadline_msr(vcpu)))
2725 kvm_lapic_switch_to_sw_timer(vcpu);
2726 if (check_tsc_unstable()) {
2727 u64 offset = kvm_compute_tsc_offset(vcpu,
2728 vcpu->arch.last_guest_tsc);
2729 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2730 vcpu->arch.tsc_catchup = 1;
2733 * On a host with synchronized TSC, there is no need to update
2734 * kvmclock on vcpu->cpu migration
2736 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2737 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2738 if (vcpu->cpu != cpu)
2739 kvm_migrate_timers(vcpu);
2743 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2746 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2748 kvm_x86_ops->vcpu_put(vcpu);
2749 kvm_put_guest_fpu(vcpu);
2750 vcpu->arch.last_host_tsc = rdtsc();
2753 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2754 struct kvm_lapic_state *s)
2756 kvm_x86_ops->sync_pir_to_irr(vcpu);
2757 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2762 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2763 struct kvm_lapic_state *s)
2765 kvm_apic_post_state_restore(vcpu, s);
2766 update_cr8_intercept(vcpu);
2771 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2773 return (!lapic_in_kernel(vcpu) ||
2774 kvm_apic_accept_pic_intr(vcpu));
2778 * if userspace requested an interrupt window, check that the
2779 * interrupt window is open.
2781 * No need to exit to userspace if we already have an interrupt queued.
2783 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2785 return kvm_arch_interrupt_allowed(vcpu) &&
2786 !kvm_cpu_has_interrupt(vcpu) &&
2787 !kvm_event_needs_reinjection(vcpu) &&
2788 kvm_cpu_accept_dm_intr(vcpu);
2791 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2792 struct kvm_interrupt *irq)
2794 if (irq->irq >= KVM_NR_INTERRUPTS)
2797 if (!irqchip_in_kernel(vcpu->kvm)) {
2798 kvm_queue_interrupt(vcpu, irq->irq, false);
2799 kvm_make_request(KVM_REQ_EVENT, vcpu);
2804 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2805 * fail for in-kernel 8259.
2807 if (pic_in_kernel(vcpu->kvm))
2810 if (vcpu->arch.pending_external_vector != -1)
2813 vcpu->arch.pending_external_vector = irq->irq;
2814 kvm_make_request(KVM_REQ_EVENT, vcpu);
2818 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2820 kvm_inject_nmi(vcpu);
2825 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2827 kvm_make_request(KVM_REQ_SMI, vcpu);
2832 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2833 struct kvm_tpr_access_ctl *tac)
2837 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2841 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2845 unsigned bank_num = mcg_cap & 0xff, bank;
2848 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2850 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2853 vcpu->arch.mcg_cap = mcg_cap;
2854 /* Init IA32_MCG_CTL to all 1s */
2855 if (mcg_cap & MCG_CTL_P)
2856 vcpu->arch.mcg_ctl = ~(u64)0;
2857 /* Init IA32_MCi_CTL to all 1s */
2858 for (bank = 0; bank < bank_num; bank++)
2859 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2864 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2865 struct kvm_x86_mce *mce)
2867 u64 mcg_cap = vcpu->arch.mcg_cap;
2868 unsigned bank_num = mcg_cap & 0xff;
2869 u64 *banks = vcpu->arch.mce_banks;
2871 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2874 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2875 * reporting is disabled
2877 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2878 vcpu->arch.mcg_ctl != ~(u64)0)
2880 banks += 4 * mce->bank;
2882 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2883 * reporting is disabled for the bank
2885 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2887 if (mce->status & MCI_STATUS_UC) {
2888 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2889 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2890 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2893 if (banks[1] & MCI_STATUS_VAL)
2894 mce->status |= MCI_STATUS_OVER;
2895 banks[2] = mce->addr;
2896 banks[3] = mce->misc;
2897 vcpu->arch.mcg_status = mce->mcg_status;
2898 banks[1] = mce->status;
2899 kvm_queue_exception(vcpu, MC_VECTOR);
2900 } else if (!(banks[1] & MCI_STATUS_VAL)
2901 || !(banks[1] & MCI_STATUS_UC)) {
2902 if (banks[1] & MCI_STATUS_VAL)
2903 mce->status |= MCI_STATUS_OVER;
2904 banks[2] = mce->addr;
2905 banks[3] = mce->misc;
2906 banks[1] = mce->status;
2908 banks[1] |= MCI_STATUS_OVER;
2912 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2913 struct kvm_vcpu_events *events)
2916 events->exception.injected =
2917 vcpu->arch.exception.pending &&
2918 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2919 events->exception.nr = vcpu->arch.exception.nr;
2920 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2921 events->exception.pad = 0;
2922 events->exception.error_code = vcpu->arch.exception.error_code;
2924 events->interrupt.injected =
2925 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2926 events->interrupt.nr = vcpu->arch.interrupt.nr;
2927 events->interrupt.soft = 0;
2928 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2930 events->nmi.injected = vcpu->arch.nmi_injected;
2931 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2932 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2933 events->nmi.pad = 0;
2935 events->sipi_vector = 0; /* never valid when reporting to user space */
2937 events->smi.smm = is_smm(vcpu);
2938 events->smi.pending = vcpu->arch.smi_pending;
2939 events->smi.smm_inside_nmi =
2940 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2941 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2943 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2944 | KVM_VCPUEVENT_VALID_SHADOW
2945 | KVM_VCPUEVENT_VALID_SMM);
2946 memset(&events->reserved, 0, sizeof(events->reserved));
2949 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2950 struct kvm_vcpu_events *events)
2952 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2953 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2954 | KVM_VCPUEVENT_VALID_SHADOW
2955 | KVM_VCPUEVENT_VALID_SMM))
2959 vcpu->arch.exception.pending = events->exception.injected;
2960 vcpu->arch.exception.nr = events->exception.nr;
2961 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2962 vcpu->arch.exception.error_code = events->exception.error_code;
2964 vcpu->arch.interrupt.pending = events->interrupt.injected;
2965 vcpu->arch.interrupt.nr = events->interrupt.nr;
2966 vcpu->arch.interrupt.soft = events->interrupt.soft;
2967 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2968 kvm_x86_ops->set_interrupt_shadow(vcpu,
2969 events->interrupt.shadow);
2971 vcpu->arch.nmi_injected = events->nmi.injected;
2972 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2973 vcpu->arch.nmi_pending = events->nmi.pending;
2974 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2976 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2977 kvm_vcpu_has_lapic(vcpu))
2978 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2980 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2981 if (events->smi.smm)
2982 vcpu->arch.hflags |= HF_SMM_MASK;
2984 vcpu->arch.hflags &= ~HF_SMM_MASK;
2985 vcpu->arch.smi_pending = events->smi.pending;
2986 if (events->smi.smm_inside_nmi)
2987 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2989 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2990 if (kvm_vcpu_has_lapic(vcpu)) {
2991 if (events->smi.latched_init)
2992 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2994 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2998 kvm_make_request(KVM_REQ_EVENT, vcpu);
3003 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3004 struct kvm_debugregs *dbgregs)
3008 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3009 kvm_get_dr(vcpu, 6, &val);
3011 dbgregs->dr7 = vcpu->arch.dr7;
3013 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3016 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3017 struct kvm_debugregs *dbgregs)
3022 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3023 kvm_update_dr0123(vcpu);
3024 vcpu->arch.dr6 = dbgregs->dr6;
3025 kvm_update_dr6(vcpu);
3026 vcpu->arch.dr7 = dbgregs->dr7;
3027 kvm_update_dr7(vcpu);
3032 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3034 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3036 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3037 u64 xstate_bv = xsave->header.xfeatures;
3041 * Copy legacy XSAVE area, to avoid complications with CPUID
3042 * leaves 0 and 1 in the loop below.
3044 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3047 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3050 * Copy each region from the possibly compacted offset to the
3051 * non-compacted offset.
3053 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3055 u64 feature = valid & -valid;
3056 int index = fls64(feature) - 1;
3057 void *src = get_xsave_addr(xsave, feature);
3060 u32 size, offset, ecx, edx;
3061 cpuid_count(XSTATE_CPUID, index,
3062 &size, &offset, &ecx, &edx);
3063 memcpy(dest + offset, src, size);
3070 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3072 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3073 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3077 * Copy legacy XSAVE area, to avoid complications with CPUID
3078 * leaves 0 and 1 in the loop below.
3080 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3082 /* Set XSTATE_BV and possibly XCOMP_BV. */
3083 xsave->header.xfeatures = xstate_bv;
3085 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3088 * Copy each region from the non-compacted offset to the
3089 * possibly compacted offset.
3091 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3093 u64 feature = valid & -valid;
3094 int index = fls64(feature) - 1;
3095 void *dest = get_xsave_addr(xsave, feature);
3098 u32 size, offset, ecx, edx;
3099 cpuid_count(XSTATE_CPUID, index,
3100 &size, &offset, &ecx, &edx);
3101 memcpy(dest, src + offset, size);
3108 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3109 struct kvm_xsave *guest_xsave)
3111 if (cpu_has_xsave) {
3112 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3113 fill_xsave((u8 *) guest_xsave->region, vcpu);
3115 memcpy(guest_xsave->region,
3116 &vcpu->arch.guest_fpu.state.fxsave,
3117 sizeof(struct fxregs_state));
3118 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3119 XFEATURE_MASK_FPSSE;
3123 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3124 struct kvm_xsave *guest_xsave)
3127 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3129 if (cpu_has_xsave) {
3131 * Here we allow setting states that are not present in
3132 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3133 * with old userspace.
3135 if (xstate_bv & ~kvm_supported_xcr0())
3137 load_xsave(vcpu, (u8 *)guest_xsave->region);
3139 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3141 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3142 guest_xsave->region, sizeof(struct fxregs_state));
3147 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3148 struct kvm_xcrs *guest_xcrs)
3150 if (!cpu_has_xsave) {
3151 guest_xcrs->nr_xcrs = 0;
3155 guest_xcrs->nr_xcrs = 1;
3156 guest_xcrs->flags = 0;
3157 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3158 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3161 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3169 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3172 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3173 /* Only support XCR0 currently */
3174 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3175 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3176 guest_xcrs->xcrs[i].value);
3185 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3186 * stopped by the hypervisor. This function will be called from the host only.
3187 * EINVAL is returned when the host attempts to set the flag for a guest that
3188 * does not support pv clocks.
3190 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3192 if (!vcpu->arch.pv_time_enabled)
3194 vcpu->arch.pvclock_set_guest_stopped_request = true;
3195 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3199 long kvm_arch_vcpu_ioctl(struct file *filp,
3200 unsigned int ioctl, unsigned long arg)
3202 struct kvm_vcpu *vcpu = filp->private_data;
3203 void __user *argp = (void __user *)arg;
3206 struct kvm_lapic_state *lapic;
3207 struct kvm_xsave *xsave;
3208 struct kvm_xcrs *xcrs;
3214 case KVM_GET_LAPIC: {
3216 if (!vcpu->arch.apic)
3218 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3223 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3227 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3232 case KVM_SET_LAPIC: {
3234 if (!vcpu->arch.apic)
3236 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3237 if (IS_ERR(u.lapic))
3238 return PTR_ERR(u.lapic);
3240 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3243 case KVM_INTERRUPT: {
3244 struct kvm_interrupt irq;
3247 if (copy_from_user(&irq, argp, sizeof irq))
3249 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3253 r = kvm_vcpu_ioctl_nmi(vcpu);
3257 r = kvm_vcpu_ioctl_smi(vcpu);
3260 case KVM_SET_CPUID: {
3261 struct kvm_cpuid __user *cpuid_arg = argp;
3262 struct kvm_cpuid cpuid;
3265 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3267 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3270 case KVM_SET_CPUID2: {
3271 struct kvm_cpuid2 __user *cpuid_arg = argp;
3272 struct kvm_cpuid2 cpuid;
3275 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3277 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3278 cpuid_arg->entries);
3281 case KVM_GET_CPUID2: {
3282 struct kvm_cpuid2 __user *cpuid_arg = argp;
3283 struct kvm_cpuid2 cpuid;
3286 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3288 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3289 cpuid_arg->entries);
3293 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3299 r = msr_io(vcpu, argp, do_get_msr, 1);
3302 r = msr_io(vcpu, argp, do_set_msr, 0);
3304 case KVM_TPR_ACCESS_REPORTING: {
3305 struct kvm_tpr_access_ctl tac;
3308 if (copy_from_user(&tac, argp, sizeof tac))
3310 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3314 if (copy_to_user(argp, &tac, sizeof tac))
3319 case KVM_SET_VAPIC_ADDR: {
3320 struct kvm_vapic_addr va;
3323 if (!lapic_in_kernel(vcpu))
3326 if (copy_from_user(&va, argp, sizeof va))
3328 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3331 case KVM_X86_SETUP_MCE: {
3335 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3337 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3340 case KVM_X86_SET_MCE: {
3341 struct kvm_x86_mce mce;
3344 if (copy_from_user(&mce, argp, sizeof mce))
3346 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3349 case KVM_GET_VCPU_EVENTS: {
3350 struct kvm_vcpu_events events;
3352 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3355 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3360 case KVM_SET_VCPU_EVENTS: {
3361 struct kvm_vcpu_events events;
3364 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3367 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3370 case KVM_GET_DEBUGREGS: {
3371 struct kvm_debugregs dbgregs;
3373 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3376 if (copy_to_user(argp, &dbgregs,
3377 sizeof(struct kvm_debugregs)))
3382 case KVM_SET_DEBUGREGS: {
3383 struct kvm_debugregs dbgregs;
3386 if (copy_from_user(&dbgregs, argp,
3387 sizeof(struct kvm_debugregs)))
3390 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3393 case KVM_GET_XSAVE: {
3394 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3399 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3402 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3407 case KVM_SET_XSAVE: {
3408 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3409 if (IS_ERR(u.xsave))
3410 return PTR_ERR(u.xsave);
3412 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3415 case KVM_GET_XCRS: {
3416 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3421 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3424 if (copy_to_user(argp, u.xcrs,
3425 sizeof(struct kvm_xcrs)))
3430 case KVM_SET_XCRS: {
3431 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3433 return PTR_ERR(u.xcrs);
3435 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3438 case KVM_SET_TSC_KHZ: {
3442 user_tsc_khz = (u32)arg;
3444 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3447 if (user_tsc_khz == 0)
3448 user_tsc_khz = tsc_khz;
3450 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3455 case KVM_GET_TSC_KHZ: {
3456 r = vcpu->arch.virtual_tsc_khz;
3459 case KVM_KVMCLOCK_CTRL: {
3460 r = kvm_set_guest_paused(vcpu);
3471 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3473 return VM_FAULT_SIGBUS;
3476 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3480 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3482 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3486 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3489 kvm->arch.ept_identity_map_addr = ident_addr;
3493 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3494 u32 kvm_nr_mmu_pages)
3496 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3499 mutex_lock(&kvm->slots_lock);
3501 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3502 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3504 mutex_unlock(&kvm->slots_lock);
3508 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3510 return kvm->arch.n_max_mmu_pages;
3513 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3518 switch (chip->chip_id) {
3519 case KVM_IRQCHIP_PIC_MASTER:
3520 memcpy(&chip->chip.pic,
3521 &pic_irqchip(kvm)->pics[0],
3522 sizeof(struct kvm_pic_state));
3524 case KVM_IRQCHIP_PIC_SLAVE:
3525 memcpy(&chip->chip.pic,
3526 &pic_irqchip(kvm)->pics[1],
3527 sizeof(struct kvm_pic_state));
3529 case KVM_IRQCHIP_IOAPIC:
3530 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3539 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3544 switch (chip->chip_id) {
3545 case KVM_IRQCHIP_PIC_MASTER:
3546 spin_lock(&pic_irqchip(kvm)->lock);
3547 memcpy(&pic_irqchip(kvm)->pics[0],
3549 sizeof(struct kvm_pic_state));
3550 spin_unlock(&pic_irqchip(kvm)->lock);
3552 case KVM_IRQCHIP_PIC_SLAVE:
3553 spin_lock(&pic_irqchip(kvm)->lock);
3554 memcpy(&pic_irqchip(kvm)->pics[1],
3556 sizeof(struct kvm_pic_state));
3557 spin_unlock(&pic_irqchip(kvm)->lock);
3559 case KVM_IRQCHIP_IOAPIC:
3560 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3566 kvm_pic_update_irq(pic_irqchip(kvm));
3570 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3572 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3573 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3574 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3578 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3581 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3582 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3583 for (i = 0; i < 3; i++)
3584 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
3585 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3589 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3591 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3592 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3593 sizeof(ps->channels));
3594 ps->flags = kvm->arch.vpit->pit_state.flags;
3595 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3596 memset(&ps->reserved, 0, sizeof(ps->reserved));
3600 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3604 u32 prev_legacy, cur_legacy;
3605 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3606 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3607 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3608 if (!prev_legacy && cur_legacy)
3610 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3611 sizeof(kvm->arch.vpit->pit_state.channels));
3612 kvm->arch.vpit->pit_state.flags = ps->flags;
3613 for (i = 0; i < 3; i++)
3614 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3616 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3620 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3621 struct kvm_reinject_control *control)
3623 if (!kvm->arch.vpit)
3625 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3626 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3627 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3632 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3633 * @kvm: kvm instance
3634 * @log: slot id and address to which we copy the log
3636 * Steps 1-4 below provide general overview of dirty page logging. See
3637 * kvm_get_dirty_log_protect() function description for additional details.
3639 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3640 * always flush the TLB (step 4) even if previous step failed and the dirty
3641 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3642 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3643 * writes will be marked dirty for next log read.
3645 * 1. Take a snapshot of the bit and clear it if needed.
3646 * 2. Write protect the corresponding page.
3647 * 3. Copy the snapshot to the userspace.
3648 * 4. Flush TLB's if needed.
3650 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3652 bool is_dirty = false;
3655 mutex_lock(&kvm->slots_lock);
3658 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3660 if (kvm_x86_ops->flush_log_dirty)
3661 kvm_x86_ops->flush_log_dirty(kvm);
3663 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3666 * All the TLBs can be flushed out of mmu lock, see the comments in
3667 * kvm_mmu_slot_remove_write_access().
3669 lockdep_assert_held(&kvm->slots_lock);
3671 kvm_flush_remote_tlbs(kvm);
3673 mutex_unlock(&kvm->slots_lock);
3677 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3680 if (!irqchip_in_kernel(kvm))
3683 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3684 irq_event->irq, irq_event->level,
3689 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3690 struct kvm_enable_cap *cap)
3698 case KVM_CAP_DISABLE_QUIRKS:
3699 kvm->arch.disabled_quirks = cap->args[0];
3702 case KVM_CAP_SPLIT_IRQCHIP: {
3703 mutex_lock(&kvm->lock);
3705 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3706 goto split_irqchip_unlock;
3708 if (irqchip_in_kernel(kvm))
3709 goto split_irqchip_unlock;
3710 if (atomic_read(&kvm->online_vcpus))
3711 goto split_irqchip_unlock;
3712 r = kvm_setup_empty_irq_routing(kvm);
3714 goto split_irqchip_unlock;
3715 /* Pairs with irqchip_in_kernel. */
3717 kvm->arch.irqchip_split = true;
3718 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3720 split_irqchip_unlock:
3721 mutex_unlock(&kvm->lock);
3731 long kvm_arch_vm_ioctl(struct file *filp,
3732 unsigned int ioctl, unsigned long arg)
3734 struct kvm *kvm = filp->private_data;
3735 void __user *argp = (void __user *)arg;
3738 * This union makes it completely explicit to gcc-3.x
3739 * that these two variables' stack usage should be
3740 * combined, not added together.
3743 struct kvm_pit_state ps;
3744 struct kvm_pit_state2 ps2;
3745 struct kvm_pit_config pit_config;
3749 case KVM_SET_TSS_ADDR:
3750 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3752 case KVM_SET_IDENTITY_MAP_ADDR: {
3756 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3758 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3761 case KVM_SET_NR_MMU_PAGES:
3762 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3764 case KVM_GET_NR_MMU_PAGES:
3765 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3767 case KVM_CREATE_IRQCHIP: {
3768 struct kvm_pic *vpic;
3770 mutex_lock(&kvm->lock);
3773 goto create_irqchip_unlock;
3775 if (atomic_read(&kvm->online_vcpus))
3776 goto create_irqchip_unlock;
3778 vpic = kvm_create_pic(kvm);
3780 r = kvm_ioapic_init(kvm);
3782 mutex_lock(&kvm->slots_lock);
3783 kvm_destroy_pic(vpic);
3784 mutex_unlock(&kvm->slots_lock);
3785 goto create_irqchip_unlock;
3788 goto create_irqchip_unlock;
3789 r = kvm_setup_default_irq_routing(kvm);
3791 mutex_lock(&kvm->slots_lock);
3792 mutex_lock(&kvm->irq_lock);
3793 kvm_ioapic_destroy(kvm);
3794 kvm_destroy_pic(vpic);
3795 mutex_unlock(&kvm->irq_lock);
3796 mutex_unlock(&kvm->slots_lock);
3797 goto create_irqchip_unlock;
3799 /* Write kvm->irq_routing before kvm->arch.vpic. */
3801 kvm->arch.vpic = vpic;
3802 create_irqchip_unlock:
3803 mutex_unlock(&kvm->lock);
3806 case KVM_CREATE_PIT:
3807 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3809 case KVM_CREATE_PIT2:
3811 if (copy_from_user(&u.pit_config, argp,
3812 sizeof(struct kvm_pit_config)))
3815 mutex_lock(&kvm->slots_lock);
3818 goto create_pit_unlock;
3820 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3824 mutex_unlock(&kvm->slots_lock);
3826 case KVM_GET_IRQCHIP: {
3827 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3828 struct kvm_irqchip *chip;
3830 chip = memdup_user(argp, sizeof(*chip));
3837 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3838 goto get_irqchip_out;
3839 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3841 goto get_irqchip_out;
3843 if (copy_to_user(argp, chip, sizeof *chip))
3844 goto get_irqchip_out;
3850 case KVM_SET_IRQCHIP: {
3851 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3852 struct kvm_irqchip *chip;
3854 chip = memdup_user(argp, sizeof(*chip));
3861 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3862 goto set_irqchip_out;
3863 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3865 goto set_irqchip_out;
3873 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3876 if (!kvm->arch.vpit)
3878 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3882 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3889 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3892 if (!kvm->arch.vpit)
3894 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3897 case KVM_GET_PIT2: {
3899 if (!kvm->arch.vpit)
3901 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3905 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3910 case KVM_SET_PIT2: {
3912 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3915 if (!kvm->arch.vpit)
3917 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3920 case KVM_REINJECT_CONTROL: {
3921 struct kvm_reinject_control control;
3923 if (copy_from_user(&control, argp, sizeof(control)))
3925 r = kvm_vm_ioctl_reinject(kvm, &control);
3928 case KVM_SET_BOOT_CPU_ID:
3930 mutex_lock(&kvm->lock);
3931 if (atomic_read(&kvm->online_vcpus) != 0)
3934 kvm->arch.bsp_vcpu_id = arg;
3935 mutex_unlock(&kvm->lock);
3937 case KVM_XEN_HVM_CONFIG: {
3939 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3940 sizeof(struct kvm_xen_hvm_config)))
3943 if (kvm->arch.xen_hvm_config.flags)
3948 case KVM_SET_CLOCK: {
3949 struct kvm_clock_data user_ns;
3954 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3962 local_irq_disable();
3963 now_ns = get_kernel_ns();
3964 delta = user_ns.clock - now_ns;
3966 kvm->arch.kvmclock_offset = delta;
3967 kvm_gen_update_masterclock(kvm);
3970 case KVM_GET_CLOCK: {
3971 struct kvm_clock_data user_ns;
3974 local_irq_disable();
3975 now_ns = get_kernel_ns();
3976 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3979 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3982 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3987 case KVM_ENABLE_CAP: {
3988 struct kvm_enable_cap cap;
3991 if (copy_from_user(&cap, argp, sizeof(cap)))
3993 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3997 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4003 static void kvm_init_msr_list(void)
4008 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4009 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4013 * Even MSRs that are valid in the host may not be exposed
4014 * to the guests in some cases.
4016 switch (msrs_to_save[i]) {
4017 case MSR_IA32_BNDCFGS:
4018 if (!kvm_x86_ops->mpx_supported())
4022 if (!kvm_x86_ops->rdtscp_supported())
4030 msrs_to_save[j] = msrs_to_save[i];
4033 num_msrs_to_save = j;
4035 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4036 switch (emulated_msrs[i]) {
4037 case MSR_IA32_SMBASE:
4038 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4046 emulated_msrs[j] = emulated_msrs[i];
4049 num_emulated_msrs = j;
4052 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4060 if (!(vcpu->arch.apic &&
4061 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4062 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4073 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4080 if (!(vcpu->arch.apic &&
4081 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4083 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4085 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4095 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4096 struct kvm_segment *var, int seg)
4098 kvm_x86_ops->set_segment(vcpu, var, seg);
4101 void kvm_get_segment(struct kvm_vcpu *vcpu,
4102 struct kvm_segment *var, int seg)
4104 kvm_x86_ops->get_segment(vcpu, var, seg);
4107 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4108 struct x86_exception *exception)
4112 BUG_ON(!mmu_is_nested(vcpu));
4114 /* NPT walks are always user-walks */
4115 access |= PFERR_USER_MASK;
4116 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4121 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4122 struct x86_exception *exception)
4124 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4125 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4128 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4129 struct x86_exception *exception)
4131 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4132 access |= PFERR_FETCH_MASK;
4133 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4136 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4137 struct x86_exception *exception)
4139 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4140 access |= PFERR_WRITE_MASK;
4141 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4144 /* uses this to access any guest's mapped memory without checking CPL */
4145 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4146 struct x86_exception *exception)
4148 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4151 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4152 struct kvm_vcpu *vcpu, u32 access,
4153 struct x86_exception *exception)
4156 int r = X86EMUL_CONTINUE;
4159 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4161 unsigned offset = addr & (PAGE_SIZE-1);
4162 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4165 if (gpa == UNMAPPED_GVA)
4166 return X86EMUL_PROPAGATE_FAULT;
4167 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4170 r = X86EMUL_IO_NEEDED;
4182 /* used for instruction fetching */
4183 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4184 gva_t addr, void *val, unsigned int bytes,
4185 struct x86_exception *exception)
4187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4188 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4192 /* Inline kvm_read_guest_virt_helper for speed. */
4193 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4195 if (unlikely(gpa == UNMAPPED_GVA))
4196 return X86EMUL_PROPAGATE_FAULT;
4198 offset = addr & (PAGE_SIZE-1);
4199 if (WARN_ON(offset + bytes > PAGE_SIZE))
4200 bytes = (unsigned)PAGE_SIZE - offset;
4201 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4203 if (unlikely(ret < 0))
4204 return X86EMUL_IO_NEEDED;
4206 return X86EMUL_CONTINUE;
4209 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4210 gva_t addr, void *val, unsigned int bytes,
4211 struct x86_exception *exception)
4213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4214 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4216 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4219 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4221 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4222 gva_t addr, void *val, unsigned int bytes,
4223 struct x86_exception *exception)
4225 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4226 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4229 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4230 unsigned long addr, void *val, unsigned int bytes)
4232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4233 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4235 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4238 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4239 gva_t addr, void *val,
4241 struct x86_exception *exception)
4243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4245 int r = X86EMUL_CONTINUE;
4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4251 unsigned offset = addr & (PAGE_SIZE-1);
4252 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4255 if (gpa == UNMAPPED_GVA)
4256 return X86EMUL_PROPAGATE_FAULT;
4257 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4259 r = X86EMUL_IO_NEEDED;
4270 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4272 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4273 gpa_t *gpa, struct x86_exception *exception,
4276 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4277 | (write ? PFERR_WRITE_MASK : 0);
4279 if (vcpu_match_mmio_gva(vcpu, gva)
4280 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4281 vcpu->arch.access, access)) {
4282 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4283 (gva & (PAGE_SIZE - 1));
4284 trace_vcpu_match_mmio(gva, *gpa, write, false);
4288 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4290 if (*gpa == UNMAPPED_GVA)
4293 /* For APIC access vmexit */
4294 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4297 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4298 trace_vcpu_match_mmio(gva, *gpa, write, true);
4305 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4306 const void *val, int bytes)
4310 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4313 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4317 struct read_write_emulator_ops {
4318 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4320 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4321 void *val, int bytes);
4322 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4323 int bytes, void *val);
4324 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4325 void *val, int bytes);
4329 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4331 if (vcpu->mmio_read_completed) {
4332 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4333 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4334 vcpu->mmio_read_completed = 0;
4341 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4342 void *val, int bytes)
4344 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4347 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4348 void *val, int bytes)
4350 return emulator_write_phys(vcpu, gpa, val, bytes);
4353 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4355 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4356 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4359 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4360 void *val, int bytes)
4362 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4363 return X86EMUL_IO_NEEDED;
4366 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4367 void *val, int bytes)
4369 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4371 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4372 return X86EMUL_CONTINUE;
4375 static const struct read_write_emulator_ops read_emultor = {
4376 .read_write_prepare = read_prepare,
4377 .read_write_emulate = read_emulate,
4378 .read_write_mmio = vcpu_mmio_read,
4379 .read_write_exit_mmio = read_exit_mmio,
4382 static const struct read_write_emulator_ops write_emultor = {
4383 .read_write_emulate = write_emulate,
4384 .read_write_mmio = write_mmio,
4385 .read_write_exit_mmio = write_exit_mmio,
4389 static int emulator_read_write_onepage(unsigned long addr, void *val,
4391 struct x86_exception *exception,
4392 struct kvm_vcpu *vcpu,
4393 const struct read_write_emulator_ops *ops)
4397 bool write = ops->write;
4398 struct kvm_mmio_fragment *frag;
4400 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4403 return X86EMUL_PROPAGATE_FAULT;
4405 /* For APIC access vmexit */
4409 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4410 return X86EMUL_CONTINUE;
4414 * Is this MMIO handled locally?
4416 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4417 if (handled == bytes)
4418 return X86EMUL_CONTINUE;
4424 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4425 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4429 return X86EMUL_CONTINUE;
4432 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4434 void *val, unsigned int bytes,
4435 struct x86_exception *exception,
4436 const struct read_write_emulator_ops *ops)
4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4442 if (ops->read_write_prepare &&
4443 ops->read_write_prepare(vcpu, val, bytes))
4444 return X86EMUL_CONTINUE;
4446 vcpu->mmio_nr_fragments = 0;
4448 /* Crossing a page boundary? */
4449 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4452 now = -addr & ~PAGE_MASK;
4453 rc = emulator_read_write_onepage(addr, val, now, exception,
4456 if (rc != X86EMUL_CONTINUE)
4459 if (ctxt->mode != X86EMUL_MODE_PROT64)
4465 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4467 if (rc != X86EMUL_CONTINUE)
4470 if (!vcpu->mmio_nr_fragments)
4473 gpa = vcpu->mmio_fragments[0].gpa;
4475 vcpu->mmio_needed = 1;
4476 vcpu->mmio_cur_fragment = 0;
4478 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4479 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4480 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4481 vcpu->run->mmio.phys_addr = gpa;
4483 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4486 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4490 struct x86_exception *exception)
4492 return emulator_read_write(ctxt, addr, val, bytes,
4493 exception, &read_emultor);
4496 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4500 struct x86_exception *exception)
4502 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4503 exception, &write_emultor);
4506 #define CMPXCHG_TYPE(t, ptr, old, new) \
4507 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4509 #ifdef CONFIG_X86_64
4510 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4512 # define CMPXCHG64(ptr, old, new) \
4513 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4516 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4521 struct x86_exception *exception)
4523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4529 /* guests cmpxchg8b have to be emulated atomically */
4530 if (bytes > 8 || (bytes & (bytes - 1)))
4533 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4535 if (gpa == UNMAPPED_GVA ||
4536 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4539 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4542 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4543 if (is_error_page(page))
4546 kaddr = kmap_atomic(page);
4547 kaddr += offset_in_page(gpa);
4550 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4553 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4556 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4559 exchanged = CMPXCHG64(kaddr, old, new);
4564 kunmap_atomic(kaddr);
4565 kvm_release_page_dirty(page);
4568 return X86EMUL_CMPXCHG_FAILED;
4570 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4571 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4573 return X86EMUL_CONTINUE;
4576 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4578 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4581 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4583 /* TODO: String I/O for in kernel device */
4586 if (vcpu->arch.pio.in)
4587 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4588 vcpu->arch.pio.size, pd);
4590 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4591 vcpu->arch.pio.port, vcpu->arch.pio.size,
4596 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4597 unsigned short port, void *val,
4598 unsigned int count, bool in)
4600 vcpu->arch.pio.port = port;
4601 vcpu->arch.pio.in = in;
4602 vcpu->arch.pio.count = count;
4603 vcpu->arch.pio.size = size;
4605 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4606 vcpu->arch.pio.count = 0;
4610 vcpu->run->exit_reason = KVM_EXIT_IO;
4611 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4612 vcpu->run->io.size = size;
4613 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4614 vcpu->run->io.count = count;
4615 vcpu->run->io.port = port;
4620 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4621 int size, unsigned short port, void *val,
4624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4627 if (vcpu->arch.pio.count)
4630 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4633 memcpy(val, vcpu->arch.pio_data, size * count);
4634 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4635 vcpu->arch.pio.count = 0;
4642 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4643 int size, unsigned short port,
4644 const void *val, unsigned int count)
4646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4648 memcpy(vcpu->arch.pio_data, val, size * count);
4649 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4650 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4653 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4655 return kvm_x86_ops->get_segment_base(vcpu, seg);
4658 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4660 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4663 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4665 if (!need_emulate_wbinvd(vcpu))
4666 return X86EMUL_CONTINUE;
4668 if (kvm_x86_ops->has_wbinvd_exit()) {
4669 int cpu = get_cpu();
4671 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4672 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4673 wbinvd_ipi, NULL, 1);
4675 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4678 return X86EMUL_CONTINUE;
4681 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4683 kvm_x86_ops->skip_emulated_instruction(vcpu);
4684 return kvm_emulate_wbinvd_noskip(vcpu);
4686 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4690 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4692 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4695 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4696 unsigned long *dest)
4698 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4701 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4702 unsigned long value)
4705 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4708 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4710 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4713 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4715 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4716 unsigned long value;
4720 value = kvm_read_cr0(vcpu);
4723 value = vcpu->arch.cr2;
4726 value = kvm_read_cr3(vcpu);
4729 value = kvm_read_cr4(vcpu);
4732 value = kvm_get_cr8(vcpu);
4735 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4742 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4744 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4749 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4752 vcpu->arch.cr2 = val;
4755 res = kvm_set_cr3(vcpu, val);
4758 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4761 res = kvm_set_cr8(vcpu, val);
4764 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4771 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4773 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4776 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4778 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4781 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4783 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4786 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4788 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4791 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4793 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4796 static unsigned long emulator_get_cached_segment_base(
4797 struct x86_emulate_ctxt *ctxt, int seg)
4799 return get_segment_base(emul_to_vcpu(ctxt), seg);
4802 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4803 struct desc_struct *desc, u32 *base3,
4806 struct kvm_segment var;
4808 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4809 *selector = var.selector;
4812 memset(desc, 0, sizeof(*desc));
4818 set_desc_limit(desc, var.limit);
4819 set_desc_base(desc, (unsigned long)var.base);
4820 #ifdef CONFIG_X86_64
4822 *base3 = var.base >> 32;
4824 desc->type = var.type;
4826 desc->dpl = var.dpl;
4827 desc->p = var.present;
4828 desc->avl = var.avl;
4836 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4837 struct desc_struct *desc, u32 base3,
4840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4841 struct kvm_segment var;
4843 var.selector = selector;
4844 var.base = get_desc_base(desc);
4845 #ifdef CONFIG_X86_64
4846 var.base |= ((u64)base3) << 32;
4848 var.limit = get_desc_limit(desc);
4850 var.limit = (var.limit << 12) | 0xfff;
4851 var.type = desc->type;
4852 var.dpl = desc->dpl;
4857 var.avl = desc->avl;
4858 var.present = desc->p;
4859 var.unusable = !var.present;
4862 kvm_set_segment(vcpu, &var, seg);
4866 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4867 u32 msr_index, u64 *pdata)
4869 struct msr_data msr;
4872 msr.index = msr_index;
4873 msr.host_initiated = false;
4874 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4882 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4883 u32 msr_index, u64 data)
4885 struct msr_data msr;
4888 msr.index = msr_index;
4889 msr.host_initiated = false;
4890 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4893 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4895 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4897 return vcpu->arch.smbase;
4900 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4902 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4904 vcpu->arch.smbase = smbase;
4907 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4910 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4913 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4914 u32 pmc, u64 *pdata)
4916 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4919 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4921 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4924 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4927 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4929 * CR0.TS may reference the host fpu state, not the guest fpu state,
4930 * so it may be clear at this point.
4935 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4940 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4941 struct x86_instruction_info *info,
4942 enum x86_intercept_stage stage)
4944 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4947 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4948 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4950 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4953 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4955 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4958 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4960 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4963 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4965 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4968 static const struct x86_emulate_ops emulate_ops = {
4969 .read_gpr = emulator_read_gpr,
4970 .write_gpr = emulator_write_gpr,
4971 .read_std = kvm_read_guest_virt_system,
4972 .write_std = kvm_write_guest_virt_system,
4973 .read_phys = kvm_read_guest_phys_system,
4974 .fetch = kvm_fetch_guest_virt,
4975 .read_emulated = emulator_read_emulated,
4976 .write_emulated = emulator_write_emulated,
4977 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4978 .invlpg = emulator_invlpg,
4979 .pio_in_emulated = emulator_pio_in_emulated,
4980 .pio_out_emulated = emulator_pio_out_emulated,
4981 .get_segment = emulator_get_segment,
4982 .set_segment = emulator_set_segment,
4983 .get_cached_segment_base = emulator_get_cached_segment_base,
4984 .get_gdt = emulator_get_gdt,
4985 .get_idt = emulator_get_idt,
4986 .set_gdt = emulator_set_gdt,
4987 .set_idt = emulator_set_idt,
4988 .get_cr = emulator_get_cr,
4989 .set_cr = emulator_set_cr,
4990 .cpl = emulator_get_cpl,
4991 .get_dr = emulator_get_dr,
4992 .set_dr = emulator_set_dr,
4993 .get_smbase = emulator_get_smbase,
4994 .set_smbase = emulator_set_smbase,
4995 .set_msr = emulator_set_msr,
4996 .get_msr = emulator_get_msr,
4997 .check_pmc = emulator_check_pmc,
4998 .read_pmc = emulator_read_pmc,
4999 .halt = emulator_halt,
5000 .wbinvd = emulator_wbinvd,
5001 .fix_hypercall = emulator_fix_hypercall,
5002 .get_fpu = emulator_get_fpu,
5003 .put_fpu = emulator_put_fpu,
5004 .intercept = emulator_intercept,
5005 .get_cpuid = emulator_get_cpuid,
5006 .set_nmi_mask = emulator_set_nmi_mask,
5009 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5011 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5013 * an sti; sti; sequence only disable interrupts for the first
5014 * instruction. So, if the last instruction, be it emulated or
5015 * not, left the system with the INT_STI flag enabled, it
5016 * means that the last instruction is an sti. We should not
5017 * leave the flag on in this case. The same goes for mov ss
5019 if (int_shadow & mask)
5021 if (unlikely(int_shadow || mask)) {
5022 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5024 kvm_make_request(KVM_REQ_EVENT, vcpu);
5028 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5030 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5031 if (ctxt->exception.vector == PF_VECTOR)
5032 return kvm_propagate_fault(vcpu, &ctxt->exception);
5034 if (ctxt->exception.error_code_valid)
5035 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5036 ctxt->exception.error_code);
5038 kvm_queue_exception(vcpu, ctxt->exception.vector);
5042 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5044 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5047 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5049 ctxt->eflags = kvm_get_rflags(vcpu);
5050 ctxt->eip = kvm_rip_read(vcpu);
5051 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5052 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5053 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5054 cs_db ? X86EMUL_MODE_PROT32 :
5055 X86EMUL_MODE_PROT16;
5056 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5057 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5058 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5059 ctxt->emul_flags = vcpu->arch.hflags;
5061 init_decode_cache(ctxt);
5062 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5065 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5070 init_emulate_ctxt(vcpu);
5074 ctxt->_eip = ctxt->eip + inc_eip;
5075 ret = emulate_int_real(ctxt, irq);
5077 if (ret != X86EMUL_CONTINUE)
5078 return EMULATE_FAIL;
5080 ctxt->eip = ctxt->_eip;
5081 kvm_rip_write(vcpu, ctxt->eip);
5082 kvm_set_rflags(vcpu, ctxt->eflags);
5084 if (irq == NMI_VECTOR)
5085 vcpu->arch.nmi_pending = 0;
5087 vcpu->arch.interrupt.pending = false;
5089 return EMULATE_DONE;
5091 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5093 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5095 int r = EMULATE_DONE;
5097 ++vcpu->stat.insn_emulation_fail;
5098 trace_kvm_emulate_insn_failed(vcpu);
5099 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5100 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5101 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5102 vcpu->run->internal.ndata = 0;
5105 kvm_queue_exception(vcpu, UD_VECTOR);
5110 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5111 bool write_fault_to_shadow_pgtable,
5117 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5120 if (!vcpu->arch.mmu.direct_map) {
5122 * Write permission should be allowed since only
5123 * write access need to be emulated.
5125 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5128 * If the mapping is invalid in guest, let cpu retry
5129 * it to generate fault.
5131 if (gpa == UNMAPPED_GVA)
5136 * Do not retry the unhandleable instruction if it faults on the
5137 * readonly host memory, otherwise it will goto a infinite loop:
5138 * retry instruction -> write #PF -> emulation fail -> retry
5139 * instruction -> ...
5141 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5144 * If the instruction failed on the error pfn, it can not be fixed,
5145 * report the error to userspace.
5147 if (is_error_noslot_pfn(pfn))
5150 kvm_release_pfn_clean(pfn);
5152 /* The instructions are well-emulated on direct mmu. */
5153 if (vcpu->arch.mmu.direct_map) {
5154 unsigned int indirect_shadow_pages;
5156 spin_lock(&vcpu->kvm->mmu_lock);
5157 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5158 spin_unlock(&vcpu->kvm->mmu_lock);
5160 if (indirect_shadow_pages)
5161 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5167 * if emulation was due to access to shadowed page table
5168 * and it failed try to unshadow page and re-enter the
5169 * guest to let CPU execute the instruction.
5171 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5174 * If the access faults on its page table, it can not
5175 * be fixed by unprotecting shadow page and it should
5176 * be reported to userspace.
5178 return !write_fault_to_shadow_pgtable;
5181 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5182 unsigned long cr2, int emulation_type)
5184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5185 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5187 last_retry_eip = vcpu->arch.last_retry_eip;
5188 last_retry_addr = vcpu->arch.last_retry_addr;
5191 * If the emulation is caused by #PF and it is non-page_table
5192 * writing instruction, it means the VM-EXIT is caused by shadow
5193 * page protected, we can zap the shadow page and retry this
5194 * instruction directly.
5196 * Note: if the guest uses a non-page-table modifying instruction
5197 * on the PDE that points to the instruction, then we will unmap
5198 * the instruction and go to an infinite loop. So, we cache the
5199 * last retried eip and the last fault address, if we meet the eip
5200 * and the address again, we can break out of the potential infinite
5203 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5205 if (!(emulation_type & EMULTYPE_RETRY))
5208 if (x86_page_table_writing_insn(ctxt))
5211 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5214 vcpu->arch.last_retry_eip = ctxt->eip;
5215 vcpu->arch.last_retry_addr = cr2;
5217 if (!vcpu->arch.mmu.direct_map)
5218 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5220 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5225 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5226 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5228 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5230 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5231 /* This is a good place to trace that we are exiting SMM. */
5232 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5234 if (unlikely(vcpu->arch.smi_pending)) {
5235 kvm_make_request(KVM_REQ_SMI, vcpu);
5236 vcpu->arch.smi_pending = 0;
5238 /* Process a latched INIT, if any. */
5239 kvm_make_request(KVM_REQ_EVENT, vcpu);
5243 kvm_mmu_reset_context(vcpu);
5246 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5248 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5250 vcpu->arch.hflags = emul_flags;
5252 if (changed & HF_SMM_MASK)
5253 kvm_smm_changed(vcpu);
5256 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5265 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5266 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5271 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5273 struct kvm_run *kvm_run = vcpu->run;
5276 * rflags is the old, "raw" value of the flags. The new value has
5277 * not been saved yet.
5279 * This is correct even for TF set by the guest, because "the
5280 * processor will not generate this exception after the instruction
5281 * that sets the TF flag".
5283 if (unlikely(rflags & X86_EFLAGS_TF)) {
5284 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5285 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5287 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5288 kvm_run->debug.arch.exception = DB_VECTOR;
5289 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5290 *r = EMULATE_USER_EXIT;
5292 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5294 * "Certain debug exceptions may clear bit 0-3. The
5295 * remaining contents of the DR6 register are never
5296 * cleared by the processor".
5298 vcpu->arch.dr6 &= ~15;
5299 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5300 kvm_queue_exception(vcpu, DB_VECTOR);
5305 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5307 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5308 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5309 struct kvm_run *kvm_run = vcpu->run;
5310 unsigned long eip = kvm_get_linear_rip(vcpu);
5311 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5312 vcpu->arch.guest_debug_dr7,
5316 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5317 kvm_run->debug.arch.pc = eip;
5318 kvm_run->debug.arch.exception = DB_VECTOR;
5319 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5320 *r = EMULATE_USER_EXIT;
5325 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5326 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5327 unsigned long eip = kvm_get_linear_rip(vcpu);
5328 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5333 vcpu->arch.dr6 &= ~15;
5334 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5335 kvm_queue_exception(vcpu, DB_VECTOR);
5344 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5351 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5352 bool writeback = true;
5353 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5356 * Clear write_fault_to_shadow_pgtable here to ensure it is
5359 vcpu->arch.write_fault_to_shadow_pgtable = false;
5360 kvm_clear_exception_queue(vcpu);
5362 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5363 init_emulate_ctxt(vcpu);
5366 * We will reenter on the same instruction since
5367 * we do not set complete_userspace_io. This does not
5368 * handle watchpoints yet, those would be handled in
5371 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5374 ctxt->interruptibility = 0;
5375 ctxt->have_exception = false;
5376 ctxt->exception.vector = -1;
5377 ctxt->perm_ok = false;
5379 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5381 r = x86_decode_insn(ctxt, insn, insn_len);
5383 trace_kvm_emulate_insn_start(vcpu);
5384 ++vcpu->stat.insn_emulation;
5385 if (r != EMULATION_OK) {
5386 if (emulation_type & EMULTYPE_TRAP_UD)
5387 return EMULATE_FAIL;
5388 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5390 return EMULATE_DONE;
5391 if (emulation_type & EMULTYPE_SKIP)
5392 return EMULATE_FAIL;
5393 return handle_emulation_failure(vcpu);
5397 if (emulation_type & EMULTYPE_SKIP) {
5398 kvm_rip_write(vcpu, ctxt->_eip);
5399 if (ctxt->eflags & X86_EFLAGS_RF)
5400 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5401 return EMULATE_DONE;
5404 if (retry_instruction(ctxt, cr2, emulation_type))
5405 return EMULATE_DONE;
5407 /* this is needed for vmware backdoor interface to work since it
5408 changes registers values during IO operation */
5409 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5410 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5411 emulator_invalidate_register_cache(ctxt);
5415 r = x86_emulate_insn(ctxt);
5417 if (r == EMULATION_INTERCEPTED)
5418 return EMULATE_DONE;
5420 if (r == EMULATION_FAILED) {
5421 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5423 return EMULATE_DONE;
5425 return handle_emulation_failure(vcpu);
5428 if (ctxt->have_exception) {
5430 if (inject_emulated_exception(vcpu))
5432 } else if (vcpu->arch.pio.count) {
5433 if (!vcpu->arch.pio.in) {
5434 /* FIXME: return into emulator if single-stepping. */
5435 vcpu->arch.pio.count = 0;
5438 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5440 r = EMULATE_USER_EXIT;
5441 } else if (vcpu->mmio_needed) {
5442 if (!vcpu->mmio_is_write)
5444 r = EMULATE_USER_EXIT;
5445 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5446 } else if (r == EMULATION_RESTART)
5452 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5453 toggle_interruptibility(vcpu, ctxt->interruptibility);
5454 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5455 if (vcpu->arch.hflags != ctxt->emul_flags)
5456 kvm_set_hflags(vcpu, ctxt->emul_flags);
5457 kvm_rip_write(vcpu, ctxt->eip);
5458 if (r == EMULATE_DONE)
5459 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5460 if (!ctxt->have_exception ||
5461 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5462 __kvm_set_rflags(vcpu, ctxt->eflags);
5465 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5466 * do nothing, and it will be requested again as soon as
5467 * the shadow expires. But we still need to check here,
5468 * because POPF has no interrupt shadow.
5470 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5471 kvm_make_request(KVM_REQ_EVENT, vcpu);
5473 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5477 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5479 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5481 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5482 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5483 size, port, &val, 1);
5484 /* do not return to emulator after return from userspace */
5485 vcpu->arch.pio.count = 0;
5488 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5490 static void tsc_bad(void *info)
5492 __this_cpu_write(cpu_tsc_khz, 0);
5495 static void tsc_khz_changed(void *data)
5497 struct cpufreq_freqs *freq = data;
5498 unsigned long khz = 0;
5502 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5503 khz = cpufreq_quick_get(raw_smp_processor_id());
5506 __this_cpu_write(cpu_tsc_khz, khz);
5509 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5512 struct cpufreq_freqs *freq = data;
5514 struct kvm_vcpu *vcpu;
5515 int i, send_ipi = 0;
5518 * We allow guests to temporarily run on slowing clocks,
5519 * provided we notify them after, or to run on accelerating
5520 * clocks, provided we notify them before. Thus time never
5523 * However, we have a problem. We can't atomically update
5524 * the frequency of a given CPU from this function; it is
5525 * merely a notifier, which can be called from any CPU.
5526 * Changing the TSC frequency at arbitrary points in time
5527 * requires a recomputation of local variables related to
5528 * the TSC for each VCPU. We must flag these local variables
5529 * to be updated and be sure the update takes place with the
5530 * new frequency before any guests proceed.
5532 * Unfortunately, the combination of hotplug CPU and frequency
5533 * change creates an intractable locking scenario; the order
5534 * of when these callouts happen is undefined with respect to
5535 * CPU hotplug, and they can race with each other. As such,
5536 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5537 * undefined; you can actually have a CPU frequency change take
5538 * place in between the computation of X and the setting of the
5539 * variable. To protect against this problem, all updates of
5540 * the per_cpu tsc_khz variable are done in an interrupt
5541 * protected IPI, and all callers wishing to update the value
5542 * must wait for a synchronous IPI to complete (which is trivial
5543 * if the caller is on the CPU already). This establishes the
5544 * necessary total order on variable updates.
5546 * Note that because a guest time update may take place
5547 * anytime after the setting of the VCPU's request bit, the
5548 * correct TSC value must be set before the request. However,
5549 * to ensure the update actually makes it to any guest which
5550 * starts running in hardware virtualization between the set
5551 * and the acquisition of the spinlock, we must also ping the
5552 * CPU after setting the request bit.
5556 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5558 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5561 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5563 spin_lock(&kvm_lock);
5564 list_for_each_entry(kvm, &vm_list, vm_list) {
5565 kvm_for_each_vcpu(i, vcpu, kvm) {
5566 if (vcpu->cpu != freq->cpu)
5568 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5569 if (vcpu->cpu != smp_processor_id())
5573 spin_unlock(&kvm_lock);
5575 if (freq->old < freq->new && send_ipi) {
5577 * We upscale the frequency. Must make the guest
5578 * doesn't see old kvmclock values while running with
5579 * the new frequency, otherwise we risk the guest sees
5580 * time go backwards.
5582 * In case we update the frequency for another cpu
5583 * (which might be in guest context) send an interrupt
5584 * to kick the cpu out of guest context. Next time
5585 * guest context is entered kvmclock will be updated,
5586 * so the guest will not see stale values.
5588 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5593 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5594 .notifier_call = kvmclock_cpufreq_notifier
5597 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5598 unsigned long action, void *hcpu)
5600 unsigned int cpu = (unsigned long)hcpu;
5604 case CPU_DOWN_FAILED:
5605 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5607 case CPU_DOWN_PREPARE:
5608 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5614 static struct notifier_block kvmclock_cpu_notifier_block = {
5615 .notifier_call = kvmclock_cpu_notifier,
5616 .priority = -INT_MAX
5619 static void kvm_timer_init(void)
5623 max_tsc_khz = tsc_khz;
5625 cpu_notifier_register_begin();
5626 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5627 #ifdef CONFIG_CPU_FREQ
5628 struct cpufreq_policy policy;
5629 memset(&policy, 0, sizeof(policy));
5631 cpufreq_get_policy(&policy, cpu);
5632 if (policy.cpuinfo.max_freq)
5633 max_tsc_khz = policy.cpuinfo.max_freq;
5636 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5637 CPUFREQ_TRANSITION_NOTIFIER);
5639 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5640 for_each_online_cpu(cpu)
5641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5643 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5644 cpu_notifier_register_done();
5648 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5650 int kvm_is_in_guest(void)
5652 return __this_cpu_read(current_vcpu) != NULL;
5655 static int kvm_is_user_mode(void)
5659 if (__this_cpu_read(current_vcpu))
5660 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5662 return user_mode != 0;
5665 static unsigned long kvm_get_guest_ip(void)
5667 unsigned long ip = 0;
5669 if (__this_cpu_read(current_vcpu))
5670 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5675 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5676 .is_in_guest = kvm_is_in_guest,
5677 .is_user_mode = kvm_is_user_mode,
5678 .get_guest_ip = kvm_get_guest_ip,
5681 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5683 __this_cpu_write(current_vcpu, vcpu);
5685 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5687 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5689 __this_cpu_write(current_vcpu, NULL);
5691 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5693 static void kvm_set_mmio_spte_mask(void)
5696 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5699 * Set the reserved bits and the present bit of an paging-structure
5700 * entry to generate page fault with PFER.RSV = 1.
5702 /* Mask the reserved physical address bits. */
5703 mask = rsvd_bits(maxphyaddr, 51);
5705 /* Bit 62 is always reserved for 32bit host. */
5706 mask |= 0x3ull << 62;
5708 /* Set the present bit. */
5711 #ifdef CONFIG_X86_64
5713 * If reserved bit is not supported, clear the present bit to disable
5716 if (maxphyaddr == 52)
5720 kvm_mmu_set_mmio_spte_mask(mask);
5723 #ifdef CONFIG_X86_64
5724 static void pvclock_gtod_update_fn(struct work_struct *work)
5728 struct kvm_vcpu *vcpu;
5731 spin_lock(&kvm_lock);
5732 list_for_each_entry(kvm, &vm_list, vm_list)
5733 kvm_for_each_vcpu(i, vcpu, kvm)
5734 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5735 atomic_set(&kvm_guest_has_master_clock, 0);
5736 spin_unlock(&kvm_lock);
5739 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5742 * Notification about pvclock gtod data update.
5744 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5747 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5748 struct timekeeper *tk = priv;
5750 update_pvclock_gtod(tk);
5752 /* disable master clock if host does not trust, or does not
5753 * use, TSC clocksource
5755 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5756 atomic_read(&kvm_guest_has_master_clock) != 0)
5757 queue_work(system_long_wq, &pvclock_gtod_work);
5762 static struct notifier_block pvclock_gtod_notifier = {
5763 .notifier_call = pvclock_gtod_notify,
5767 int kvm_arch_init(void *opaque)
5770 struct kvm_x86_ops *ops = opaque;
5773 printk(KERN_ERR "kvm: already loaded the other module\n");
5778 if (!ops->cpu_has_kvm_support()) {
5779 printk(KERN_ERR "kvm: no hardware support\n");
5783 if (ops->disabled_by_bios()) {
5784 printk(KERN_ERR "kvm: disabled by bios\n");
5790 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5792 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5796 #ifdef CONFIG_PREEMPT_RT_FULL
5797 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5798 printk(KERN_ERR "RT requires X86_FEATURE_CONSTANT_TSC\n");
5803 r = kvm_mmu_module_init();
5805 goto out_free_percpu;
5807 kvm_set_mmio_spte_mask();
5811 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5812 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5816 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5819 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5822 #ifdef CONFIG_X86_64
5823 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5829 free_percpu(shared_msrs);
5834 void kvm_arch_exit(void)
5836 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5838 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5839 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5840 CPUFREQ_TRANSITION_NOTIFIER);
5841 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5842 #ifdef CONFIG_X86_64
5843 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5846 kvm_mmu_module_exit();
5847 free_percpu(shared_msrs);
5850 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5852 ++vcpu->stat.halt_exits;
5853 if (lapic_in_kernel(vcpu)) {
5854 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5857 vcpu->run->exit_reason = KVM_EXIT_HLT;
5861 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5863 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5865 kvm_x86_ops->skip_emulated_instruction(vcpu);
5866 return kvm_vcpu_halt(vcpu);
5868 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5871 * kvm_pv_kick_cpu_op: Kick a vcpu.
5873 * @apicid - apicid of vcpu to be kicked.
5875 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5877 struct kvm_lapic_irq lapic_irq;
5879 lapic_irq.shorthand = 0;
5880 lapic_irq.dest_mode = 0;
5881 lapic_irq.dest_id = apicid;
5882 lapic_irq.msi_redir_hint = false;
5884 lapic_irq.delivery_mode = APIC_DM_REMRD;
5885 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5888 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5890 unsigned long nr, a0, a1, a2, a3, ret;
5891 int op_64_bit, r = 1;
5893 kvm_x86_ops->skip_emulated_instruction(vcpu);
5895 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5896 return kvm_hv_hypercall(vcpu);
5898 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5899 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5900 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5901 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5902 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5904 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5906 op_64_bit = is_64_bit_mode(vcpu);
5915 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5921 case KVM_HC_VAPIC_POLL_IRQ:
5924 case KVM_HC_KICK_CPU:
5925 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5935 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5936 ++vcpu->stat.hypercalls;
5939 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5941 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5943 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5944 char instruction[3];
5945 unsigned long rip = kvm_rip_read(vcpu);
5947 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5949 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5952 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5954 return vcpu->run->request_interrupt_window &&
5955 likely(!pic_in_kernel(vcpu->kvm));
5958 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5960 struct kvm_run *kvm_run = vcpu->run;
5962 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5963 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5964 kvm_run->cr8 = kvm_get_cr8(vcpu);
5965 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5966 kvm_run->ready_for_interrupt_injection =
5967 pic_in_kernel(vcpu->kvm) ||
5968 kvm_vcpu_ready_for_interrupt_injection(vcpu);
5971 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5975 if (!kvm_x86_ops->update_cr8_intercept)
5978 if (!vcpu->arch.apic)
5981 if (!vcpu->arch.apic->vapic_addr)
5982 max_irr = kvm_lapic_find_highest_irr(vcpu);
5989 tpr = kvm_lapic_get_cr8(vcpu);
5991 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5994 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5998 /* try to reinject previous events if any */
5999 if (vcpu->arch.exception.pending) {
6000 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6001 vcpu->arch.exception.has_error_code,
6002 vcpu->arch.exception.error_code);
6004 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6005 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6008 if (vcpu->arch.exception.nr == DB_VECTOR &&
6009 (vcpu->arch.dr7 & DR7_GD)) {
6010 vcpu->arch.dr7 &= ~DR7_GD;
6011 kvm_update_dr7(vcpu);
6014 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6015 vcpu->arch.exception.has_error_code,
6016 vcpu->arch.exception.error_code,
6017 vcpu->arch.exception.reinject);
6021 if (vcpu->arch.nmi_injected) {
6022 kvm_x86_ops->set_nmi(vcpu);
6026 if (vcpu->arch.interrupt.pending) {
6027 kvm_x86_ops->set_irq(vcpu);
6031 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6032 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6037 /* try to inject new event if pending */
6038 if (vcpu->arch.nmi_pending) {
6039 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6040 --vcpu->arch.nmi_pending;
6041 vcpu->arch.nmi_injected = true;
6042 kvm_x86_ops->set_nmi(vcpu);
6044 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6046 * Because interrupts can be injected asynchronously, we are
6047 * calling check_nested_events again here to avoid a race condition.
6048 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6049 * proposal and current concerns. Perhaps we should be setting
6050 * KVM_REQ_EVENT only on certain events and not unconditionally?
6052 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6053 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6057 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6058 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6060 kvm_x86_ops->set_irq(vcpu);
6066 static void process_nmi(struct kvm_vcpu *vcpu)
6071 * x86 is limited to one NMI running, and one NMI pending after it.
6072 * If an NMI is already in progress, limit further NMIs to just one.
6073 * Otherwise, allow two (and we'll inject the first one immediately).
6075 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6078 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6079 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6080 kvm_make_request(KVM_REQ_EVENT, vcpu);
6083 #define put_smstate(type, buf, offset, val) \
6084 *(type *)((buf) + (offset) - 0x7e00) = val
6086 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6089 flags |= seg->g << 23;
6090 flags |= seg->db << 22;
6091 flags |= seg->l << 21;
6092 flags |= seg->avl << 20;
6093 flags |= seg->present << 15;
6094 flags |= seg->dpl << 13;
6095 flags |= seg->s << 12;
6096 flags |= seg->type << 8;
6100 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6102 struct kvm_segment seg;
6105 kvm_get_segment(vcpu, &seg, n);
6106 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6109 offset = 0x7f84 + n * 12;
6111 offset = 0x7f2c + (n - 3) * 12;
6113 put_smstate(u32, buf, offset + 8, seg.base);
6114 put_smstate(u32, buf, offset + 4, seg.limit);
6115 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6118 #ifdef CONFIG_X86_64
6119 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6121 struct kvm_segment seg;
6125 kvm_get_segment(vcpu, &seg, n);
6126 offset = 0x7e00 + n * 16;
6128 flags = process_smi_get_segment_flags(&seg) >> 8;
6129 put_smstate(u16, buf, offset, seg.selector);
6130 put_smstate(u16, buf, offset + 2, flags);
6131 put_smstate(u32, buf, offset + 4, seg.limit);
6132 put_smstate(u64, buf, offset + 8, seg.base);
6136 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6139 struct kvm_segment seg;
6143 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6144 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6145 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6146 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6148 for (i = 0; i < 8; i++)
6149 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6151 kvm_get_dr(vcpu, 6, &val);
6152 put_smstate(u32, buf, 0x7fcc, (u32)val);
6153 kvm_get_dr(vcpu, 7, &val);
6154 put_smstate(u32, buf, 0x7fc8, (u32)val);
6156 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6157 put_smstate(u32, buf, 0x7fc4, seg.selector);
6158 put_smstate(u32, buf, 0x7f64, seg.base);
6159 put_smstate(u32, buf, 0x7f60, seg.limit);
6160 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6162 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6163 put_smstate(u32, buf, 0x7fc0, seg.selector);
6164 put_smstate(u32, buf, 0x7f80, seg.base);
6165 put_smstate(u32, buf, 0x7f7c, seg.limit);
6166 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6168 kvm_x86_ops->get_gdt(vcpu, &dt);
6169 put_smstate(u32, buf, 0x7f74, dt.address);
6170 put_smstate(u32, buf, 0x7f70, dt.size);
6172 kvm_x86_ops->get_idt(vcpu, &dt);
6173 put_smstate(u32, buf, 0x7f58, dt.address);
6174 put_smstate(u32, buf, 0x7f54, dt.size);
6176 for (i = 0; i < 6; i++)
6177 process_smi_save_seg_32(vcpu, buf, i);
6179 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6182 put_smstate(u32, buf, 0x7efc, 0x00020000);
6183 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6186 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6188 #ifdef CONFIG_X86_64
6190 struct kvm_segment seg;
6194 for (i = 0; i < 16; i++)
6195 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6197 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6198 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6200 kvm_get_dr(vcpu, 6, &val);
6201 put_smstate(u64, buf, 0x7f68, val);
6202 kvm_get_dr(vcpu, 7, &val);
6203 put_smstate(u64, buf, 0x7f60, val);
6205 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6206 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6207 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6209 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6212 put_smstate(u32, buf, 0x7efc, 0x00020064);
6214 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6216 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6217 put_smstate(u16, buf, 0x7e90, seg.selector);
6218 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6219 put_smstate(u32, buf, 0x7e94, seg.limit);
6220 put_smstate(u64, buf, 0x7e98, seg.base);
6222 kvm_x86_ops->get_idt(vcpu, &dt);
6223 put_smstate(u32, buf, 0x7e84, dt.size);
6224 put_smstate(u64, buf, 0x7e88, dt.address);
6226 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6227 put_smstate(u16, buf, 0x7e70, seg.selector);
6228 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6229 put_smstate(u32, buf, 0x7e74, seg.limit);
6230 put_smstate(u64, buf, 0x7e78, seg.base);
6232 kvm_x86_ops->get_gdt(vcpu, &dt);
6233 put_smstate(u32, buf, 0x7e64, dt.size);
6234 put_smstate(u64, buf, 0x7e68, dt.address);
6236 for (i = 0; i < 6; i++)
6237 process_smi_save_seg_64(vcpu, buf, i);
6243 static void process_smi(struct kvm_vcpu *vcpu)
6245 struct kvm_segment cs, ds;
6251 vcpu->arch.smi_pending = true;
6255 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6256 vcpu->arch.hflags |= HF_SMM_MASK;
6257 memset(buf, 0, 512);
6258 if (guest_cpuid_has_longmode(vcpu))
6259 process_smi_save_state_64(vcpu, buf);
6261 process_smi_save_state_32(vcpu, buf);
6263 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6265 if (kvm_x86_ops->get_nmi_mask(vcpu))
6266 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6268 kvm_x86_ops->set_nmi_mask(vcpu, true);
6270 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6271 kvm_rip_write(vcpu, 0x8000);
6273 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6274 kvm_x86_ops->set_cr0(vcpu, cr0);
6275 vcpu->arch.cr0 = cr0;
6277 kvm_x86_ops->set_cr4(vcpu, 0);
6279 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6280 dt.address = dt.size = 0;
6281 kvm_x86_ops->set_idt(vcpu, &dt);
6283 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6285 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6286 cs.base = vcpu->arch.smbase;
6291 cs.limit = ds.limit = 0xffffffff;
6292 cs.type = ds.type = 0x3;
6293 cs.dpl = ds.dpl = 0;
6298 cs.avl = ds.avl = 0;
6299 cs.present = ds.present = 1;
6300 cs.unusable = ds.unusable = 0;
6301 cs.padding = ds.padding = 0;
6303 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6304 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6305 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6306 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6307 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6308 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6310 if (guest_cpuid_has_longmode(vcpu))
6311 kvm_x86_ops->set_efer(vcpu, 0);
6313 kvm_update_cpuid(vcpu);
6314 kvm_mmu_reset_context(vcpu);
6317 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6319 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6322 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
6324 if (irqchip_split(vcpu->kvm))
6325 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6327 kvm_x86_ops->sync_pir_to_irr(vcpu);
6328 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
6330 kvm_x86_ops->load_eoi_exitmap(vcpu);
6333 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6335 ++vcpu->stat.tlb_flush;
6336 kvm_x86_ops->tlb_flush(vcpu);
6339 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6341 struct page *page = NULL;
6343 if (!lapic_in_kernel(vcpu))
6346 if (!kvm_x86_ops->set_apic_access_page_addr)
6349 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6350 if (is_error_page(page))
6352 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6355 * Do not pin apic access page in memory, the MMU notifier
6356 * will call us again if it is migrated or swapped out.
6360 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6362 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6363 unsigned long address)
6366 * The physical address of apic access page is stored in the VMCS.
6367 * Update it when it becomes invalid.
6369 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6370 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6374 * Returns 1 to let vcpu_run() continue the guest execution loop without
6375 * exiting to the userspace. Otherwise, the value will be returned to the
6378 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6382 dm_request_for_irq_injection(vcpu) &&
6383 kvm_cpu_accept_dm_intr(vcpu);
6385 bool req_immediate_exit = false;
6387 if (vcpu->requests) {
6388 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6389 kvm_mmu_unload(vcpu);
6390 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6391 __kvm_migrate_timers(vcpu);
6392 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6393 kvm_gen_update_masterclock(vcpu->kvm);
6394 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6395 kvm_gen_kvmclock_update(vcpu);
6396 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6397 r = kvm_guest_time_update(vcpu);
6401 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6402 kvm_mmu_sync_roots(vcpu);
6403 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6404 kvm_vcpu_flush_tlb(vcpu);
6405 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6406 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6410 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6411 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6415 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6416 vcpu->fpu_active = 0;
6417 kvm_x86_ops->fpu_deactivate(vcpu);
6419 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6420 /* Page is swapped out. Do synthetic halt */
6421 vcpu->arch.apf.halted = true;
6425 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6426 record_steal_time(vcpu);
6427 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6429 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6431 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6432 kvm_pmu_handle_event(vcpu);
6433 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6434 kvm_pmu_deliver_pmi(vcpu);
6435 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6436 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6437 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6438 (void *) vcpu->arch.eoi_exit_bitmap)) {
6439 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6440 vcpu->run->eoi.vector =
6441 vcpu->arch.pending_ioapic_eoi;
6446 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6447 vcpu_scan_ioapic(vcpu);
6448 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6449 kvm_vcpu_reload_apic_access_page(vcpu);
6450 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6451 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6452 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6456 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6457 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6458 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6465 * KVM_REQ_EVENT is not set when posted interrupts are set by
6466 * VT-d hardware, so we have to update RVI unconditionally.
6468 if (kvm_lapic_enabled(vcpu)) {
6470 * Update architecture specific hints for APIC
6471 * virtual interrupt delivery.
6473 if (kvm_x86_ops->hwapic_irr_update)
6474 kvm_x86_ops->hwapic_irr_update(vcpu,
6475 kvm_lapic_find_highest_irr(vcpu));
6478 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6479 kvm_apic_accept_events(vcpu);
6480 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6485 if (inject_pending_event(vcpu, req_int_win) != 0)
6486 req_immediate_exit = true;
6487 /* enable NMI/IRQ window open exits if needed */
6488 else if (vcpu->arch.nmi_pending)
6489 kvm_x86_ops->enable_nmi_window(vcpu);
6490 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6491 kvm_x86_ops->enable_irq_window(vcpu);
6493 if (kvm_lapic_enabled(vcpu)) {
6494 update_cr8_intercept(vcpu);
6495 kvm_lapic_sync_to_vapic(vcpu);
6499 r = kvm_mmu_reload(vcpu);
6501 goto cancel_injection;
6506 kvm_x86_ops->prepare_guest_switch(vcpu);
6507 if (vcpu->fpu_active)
6508 kvm_load_guest_fpu(vcpu);
6509 kvm_load_guest_xcr0(vcpu);
6511 vcpu->mode = IN_GUEST_MODE;
6513 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6515 /* We should set ->mode before check ->requests,
6516 * see the comment in make_all_cpus_request.
6518 smp_mb__after_srcu_read_unlock();
6520 local_irq_disable();
6522 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6523 || need_resched() || signal_pending(current)) {
6524 vcpu->mode = OUTSIDE_GUEST_MODE;
6528 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6530 goto cancel_injection;
6533 if (req_immediate_exit)
6534 smp_send_reschedule(vcpu->cpu);
6536 trace_kvm_entry(vcpu->vcpu_id);
6537 wait_lapic_expire(vcpu);
6538 __kvm_guest_enter();
6540 if (unlikely(vcpu->arch.switch_db_regs)) {
6542 set_debugreg(vcpu->arch.eff_db[0], 0);
6543 set_debugreg(vcpu->arch.eff_db[1], 1);
6544 set_debugreg(vcpu->arch.eff_db[2], 2);
6545 set_debugreg(vcpu->arch.eff_db[3], 3);
6546 set_debugreg(vcpu->arch.dr6, 6);
6547 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6550 kvm_x86_ops->run(vcpu);
6553 * Do this here before restoring debug registers on the host. And
6554 * since we do this before handling the vmexit, a DR access vmexit
6555 * can (a) read the correct value of the debug registers, (b) set
6556 * KVM_DEBUGREG_WONT_EXIT again.
6558 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6559 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6560 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6561 kvm_update_dr0123(vcpu);
6562 kvm_update_dr6(vcpu);
6563 kvm_update_dr7(vcpu);
6564 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6568 * If the guest has used debug registers, at least dr7
6569 * will be disabled while returning to the host.
6570 * If we don't have active breakpoints in the host, we don't
6571 * care about the messed up debug address registers. But if
6572 * we have some of them active, restore the old state.
6574 if (hw_breakpoint_active())
6575 hw_breakpoint_restore();
6577 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6579 vcpu->mode = OUTSIDE_GUEST_MODE;
6582 /* Interrupt is enabled by handle_external_intr() */
6583 kvm_x86_ops->handle_external_intr(vcpu);
6588 * We must have an instruction between local_irq_enable() and
6589 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6590 * the interrupt shadow. The stat.exits increment will do nicely.
6591 * But we need to prevent reordering, hence this barrier():
6599 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6602 * Profile KVM exit RIPs:
6604 if (unlikely(prof_on == KVM_PROFILING)) {
6605 unsigned long rip = kvm_rip_read(vcpu);
6606 profile_hit(KVM_PROFILING, (void *)rip);
6609 if (unlikely(vcpu->arch.tsc_always_catchup))
6610 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6612 if (vcpu->arch.apic_attention)
6613 kvm_lapic_sync_from_vapic(vcpu);
6615 r = kvm_x86_ops->handle_exit(vcpu);
6619 kvm_x86_ops->cancel_injection(vcpu);
6620 if (unlikely(vcpu->arch.apic_attention))
6621 kvm_lapic_sync_from_vapic(vcpu);
6626 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6628 if (!kvm_arch_vcpu_runnable(vcpu) &&
6629 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6630 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6631 kvm_vcpu_block(vcpu);
6632 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6634 if (kvm_x86_ops->post_block)
6635 kvm_x86_ops->post_block(vcpu);
6637 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6641 kvm_apic_accept_events(vcpu);
6642 switch(vcpu->arch.mp_state) {
6643 case KVM_MP_STATE_HALTED:
6644 vcpu->arch.pv.pv_unhalted = false;
6645 vcpu->arch.mp_state =
6646 KVM_MP_STATE_RUNNABLE;
6647 case KVM_MP_STATE_RUNNABLE:
6648 vcpu->arch.apf.halted = false;
6650 case KVM_MP_STATE_INIT_RECEIVED:
6659 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6661 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6662 !vcpu->arch.apf.halted);
6665 static int vcpu_run(struct kvm_vcpu *vcpu)
6668 struct kvm *kvm = vcpu->kvm;
6670 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6673 if (kvm_vcpu_running(vcpu)) {
6674 r = vcpu_enter_guest(vcpu);
6676 r = vcpu_block(kvm, vcpu);
6682 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6683 if (kvm_cpu_has_pending_timer(vcpu))
6684 kvm_inject_pending_timer_irqs(vcpu);
6686 if (dm_request_for_irq_injection(vcpu) &&
6687 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6689 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6690 ++vcpu->stat.request_irq_exits;
6694 kvm_check_async_pf_completion(vcpu);
6696 if (signal_pending(current)) {
6698 vcpu->run->exit_reason = KVM_EXIT_INTR;
6699 ++vcpu->stat.signal_exits;
6702 if (need_resched()) {
6703 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6705 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6709 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6714 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6717 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6718 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6719 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6720 if (r != EMULATE_DONE)
6725 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6727 BUG_ON(!vcpu->arch.pio.count);
6729 return complete_emulated_io(vcpu);
6733 * Implements the following, as a state machine:
6737 * for each mmio piece in the fragment
6745 * for each mmio piece in the fragment
6750 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6752 struct kvm_run *run = vcpu->run;
6753 struct kvm_mmio_fragment *frag;
6756 BUG_ON(!vcpu->mmio_needed);
6758 /* Complete previous fragment */
6759 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6760 len = min(8u, frag->len);
6761 if (!vcpu->mmio_is_write)
6762 memcpy(frag->data, run->mmio.data, len);
6764 if (frag->len <= 8) {
6765 /* Switch to the next fragment. */
6767 vcpu->mmio_cur_fragment++;
6769 /* Go forward to the next mmio piece. */
6775 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6776 vcpu->mmio_needed = 0;
6778 /* FIXME: return into emulator if single-stepping. */
6779 if (vcpu->mmio_is_write)
6781 vcpu->mmio_read_completed = 1;
6782 return complete_emulated_io(vcpu);
6785 run->exit_reason = KVM_EXIT_MMIO;
6786 run->mmio.phys_addr = frag->gpa;
6787 if (vcpu->mmio_is_write)
6788 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6789 run->mmio.len = min(8u, frag->len);
6790 run->mmio.is_write = vcpu->mmio_is_write;
6791 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6796 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6798 struct fpu *fpu = ¤t->thread.fpu;
6802 fpu__activate_curr(fpu);
6804 if (vcpu->sigset_active)
6805 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6807 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6808 kvm_vcpu_block(vcpu);
6809 kvm_apic_accept_events(vcpu);
6810 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6815 /* re-sync apic's tpr */
6816 if (!lapic_in_kernel(vcpu)) {
6817 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6823 if (unlikely(vcpu->arch.complete_userspace_io)) {
6824 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6825 vcpu->arch.complete_userspace_io = NULL;
6830 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6835 post_kvm_run_save(vcpu);
6836 if (vcpu->sigset_active)
6837 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6842 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6844 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6846 * We are here if userspace calls get_regs() in the middle of
6847 * instruction emulation. Registers state needs to be copied
6848 * back from emulation context to vcpu. Userspace shouldn't do
6849 * that usually, but some bad designed PV devices (vmware
6850 * backdoor interface) need this to work
6852 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6853 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6855 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6856 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6857 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6858 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6859 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6860 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6861 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6862 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6863 #ifdef CONFIG_X86_64
6864 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6865 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6866 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6867 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6868 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6869 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6870 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6871 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6874 regs->rip = kvm_rip_read(vcpu);
6875 regs->rflags = kvm_get_rflags(vcpu);
6880 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6882 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6883 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6885 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6886 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6887 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6888 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6889 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6890 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6891 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6892 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6893 #ifdef CONFIG_X86_64
6894 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6895 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6896 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6897 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6898 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6899 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6900 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6901 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6904 kvm_rip_write(vcpu, regs->rip);
6905 kvm_set_rflags(vcpu, regs->rflags);
6907 vcpu->arch.exception.pending = false;
6909 kvm_make_request(KVM_REQ_EVENT, vcpu);
6914 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6916 struct kvm_segment cs;
6918 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6922 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6924 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6925 struct kvm_sregs *sregs)
6929 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6930 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6931 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6932 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6933 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6934 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6936 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6937 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6939 kvm_x86_ops->get_idt(vcpu, &dt);
6940 sregs->idt.limit = dt.size;
6941 sregs->idt.base = dt.address;
6942 kvm_x86_ops->get_gdt(vcpu, &dt);
6943 sregs->gdt.limit = dt.size;
6944 sregs->gdt.base = dt.address;
6946 sregs->cr0 = kvm_read_cr0(vcpu);
6947 sregs->cr2 = vcpu->arch.cr2;
6948 sregs->cr3 = kvm_read_cr3(vcpu);
6949 sregs->cr4 = kvm_read_cr4(vcpu);
6950 sregs->cr8 = kvm_get_cr8(vcpu);
6951 sregs->efer = vcpu->arch.efer;
6952 sregs->apic_base = kvm_get_apic_base(vcpu);
6954 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6956 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6957 set_bit(vcpu->arch.interrupt.nr,
6958 (unsigned long *)sregs->interrupt_bitmap);
6963 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6964 struct kvm_mp_state *mp_state)
6966 kvm_apic_accept_events(vcpu);
6967 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6968 vcpu->arch.pv.pv_unhalted)
6969 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6971 mp_state->mp_state = vcpu->arch.mp_state;
6976 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6977 struct kvm_mp_state *mp_state)
6979 if (!kvm_vcpu_has_lapic(vcpu) &&
6980 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6983 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6984 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6985 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6987 vcpu->arch.mp_state = mp_state->mp_state;
6988 kvm_make_request(KVM_REQ_EVENT, vcpu);
6992 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6993 int reason, bool has_error_code, u32 error_code)
6995 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6998 init_emulate_ctxt(vcpu);
7000 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7001 has_error_code, error_code);
7004 return EMULATE_FAIL;
7006 kvm_rip_write(vcpu, ctxt->eip);
7007 kvm_set_rflags(vcpu, ctxt->eflags);
7008 kvm_make_request(KVM_REQ_EVENT, vcpu);
7009 return EMULATE_DONE;
7011 EXPORT_SYMBOL_GPL(kvm_task_switch);
7013 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7014 struct kvm_sregs *sregs)
7016 struct msr_data apic_base_msr;
7017 int mmu_reset_needed = 0;
7018 int pending_vec, max_bits, idx;
7021 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7024 dt.size = sregs->idt.limit;
7025 dt.address = sregs->idt.base;
7026 kvm_x86_ops->set_idt(vcpu, &dt);
7027 dt.size = sregs->gdt.limit;
7028 dt.address = sregs->gdt.base;
7029 kvm_x86_ops->set_gdt(vcpu, &dt);
7031 vcpu->arch.cr2 = sregs->cr2;
7032 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7033 vcpu->arch.cr3 = sregs->cr3;
7034 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7036 kvm_set_cr8(vcpu, sregs->cr8);
7038 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7039 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7040 apic_base_msr.data = sregs->apic_base;
7041 apic_base_msr.host_initiated = true;
7042 kvm_set_apic_base(vcpu, &apic_base_msr);
7044 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7045 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7046 vcpu->arch.cr0 = sregs->cr0;
7048 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7049 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7050 if (sregs->cr4 & X86_CR4_OSXSAVE)
7051 kvm_update_cpuid(vcpu);
7053 idx = srcu_read_lock(&vcpu->kvm->srcu);
7054 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7055 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7056 mmu_reset_needed = 1;
7058 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7060 if (mmu_reset_needed)
7061 kvm_mmu_reset_context(vcpu);
7063 max_bits = KVM_NR_INTERRUPTS;
7064 pending_vec = find_first_bit(
7065 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7066 if (pending_vec < max_bits) {
7067 kvm_queue_interrupt(vcpu, pending_vec, false);
7068 pr_debug("Set back pending irq %d\n", pending_vec);
7071 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7072 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7073 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7074 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7075 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7076 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7078 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7079 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7081 update_cr8_intercept(vcpu);
7083 /* Older userspace won't unhalt the vcpu on reset. */
7084 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7085 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7087 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7089 kvm_make_request(KVM_REQ_EVENT, vcpu);
7094 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7095 struct kvm_guest_debug *dbg)
7097 unsigned long rflags;
7100 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7102 if (vcpu->arch.exception.pending)
7104 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7105 kvm_queue_exception(vcpu, DB_VECTOR);
7107 kvm_queue_exception(vcpu, BP_VECTOR);
7111 * Read rflags as long as potentially injected trace flags are still
7114 rflags = kvm_get_rflags(vcpu);
7116 vcpu->guest_debug = dbg->control;
7117 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7118 vcpu->guest_debug = 0;
7120 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7121 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7122 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7123 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7125 for (i = 0; i < KVM_NR_DB_REGS; i++)
7126 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7128 kvm_update_dr7(vcpu);
7130 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7131 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7132 get_segment_base(vcpu, VCPU_SREG_CS);
7135 * Trigger an rflags update that will inject or remove the trace
7138 kvm_set_rflags(vcpu, rflags);
7140 kvm_x86_ops->update_bp_intercept(vcpu);
7150 * Translate a guest virtual address to a guest physical address.
7152 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7153 struct kvm_translation *tr)
7155 unsigned long vaddr = tr->linear_address;
7159 idx = srcu_read_lock(&vcpu->kvm->srcu);
7160 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7161 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7162 tr->physical_address = gpa;
7163 tr->valid = gpa != UNMAPPED_GVA;
7170 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7172 struct fxregs_state *fxsave =
7173 &vcpu->arch.guest_fpu.state.fxsave;
7175 memcpy(fpu->fpr, fxsave->st_space, 128);
7176 fpu->fcw = fxsave->cwd;
7177 fpu->fsw = fxsave->swd;
7178 fpu->ftwx = fxsave->twd;
7179 fpu->last_opcode = fxsave->fop;
7180 fpu->last_ip = fxsave->rip;
7181 fpu->last_dp = fxsave->rdp;
7182 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7187 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7189 struct fxregs_state *fxsave =
7190 &vcpu->arch.guest_fpu.state.fxsave;
7192 memcpy(fxsave->st_space, fpu->fpr, 128);
7193 fxsave->cwd = fpu->fcw;
7194 fxsave->swd = fpu->fsw;
7195 fxsave->twd = fpu->ftwx;
7196 fxsave->fop = fpu->last_opcode;
7197 fxsave->rip = fpu->last_ip;
7198 fxsave->rdp = fpu->last_dp;
7199 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7204 static void fx_init(struct kvm_vcpu *vcpu)
7206 fpstate_init(&vcpu->arch.guest_fpu.state);
7208 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7209 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7212 * Ensure guest xcr0 is valid for loading
7214 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7216 vcpu->arch.cr0 |= X86_CR0_ET;
7219 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7221 if (vcpu->guest_fpu_loaded)
7225 * Restore all possible states in the guest,
7226 * and assume host would use all available bits.
7227 * Guest xcr0 would be loaded later.
7229 kvm_put_guest_xcr0(vcpu);
7230 vcpu->guest_fpu_loaded = 1;
7231 __kernel_fpu_begin();
7232 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7236 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7238 kvm_put_guest_xcr0(vcpu);
7240 if (!vcpu->guest_fpu_loaded) {
7241 vcpu->fpu_counter = 0;
7245 vcpu->guest_fpu_loaded = 0;
7246 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7248 ++vcpu->stat.fpu_reload;
7250 * If using eager FPU mode, or if the guest is a frequent user
7251 * of the FPU, just leave the FPU active for next time.
7252 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7253 * the FPU in bursts will revert to loading it on demand.
7255 if (!vcpu->arch.eager_fpu) {
7256 if (++vcpu->fpu_counter < 5)
7257 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7262 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7264 kvmclock_reset(vcpu);
7266 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7267 kvm_x86_ops->vcpu_free(vcpu);
7270 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7273 struct kvm_vcpu *vcpu;
7275 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7276 printk_once(KERN_WARNING
7277 "kvm: SMP vm created on host with unstable TSC; "
7278 "guest TSC will not be reliable\n");
7280 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7285 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7289 kvm_vcpu_mtrr_init(vcpu);
7290 r = vcpu_load(vcpu);
7293 kvm_vcpu_reset(vcpu, false);
7294 kvm_mmu_setup(vcpu);
7299 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7301 struct msr_data msr;
7302 struct kvm *kvm = vcpu->kvm;
7304 if (vcpu_load(vcpu))
7307 msr.index = MSR_IA32_TSC;
7308 msr.host_initiated = true;
7309 kvm_write_tsc(vcpu, &msr);
7312 if (!kvmclock_periodic_sync)
7315 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7316 KVMCLOCK_SYNC_PERIOD);
7319 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7322 vcpu->arch.apf.msr_val = 0;
7324 r = vcpu_load(vcpu);
7326 kvm_mmu_unload(vcpu);
7329 kvm_x86_ops->vcpu_free(vcpu);
7332 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7334 vcpu->arch.hflags = 0;
7336 atomic_set(&vcpu->arch.nmi_queued, 0);
7337 vcpu->arch.nmi_pending = 0;
7338 vcpu->arch.nmi_injected = false;
7339 kvm_clear_interrupt_queue(vcpu);
7340 kvm_clear_exception_queue(vcpu);
7342 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7343 kvm_update_dr0123(vcpu);
7344 vcpu->arch.dr6 = DR6_INIT;
7345 kvm_update_dr6(vcpu);
7346 vcpu->arch.dr7 = DR7_FIXED_1;
7347 kvm_update_dr7(vcpu);
7351 kvm_make_request(KVM_REQ_EVENT, vcpu);
7352 vcpu->arch.apf.msr_val = 0;
7353 vcpu->arch.st.msr_val = 0;
7355 kvmclock_reset(vcpu);
7357 kvm_clear_async_pf_completion_queue(vcpu);
7358 kvm_async_pf_hash_reset(vcpu);
7359 vcpu->arch.apf.halted = false;
7362 kvm_pmu_reset(vcpu);
7363 vcpu->arch.smbase = 0x30000;
7366 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7367 vcpu->arch.regs_avail = ~0;
7368 vcpu->arch.regs_dirty = ~0;
7370 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7373 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7375 struct kvm_segment cs;
7377 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7378 cs.selector = vector << 8;
7379 cs.base = vector << 12;
7380 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7381 kvm_rip_write(vcpu, 0);
7384 int kvm_arch_hardware_enable(void)
7387 struct kvm_vcpu *vcpu;
7392 bool stable, backwards_tsc = false;
7394 kvm_shared_msr_cpu_online();
7395 ret = kvm_x86_ops->hardware_enable();
7399 local_tsc = rdtsc();
7400 stable = !check_tsc_unstable();
7401 list_for_each_entry(kvm, &vm_list, vm_list) {
7402 kvm_for_each_vcpu(i, vcpu, kvm) {
7403 if (!stable && vcpu->cpu == smp_processor_id())
7404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7405 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7406 backwards_tsc = true;
7407 if (vcpu->arch.last_host_tsc > max_tsc)
7408 max_tsc = vcpu->arch.last_host_tsc;
7414 * Sometimes, even reliable TSCs go backwards. This happens on
7415 * platforms that reset TSC during suspend or hibernate actions, but
7416 * maintain synchronization. We must compensate. Fortunately, we can
7417 * detect that condition here, which happens early in CPU bringup,
7418 * before any KVM threads can be running. Unfortunately, we can't
7419 * bring the TSCs fully up to date with real time, as we aren't yet far
7420 * enough into CPU bringup that we know how much real time has actually
7421 * elapsed; our helper function, get_kernel_ns() will be using boot
7422 * variables that haven't been updated yet.
7424 * So we simply find the maximum observed TSC above, then record the
7425 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7426 * the adjustment will be applied. Note that we accumulate
7427 * adjustments, in case multiple suspend cycles happen before some VCPU
7428 * gets a chance to run again. In the event that no KVM threads get a
7429 * chance to run, we will miss the entire elapsed period, as we'll have
7430 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7431 * loose cycle time. This isn't too big a deal, since the loss will be
7432 * uniform across all VCPUs (not to mention the scenario is extremely
7433 * unlikely). It is possible that a second hibernate recovery happens
7434 * much faster than a first, causing the observed TSC here to be
7435 * smaller; this would require additional padding adjustment, which is
7436 * why we set last_host_tsc to the local tsc observed here.
7438 * N.B. - this code below runs only on platforms with reliable TSC,
7439 * as that is the only way backwards_tsc is set above. Also note
7440 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7441 * have the same delta_cyc adjustment applied if backwards_tsc
7442 * is detected. Note further, this adjustment is only done once,
7443 * as we reset last_host_tsc on all VCPUs to stop this from being
7444 * called multiple times (one for each physical CPU bringup).
7446 * Platforms with unreliable TSCs don't have to deal with this, they
7447 * will be compensated by the logic in vcpu_load, which sets the TSC to
7448 * catchup mode. This will catchup all VCPUs to real time, but cannot
7449 * guarantee that they stay in perfect synchronization.
7451 if (backwards_tsc) {
7452 u64 delta_cyc = max_tsc - local_tsc;
7453 backwards_tsc_observed = true;
7454 list_for_each_entry(kvm, &vm_list, vm_list) {
7455 kvm_for_each_vcpu(i, vcpu, kvm) {
7456 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7457 vcpu->arch.last_host_tsc = local_tsc;
7458 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7462 * We have to disable TSC offset matching.. if you were
7463 * booting a VM while issuing an S4 host suspend....
7464 * you may have some problem. Solving this issue is
7465 * left as an exercise to the reader.
7467 kvm->arch.last_tsc_nsec = 0;
7468 kvm->arch.last_tsc_write = 0;
7475 void kvm_arch_hardware_disable(void)
7477 kvm_x86_ops->hardware_disable();
7478 drop_user_return_notifiers();
7481 int kvm_arch_hardware_setup(void)
7485 r = kvm_x86_ops->hardware_setup();
7489 if (kvm_has_tsc_control) {
7491 * Make sure the user can only configure tsc_khz values that
7492 * fit into a signed integer.
7493 * A min value is not calculated needed because it will always
7494 * be 1 on all machines.
7496 u64 max = min(0x7fffffffULL,
7497 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7498 kvm_max_guest_tsc_khz = max;
7500 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7503 kvm_init_msr_list();
7507 void kvm_arch_hardware_unsetup(void)
7509 kvm_x86_ops->hardware_unsetup();
7512 void kvm_arch_check_processor_compat(void *rtn)
7514 kvm_x86_ops->check_processor_compatibility(rtn);
7517 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7519 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7521 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7523 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7525 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7528 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7530 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7533 struct static_key kvm_no_apic_vcpu __read_mostly;
7535 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7541 BUG_ON(vcpu->kvm == NULL);
7544 vcpu->arch.pv.pv_unhalted = false;
7545 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7546 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7547 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7549 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7551 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7556 vcpu->arch.pio_data = page_address(page);
7558 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7560 r = kvm_mmu_create(vcpu);
7562 goto fail_free_pio_data;
7564 if (irqchip_in_kernel(kvm)) {
7565 r = kvm_create_lapic(vcpu);
7567 goto fail_mmu_destroy;
7569 static_key_slow_inc(&kvm_no_apic_vcpu);
7571 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7573 if (!vcpu->arch.mce_banks) {
7575 goto fail_free_lapic;
7577 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7579 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7581 goto fail_free_mce_banks;
7586 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7587 vcpu->arch.pv_time_enabled = false;
7589 vcpu->arch.guest_supported_xcr0 = 0;
7590 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7592 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7594 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7596 kvm_async_pf_hash_reset(vcpu);
7599 vcpu->arch.pending_external_vector = -1;
7603 fail_free_mce_banks:
7604 kfree(vcpu->arch.mce_banks);
7606 kvm_free_lapic(vcpu);
7608 kvm_mmu_destroy(vcpu);
7610 free_page((unsigned long)vcpu->arch.pio_data);
7615 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7619 kvm_pmu_destroy(vcpu);
7620 kfree(vcpu->arch.mce_banks);
7621 kvm_free_lapic(vcpu);
7622 idx = srcu_read_lock(&vcpu->kvm->srcu);
7623 kvm_mmu_destroy(vcpu);
7624 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7625 free_page((unsigned long)vcpu->arch.pio_data);
7626 if (!lapic_in_kernel(vcpu))
7627 static_key_slow_dec(&kvm_no_apic_vcpu);
7630 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7632 kvm_x86_ops->sched_in(vcpu, cpu);
7635 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7640 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7641 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7642 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7643 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7644 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7646 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7647 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7648 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7649 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7650 &kvm->arch.irq_sources_bitmap);
7652 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7653 mutex_init(&kvm->arch.apic_map_lock);
7654 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7656 pvclock_update_vm_gtod_copy(kvm);
7658 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7659 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7664 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7667 r = vcpu_load(vcpu);
7669 kvm_mmu_unload(vcpu);
7673 static void kvm_free_vcpus(struct kvm *kvm)
7676 struct kvm_vcpu *vcpu;
7679 * Unpin any mmu pages first.
7681 kvm_for_each_vcpu(i, vcpu, kvm) {
7682 kvm_clear_async_pf_completion_queue(vcpu);
7683 kvm_unload_vcpu_mmu(vcpu);
7685 kvm_for_each_vcpu(i, vcpu, kvm)
7686 kvm_arch_vcpu_free(vcpu);
7688 mutex_lock(&kvm->lock);
7689 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7690 kvm->vcpus[i] = NULL;
7692 atomic_set(&kvm->online_vcpus, 0);
7693 mutex_unlock(&kvm->lock);
7696 void kvm_arch_sync_events(struct kvm *kvm)
7698 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7699 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7700 kvm_free_all_assigned_devices(kvm);
7704 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7708 struct kvm_memslots *slots = kvm_memslots(kvm);
7709 struct kvm_memory_slot *slot, old;
7711 /* Called with kvm->slots_lock held. */
7712 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7715 slot = id_to_memslot(slots, id);
7717 if (WARN_ON(slot->npages))
7721 * MAP_SHARED to prevent internal slot pages from being moved
7724 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7725 MAP_SHARED | MAP_ANONYMOUS, 0);
7726 if (IS_ERR((void *)hva))
7727 return PTR_ERR((void *)hva);
7736 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7737 struct kvm_userspace_memory_region m;
7739 m.slot = id | (i << 16);
7741 m.guest_phys_addr = gpa;
7742 m.userspace_addr = hva;
7743 m.memory_size = size;
7744 r = __kvm_set_memory_region(kvm, &m);
7750 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7756 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7758 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7762 mutex_lock(&kvm->slots_lock);
7763 r = __x86_set_memory_region(kvm, id, gpa, size);
7764 mutex_unlock(&kvm->slots_lock);
7768 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7770 void kvm_arch_destroy_vm(struct kvm *kvm)
7772 if (current->mm == kvm->mm) {
7774 * Free memory regions allocated on behalf of userspace,
7775 * unless the the memory map has changed due to process exit
7778 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7779 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7780 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7782 kvm_iommu_unmap_guest(kvm);
7783 kfree(kvm->arch.vpic);
7784 kfree(kvm->arch.vioapic);
7785 kvm_free_vcpus(kvm);
7786 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7789 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7790 struct kvm_memory_slot *dont)
7794 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7795 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7796 kvfree(free->arch.rmap[i]);
7797 free->arch.rmap[i] = NULL;
7802 if (!dont || free->arch.lpage_info[i - 1] !=
7803 dont->arch.lpage_info[i - 1]) {
7804 kvfree(free->arch.lpage_info[i - 1]);
7805 free->arch.lpage_info[i - 1] = NULL;
7810 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7811 unsigned long npages)
7815 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7820 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7821 slot->base_gfn, level) + 1;
7823 slot->arch.rmap[i] =
7824 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7825 if (!slot->arch.rmap[i])
7830 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7831 sizeof(*slot->arch.lpage_info[i - 1]));
7832 if (!slot->arch.lpage_info[i - 1])
7835 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7836 slot->arch.lpage_info[i - 1][0].write_count = 1;
7837 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7838 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7839 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7841 * If the gfn and userspace address are not aligned wrt each
7842 * other, or if explicitly asked to, disable large page
7843 * support for this slot
7845 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7846 !kvm_largepages_enabled()) {
7849 for (j = 0; j < lpages; ++j)
7850 slot->arch.lpage_info[i - 1][j].write_count = 1;
7857 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7858 kvfree(slot->arch.rmap[i]);
7859 slot->arch.rmap[i] = NULL;
7863 kvfree(slot->arch.lpage_info[i - 1]);
7864 slot->arch.lpage_info[i - 1] = NULL;
7869 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7872 * memslots->generation has been incremented.
7873 * mmio generation may have reached its maximum value.
7875 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7878 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7879 struct kvm_memory_slot *memslot,
7880 const struct kvm_userspace_memory_region *mem,
7881 enum kvm_mr_change change)
7886 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7887 struct kvm_memory_slot *new)
7889 /* Still write protect RO slot */
7890 if (new->flags & KVM_MEM_READONLY) {
7891 kvm_mmu_slot_remove_write_access(kvm, new);
7896 * Call kvm_x86_ops dirty logging hooks when they are valid.
7898 * kvm_x86_ops->slot_disable_log_dirty is called when:
7900 * - KVM_MR_CREATE with dirty logging is disabled
7901 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7903 * The reason is, in case of PML, we need to set D-bit for any slots
7904 * with dirty logging disabled in order to eliminate unnecessary GPA
7905 * logging in PML buffer (and potential PML buffer full VMEXT). This
7906 * guarantees leaving PML enabled during guest's lifetime won't have
7907 * any additonal overhead from PML when guest is running with dirty
7908 * logging disabled for memory slots.
7910 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7911 * to dirty logging mode.
7913 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7915 * In case of write protect:
7917 * Write protect all pages for dirty logging.
7919 * All the sptes including the large sptes which point to this
7920 * slot are set to readonly. We can not create any new large
7921 * spte on this slot until the end of the logging.
7923 * See the comments in fast_page_fault().
7925 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7926 if (kvm_x86_ops->slot_enable_log_dirty)
7927 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7929 kvm_mmu_slot_remove_write_access(kvm, new);
7931 if (kvm_x86_ops->slot_disable_log_dirty)
7932 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7936 void kvm_arch_commit_memory_region(struct kvm *kvm,
7937 const struct kvm_userspace_memory_region *mem,
7938 const struct kvm_memory_slot *old,
7939 const struct kvm_memory_slot *new,
7940 enum kvm_mr_change change)
7942 int nr_mmu_pages = 0;
7944 if (!kvm->arch.n_requested_mmu_pages)
7945 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7948 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7951 * Dirty logging tracks sptes in 4k granularity, meaning that large
7952 * sptes have to be split. If live migration is successful, the guest
7953 * in the source machine will be destroyed and large sptes will be
7954 * created in the destination. However, if the guest continues to run
7955 * in the source machine (for example if live migration fails), small
7956 * sptes will remain around and cause bad performance.
7958 * Scan sptes if dirty logging has been stopped, dropping those
7959 * which can be collapsed into a single large-page spte. Later
7960 * page faults will create the large-page sptes.
7962 if ((change != KVM_MR_DELETE) &&
7963 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7964 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7965 kvm_mmu_zap_collapsible_sptes(kvm, new);
7968 * Set up write protection and/or dirty logging for the new slot.
7970 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7971 * been zapped so no dirty logging staff is needed for old slot. For
7972 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7973 * new and it's also covered when dealing with the new slot.
7975 * FIXME: const-ify all uses of struct kvm_memory_slot.
7977 if (change != KVM_MR_DELETE)
7978 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7981 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7983 kvm_mmu_invalidate_zap_all_pages(kvm);
7986 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7987 struct kvm_memory_slot *slot)
7989 kvm_mmu_invalidate_zap_all_pages(kvm);
7992 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7994 if (!list_empty_careful(&vcpu->async_pf.done))
7997 if (kvm_apic_has_events(vcpu))
8000 if (vcpu->arch.pv.pv_unhalted)
8003 if (atomic_read(&vcpu->arch.nmi_queued))
8006 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8009 if (kvm_arch_interrupt_allowed(vcpu) &&
8010 kvm_cpu_has_interrupt(vcpu))
8016 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8018 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8019 kvm_x86_ops->check_nested_events(vcpu, false);
8021 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8024 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8026 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8029 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8031 return kvm_x86_ops->interrupt_allowed(vcpu);
8034 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8036 if (is_64_bit_mode(vcpu))
8037 return kvm_rip_read(vcpu);
8038 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8039 kvm_rip_read(vcpu));
8041 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8043 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8045 return kvm_get_linear_rip(vcpu) == linear_rip;
8047 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8049 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8051 unsigned long rflags;
8053 rflags = kvm_x86_ops->get_rflags(vcpu);
8054 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8055 rflags &= ~X86_EFLAGS_TF;
8058 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8060 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8062 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8063 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8064 rflags |= X86_EFLAGS_TF;
8065 kvm_x86_ops->set_rflags(vcpu, rflags);
8068 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8070 __kvm_set_rflags(vcpu, rflags);
8071 kvm_make_request(KVM_REQ_EVENT, vcpu);
8073 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8075 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8079 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8083 r = kvm_mmu_reload(vcpu);
8087 if (!vcpu->arch.mmu.direct_map &&
8088 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8091 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8094 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8096 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8099 static inline u32 kvm_async_pf_next_probe(u32 key)
8101 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8104 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8106 u32 key = kvm_async_pf_hash_fn(gfn);
8108 while (vcpu->arch.apf.gfns[key] != ~0)
8109 key = kvm_async_pf_next_probe(key);
8111 vcpu->arch.apf.gfns[key] = gfn;
8114 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8117 u32 key = kvm_async_pf_hash_fn(gfn);
8119 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8120 (vcpu->arch.apf.gfns[key] != gfn &&
8121 vcpu->arch.apf.gfns[key] != ~0); i++)
8122 key = kvm_async_pf_next_probe(key);
8127 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8129 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8132 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8136 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8138 vcpu->arch.apf.gfns[i] = ~0;
8140 j = kvm_async_pf_next_probe(j);
8141 if (vcpu->arch.apf.gfns[j] == ~0)
8143 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8145 * k lies cyclically in ]i,j]
8147 * |....j i.k.| or |.k..j i...|
8149 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8150 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8155 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8158 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8162 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8163 struct kvm_async_pf *work)
8165 struct x86_exception fault;
8167 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8168 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8170 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8171 (vcpu->arch.apf.send_user_only &&
8172 kvm_x86_ops->get_cpl(vcpu) == 0))
8173 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8174 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8175 fault.vector = PF_VECTOR;
8176 fault.error_code_valid = true;
8177 fault.error_code = 0;
8178 fault.nested_page_fault = false;
8179 fault.address = work->arch.token;
8180 kvm_inject_page_fault(vcpu, &fault);
8184 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8185 struct kvm_async_pf *work)
8187 struct x86_exception fault;
8189 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8190 if (work->wakeup_all)
8191 work->arch.token = ~0; /* broadcast wakeup */
8193 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8195 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8196 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8197 fault.vector = PF_VECTOR;
8198 fault.error_code_valid = true;
8199 fault.error_code = 0;
8200 fault.nested_page_fault = false;
8201 fault.address = work->arch.token;
8202 kvm_inject_page_fault(vcpu, &fault);
8204 vcpu->arch.apf.halted = false;
8205 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8208 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8210 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8213 return !kvm_event_needs_reinjection(vcpu) &&
8214 kvm_x86_ops->interrupt_allowed(vcpu);
8217 void kvm_arch_start_assignment(struct kvm *kvm)
8219 atomic_inc(&kvm->arch.assigned_device_count);
8221 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8223 void kvm_arch_end_assignment(struct kvm *kvm)
8225 atomic_dec(&kvm->arch.assigned_device_count);
8227 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8229 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8231 return atomic_read(&kvm->arch.assigned_device_count);
8233 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8235 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8237 atomic_inc(&kvm->arch.noncoherent_dma_count);
8239 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8241 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8243 atomic_dec(&kvm->arch.noncoherent_dma_count);
8245 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8247 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8249 return atomic_read(&kvm->arch.noncoherent_dma_count);
8251 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8253 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8254 struct irq_bypass_producer *prod)
8256 struct kvm_kernel_irqfd *irqfd =
8257 container_of(cons, struct kvm_kernel_irqfd, consumer);
8259 if (kvm_x86_ops->update_pi_irte) {
8260 irqfd->producer = prod;
8261 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8262 prod->irq, irqfd->gsi, 1);
8268 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8269 struct irq_bypass_producer *prod)
8272 struct kvm_kernel_irqfd *irqfd =
8273 container_of(cons, struct kvm_kernel_irqfd, consumer);
8275 if (!kvm_x86_ops->update_pi_irte) {
8276 WARN_ON(irqfd->producer != NULL);
8280 WARN_ON(irqfd->producer != prod);
8281 irqfd->producer = NULL;
8284 * When producer of consumer is unregistered, we change back to
8285 * remapped mode, so we can re-use the current implementation
8286 * when the irq is masked/disabed or the consumer side (KVM
8287 * int this case doesn't want to receive the interrupts.
8289 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8291 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8292 " fails: %d\n", irqfd->consumer.token, ret);
8295 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8296 uint32_t guest_irq, bool set)
8298 if (!kvm_x86_ops->update_pi_irte)
8301 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8310 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8311 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8312 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8313 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8314 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8315 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8316 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8317 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8318 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8319 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8320 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);