kernel/arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53 #define __ex_clear(x, reg) \
  54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id vmx_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  64
  65 static bool __read_mostly enable_vpid = 1;
  66 module_param_named(vpid, enable_vpid, bool, 0444);
  67
  68 static bool __read_mostly flexpriority_enabled = 1;
  69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_ept = 1;
  72 module_param_named(ept, enable_ept, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_unrestricted_guest = 1;
  75 module_param_named(unrestricted_guest,
  76                         enable_unrestricted_guest, bool, S_IRUGO);
  77
  78 static bool __read_mostly enable_ept_ad_bits = 1;
  79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  80
  81 static bool __read_mostly emulate_invalid_guest_state = true;
  82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  83
  84 static bool __read_mostly vmm_exclusive = 1;
  85 module_param(vmm_exclusive, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 110 #define KVM_VM_CR0_ALWAYS_ON                                            \
 111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 115
 116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 118
 119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 120
 121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 122
 123 /*
 124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 125  * ple_gap:    upper bound on the amount of time between two successive
 126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 127  *             According to test, this time is usually smaller than 128 cycles.
 128  * ple_window: upper bound on the amount of time a guest is allowed to execute
 129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 130  *             less than 2^12 cycles
 131  * Time is measured based on a counter that runs at the same rate as the TSC,
 132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 133  */
 134 #define KVM_VMX_DEFAULT_PLE_GAP           128
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 140
 141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 142 module_param(ple_gap, int, S_IRUGO);
 143
 144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 145 module_param(ple_window, int, S_IRUGO);
 146
 147 /* Default doubles per-vcpu window every exit. */
 148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 149 module_param(ple_window_grow, int, S_IRUGO);
 150
 151 /* Default resets per-vcpu window every exit to ple_window. */
 152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 153 module_param(ple_window_shrink, int, S_IRUGO);
 154
 155 /* Default is to compute the maximum so we can never overflow. */
 156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 158 module_param(ple_window_max, int, S_IRUGO);
 159
 160 extern const ulong vmx_return;
 161
 162 #define NR_AUTOLOAD_MSRS 8
 163 #define VMCS02_POOL_SIZE 1
 164
 165 struct vmcs {
 166         u32 revision_id;
 167         u32 abort;
 168         char data[0];
 169 };
 170
 171 /*
 172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 174  * loaded on this CPU (so we can clear them if the CPU goes down).
 175  */
 176 struct loaded_vmcs {
 177         struct vmcs *vmcs;
 178         int cpu;
 179         int launched;
 180         struct list_head loaded_vmcss_on_cpu_link;
 181 };
 182
 183 struct shared_msr_entry {
 184         unsigned index;
 185         u64 data;
 186         u64 mask;
 187 };
 188
 189 /*
 190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 197  * underlying hardware which will be used to run L2.
 198  * This structure is packed to ensure that its layout is identical across
 199  * machines (necessary for live migration).
 200  * If there are changes in this struct, VMCS12_REVISION must be changed.
 201  */
 202 typedef u64 natural_width;
 203 struct __packed vmcs12 {
 204         /* According to the Intel spec, a VMCS region must start with the
 205          * following two fields. Then follow implementation-specific data.
 206          */
 207         u32 revision_id;
 208         u32 abort;
 209
 210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 211         u32 padding[7]; /* room for future expansion */
 212
 213         u64 io_bitmap_a;
 214         u64 io_bitmap_b;
 215         u64 msr_bitmap;
 216         u64 vm_exit_msr_store_addr;
 217         u64 vm_exit_msr_load_addr;
 218         u64 vm_entry_msr_load_addr;
 219         u64 tsc_offset;
 220         u64 virtual_apic_page_addr;
 221         u64 apic_access_addr;
 222         u64 posted_intr_desc_addr;
 223         u64 ept_pointer;
 224         u64 eoi_exit_bitmap0;
 225         u64 eoi_exit_bitmap1;
 226         u64 eoi_exit_bitmap2;
 227         u64 eoi_exit_bitmap3;
 228         u64 xss_exit_bitmap;
 229         u64 guest_physical_address;
 230         u64 vmcs_link_pointer;
 231         u64 guest_ia32_debugctl;
 232         u64 guest_ia32_pat;
 233         u64 guest_ia32_efer;
 234         u64 guest_ia32_perf_global_ctrl;
 235         u64 guest_pdptr0;
 236         u64 guest_pdptr1;
 237         u64 guest_pdptr2;
 238         u64 guest_pdptr3;
 239         u64 guest_bndcfgs;
 240         u64 host_ia32_pat;
 241         u64 host_ia32_efer;
 242         u64 host_ia32_perf_global_ctrl;
 243         u64 padding64[8]; /* room for future expansion */
 244         /*
 245          * To allow migration of L1 (complete with its L2 guests) between
 246          * machines of different natural widths (32 or 64 bit), we cannot have
 247          * unsigned long fields with no explict size. We use u64 (aliased
 248          * natural_width) instead. Luckily, x86 is little-endian.
 249          */
 250         natural_width cr0_guest_host_mask;
 251         natural_width cr4_guest_host_mask;
 252         natural_width cr0_read_shadow;
 253         natural_width cr4_read_shadow;
 254         natural_width cr3_target_value0;
 255         natural_width cr3_target_value1;
 256         natural_width cr3_target_value2;
 257         natural_width cr3_target_value3;
 258         natural_width exit_qualification;
 259         natural_width guest_linear_address;
 260         natural_width guest_cr0;
 261         natural_width guest_cr3;
 262         natural_width guest_cr4;
 263         natural_width guest_es_base;
 264         natural_width guest_cs_base;
 265         natural_width guest_ss_base;
 266         natural_width guest_ds_base;
 267         natural_width guest_fs_base;
 268         natural_width guest_gs_base;
 269         natural_width guest_ldtr_base;
 270         natural_width guest_tr_base;
 271         natural_width guest_gdtr_base;
 272         natural_width guest_idtr_base;
 273         natural_width guest_dr7;
 274         natural_width guest_rsp;
 275         natural_width guest_rip;
 276         natural_width guest_rflags;
 277         natural_width guest_pending_dbg_exceptions;
 278         natural_width guest_sysenter_esp;
 279         natural_width guest_sysenter_eip;
 280         natural_width host_cr0;
 281         natural_width host_cr3;
 282         natural_width host_cr4;
 283         natural_width host_fs_base;
 284         natural_width host_gs_base;
 285         natural_width host_tr_base;
 286         natural_width host_gdtr_base;
 287         natural_width host_idtr_base;
 288         natural_width host_ia32_sysenter_esp;
 289         natural_width host_ia32_sysenter_eip;
 290         natural_width host_rsp;
 291         natural_width host_rip;
 292         natural_width paddingl[8]; /* room for future expansion */
 293         u32 pin_based_vm_exec_control;
 294         u32 cpu_based_vm_exec_control;
 295         u32 exception_bitmap;
 296         u32 page_fault_error_code_mask;
 297         u32 page_fault_error_code_match;
 298         u32 cr3_target_count;
 299         u32 vm_exit_controls;
 300         u32 vm_exit_msr_store_count;
 301         u32 vm_exit_msr_load_count;
 302         u32 vm_entry_controls;
 303         u32 vm_entry_msr_load_count;
 304         u32 vm_entry_intr_info_field;
 305         u32 vm_entry_exception_error_code;
 306         u32 vm_entry_instruction_len;
 307         u32 tpr_threshold;
 308         u32 secondary_vm_exec_control;
 309         u32 vm_instruction_error;
 310         u32 vm_exit_reason;
 311         u32 vm_exit_intr_info;
 312         u32 vm_exit_intr_error_code;
 313         u32 idt_vectoring_info_field;
 314         u32 idt_vectoring_error_code;
 315         u32 vm_exit_instruction_len;
 316         u32 vmx_instruction_info;
 317         u32 guest_es_limit;
 318         u32 guest_cs_limit;
 319         u32 guest_ss_limit;
 320         u32 guest_ds_limit;
 321         u32 guest_fs_limit;
 322         u32 guest_gs_limit;
 323         u32 guest_ldtr_limit;
 324         u32 guest_tr_limit;
 325         u32 guest_gdtr_limit;
 326         u32 guest_idtr_limit;
 327         u32 guest_es_ar_bytes;
 328         u32 guest_cs_ar_bytes;
 329         u32 guest_ss_ar_bytes;
 330         u32 guest_ds_ar_bytes;
 331         u32 guest_fs_ar_bytes;
 332         u32 guest_gs_ar_bytes;
 333         u32 guest_ldtr_ar_bytes;
 334         u32 guest_tr_ar_bytes;
 335         u32 guest_interruptibility_info;
 336         u32 guest_activity_state;
 337         u32 guest_sysenter_cs;
 338         u32 host_ia32_sysenter_cs;
 339         u32 vmx_preemption_timer_value;
 340         u32 padding32[7]; /* room for future expansion */
 341         u16 virtual_processor_id;
 342         u16 posted_intr_nv;
 343         u16 guest_es_selector;
 344         u16 guest_cs_selector;
 345         u16 guest_ss_selector;
 346         u16 guest_ds_selector;
 347         u16 guest_fs_selector;
 348         u16 guest_gs_selector;
 349         u16 guest_ldtr_selector;
 350         u16 guest_tr_selector;
 351         u16 guest_intr_status;
 352         u16 host_es_selector;
 353         u16 host_cs_selector;
 354         u16 host_ss_selector;
 355         u16 host_ds_selector;
 356         u16 host_fs_selector;
 357         u16 host_gs_selector;
 358         u16 host_tr_selector;
 359 };
 360
 361 /*
 362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 365  */
 366 #define VMCS12_REVISION 0x11e57ed0
 367
 368 /*
 369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 371  * current implementation, 4K are reserved to avoid future complications.
 372  */
 373 #define VMCS12_SIZE 0x1000
 374
 375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 376 struct vmcs02_list {
 377         struct list_head list;
 378         gpa_t vmptr;
 379         struct loaded_vmcs vmcs02;
 380 };
 381
 382 /*
 383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 385  */
 386 struct nested_vmx {
 387         /* Has the level1 guest done vmxon? */
 388         bool vmxon;
 389         gpa_t vmxon_ptr;
 390
 391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 392         gpa_t current_vmptr;
 393         /* The host-usable pointer to the above */
 394         struct page *current_vmcs12_page;
 395         struct vmcs12 *current_vmcs12;
 396         struct vmcs *current_shadow_vmcs;
 397         /*
 398          * Indicates if the shadow vmcs must be updated with the
 399          * data hold by vmcs12
 400          */
 401         bool sync_shadow_vmcs;
 402
 403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 404         struct list_head vmcs02_pool;
 405         int vmcs02_num;
 406         u64 vmcs01_tsc_offset;
 407         /* L2 must run next, and mustn't decide to exit to L1. */
 408         bool nested_run_pending;
 409         /*
 410          * Guest pages referred to in vmcs02 with host-physical pointers, so
 411          * we must keep them pinned while L2 runs.
 412          */
 413         struct page *apic_access_page;
 414         struct page *virtual_apic_page;
 415         struct page *pi_desc_page;
 416         struct pi_desc *pi_desc;
 417         bool pi_pending;
 418         u16 posted_intr_nv;
 419         u64 msr_ia32_feature_control;
 420
 421         struct hrtimer preemption_timer;
 422         bool preemption_timer_expired;
 423
 424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 425         u64 vmcs01_debugctl;
 426
 427         u32 nested_vmx_procbased_ctls_low;
 428         u32 nested_vmx_procbased_ctls_high;
 429         u32 nested_vmx_true_procbased_ctls_low;
 430         u32 nested_vmx_secondary_ctls_low;
 431         u32 nested_vmx_secondary_ctls_high;
 432         u32 nested_vmx_pinbased_ctls_low;
 433         u32 nested_vmx_pinbased_ctls_high;
 434         u32 nested_vmx_exit_ctls_low;
 435         u32 nested_vmx_exit_ctls_high;
 436         u32 nested_vmx_true_exit_ctls_low;
 437         u32 nested_vmx_entry_ctls_low;
 438         u32 nested_vmx_entry_ctls_high;
 439         u32 nested_vmx_true_entry_ctls_low;
 440         u32 nested_vmx_misc_low;
 441         u32 nested_vmx_misc_high;
 442         u32 nested_vmx_ept_caps;
 443 };
 444
 445 #define POSTED_INTR_ON  0
 446 /* Posted-Interrupt Descriptor */
 447 struct pi_desc {
 448         u32 pir[8];     /* Posted interrupt requested */
 449         u32 control;    /* bit 0 of control is outstanding notification bit */
 450         u32 rsvd[7];
 451 } __aligned(64);
 452
 453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 454 {
 455         return test_and_set_bit(POSTED_INTR_ON,
 456                         (unsigned long *)&pi_desc->control);
 457 }
 458
 459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 460 {
 461         return test_and_clear_bit(POSTED_INTR_ON,
 462                         (unsigned long *)&pi_desc->control);
 463 }
 464
 465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 466 {
 467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 468 }
 469
 470 struct vcpu_vmx {
 471         struct kvm_vcpu       vcpu;
 472         unsigned long         host_rsp;
 473         u8                    fail;
 474         bool                  nmi_known_unmasked;
 475         u32                   exit_intr_info;
 476         u32                   idt_vectoring_info;
 477         ulong                 rflags;
 478         struct shared_msr_entry *guest_msrs;
 479         int                   nmsrs;
 480         int                   save_nmsrs;
 481         unsigned long         host_idt_base;
 482 #ifdef CONFIG_X86_64
 483         u64                   msr_host_kernel_gs_base;
 484         u64                   msr_guest_kernel_gs_base;
 485 #endif
 486         u32 vm_entry_controls_shadow;
 487         u32 vm_exit_controls_shadow;
 488         /*
 489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 490          * non-nested (L1) guest, it always points to vmcs01. For a nested
 491          * guest (L2), it points to a different VMCS.
 492          */
 493         struct loaded_vmcs    vmcs01;
 494         struct loaded_vmcs   *loaded_vmcs;
 495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 496         struct msr_autoload {
 497                 unsigned nr;
 498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 500         } msr_autoload;
 501         struct {
 502                 int           loaded;
 503                 u16           fs_sel, gs_sel, ldt_sel;
 504 #ifdef CONFIG_X86_64
 505                 u16           ds_sel, es_sel;
 506 #endif
 507                 int           gs_ldt_reload_needed;
 508                 int           fs_reload_needed;
 509                 u64           msr_host_bndcfgs;
 510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 511         } host_state;
 512         struct {
 513                 int vm86_active;
 514                 ulong save_rflags;
 515                 struct kvm_segment segs[8];
 516         } rmode;
 517         struct {
 518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 519                 struct kvm_save_segment {
 520                         u16 selector;
 521                         unsigned long base;
 522                         u32 limit;
 523                         u32 ar;
 524                 } seg[8];
 525         } segment_cache;
 526         int vpid;
 527         bool emulation_required;
 528
 529         /* Support for vnmi-less CPUs */
 530         int soft_vnmi_blocked;
 531         ktime_t entry_time;
 532         s64 vnmi_blocked_time;
 533         u32 exit_reason;
 534
 535         bool rdtscp_enabled;
 536
 537         /* Posted interrupt descriptor */
 538         struct pi_desc pi_desc;
 539
 540         /* Support for a guest hypervisor (nested VMX) */
 541         struct nested_vmx nested;
 542
 543         /* Dynamic PLE window. */
 544         int ple_window;
 545         bool ple_window_dirty;
 546
 547         /* Support for PML */
 548 #define PML_ENTITY_NUM          512
 549         struct page *pml_pg;
 550 };
 551
 552 enum segment_cache_field {
 553         SEG_FIELD_SEL = 0,
 554         SEG_FIELD_BASE = 1,
 555         SEG_FIELD_LIMIT = 2,
 556         SEG_FIELD_AR = 3,
 557
 558         SEG_FIELD_NR = 4
 559 };
 560
 561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 562 {
 563         return container_of(vcpu, struct vcpu_vmx, vcpu);
 564 }
 565
 566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 570
 571
 572 static unsigned long shadow_read_only_fields[] = {
 573         /*
 574          * We do NOT shadow fields that are modified when L0
 575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 576          * VMXON...) executed by L1.
 577          * For example, VM_INSTRUCTION_ERROR is read
 578          * by L1 if a vmx instruction fails (part of the error path).
 579          * Note the code assumes this logic. If for some reason
 580          * we start shadowing these fields then we need to
 581          * force a shadow sync when L0 emulates vmx instructions
 582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 583          * by nested_vmx_failValid)
 584          */
 585         VM_EXIT_REASON,
 586         VM_EXIT_INTR_INFO,
 587         VM_EXIT_INSTRUCTION_LEN,
 588         IDT_VECTORING_INFO_FIELD,
 589         IDT_VECTORING_ERROR_CODE,
 590         VM_EXIT_INTR_ERROR_CODE,
 591         EXIT_QUALIFICATION,
 592         GUEST_LINEAR_ADDRESS,
 593         GUEST_PHYSICAL_ADDRESS
 594 };
 595 static int max_shadow_read_only_fields =
 596         ARRAY_SIZE(shadow_read_only_fields);
 597
 598 static unsigned long shadow_read_write_fields[] = {
 599         TPR_THRESHOLD,
 600         GUEST_RIP,
 601         GUEST_RSP,
 602         GUEST_CR0,
 603         GUEST_CR3,
 604         GUEST_CR4,
 605         GUEST_INTERRUPTIBILITY_INFO,
 606         GUEST_RFLAGS,
 607         GUEST_CS_SELECTOR,
 608         GUEST_CS_AR_BYTES,
 609         GUEST_CS_LIMIT,
 610         GUEST_CS_BASE,
 611         GUEST_ES_BASE,
 612         GUEST_BNDCFGS,
 613         CR0_GUEST_HOST_MASK,
 614         CR0_READ_SHADOW,
 615         CR4_READ_SHADOW,
 616         TSC_OFFSET,
 617         EXCEPTION_BITMAP,
 618         CPU_BASED_VM_EXEC_CONTROL,
 619         VM_ENTRY_EXCEPTION_ERROR_CODE,
 620         VM_ENTRY_INTR_INFO_FIELD,
 621         VM_ENTRY_INSTRUCTION_LEN,
 622         VM_ENTRY_EXCEPTION_ERROR_CODE,
 623         HOST_FS_BASE,
 624         HOST_GS_BASE,
 625         HOST_FS_SELECTOR,
 626         HOST_GS_SELECTOR
 627 };
 628 static int max_shadow_read_write_fields =
 629         ARRAY_SIZE(shadow_read_write_fields);
 630
 631 static const unsigned short vmcs_field_to_offset_table[] = {
 632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 633         FIELD(POSTED_INTR_NV, posted_intr_nv),
 634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 643         FIELD(HOST_ES_SELECTOR, host_es_selector),
 644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 650         FIELD64(IO_BITMAP_A, io_bitmap_a),
 651         FIELD64(IO_BITMAP_B, io_bitmap_b),
 652         FIELD64(MSR_BITMAP, msr_bitmap),
 653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 656         FIELD64(TSC_OFFSET, tsc_offset),
 657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 660         FIELD64(EPT_POINTER, ept_pointer),
 661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 694         FIELD(TPR_THRESHOLD, tpr_threshold),
 695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 697         FIELD(VM_EXIT_REASON, vm_exit_reason),
 698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 735         FIELD(EXIT_QUALIFICATION, exit_qualification),
 736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 737         FIELD(GUEST_CR0, guest_cr0),
 738         FIELD(GUEST_CR3, guest_cr3),
 739         FIELD(GUEST_CR4, guest_cr4),
 740         FIELD(GUEST_ES_BASE, guest_es_base),
 741         FIELD(GUEST_CS_BASE, guest_cs_base),
 742         FIELD(GUEST_SS_BASE, guest_ss_base),
 743         FIELD(GUEST_DS_BASE, guest_ds_base),
 744         FIELD(GUEST_FS_BASE, guest_fs_base),
 745         FIELD(GUEST_GS_BASE, guest_gs_base),
 746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 747         FIELD(GUEST_TR_BASE, guest_tr_base),
 748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 750         FIELD(GUEST_DR7, guest_dr7),
 751         FIELD(GUEST_RSP, guest_rsp),
 752         FIELD(GUEST_RIP, guest_rip),
 753         FIELD(GUEST_RFLAGS, guest_rflags),
 754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 757         FIELD(HOST_CR0, host_cr0),
 758         FIELD(HOST_CR3, host_cr3),
 759         FIELD(HOST_CR4, host_cr4),
 760         FIELD(HOST_FS_BASE, host_fs_base),
 761         FIELD(HOST_GS_BASE, host_gs_base),
 762         FIELD(HOST_TR_BASE, host_tr_base),
 763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 764         FIELD(HOST_IDTR_BASE, host_idtr_base),
 765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 767         FIELD(HOST_RSP, host_rsp),
 768         FIELD(HOST_RIP, host_rip),
 769 };
 770
 771 static inline short vmcs_field_to_offset(unsigned long field)
 772 {
 773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 774
 775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 776             vmcs_field_to_offset_table[field] == 0)
 777                 return -ENOENT;
 778
 779         return vmcs_field_to_offset_table[field];
 780 }
 781
 782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 783 {
 784         return to_vmx(vcpu)->nested.current_vmcs12;
 785 }
 786
 787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 788 {
 789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 790         if (is_error_page(page))
 791                 return NULL;
 792
 793         return page;
 794 }
 795
 796 static void nested_release_page(struct page *page)
 797 {
 798         kvm_release_page_dirty(page);
 799 }
 800
 801 static void nested_release_page_clean(struct page *page)
 802 {
 803         kvm_release_page_clean(page);
 804 }
 805
 806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 807 static u64 construct_eptp(unsigned long root_hpa);
 808 static void kvm_cpu_vmxon(u64 addr);
 809 static void kvm_cpu_vmxoff(void);
 810 static bool vmx_mpx_supported(void);
 811 static bool vmx_xsaves_supported(void);
 812 static int vmx_vm_has_apicv(struct kvm *kvm);
 813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 815                             struct kvm_segment *var, int seg);
 816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 817                             struct kvm_segment *var, int seg);
 818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 823 static int alloc_identity_pagetable(struct kvm *kvm);
 824
 825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 827 /*
 828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 830  */
 831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 833
 834 static unsigned long *vmx_io_bitmap_a;
 835 static unsigned long *vmx_io_bitmap_b;
 836 static unsigned long *vmx_msr_bitmap_legacy;
 837 static unsigned long *vmx_msr_bitmap_longmode;
 838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 840 static unsigned long *vmx_msr_bitmap_nested;
 841 static unsigned long *vmx_vmread_bitmap;
 842 static unsigned long *vmx_vmwrite_bitmap;
 843
 844 static bool cpu_has_load_ia32_efer;
 845 static bool cpu_has_load_perf_global_ctrl;
 846
 847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 848 static DEFINE_SPINLOCK(vmx_vpid_lock);
 849
 850 static struct vmcs_config {
 851         int size;
 852         int order;
 853         u32 revision_id;
 854         u32 pin_based_exec_ctrl;
 855         u32 cpu_based_exec_ctrl;
 856         u32 cpu_based_2nd_exec_ctrl;
 857         u32 vmexit_ctrl;
 858         u32 vmentry_ctrl;
 859 } vmcs_config;
 860
 861 static struct vmx_capability {
 862         u32 ept;
 863         u32 vpid;
 864 } vmx_capability;
 865
 866 #define VMX_SEGMENT_FIELD(seg)                                  \
 867         [VCPU_SREG_##seg] = {                                   \
 868                 .selector = GUEST_##seg##_SELECTOR,             \
 869                 .base = GUEST_##seg##_BASE,                     \
 870                 .limit = GUEST_##seg##_LIMIT,                   \
 871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 872         }
 873
 874 static const struct kvm_vmx_segment_field {
 875         unsigned selector;
 876         unsigned base;
 877         unsigned limit;
 878         unsigned ar_bytes;
 879 } kvm_vmx_segment_fields[] = {
 880         VMX_SEGMENT_FIELD(CS),
 881         VMX_SEGMENT_FIELD(DS),
 882         VMX_SEGMENT_FIELD(ES),
 883         VMX_SEGMENT_FIELD(FS),
 884         VMX_SEGMENT_FIELD(GS),
 885         VMX_SEGMENT_FIELD(SS),
 886         VMX_SEGMENT_FIELD(TR),
 887         VMX_SEGMENT_FIELD(LDTR),
 888 };
 889
 890 static u64 host_efer;
 891
 892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 893
 894 /*
 895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 896  * away by decrementing the array size.
 897  */
 898 static const u32 vmx_msr_index[] = {
 899 #ifdef CONFIG_X86_64
 900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 901 #endif
 902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 903 };
 904
 905 static inline bool is_page_fault(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 908                              INTR_INFO_VALID_MASK)) ==
 909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 910 }
 911
 912 static inline bool is_no_device(u32 intr_info)
 913 {
 914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 915                              INTR_INFO_VALID_MASK)) ==
 916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 917 }
 918
 919 static inline bool is_invalid_opcode(u32 intr_info)
 920 {
 921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 922                              INTR_INFO_VALID_MASK)) ==
 923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 924 }
 925
 926 static inline bool is_external_interrupt(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static inline bool is_machine_check(u32 intr_info)
 933 {
 934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 935                              INTR_INFO_VALID_MASK)) ==
 936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 937 }
 938
 939 static inline bool cpu_has_vmx_msr_bitmap(void)
 940 {
 941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 942 }
 943
 944 static inline bool cpu_has_vmx_tpr_shadow(void)
 945 {
 946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 947 }
 948
 949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 950 {
 951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 952 }
 953
 954 static inline bool cpu_has_secondary_exec_ctrls(void)
 955 {
 956         return vmcs_config.cpu_based_exec_ctrl &
 957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 958 }
 959
 960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 961 {
 962         return vmcs_config.cpu_based_2nd_exec_ctrl &
 963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 964 }
 965
 966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 967 {
 968         return vmcs_config.cpu_based_2nd_exec_ctrl &
 969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 970 }
 971
 972 static inline bool cpu_has_vmx_apic_register_virt(void)
 973 {
 974         return vmcs_config.cpu_based_2nd_exec_ctrl &
 975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 976 }
 977
 978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 979 {
 980         return vmcs_config.cpu_based_2nd_exec_ctrl &
 981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 982 }
 983
 984 static inline bool cpu_has_vmx_posted_intr(void)
 985 {
 986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 987 }
 988
 989 static inline bool cpu_has_vmx_apicv(void)
 990 {
 991         return cpu_has_vmx_apic_register_virt() &&
 992                 cpu_has_vmx_virtual_intr_delivery() &&
 993                 cpu_has_vmx_posted_intr();
 994 }
 995
 996 static inline bool cpu_has_vmx_flexpriority(void)
 997 {
 998         return cpu_has_vmx_tpr_shadow() &&
 999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (is_guest_mode(vcpu))
2172                 msr_bitmap = vmx_msr_bitmap_nested;
2173         else if (irqchip_in_kernel(vcpu->kvm) &&
2174                 apic_x2apic_mode(vcpu->arch.apic)) {
2175                 if (is_long_mode(vcpu))
2176                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177                 else
2178                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179         } else {
2180                 if (is_long_mode(vcpu))
2181                         msr_bitmap = vmx_msr_bitmap_longmode;
2182                 else
2183                         msr_bitmap = vmx_msr_bitmap_legacy;
2184         }
2185
2186         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187 }
2188
2189 /*
2190  * Set up the vmcs to automatically save and restore system
2191  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2192  * mode, as fiddling with msrs is very expensive.
2193  */
2194 static void setup_msrs(struct vcpu_vmx *vmx)
2195 {
2196         int save_nmsrs, index;
2197
2198         save_nmsrs = 0;
2199 #ifdef CONFIG_X86_64
2200         if (is_long_mode(&vmx->vcpu)) {
2201                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_LSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_CSTAR);
2208                 if (index >= 0)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211                 if (index >= 0 && vmx->rdtscp_enabled)
2212                         move_msr_up(vmx, index, save_nmsrs++);
2213                 /*
2214                  * MSR_STAR is only needed on long mode guests, and only
2215                  * if efer.sce is enabled.
2216                  */
2217                 index = __find_msr_index(vmx, MSR_STAR);
2218                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2219                         move_msr_up(vmx, index, save_nmsrs++);
2220         }
2221 #endif
2222         index = __find_msr_index(vmx, MSR_EFER);
2223         if (index >= 0 && update_transition_efer(vmx, index))
2224                 move_msr_up(vmx, index, save_nmsrs++);
2225
2226         vmx->save_nmsrs = save_nmsrs;
2227
2228         if (cpu_has_vmx_msr_bitmap())
2229                 vmx_set_msr_bitmap(&vmx->vcpu);
2230 }
2231
2232 /*
2233  * reads and returns guest's timestamp counter "register"
2234  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2235  */
2236 static u64 guest_read_tsc(void)
2237 {
2238         u64 host_tsc, tsc_offset;
2239
2240         rdtscll(host_tsc);
2241         tsc_offset = vmcs_read64(TSC_OFFSET);
2242         return host_tsc + tsc_offset;
2243 }
2244
2245 /*
2246  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247  * counter, even if a nested guest (L2) is currently running.
2248  */
2249 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2250 {
2251         u64 tsc_offset;
2252
2253         tsc_offset = is_guest_mode(vcpu) ?
2254                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255                 vmcs_read64(TSC_OFFSET);
2256         return host_tsc + tsc_offset;
2257 }
2258
2259 /*
2260  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2261  * software catchup for faster rates on slower CPUs.
2262  */
2263 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2264 {
2265         if (!scale)
2266                 return;
2267
2268         if (user_tsc_khz > tsc_khz) {
2269                 vcpu->arch.tsc_catchup = 1;
2270                 vcpu->arch.tsc_always_catchup = 1;
2271         } else
2272                 WARN(1, "user requested TSC rate below hardware speed\n");
2273 }
2274
2275 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276 {
2277         return vmcs_read64(TSC_OFFSET);
2278 }
2279
2280 /*
2281  * writes 'offset' into guest's timestamp counter offset register
2282  */
2283 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2284 {
2285         if (is_guest_mode(vcpu)) {
2286                 /*
2287                  * We're here if L1 chose not to trap WRMSR to TSC. According
2288                  * to the spec, this should set L1's TSC; The offset that L1
2289                  * set for L2 remains unchanged, and still needs to be added
2290                  * to the newly set TSC to get L2's TSC.
2291                  */
2292                 struct vmcs12 *vmcs12;
2293                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294                 /* recalculate vmcs02.TSC_OFFSET: */
2295                 vmcs12 = get_vmcs12(vcpu);
2296                 vmcs_write64(TSC_OFFSET, offset +
2297                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298                          vmcs12->tsc_offset : 0));
2299         } else {
2300                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301                                            vmcs_read64(TSC_OFFSET), offset);
2302                 vmcs_write64(TSC_OFFSET, offset);
2303         }
2304 }
2305
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2307 {
2308         u64 offset = vmcs_read64(TSC_OFFSET);
2309
2310         vmcs_write64(TSC_OFFSET, offset + adjustment);
2311         if (is_guest_mode(vcpu)) {
2312                 /* Even when running L2, the adjustment needs to apply to L1 */
2313                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2314         } else
2315                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316                                            offset + adjustment);
2317 }
2318
2319 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320 {
2321         return target_tsc - native_read_tsc();
2322 }
2323
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325 {
2326         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328 }
2329
2330 /*
2331  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333  * all guests if the "nested" module option is off, and can also be disabled
2334  * for a single guest by disabling its VMX cpuid bit.
2335  */
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337 {
2338         return nested && guest_cpuid_has_vmx(vcpu);
2339 }
2340
2341 /*
2342  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343  * returned for the various VMX controls MSRs when nested VMX is enabled.
2344  * The same values should also be used to verify that vmcs12 control fields are
2345  * valid during nested entry from L1 to L2.
2346  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348  * bit in the high half is on if the corresponding bit in the control field
2349  * may be on. See also vmx_control_verify().
2350  */
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2352 {
2353         /*
2354          * Note that as a general rule, the high half of the MSRs (bits in
2355          * the control fields which may be 1) should be initialized by the
2356          * intersection of the underlying hardware's MSR (i.e., features which
2357          * can be supported) and the list of features we want to expose -
2358          * because they are known to be properly supported in our code.
2359          * Also, usually, the low half of the MSRs (bits which must be 1) can
2360          * be set to 0, meaning that L1 may turn off any of these bits. The
2361          * reason is that if one of these bits is necessary, it will appear
2362          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363          * fields of vmcs01 and vmcs02, will turn these bits off - and
2364          * nested_vmx_exit_handled() will not pass related exits to L1.
2365          * These rules have exceptions below.
2366          */
2367
2368         /* pin-based controls */
2369         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2370                 vmx->nested.nested_vmx_pinbased_ctls_low,
2371                 vmx->nested.nested_vmx_pinbased_ctls_high);
2372         vmx->nested.nested_vmx_pinbased_ctls_low |=
2373                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374         vmx->nested.nested_vmx_pinbased_ctls_high &=
2375                 PIN_BASED_EXT_INTR_MASK |
2376                 PIN_BASED_NMI_EXITING |
2377                 PIN_BASED_VIRTUAL_NMIS;
2378         vmx->nested.nested_vmx_pinbased_ctls_high |=
2379                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2380                 PIN_BASED_VMX_PREEMPTION_TIMER;
2381         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383                         PIN_BASED_POSTED_INTR;
2384
2385         /* exit controls */
2386         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2387                 vmx->nested.nested_vmx_exit_ctls_low,
2388                 vmx->nested.nested_vmx_exit_ctls_high);
2389         vmx->nested.nested_vmx_exit_ctls_low =
2390                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2391
2392         vmx->nested.nested_vmx_exit_ctls_high &=
2393 #ifdef CONFIG_X86_64
2394                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2395 #endif
2396                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2397         vmx->nested.nested_vmx_exit_ctls_high |=
2398                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2399                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2400                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
2402         if (vmx_mpx_supported())
2403                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2404
2405         /* We support free control of debug control saving. */
2406         vmx->nested.nested_vmx_true_exit_ctls_low =
2407                 vmx->nested.nested_vmx_exit_ctls_low &
2408                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
2410         /* entry controls */
2411         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2412                 vmx->nested.nested_vmx_entry_ctls_low,
2413                 vmx->nested.nested_vmx_entry_ctls_high);
2414         vmx->nested.nested_vmx_entry_ctls_low =
2415                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416         vmx->nested.nested_vmx_entry_ctls_high &=
2417 #ifdef CONFIG_X86_64
2418                 VM_ENTRY_IA32E_MODE |
2419 #endif
2420                 VM_ENTRY_LOAD_IA32_PAT;
2421         vmx->nested.nested_vmx_entry_ctls_high |=
2422                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2423         if (vmx_mpx_supported())
2424                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2425
2426         /* We support free control of debug control loading. */
2427         vmx->nested.nested_vmx_true_entry_ctls_low =
2428                 vmx->nested.nested_vmx_entry_ctls_low &
2429                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
2431         /* cpu-based controls */
2432         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2433                 vmx->nested.nested_vmx_procbased_ctls_low,
2434                 vmx->nested.nested_vmx_procbased_ctls_high);
2435         vmx->nested.nested_vmx_procbased_ctls_low =
2436                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437         vmx->nested.nested_vmx_procbased_ctls_high &=
2438                 CPU_BASED_VIRTUAL_INTR_PENDING |
2439                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2440                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442                 CPU_BASED_CR3_STORE_EXITING |
2443 #ifdef CONFIG_X86_64
2444                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445 #endif
2446                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2448                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2449                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2450                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451         /*
2452          * We can allow some features even when not supported by the
2453          * hardware. For example, L1 can specify an MSR bitmap - and we
2454          * can use it to avoid exits to L1 - even when L0 runs L2
2455          * without MSR bitmaps.
2456          */
2457         vmx->nested.nested_vmx_procbased_ctls_high |=
2458                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2459                 CPU_BASED_USE_MSR_BITMAPS;
2460
2461         /* We support free control of CR3 access interception. */
2462         vmx->nested.nested_vmx_true_procbased_ctls_low =
2463                 vmx->nested.nested_vmx_procbased_ctls_low &
2464                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
2466         /* secondary cpu-based controls */
2467         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2468                 vmx->nested.nested_vmx_secondary_ctls_low,
2469                 vmx->nested.nested_vmx_secondary_ctls_high);
2470         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471         vmx->nested.nested_vmx_secondary_ctls_high &=
2472                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473                 SECONDARY_EXEC_RDTSCP |
2474                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2475                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2477                 SECONDARY_EXEC_WBINVD_EXITING |
2478                 SECONDARY_EXEC_XSAVES;
2479
2480         if (enable_ept) {
2481                 /* nested EPT: emulate EPT also to L1 */
2482                 vmx->nested.nested_vmx_secondary_ctls_high |=
2483                         SECONDARY_EXEC_ENABLE_EPT;
2484                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2485                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486                          VMX_EPT_INVEPT_BIT;
2487                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2488                 /*
2489                  * For nested guests, we don't do anything specific
2490                  * for single context invalidation. Hence, only advertise
2491                  * support for global context invalidation.
2492                  */
2493                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2494         } else
2495                 vmx->nested.nested_vmx_ept_caps = 0;
2496
2497         if (enable_unrestricted_guest)
2498                 vmx->nested.nested_vmx_secondary_ctls_high |=
2499                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
2501         /* miscellaneous data */
2502         rdmsr(MSR_IA32_VMX_MISC,
2503                 vmx->nested.nested_vmx_misc_low,
2504                 vmx->nested.nested_vmx_misc_high);
2505         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506         vmx->nested.nested_vmx_misc_low |=
2507                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2508                 VMX_MISC_ACTIVITY_HLT;
2509         vmx->nested.nested_vmx_misc_high = 0;
2510 }
2511
2512 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513 {
2514         /*
2515          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516          */
2517         return ((control & high) | low) == control;
2518 }
2519
2520 static inline u64 vmx_control_msr(u32 low, u32 high)
2521 {
2522         return low | ((u64)high << 32);
2523 }
2524
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527 {
2528         struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
2530         switch (msr_index) {
2531         case MSR_IA32_VMX_BASIC:
2532                 /*
2533                  * This MSR reports some information about VMX support. We
2534                  * should return information about the VMX we emulate for the
2535                  * guest, and the VMCS structure we give it - not about the
2536                  * VMX support of the underlying hardware.
2537                  */
2538                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2539                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541                 break;
2542         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543         case MSR_IA32_VMX_PINBASED_CTLS:
2544                 *pdata = vmx_control_msr(
2545                         vmx->nested.nested_vmx_pinbased_ctls_low,
2546                         vmx->nested.nested_vmx_pinbased_ctls_high);
2547                 break;
2548         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2549                 *pdata = vmx_control_msr(
2550                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2551                         vmx->nested.nested_vmx_procbased_ctls_high);
2552                 break;
2553         case MSR_IA32_VMX_PROCBASED_CTLS:
2554                 *pdata = vmx_control_msr(
2555                         vmx->nested.nested_vmx_procbased_ctls_low,
2556                         vmx->nested.nested_vmx_procbased_ctls_high);
2557                 break;
2558         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2559                 *pdata = vmx_control_msr(
2560                         vmx->nested.nested_vmx_true_exit_ctls_low,
2561                         vmx->nested.nested_vmx_exit_ctls_high);
2562                 break;
2563         case MSR_IA32_VMX_EXIT_CTLS:
2564                 *pdata = vmx_control_msr(
2565                         vmx->nested.nested_vmx_exit_ctls_low,
2566                         vmx->nested.nested_vmx_exit_ctls_high);
2567                 break;
2568         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2569                 *pdata = vmx_control_msr(
2570                         vmx->nested.nested_vmx_true_entry_ctls_low,
2571                         vmx->nested.nested_vmx_entry_ctls_high);
2572                 break;
2573         case MSR_IA32_VMX_ENTRY_CTLS:
2574                 *pdata = vmx_control_msr(
2575                         vmx->nested.nested_vmx_entry_ctls_low,
2576                         vmx->nested.nested_vmx_entry_ctls_high);
2577                 break;
2578         case MSR_IA32_VMX_MISC:
2579                 *pdata = vmx_control_msr(
2580                         vmx->nested.nested_vmx_misc_low,
2581                         vmx->nested.nested_vmx_misc_high);
2582                 break;
2583         /*
2584          * These MSRs specify bits which the guest must keep fixed (on or off)
2585          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586          * We picked the standard core2 setting.
2587          */
2588 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2590         case MSR_IA32_VMX_CR0_FIXED0:
2591                 *pdata = VMXON_CR0_ALWAYSON;
2592                 break;
2593         case MSR_IA32_VMX_CR0_FIXED1:
2594                 *pdata = -1ULL;
2595                 break;
2596         case MSR_IA32_VMX_CR4_FIXED0:
2597                 *pdata = VMXON_CR4_ALWAYSON;
2598                 break;
2599         case MSR_IA32_VMX_CR4_FIXED1:
2600                 *pdata = -1ULL;
2601                 break;
2602         case MSR_IA32_VMX_VMCS_ENUM:
2603                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2604                 break;
2605         case MSR_IA32_VMX_PROCBASED_CTLS2:
2606                 *pdata = vmx_control_msr(
2607                         vmx->nested.nested_vmx_secondary_ctls_low,
2608                         vmx->nested.nested_vmx_secondary_ctls_high);
2609                 break;
2610         case MSR_IA32_VMX_EPT_VPID_CAP:
2611                 /* Currently, no nested vpid support */
2612                 *pdata = vmx->nested.nested_vmx_ept_caps;
2613                 break;
2614         default:
2615                 return 1;
2616         }
2617
2618         return 0;
2619 }
2620
2621 /*
2622  * Reads an msr value (of 'msr_index') into 'pdata'.
2623  * Returns 0 on success, non-0 otherwise.
2624  * Assumes vcpu_load() was already called.
2625  */
2626 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2627 {
2628         u64 data;
2629         struct shared_msr_entry *msr;
2630
2631         if (!pdata) {
2632                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2633                 return -EINVAL;
2634         }
2635
2636         switch (msr_index) {
2637 #ifdef CONFIG_X86_64
2638         case MSR_FS_BASE:
2639                 data = vmcs_readl(GUEST_FS_BASE);
2640                 break;
2641         case MSR_GS_BASE:
2642                 data = vmcs_readl(GUEST_GS_BASE);
2643                 break;
2644         case MSR_KERNEL_GS_BASE:
2645                 vmx_load_host_state(to_vmx(vcpu));
2646                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2647                 break;
2648 #endif
2649         case MSR_EFER:
2650                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2651         case MSR_IA32_TSC:
2652                 data = guest_read_tsc();
2653                 break;
2654         case MSR_IA32_SYSENTER_CS:
2655                 data = vmcs_read32(GUEST_SYSENTER_CS);
2656                 break;
2657         case MSR_IA32_SYSENTER_EIP:
2658                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2659                 break;
2660         case MSR_IA32_SYSENTER_ESP:
2661                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2662                 break;
2663         case MSR_IA32_BNDCFGS:
2664                 if (!vmx_mpx_supported())
2665                         return 1;
2666                 data = vmcs_read64(GUEST_BNDCFGS);
2667                 break;
2668         case MSR_IA32_FEATURE_CONTROL:
2669                 if (!nested_vmx_allowed(vcpu))
2670                         return 1;
2671                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672                 break;
2673         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674                 if (!nested_vmx_allowed(vcpu))
2675                         return 1;
2676                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2677         case MSR_IA32_XSS:
2678                 if (!vmx_xsaves_supported())
2679                         return 1;
2680                 data = vcpu->arch.ia32_xss;
2681                 break;
2682         case MSR_TSC_AUX:
2683                 if (!to_vmx(vcpu)->rdtscp_enabled)
2684                         return 1;
2685                 /* Otherwise falls through */
2686         default:
2687                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2688                 if (msr) {
2689                         data = msr->data;
2690                         break;
2691                 }
2692                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2693         }
2694
2695         *pdata = data;
2696         return 0;
2697 }
2698
2699 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2700
2701 /*
2702  * Writes msr value into into the appropriate "register".
2703  * Returns 0 on success, non-0 otherwise.
2704  * Assumes vcpu_load() was already called.
2705  */
2706 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2707 {
2708         struct vcpu_vmx *vmx = to_vmx(vcpu);
2709         struct shared_msr_entry *msr;
2710         int ret = 0;
2711         u32 msr_index = msr_info->index;
2712         u64 data = msr_info->data;
2713
2714         switch (msr_index) {
2715         case MSR_EFER:
2716                 ret = kvm_set_msr_common(vcpu, msr_info);
2717                 break;
2718 #ifdef CONFIG_X86_64
2719         case MSR_FS_BASE:
2720                 vmx_segment_cache_clear(vmx);
2721                 vmcs_writel(GUEST_FS_BASE, data);
2722                 break;
2723         case MSR_GS_BASE:
2724                 vmx_segment_cache_clear(vmx);
2725                 vmcs_writel(GUEST_GS_BASE, data);
2726                 break;
2727         case MSR_KERNEL_GS_BASE:
2728                 vmx_load_host_state(vmx);
2729                 vmx->msr_guest_kernel_gs_base = data;
2730                 break;
2731 #endif
2732         case MSR_IA32_SYSENTER_CS:
2733                 vmcs_write32(GUEST_SYSENTER_CS, data);
2734                 break;
2735         case MSR_IA32_SYSENTER_EIP:
2736                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2737                 break;
2738         case MSR_IA32_SYSENTER_ESP:
2739                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2740                 break;
2741         case MSR_IA32_BNDCFGS:
2742                 if (!vmx_mpx_supported())
2743                         return 1;
2744                 vmcs_write64(GUEST_BNDCFGS, data);
2745                 break;
2746         case MSR_IA32_TSC:
2747                 kvm_write_tsc(vcpu, msr_info);
2748                 break;
2749         case MSR_IA32_CR_PAT:
2750                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2751                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752                                 return 1;
2753                         vmcs_write64(GUEST_IA32_PAT, data);
2754                         vcpu->arch.pat = data;
2755                         break;
2756                 }
2757                 ret = kvm_set_msr_common(vcpu, msr_info);
2758                 break;
2759         case MSR_IA32_TSC_ADJUST:
2760                 ret = kvm_set_msr_common(vcpu, msr_info);
2761                 break;
2762         case MSR_IA32_FEATURE_CONTROL:
2763                 if (!nested_vmx_allowed(vcpu) ||
2764                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766                         return 1;
2767                 vmx->nested.msr_ia32_feature_control = data;
2768                 if (msr_info->host_initiated && data == 0)
2769                         vmx_leave_nested(vcpu);
2770                 break;
2771         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772                 return 1; /* they are read-only */
2773         case MSR_IA32_XSS:
2774                 if (!vmx_xsaves_supported())
2775                         return 1;
2776                 /*
2777                  * The only supported bit as of Skylake is bit 8, but
2778                  * it is not supported on KVM.
2779                  */
2780                 if (data != 0)
2781                         return 1;
2782                 vcpu->arch.ia32_xss = data;
2783                 if (vcpu->arch.ia32_xss != host_xss)
2784                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785                                 vcpu->arch.ia32_xss, host_xss);
2786                 else
2787                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2788                 break;
2789         case MSR_TSC_AUX:
2790                 if (!vmx->rdtscp_enabled)
2791                         return 1;
2792                 /* Check reserved bit, higher 32 bits should be zero */
2793                 if ((data >> 32) != 0)
2794                         return 1;
2795                 /* Otherwise falls through */
2796         default:
2797                 msr = find_msr_entry(vmx, msr_index);
2798                 if (msr) {
2799                         u64 old_msr_data = msr->data;
2800                         msr->data = data;
2801                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802                                 preempt_disable();
2803                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2804                                                          msr->mask);
2805                                 preempt_enable();
2806                                 if (ret)
2807                                         msr->data = old_msr_data;
2808                         }
2809                         break;
2810                 }
2811                 ret = kvm_set_msr_common(vcpu, msr_info);
2812         }
2813
2814         return ret;
2815 }
2816
2817 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2818 {
2819         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2820         switch (reg) {
2821         case VCPU_REGS_RSP:
2822                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2823                 break;
2824         case VCPU_REGS_RIP:
2825                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826                 break;
2827         case VCPU_EXREG_PDPTR:
2828                 if (enable_ept)
2829                         ept_save_pdptrs(vcpu);
2830                 break;
2831         default:
2832                 break;
2833         }
2834 }
2835
2836 static __init int cpu_has_kvm_support(void)
2837 {
2838         return cpu_has_vmx();
2839 }
2840
2841 static __init int vmx_disabled_by_bios(void)
2842 {
2843         u64 msr;
2844
2845         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2846         if (msr & FEATURE_CONTROL_LOCKED) {
2847                 /* launched w/ TXT and VMX disabled */
2848                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2849                         && tboot_enabled())
2850                         return 1;
2851                 /* launched w/o TXT and VMX only enabled w/ TXT */
2852                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2854                         && !tboot_enabled()) {
2855                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2856                                 "activate TXT before enabling KVM\n");
2857                         return 1;
2858                 }
2859                 /* launched w/o TXT and VMX disabled */
2860                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861                         && !tboot_enabled())
2862                         return 1;
2863         }
2864
2865         return 0;
2866 }
2867
2868 static void kvm_cpu_vmxon(u64 addr)
2869 {
2870         asm volatile (ASM_VMX_VMXON_RAX
2871                         : : "a"(&addr), "m"(addr)
2872                         : "memory", "cc");
2873 }
2874
2875 static int hardware_enable(void)
2876 {
2877         int cpu = raw_smp_processor_id();
2878         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2879         u64 old, test_bits;
2880
2881         if (cr4_read_shadow() & X86_CR4_VMXE)
2882                 return -EBUSY;
2883
2884         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2885
2886         /*
2887          * Now we can enable the vmclear operation in kdump
2888          * since the loaded_vmcss_on_cpu list on this cpu
2889          * has been initialized.
2890          *
2891          * Though the cpu is not in VMX operation now, there
2892          * is no problem to enable the vmclear operation
2893          * for the loaded_vmcss_on_cpu list is empty!
2894          */
2895         crash_enable_local_vmclear(cpu);
2896
2897         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2898
2899         test_bits = FEATURE_CONTROL_LOCKED;
2900         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901         if (tboot_enabled())
2902                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903
2904         if ((old & test_bits) != test_bits) {
2905                 /* enable and lock */
2906                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907         }
2908         cr4_set_bits(X86_CR4_VMXE);
2909
2910         if (vmm_exclusive) {
2911                 kvm_cpu_vmxon(phys_addr);
2912                 ept_sync_global();
2913         }
2914
2915         native_store_gdt(this_cpu_ptr(&host_gdt));
2916
2917         return 0;
2918 }
2919
2920 static void vmclear_local_loaded_vmcss(void)
2921 {
2922         int cpu = raw_smp_processor_id();
2923         struct loaded_vmcs *v, *n;
2924
2925         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926                                  loaded_vmcss_on_cpu_link)
2927                 __loaded_vmcs_clear(v);
2928 }
2929
2930
2931 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2932  * tricks.
2933  */
2934 static void kvm_cpu_vmxoff(void)
2935 {
2936         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2937 }
2938
2939 static void hardware_disable(void)
2940 {
2941         if (vmm_exclusive) {
2942                 vmclear_local_loaded_vmcss();
2943                 kvm_cpu_vmxoff();
2944         }
2945         cr4_clear_bits(X86_CR4_VMXE);
2946 }
2947
2948 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2949                                       u32 msr, u32 *result)
2950 {
2951         u32 vmx_msr_low, vmx_msr_high;
2952         u32 ctl = ctl_min | ctl_opt;
2953
2954         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955
2956         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2958
2959         /* Ensure minimum (required) set of control bits are supported. */
2960         if (ctl_min & ~ctl)
2961                 return -EIO;
2962
2963         *result = ctl;
2964         return 0;
2965 }
2966
2967 static __init bool allow_1_setting(u32 msr, u32 ctl)
2968 {
2969         u32 vmx_msr_low, vmx_msr_high;
2970
2971         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972         return vmx_msr_high & ctl;
2973 }
2974
2975 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2976 {
2977         u32 vmx_msr_low, vmx_msr_high;
2978         u32 min, opt, min2, opt2;
2979         u32 _pin_based_exec_control = 0;
2980         u32 _cpu_based_exec_control = 0;
2981         u32 _cpu_based_2nd_exec_control = 0;
2982         u32 _vmexit_control = 0;
2983         u32 _vmentry_control = 0;
2984
2985         min = CPU_BASED_HLT_EXITING |
2986 #ifdef CONFIG_X86_64
2987               CPU_BASED_CR8_LOAD_EXITING |
2988               CPU_BASED_CR8_STORE_EXITING |
2989 #endif
2990               CPU_BASED_CR3_LOAD_EXITING |
2991               CPU_BASED_CR3_STORE_EXITING |
2992               CPU_BASED_USE_IO_BITMAPS |
2993               CPU_BASED_MOV_DR_EXITING |
2994               CPU_BASED_USE_TSC_OFFSETING |
2995               CPU_BASED_MWAIT_EXITING |
2996               CPU_BASED_MONITOR_EXITING |
2997               CPU_BASED_INVLPG_EXITING |
2998               CPU_BASED_RDPMC_EXITING;
2999
3000         opt = CPU_BASED_TPR_SHADOW |
3001               CPU_BASED_USE_MSR_BITMAPS |
3002               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3003         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004                                 &_cpu_based_exec_control) < 0)
3005                 return -EIO;
3006 #ifdef CONFIG_X86_64
3007         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009                                            ~CPU_BASED_CR8_STORE_EXITING;
3010 #endif
3011         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3012                 min2 = 0;
3013                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3014                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3015                         SECONDARY_EXEC_WBINVD_EXITING |
3016                         SECONDARY_EXEC_ENABLE_VPID |
3017                         SECONDARY_EXEC_ENABLE_EPT |
3018                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3019                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3020                         SECONDARY_EXEC_RDTSCP |
3021                         SECONDARY_EXEC_ENABLE_INVPCID |
3022                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3023                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3024                         SECONDARY_EXEC_SHADOW_VMCS |
3025                         SECONDARY_EXEC_XSAVES |
3026                         SECONDARY_EXEC_ENABLE_PML;
3027                 if (adjust_vmx_controls(min2, opt2,
3028                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3029                                         &_cpu_based_2nd_exec_control) < 0)
3030                         return -EIO;
3031         }
3032 #ifndef CONFIG_X86_64
3033         if (!(_cpu_based_2nd_exec_control &
3034                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3036 #endif
3037
3038         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039                 _cpu_based_2nd_exec_control &= ~(
3040                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3041                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3043
3044         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3045                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046                    enabled */
3047                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048                                              CPU_BASED_CR3_STORE_EXITING |
3049                                              CPU_BASED_INVLPG_EXITING);
3050                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051                       vmx_capability.ept, vmx_capability.vpid);
3052         }
3053
3054         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3055 #ifdef CONFIG_X86_64
3056         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057 #endif
3058         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3059                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3060         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061                                 &_vmexit_control) < 0)
3062                 return -EIO;
3063
3064         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067                                 &_pin_based_exec_control) < 0)
3068                 return -EIO;
3069
3070         if (!(_cpu_based_2nd_exec_control &
3071                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074
3075         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3076         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3077         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078                                 &_vmentry_control) < 0)
3079                 return -EIO;
3080
3081         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3082
3083         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3085                 return -EIO;
3086
3087 #ifdef CONFIG_X86_64
3088         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089         if (vmx_msr_high & (1u<<16))
3090                 return -EIO;
3091 #endif
3092
3093         /* Require Write-Back (WB) memory type for VMCS accesses. */
3094         if (((vmx_msr_high >> 18) & 15) != 6)
3095                 return -EIO;
3096
3097         vmcs_conf->size = vmx_msr_high & 0x1fff;
3098         vmcs_conf->order = get_order(vmcs_config.size);
3099         vmcs_conf->revision_id = vmx_msr_low;
3100
3101         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3103         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3104         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3105         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3106
3107         cpu_has_load_ia32_efer =
3108                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109                                 VM_ENTRY_LOAD_IA32_EFER)
3110                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111                                    VM_EXIT_LOAD_IA32_EFER);
3112
3113         cpu_has_load_perf_global_ctrl =
3114                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3118
3119         /*
3120          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121          * but due to arrata below it can't be used. Workaround is to use
3122          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123          *
3124          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3125          *
3126          * AAK155             (model 26)
3127          * AAP115             (model 30)
3128          * AAT100             (model 37)
3129          * BC86,AAY89,BD102   (model 44)
3130          * BA97               (model 46)
3131          *
3132          */
3133         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134                 switch (boot_cpu_data.x86_model) {
3135                 case 26:
3136                 case 30:
3137                 case 37:
3138                 case 44:
3139                 case 46:
3140                         cpu_has_load_perf_global_ctrl = false;
3141                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142                                         "does not work properly. Using workaround\n");
3143                         break;
3144                 default:
3145                         break;
3146                 }
3147         }
3148
3149         if (cpu_has_xsaves)
3150                 rdmsrl(MSR_IA32_XSS, host_xss);
3151
3152         return 0;
3153 }
3154
3155 static struct vmcs *alloc_vmcs_cpu(int cpu)
3156 {
3157         int node = cpu_to_node(cpu);
3158         struct page *pages;
3159         struct vmcs *vmcs;
3160
3161         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3162         if (!pages)
3163                 return NULL;
3164         vmcs = page_address(pages);
3165         memset(vmcs, 0, vmcs_config.size);
3166         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3167         return vmcs;
3168 }
3169
3170 static struct vmcs *alloc_vmcs(void)
3171 {
3172         return alloc_vmcs_cpu(raw_smp_processor_id());
3173 }
3174
3175 static void free_vmcs(struct vmcs *vmcs)
3176 {
3177         free_pages((unsigned long)vmcs, vmcs_config.order);
3178 }
3179
3180 /*
3181  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182  */
3183 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184 {
3185         if (!loaded_vmcs->vmcs)
3186                 return;
3187         loaded_vmcs_clear(loaded_vmcs);
3188         free_vmcs(loaded_vmcs->vmcs);
3189         loaded_vmcs->vmcs = NULL;
3190 }
3191
3192 static void free_kvm_area(void)
3193 {
3194         int cpu;
3195
3196         for_each_possible_cpu(cpu) {
3197                 free_vmcs(per_cpu(vmxarea, cpu));
3198                 per_cpu(vmxarea, cpu) = NULL;
3199         }
3200 }
3201
3202 static void init_vmcs_shadow_fields(void)
3203 {
3204         int i, j;
3205
3206         /* No checks for read only fields yet */
3207
3208         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209                 switch (shadow_read_write_fields[i]) {
3210                 case GUEST_BNDCFGS:
3211                         if (!vmx_mpx_supported())
3212                                 continue;
3213                         break;
3214                 default:
3215                         break;
3216                 }
3217
3218                 if (j < i)
3219                         shadow_read_write_fields[j] =
3220                                 shadow_read_write_fields[i];
3221                 j++;
3222         }
3223         max_shadow_read_write_fields = j;
3224
3225         /* shadowed fields guest access without vmexit */
3226         for (i = 0; i < max_shadow_read_write_fields; i++) {
3227                 clear_bit(shadow_read_write_fields[i],
3228                           vmx_vmwrite_bitmap);
3229                 clear_bit(shadow_read_write_fields[i],
3230                           vmx_vmread_bitmap);
3231         }
3232         for (i = 0; i < max_shadow_read_only_fields; i++)
3233                 clear_bit(shadow_read_only_fields[i],
3234                           vmx_vmread_bitmap);
3235 }
3236
3237 static __init int alloc_kvm_area(void)
3238 {
3239         int cpu;
3240
3241         for_each_possible_cpu(cpu) {
3242                 struct vmcs *vmcs;
3243
3244                 vmcs = alloc_vmcs_cpu(cpu);
3245                 if (!vmcs) {
3246                         free_kvm_area();
3247                         return -ENOMEM;
3248                 }
3249
3250                 per_cpu(vmxarea, cpu) = vmcs;
3251         }
3252         return 0;
3253 }
3254
3255 static bool emulation_required(struct kvm_vcpu *vcpu)
3256 {
3257         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3258 }
3259
3260 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3261                 struct kvm_segment *save)
3262 {
3263         if (!emulate_invalid_guest_state) {
3264                 /*
3265                  * CS and SS RPL should be equal during guest entry according
3266                  * to VMX spec, but in reality it is not always so. Since vcpu
3267                  * is in the middle of the transition from real mode to
3268                  * protected mode it is safe to assume that RPL 0 is a good
3269                  * default value.
3270                  */
3271                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3272                         save->selector &= ~SEGMENT_RPL_MASK;
3273                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3274                 save->s = 1;
3275         }
3276         vmx_set_segment(vcpu, save, seg);
3277 }
3278
3279 static void enter_pmode(struct kvm_vcpu *vcpu)
3280 {
3281         unsigned long flags;
3282         struct vcpu_vmx *vmx = to_vmx(vcpu);
3283
3284         /*
3285          * Update real mode segment cache. It may be not up-to-date if sement
3286          * register was written while vcpu was in a guest mode.
3287          */
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294
3295         vmx->rmode.vm86_active = 0;
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3300
3301         flags = vmcs_readl(GUEST_RFLAGS);
3302         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3304         vmcs_writel(GUEST_RFLAGS, flags);
3305
3306         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3308
3309         update_exception_bitmap(vcpu);
3310
3311         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3317 }
3318
3319 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3320 {
3321         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3322         struct kvm_segment var = *save;
3323
3324         var.dpl = 0x3;
3325         if (seg == VCPU_SREG_CS)
3326                 var.type = 0x3;
3327
3328         if (!emulate_invalid_guest_state) {
3329                 var.selector = var.base >> 4;
3330                 var.base = var.base & 0xffff0;
3331                 var.limit = 0xffff;
3332                 var.g = 0;
3333                 var.db = 0;
3334                 var.present = 1;
3335                 var.s = 1;
3336                 var.l = 0;
3337                 var.unusable = 0;
3338                 var.type = 0x3;
3339                 var.avl = 0;
3340                 if (save->base & 0xf)
3341                         printk_once(KERN_WARNING "kvm: segment base is not "
3342                                         "paragraph aligned when entering "
3343                                         "protected mode (seg=%d)", seg);
3344         }
3345
3346         vmcs_write16(sf->selector, var.selector);
3347         vmcs_write32(sf->base, var.base);
3348         vmcs_write32(sf->limit, var.limit);
3349         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3350 }
3351
3352 static void enter_rmode(struct kvm_vcpu *vcpu)
3353 {
3354         unsigned long flags;
3355         struct vcpu_vmx *vmx = to_vmx(vcpu);
3356
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3364
3365         vmx->rmode.vm86_active = 1;
3366
3367         /*
3368          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3369          * vcpu. Warn the user that an update is overdue.
3370          */
3371         if (!vcpu->kvm->arch.tss_addr)
3372                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373                              "called before entering vcpu\n");
3374
3375         vmx_segment_cache_clear(vmx);
3376
3377         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3378         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3379         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380
3381         flags = vmcs_readl(GUEST_RFLAGS);
3382         vmx->rmode.save_rflags = flags;
3383
3384         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3385
3386         vmcs_writel(GUEST_RFLAGS, flags);
3387         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3388         update_exception_bitmap(vcpu);
3389
3390         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3391         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3392         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3393         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3394         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3395         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3396
3397         kvm_mmu_reset_context(vcpu);
3398 }
3399
3400 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3401 {
3402         struct vcpu_vmx *vmx = to_vmx(vcpu);
3403         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3404
3405         if (!msr)
3406                 return;
3407
3408         /*
3409          * Force kernel_gs_base reloading before EFER changes, as control
3410          * of this msr depends on is_long_mode().
3411          */
3412         vmx_load_host_state(to_vmx(vcpu));
3413         vcpu->arch.efer = efer;
3414         if (efer & EFER_LMA) {
3415                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3416                 msr->data = efer;
3417         } else {
3418                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3419
3420                 msr->data = efer & ~EFER_LME;
3421         }
3422         setup_msrs(vmx);
3423 }
3424
3425 #ifdef CONFIG_X86_64
3426
3427 static void enter_lmode(struct kvm_vcpu *vcpu)
3428 {
3429         u32 guest_tr_ar;
3430
3431         vmx_segment_cache_clear(to_vmx(vcpu));
3432
3433         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3434         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3435                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3436                                      __func__);
3437                 vmcs_write32(GUEST_TR_AR_BYTES,
3438                              (guest_tr_ar & ~AR_TYPE_MASK)
3439                              | AR_TYPE_BUSY_64_TSS);
3440         }
3441         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3442 }
3443
3444 static void exit_lmode(struct kvm_vcpu *vcpu)
3445 {
3446         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3447         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3448 }
3449
3450 #endif
3451
3452 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3453 {
3454         vpid_sync_context(to_vmx(vcpu));
3455         if (enable_ept) {
3456                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3457                         return;
3458                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3459         }
3460 }
3461
3462 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3463 {
3464         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3465
3466         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3467         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3468 }
3469
3470 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3471 {
3472         if (enable_ept && is_paging(vcpu))
3473                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3474         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3475 }
3476
3477 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3478 {
3479         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3480
3481         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3482         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3483 }
3484
3485 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3486 {
3487         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3488
3489         if (!test_bit(VCPU_EXREG_PDPTR,
3490                       (unsigned long *)&vcpu->arch.regs_dirty))
3491                 return;
3492
3493         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3494                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3495                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3496                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3497                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3498         }
3499 }
3500
3501 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3502 {
3503         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3504
3505         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3506                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3507                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3508                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3509                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3510         }
3511
3512         __set_bit(VCPU_EXREG_PDPTR,
3513                   (unsigned long *)&vcpu->arch.regs_avail);
3514         __set_bit(VCPU_EXREG_PDPTR,
3515                   (unsigned long *)&vcpu->arch.regs_dirty);
3516 }
3517
3518 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3519
3520 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3521                                         unsigned long cr0,
3522                                         struct kvm_vcpu *vcpu)
3523 {
3524         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3525                 vmx_decache_cr3(vcpu);
3526         if (!(cr0 & X86_CR0_PG)) {
3527                 /* From paging/starting to nonpaging */
3528                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3529                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3530                              (CPU_BASED_CR3_LOAD_EXITING |
3531                               CPU_BASED_CR3_STORE_EXITING));
3532                 vcpu->arch.cr0 = cr0;
3533                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3534         } else if (!is_paging(vcpu)) {
3535                 /* From nonpaging to paging */
3536                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3537                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3538                              ~(CPU_BASED_CR3_LOAD_EXITING |
3539                                CPU_BASED_CR3_STORE_EXITING));
3540                 vcpu->arch.cr0 = cr0;
3541                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3542         }
3543
3544         if (!(cr0 & X86_CR0_WP))
3545                 *hw_cr0 &= ~X86_CR0_WP;
3546 }
3547
3548 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3549 {
3550         struct vcpu_vmx *vmx = to_vmx(vcpu);
3551         unsigned long hw_cr0;
3552
3553         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3554         if (enable_unrestricted_guest)
3555                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3556         else {
3557                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3558
3559                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3560                         enter_pmode(vcpu);
3561
3562                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3563                         enter_rmode(vcpu);
3564         }
3565
3566 #ifdef CONFIG_X86_64
3567         if (vcpu->arch.efer & EFER_LME) {
3568                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3569                         enter_lmode(vcpu);
3570                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3571                         exit_lmode(vcpu);
3572         }
3573 #endif
3574
3575         if (enable_ept)
3576                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3577
3578         if (!vcpu->fpu_active)
3579                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3580
3581         vmcs_writel(CR0_READ_SHADOW, cr0);
3582         vmcs_writel(GUEST_CR0, hw_cr0);
3583         vcpu->arch.cr0 = cr0;
3584
3585         /* depends on vcpu->arch.cr0 to be set to a new value */
3586         vmx->emulation_required = emulation_required(vcpu);
3587 }
3588
3589 static u64 construct_eptp(unsigned long root_hpa)
3590 {
3591         u64 eptp;
3592
3593         /* TODO write the value reading from MSR */
3594         eptp = VMX_EPT_DEFAULT_MT |
3595                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3596         if (enable_ept_ad_bits)
3597                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3598         eptp |= (root_hpa & PAGE_MASK);
3599
3600         return eptp;
3601 }
3602
3603 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3604 {
3605         unsigned long guest_cr3;
3606         u64 eptp;
3607
3608         guest_cr3 = cr3;
3609         if (enable_ept) {
3610                 eptp = construct_eptp(cr3);
3611                 vmcs_write64(EPT_POINTER, eptp);
3612                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3613                         guest_cr3 = kvm_read_cr3(vcpu);
3614                 else
3615                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3616                 ept_load_pdptrs(vcpu);
3617         }
3618
3619         vmx_flush_tlb(vcpu);
3620         vmcs_writel(GUEST_CR3, guest_cr3);
3621 }
3622
3623 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3624 {
3625         /*
3626          * Pass through host's Machine Check Enable value to hw_cr4, which
3627          * is in force while we are in guest mode.  Do not let guests control
3628          * this bit, even if host CR4.MCE == 0.
3629          */
3630         unsigned long hw_cr4 =
3631                 (cr4_read_shadow() & X86_CR4_MCE) |
3632                 (cr4 & ~X86_CR4_MCE) |
3633                 (to_vmx(vcpu)->rmode.vm86_active ?
3634                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3635
3636         if (cr4 & X86_CR4_VMXE) {
3637                 /*
3638                  * To use VMXON (and later other VMX instructions), a guest
3639                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3640                  * So basically the check on whether to allow nested VMX
3641                  * is here.
3642                  */
3643                 if (!nested_vmx_allowed(vcpu))
3644                         return 1;
3645         }
3646         if (to_vmx(vcpu)->nested.vmxon &&
3647             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3648                 return 1;
3649
3650         vcpu->arch.cr4 = cr4;
3651         if (enable_ept) {
3652                 if (!is_paging(vcpu)) {
3653                         hw_cr4 &= ~X86_CR4_PAE;
3654                         hw_cr4 |= X86_CR4_PSE;
3655                         /*
3656                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3657                          * in hardware. However KVM always uses paging mode to
3658                          * emulate guest non-paging mode with TDP.
3659                          * To emulate this behavior, SMEP/SMAP needs to be
3660                          * manually disabled when guest switches to non-paging
3661                          * mode.
3662                          */
3663                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3664                 } else if (!(cr4 & X86_CR4_PAE)) {
3665                         hw_cr4 &= ~X86_CR4_PAE;
3666                 }
3667         }
3668
3669         vmcs_writel(CR4_READ_SHADOW, cr4);
3670         vmcs_writel(GUEST_CR4, hw_cr4);
3671         return 0;
3672 }
3673
3674 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3675                             struct kvm_segment *var, int seg)
3676 {
3677         struct vcpu_vmx *vmx = to_vmx(vcpu);
3678         u32 ar;
3679
3680         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3681                 *var = vmx->rmode.segs[seg];
3682                 if (seg == VCPU_SREG_TR
3683                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3684                         return;
3685                 var->base = vmx_read_guest_seg_base(vmx, seg);
3686                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3687                 return;
3688         }
3689         var->base = vmx_read_guest_seg_base(vmx, seg);
3690         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3691         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3692         ar = vmx_read_guest_seg_ar(vmx, seg);
3693         var->unusable = (ar >> 16) & 1;
3694         var->type = ar & 15;
3695         var->s = (ar >> 4) & 1;
3696         var->dpl = (ar >> 5) & 3;
3697         /*
3698          * Some userspaces do not preserve unusable property. Since usable
3699          * segment has to be present according to VMX spec we can use present
3700          * property to amend userspace bug by making unusable segment always
3701          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3702          * segment as unusable.
3703          */
3704         var->present = !var->unusable;
3705         var->avl = (ar >> 12) & 1;
3706         var->l = (ar >> 13) & 1;
3707         var->db = (ar >> 14) & 1;
3708         var->g = (ar >> 15) & 1;
3709 }
3710
3711 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3712 {
3713         struct kvm_segment s;
3714
3715         if (to_vmx(vcpu)->rmode.vm86_active) {
3716                 vmx_get_segment(vcpu, &s, seg);
3717                 return s.base;
3718         }
3719         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3720 }
3721
3722 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3723 {
3724         struct vcpu_vmx *vmx = to_vmx(vcpu);
3725
3726         if (unlikely(vmx->rmode.vm86_active))
3727                 return 0;
3728         else {
3729                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3730                 return AR_DPL(ar);
3731         }
3732 }
3733
3734 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3735 {
3736         u32 ar;
3737
3738         if (var->unusable || !var->present)
3739                 ar = 1 << 16;
3740         else {
3741                 ar = var->type & 15;
3742                 ar |= (var->s & 1) << 4;
3743                 ar |= (var->dpl & 3) << 5;
3744                 ar |= (var->present & 1) << 7;
3745                 ar |= (var->avl & 1) << 12;
3746                 ar |= (var->l & 1) << 13;
3747                 ar |= (var->db & 1) << 14;
3748                 ar |= (var->g & 1) << 15;
3749         }
3750
3751         return ar;
3752 }
3753
3754 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3755                             struct kvm_segment *var, int seg)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3759
3760         vmx_segment_cache_clear(vmx);
3761
3762         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3763                 vmx->rmode.segs[seg] = *var;
3764                 if (seg == VCPU_SREG_TR)
3765                         vmcs_write16(sf->selector, var->selector);
3766                 else if (var->s)
3767                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3768                 goto out;
3769         }
3770
3771         vmcs_writel(sf->base, var->base);
3772         vmcs_write32(sf->limit, var->limit);
3773         vmcs_write16(sf->selector, var->selector);
3774
3775         /*
3776          *   Fix the "Accessed" bit in AR field of segment registers for older
3777          * qemu binaries.
3778          *   IA32 arch specifies that at the time of processor reset the
3779          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3780          * is setting it to 0 in the userland code. This causes invalid guest
3781          * state vmexit when "unrestricted guest" mode is turned on.
3782          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3783          * tree. Newer qemu binaries with that qemu fix would not need this
3784          * kvm hack.
3785          */
3786         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3787                 var->type |= 0x1; /* Accessed */
3788
3789         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3790
3791 out:
3792         vmx->emulation_required = emulation_required(vcpu);
3793 }
3794
3795 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3796 {
3797         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3798
3799         *db = (ar >> 14) & 1;
3800         *l = (ar >> 13) & 1;
3801 }
3802
3803 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3804 {
3805         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3806         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3807 }
3808
3809 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3810 {
3811         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3812         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3813 }
3814
3815 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3816 {
3817         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3818         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3819 }
3820
3821 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3822 {
3823         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3824         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3825 }
3826
3827 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3828 {
3829         struct kvm_segment var;
3830         u32 ar;
3831
3832         vmx_get_segment(vcpu, &var, seg);
3833         var.dpl = 0x3;
3834         if (seg == VCPU_SREG_CS)
3835                 var.type = 0x3;
3836         ar = vmx_segment_access_rights(&var);
3837
3838         if (var.base != (var.selector << 4))
3839                 return false;
3840         if (var.limit != 0xffff)
3841                 return false;
3842         if (ar != 0xf3)
3843                 return false;
3844
3845         return true;
3846 }
3847
3848 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3849 {
3850         struct kvm_segment cs;
3851         unsigned int cs_rpl;
3852
3853         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3854         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3855
3856         if (cs.unusable)
3857                 return false;
3858         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3859                 return false;
3860         if (!cs.s)
3861                 return false;
3862         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3863                 if (cs.dpl > cs_rpl)
3864                         return false;
3865         } else {
3866                 if (cs.dpl != cs_rpl)
3867                         return false;
3868         }
3869         if (!cs.present)
3870                 return false;
3871
3872         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3873         return true;
3874 }
3875
3876 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3877 {
3878         struct kvm_segment ss;
3879         unsigned int ss_rpl;
3880
3881         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3882         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3883
3884         if (ss.unusable)
3885                 return true;
3886         if (ss.type != 3 && ss.type != 7)
3887                 return false;
3888         if (!ss.s)
3889                 return false;
3890         if (ss.dpl != ss_rpl) /* DPL != RPL */
3891                 return false;
3892         if (!ss.present)
3893                 return false;
3894
3895         return true;
3896 }
3897
3898 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3899 {
3900         struct kvm_segment var;
3901         unsigned int rpl;
3902
3903         vmx_get_segment(vcpu, &var, seg);
3904         rpl = var.selector & SEGMENT_RPL_MASK;
3905
3906         if (var.unusable)
3907                 return true;
3908         if (!var.s)
3909                 return false;
3910         if (!var.present)
3911                 return false;
3912         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3913                 if (var.dpl < rpl) /* DPL < RPL */
3914                         return false;
3915         }
3916
3917         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3918          * rights flags
3919          */
3920         return true;
3921 }
3922
3923 static bool tr_valid(struct kvm_vcpu *vcpu)
3924 {
3925         struct kvm_segment tr;
3926
3927         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3928
3929         if (tr.unusable)
3930                 return false;
3931         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3932                 return false;
3933         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3934                 return false;
3935         if (!tr.present)
3936                 return false;
3937
3938         return true;
3939 }
3940
3941 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3942 {
3943         struct kvm_segment ldtr;
3944
3945         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3946
3947         if (ldtr.unusable)
3948                 return true;
3949         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3950                 return false;
3951         if (ldtr.type != 2)
3952                 return false;
3953         if (!ldtr.present)
3954                 return false;
3955
3956         return true;
3957 }
3958
3959 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3960 {
3961         struct kvm_segment cs, ss;
3962
3963         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3964         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3965
3966         return ((cs.selector & SEGMENT_RPL_MASK) ==
3967                  (ss.selector & SEGMENT_RPL_MASK));
3968 }
3969
3970 /*
3971  * Check if guest state is valid. Returns true if valid, false if
3972  * not.
3973  * We assume that registers are always usable
3974  */
3975 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3976 {
3977         if (enable_unrestricted_guest)
3978                 return true;
3979
3980         /* real mode guest state checks */
3981         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3982                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3983                         return false;
3984                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3985                         return false;
3986                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3987                         return false;
3988                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3989                         return false;
3990                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3991                         return false;
3992                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3993                         return false;
3994         } else {
3995         /* protected mode guest state checks */
3996                 if (!cs_ss_rpl_check(vcpu))
3997                         return false;
3998                 if (!code_segment_valid(vcpu))
3999                         return false;
4000                 if (!stack_segment_valid(vcpu))
4001                         return false;
4002                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4003                         return false;
4004                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4005                         return false;
4006                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4007                         return false;
4008                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4009                         return false;
4010                 if (!tr_valid(vcpu))
4011                         return false;
4012                 if (!ldtr_valid(vcpu))
4013                         return false;
4014         }
4015         /* TODO:
4016          * - Add checks on RIP
4017          * - Add checks on RFLAGS
4018          */
4019
4020         return true;
4021 }
4022
4023 static int init_rmode_tss(struct kvm *kvm)
4024 {
4025         gfn_t fn;
4026         u16 data = 0;
4027         int idx, r;
4028
4029         idx = srcu_read_lock(&kvm->srcu);
4030         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4031         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4032         if (r < 0)
4033                 goto out;
4034         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4035         r = kvm_write_guest_page(kvm, fn++, &data,
4036                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4037         if (r < 0)
4038                 goto out;
4039         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4040         if (r < 0)
4041                 goto out;
4042         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4043         if (r < 0)
4044                 goto out;
4045         data = ~0;
4046         r = kvm_write_guest_page(kvm, fn, &data,
4047                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4048                                  sizeof(u8));
4049 out:
4050         srcu_read_unlock(&kvm->srcu, idx);
4051         return r;
4052 }
4053
4054 static int init_rmode_identity_map(struct kvm *kvm)
4055 {
4056         int i, idx, r = 0;
4057         pfn_t identity_map_pfn;
4058         u32 tmp;
4059
4060         if (!enable_ept)
4061                 return 0;
4062
4063         /* Protect kvm->arch.ept_identity_pagetable_done. */
4064         mutex_lock(&kvm->slots_lock);
4065
4066         if (likely(kvm->arch.ept_identity_pagetable_done))
4067                 goto out2;
4068
4069         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4070
4071         r = alloc_identity_pagetable(kvm);
4072         if (r < 0)
4073                 goto out2;
4074
4075         idx = srcu_read_lock(&kvm->srcu);
4076         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4077         if (r < 0)
4078                 goto out;
4079         /* Set up identity-mapping pagetable for EPT in real mode */
4080         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4081                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4082                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4083                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4084                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4085                 if (r < 0)
4086                         goto out;
4087         }
4088         kvm->arch.ept_identity_pagetable_done = true;
4089
4090 out:
4091         srcu_read_unlock(&kvm->srcu, idx);
4092
4093 out2:
4094         mutex_unlock(&kvm->slots_lock);
4095         return r;
4096 }
4097
4098 static void seg_setup(int seg)
4099 {
4100         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4101         unsigned int ar;
4102
4103         vmcs_write16(sf->selector, 0);
4104         vmcs_writel(sf->base, 0);
4105         vmcs_write32(sf->limit, 0xffff);
4106         ar = 0x93;
4107         if (seg == VCPU_SREG_CS)
4108                 ar |= 0x08; /* code segment */
4109
4110         vmcs_write32(sf->ar_bytes, ar);
4111 }
4112
4113 static int alloc_apic_access_page(struct kvm *kvm)
4114 {
4115         struct page *page;
4116         struct kvm_userspace_memory_region kvm_userspace_mem;
4117         int r = 0;
4118
4119         mutex_lock(&kvm->slots_lock);
4120         if (kvm->arch.apic_access_page_done)
4121                 goto out;
4122         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4123         kvm_userspace_mem.flags = 0;
4124         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4125         kvm_userspace_mem.memory_size = PAGE_SIZE;
4126         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4127         if (r)
4128                 goto out;
4129
4130         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4131         if (is_error_page(page)) {
4132                 r = -EFAULT;
4133                 goto out;
4134         }
4135
4136         /*
4137          * Do not pin the page in memory, so that memory hot-unplug
4138          * is able to migrate it.
4139          */
4140         put_page(page);
4141         kvm->arch.apic_access_page_done = true;
4142 out:
4143         mutex_unlock(&kvm->slots_lock);
4144         return r;
4145 }
4146
4147 static int alloc_identity_pagetable(struct kvm *kvm)
4148 {
4149         /* Called with kvm->slots_lock held. */
4150
4151         struct kvm_userspace_memory_region kvm_userspace_mem;
4152         int r = 0;
4153
4154         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4155
4156         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4157         kvm_userspace_mem.flags = 0;
4158         kvm_userspace_mem.guest_phys_addr =
4159                 kvm->arch.ept_identity_map_addr;
4160         kvm_userspace_mem.memory_size = PAGE_SIZE;
4161         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4162
4163         return r;
4164 }
4165
4166 static void allocate_vpid(struct vcpu_vmx *vmx)
4167 {
4168         int vpid;
4169
4170         vmx->vpid = 0;
4171         if (!enable_vpid)
4172                 return;
4173         spin_lock(&vmx_vpid_lock);
4174         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4175         if (vpid < VMX_NR_VPIDS) {
4176                 vmx->vpid = vpid;
4177                 __set_bit(vpid, vmx_vpid_bitmap);
4178         }
4179         spin_unlock(&vmx_vpid_lock);
4180 }
4181
4182 static void free_vpid(struct vcpu_vmx *vmx)
4183 {
4184         if (!enable_vpid)
4185                 return;
4186         spin_lock(&vmx_vpid_lock);
4187         if (vmx->vpid != 0)
4188                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4189         spin_unlock(&vmx_vpid_lock);
4190 }
4191
4192 #define MSR_TYPE_R      1
4193 #define MSR_TYPE_W      2
4194 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4195                                                 u32 msr, int type)
4196 {
4197         int f = sizeof(unsigned long);
4198
4199         if (!cpu_has_vmx_msr_bitmap())
4200                 return;
4201
4202         /*
4203          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4204          * have the write-low and read-high bitmap offsets the wrong way round.
4205          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4206          */
4207         if (msr <= 0x1fff) {
4208                 if (type & MSR_TYPE_R)
4209                         /* read-low */
4210                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4211
4212                 if (type & MSR_TYPE_W)
4213                         /* write-low */
4214                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4215
4216         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4217                 msr &= 0x1fff;
4218                 if (type & MSR_TYPE_R)
4219                         /* read-high */
4220                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4221
4222                 if (type & MSR_TYPE_W)
4223                         /* write-high */
4224                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4225
4226         }
4227 }
4228
4229 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4230                                                 u32 msr, int type)
4231 {
4232         int f = sizeof(unsigned long);
4233
4234         if (!cpu_has_vmx_msr_bitmap())
4235                 return;
4236
4237         /*
4238          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4239          * have the write-low and read-high bitmap offsets the wrong way round.
4240          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4241          */
4242         if (msr <= 0x1fff) {
4243                 if (type & MSR_TYPE_R)
4244                         /* read-low */
4245                         __set_bit(msr, msr_bitmap + 0x000 / f);
4246
4247                 if (type & MSR_TYPE_W)
4248                         /* write-low */
4249                         __set_bit(msr, msr_bitmap + 0x800 / f);
4250
4251         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4252                 msr &= 0x1fff;
4253                 if (type & MSR_TYPE_R)
4254                         /* read-high */
4255                         __set_bit(msr, msr_bitmap + 0x400 / f);
4256
4257                 if (type & MSR_TYPE_W)
4258                         /* write-high */
4259                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4260
4261         }
4262 }
4263
4264 /*
4265  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4266  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4267  */
4268 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4269                                                unsigned long *msr_bitmap_nested,
4270                                                u32 msr, int type)
4271 {
4272         int f = sizeof(unsigned long);
4273
4274         if (!cpu_has_vmx_msr_bitmap()) {
4275                 WARN_ON(1);
4276                 return;
4277         }
4278
4279         /*
4280          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4281          * have the write-low and read-high bitmap offsets the wrong way round.
4282          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4283          */
4284         if (msr <= 0x1fff) {
4285                 if (type & MSR_TYPE_R &&
4286                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4287                         /* read-low */
4288                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4289
4290                 if (type & MSR_TYPE_W &&
4291                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4292                         /* write-low */
4293                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4294
4295         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4296                 msr &= 0x1fff;
4297                 if (type & MSR_TYPE_R &&
4298                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4299                         /* read-high */
4300                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4301
4302                 if (type & MSR_TYPE_W &&
4303                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4304                         /* write-high */
4305                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4306
4307         }
4308 }
4309
4310 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4311 {
4312         if (!longmode_only)
4313                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4314                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4315         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4316                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4317 }
4318
4319 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4320 {
4321         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322                         msr, MSR_TYPE_R);
4323         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4324                         msr, MSR_TYPE_R);
4325 }
4326
4327 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4328 {
4329         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330                         msr, MSR_TYPE_R);
4331         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4332                         msr, MSR_TYPE_R);
4333 }
4334
4335 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4336 {
4337         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4338                         msr, MSR_TYPE_W);
4339         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4340                         msr, MSR_TYPE_W);
4341 }
4342
4343 static int vmx_vm_has_apicv(struct kvm *kvm)
4344 {
4345         return enable_apicv && irqchip_in_kernel(kvm);
4346 }
4347
4348 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4349 {
4350         struct vcpu_vmx *vmx = to_vmx(vcpu);
4351         int max_irr;
4352         void *vapic_page;
4353         u16 status;
4354
4355         if (vmx->nested.pi_desc &&
4356             vmx->nested.pi_pending) {
4357                 vmx->nested.pi_pending = false;
4358                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4359                         return 0;
4360
4361                 max_irr = find_last_bit(
4362                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4363
4364                 if (max_irr == 256)
4365                         return 0;
4366
4367                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4368                 if (!vapic_page) {
4369                         WARN_ON(1);
4370                         return -ENOMEM;
4371                 }
4372                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4373                 kunmap(vmx->nested.virtual_apic_page);
4374
4375                 status = vmcs_read16(GUEST_INTR_STATUS);
4376                 if ((u8)max_irr > ((u8)status & 0xff)) {
4377                         status &= ~0xff;
4378                         status |= (u8)max_irr;
4379                         vmcs_write16(GUEST_INTR_STATUS, status);
4380                 }
4381         }
4382         return 0;
4383 }
4384
4385 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4386 {
4387 #ifdef CONFIG_SMP
4388         if (vcpu->mode == IN_GUEST_MODE) {
4389                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4390                                 POSTED_INTR_VECTOR);
4391                 return true;
4392         }
4393 #endif
4394         return false;
4395 }
4396
4397 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4398                                                 int vector)
4399 {
4400         struct vcpu_vmx *vmx = to_vmx(vcpu);
4401
4402         if (is_guest_mode(vcpu) &&
4403             vector == vmx->nested.posted_intr_nv) {
4404                 /* the PIR and ON have been set by L1. */
4405                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4406                 /*
4407                  * If a posted intr is not recognized by hardware,
4408                  * we will accomplish it in the next vmentry.
4409                  */
4410                 vmx->nested.pi_pending = true;
4411                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4412                 return 0;
4413         }
4414         return -1;
4415 }
4416 /*
4417  * Send interrupt to vcpu via posted interrupt way.
4418  * 1. If target vcpu is running(non-root mode), send posted interrupt
4419  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4420  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4421  * interrupt from PIR in next vmentry.
4422  */
4423 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4424 {
4425         struct vcpu_vmx *vmx = to_vmx(vcpu);
4426         int r;
4427
4428         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4429         if (!r)
4430                 return;
4431
4432         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4433                 return;
4434
4435         r = pi_test_and_set_on(&vmx->pi_desc);
4436         kvm_make_request(KVM_REQ_EVENT, vcpu);
4437         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4438                 kvm_vcpu_kick(vcpu);
4439 }
4440
4441 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4442 {
4443         struct vcpu_vmx *vmx = to_vmx(vcpu);
4444
4445         if (!pi_test_and_clear_on(&vmx->pi_desc))
4446                 return;
4447
4448         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4449 }
4450
4451 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4452 {
4453         return;
4454 }
4455
4456 /*
4457  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4458  * will not change in the lifetime of the guest.
4459  * Note that host-state that does change is set elsewhere. E.g., host-state
4460  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4461  */
4462 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4463 {
4464         u32 low32, high32;
4465         unsigned long tmpl;
4466         struct desc_ptr dt;
4467         unsigned long cr4;
4468
4469         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4470         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4471
4472         /* Save the most likely value for this task's CR4 in the VMCS. */
4473         cr4 = cr4_read_shadow();
4474         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4475         vmx->host_state.vmcs_host_cr4 = cr4;
4476
4477         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4478 #ifdef CONFIG_X86_64
4479         /*
4480          * Load null selectors, so we can avoid reloading them in
4481          * __vmx_load_host_state(), in case userspace uses the null selectors
4482          * too (the expected case).
4483          */
4484         vmcs_write16(HOST_DS_SELECTOR, 0);
4485         vmcs_write16(HOST_ES_SELECTOR, 0);
4486 #else
4487         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4488         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4489 #endif
4490         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4491         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4492
4493         native_store_idt(&dt);
4494         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4495         vmx->host_idt_base = dt.address;
4496
4497         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4498
4499         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4500         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4501         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4502         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4503
4504         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4505                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4506                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4507         }
4508 }
4509
4510 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4511 {
4512         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4513         if (enable_ept)
4514                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4515         if (is_guest_mode(&vmx->vcpu))
4516                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4517                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4518         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4519 }
4520
4521 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4522 {
4523         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4524
4525         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4526                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4527         return pin_based_exec_ctrl;
4528 }
4529
4530 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4531 {
4532         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4533
4534         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4535                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4536
4537         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4538                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4539 #ifdef CONFIG_X86_64
4540                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4541                                 CPU_BASED_CR8_LOAD_EXITING;
4542 #endif
4543         }
4544         if (!enable_ept)
4545                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4546                                 CPU_BASED_CR3_LOAD_EXITING  |
4547                                 CPU_BASED_INVLPG_EXITING;
4548         return exec_control;
4549 }
4550
4551 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4552 {
4553         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4554         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4555                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4556         if (vmx->vpid == 0)
4557                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4558         if (!enable_ept) {
4559                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4560                 enable_unrestricted_guest = 0;
4561                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4562                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4563         }
4564         if (!enable_unrestricted_guest)
4565                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4566         if (!ple_gap)
4567                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4568         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4569                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4570                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4571         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4572         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4573            (handle_vmptrld).
4574            We can NOT enable shadow_vmcs here because we don't have yet
4575            a current VMCS12
4576         */
4577         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4578         /* PML is enabled/disabled in creating/destorying vcpu */
4579         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4580
4581         return exec_control;
4582 }
4583
4584 static void ept_set_mmio_spte_mask(void)
4585 {
4586         /*
4587          * EPT Misconfigurations can be generated if the value of bits 2:0
4588          * of an EPT paging-structure entry is 110b (write/execute).
4589          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4590          * spte.
4591          */
4592         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4593 }
4594
4595 #define VMX_XSS_EXIT_BITMAP 0
4596 /*
4597  * Sets up the vmcs for emulated real mode.
4598  */
4599 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4600 {
4601 #ifdef CONFIG_X86_64
4602         unsigned long a;
4603 #endif
4604         int i;
4605
4606         /* I/O */
4607         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4608         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4609
4610         if (enable_shadow_vmcs) {
4611                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4612                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4613         }
4614         if (cpu_has_vmx_msr_bitmap())
4615                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4616
4617         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4618
4619         /* Control */
4620         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4621
4622         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4623
4624         if (cpu_has_secondary_exec_ctrls()) {
4625                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4626                                 vmx_secondary_exec_control(vmx));
4627         }
4628
4629         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4630                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4631                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4632                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4633                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4634
4635                 vmcs_write16(GUEST_INTR_STATUS, 0);
4636
4637                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4638                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4639         }
4640
4641         if (ple_gap) {
4642                 vmcs_write32(PLE_GAP, ple_gap);
4643                 vmx->ple_window = ple_window;
4644                 vmx->ple_window_dirty = true;
4645         }
4646
4647         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4648         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4649         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4650
4651         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4652         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4653         vmx_set_constant_host_state(vmx);
4654 #ifdef CONFIG_X86_64
4655         rdmsrl(MSR_FS_BASE, a);
4656         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4657         rdmsrl(MSR_GS_BASE, a);
4658         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4659 #else
4660         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4661         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4662 #endif
4663
4664         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4665         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4666         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4667         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4668         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4669
4670         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4671                 u32 msr_low, msr_high;
4672                 u64 host_pat;
4673                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4674                 host_pat = msr_low | ((u64) msr_high << 32);
4675                 /* Write the default value follow host pat */
4676                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4677                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4678                 vmx->vcpu.arch.pat = host_pat;
4679         }
4680
4681         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4682                 u32 index = vmx_msr_index[i];
4683                 u32 data_low, data_high;
4684                 int j = vmx->nmsrs;
4685
4686                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4687                         continue;
4688                 if (wrmsr_safe(index, data_low, data_high) < 0)
4689                         continue;
4690                 vmx->guest_msrs[j].index = i;
4691                 vmx->guest_msrs[j].data = 0;
4692                 vmx->guest_msrs[j].mask = -1ull;
4693                 ++vmx->nmsrs;
4694         }
4695
4696
4697         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4698
4699         /* 22.2.1, 20.8.1 */
4700         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4701
4702         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4703         set_cr4_guest_host_mask(vmx);
4704
4705         if (vmx_xsaves_supported())
4706                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4707
4708         return 0;
4709 }
4710
4711 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4712 {
4713         struct vcpu_vmx *vmx = to_vmx(vcpu);
4714         struct msr_data apic_base_msr;
4715
4716         vmx->rmode.vm86_active = 0;
4717
4718         vmx->soft_vnmi_blocked = 0;
4719
4720         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4721         kvm_set_cr8(&vmx->vcpu, 0);
4722         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4723         if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4724                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4725         apic_base_msr.host_initiated = true;
4726         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4727
4728         vmx_segment_cache_clear(vmx);
4729
4730         seg_setup(VCPU_SREG_CS);
4731         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4732         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4733
4734         seg_setup(VCPU_SREG_DS);
4735         seg_setup(VCPU_SREG_ES);
4736         seg_setup(VCPU_SREG_FS);
4737         seg_setup(VCPU_SREG_GS);
4738         seg_setup(VCPU_SREG_SS);
4739
4740         vmcs_write16(GUEST_TR_SELECTOR, 0);
4741         vmcs_writel(GUEST_TR_BASE, 0);
4742         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4743         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4744
4745         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4746         vmcs_writel(GUEST_LDTR_BASE, 0);
4747         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4748         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4749
4750         vmcs_write32(GUEST_SYSENTER_CS, 0);
4751         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4752         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4753
4754         vmcs_writel(GUEST_RFLAGS, 0x02);
4755         kvm_rip_write(vcpu, 0xfff0);
4756
4757         vmcs_writel(GUEST_GDTR_BASE, 0);
4758         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4759
4760         vmcs_writel(GUEST_IDTR_BASE, 0);
4761         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4762
4763         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4764         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4765         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4766
4767         /* Special registers */
4768         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4769
4770         setup_msrs(vmx);
4771
4772         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4773
4774         if (cpu_has_vmx_tpr_shadow()) {
4775                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4776                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4777                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4778                                      __pa(vmx->vcpu.arch.apic->regs));
4779                 vmcs_write32(TPR_THRESHOLD, 0);
4780         }
4781
4782         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4783
4784         if (vmx_vm_has_apicv(vcpu->kvm))
4785                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4786
4787         if (vmx->vpid != 0)
4788                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4789
4790         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4791         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4792         vmx_set_cr4(&vmx->vcpu, 0);
4793         vmx_set_efer(&vmx->vcpu, 0);
4794         vmx_fpu_activate(&vmx->vcpu);
4795         update_exception_bitmap(&vmx->vcpu);
4796
4797         vpid_sync_context(vmx);
4798 }
4799
4800 /*
4801  * In nested virtualization, check if L1 asked to exit on external interrupts.
4802  * For most existing hypervisors, this will always return true.
4803  */
4804 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4805 {
4806         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4807                 PIN_BASED_EXT_INTR_MASK;
4808 }
4809
4810 /*
4811  * In nested virtualization, check if L1 has set
4812  * VM_EXIT_ACK_INTR_ON_EXIT
4813  */
4814 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4815 {
4816         return get_vmcs12(vcpu)->vm_exit_controls &
4817                 VM_EXIT_ACK_INTR_ON_EXIT;
4818 }
4819
4820 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4821 {
4822         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4823                 PIN_BASED_NMI_EXITING;
4824 }
4825
4826 static void enable_irq_window(struct kvm_vcpu *vcpu)
4827 {
4828         u32 cpu_based_vm_exec_control;
4829
4830         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4831         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4832         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4833 }
4834
4835 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4836 {
4837         u32 cpu_based_vm_exec_control;
4838
4839         if (!cpu_has_virtual_nmis() ||
4840             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4841                 enable_irq_window(vcpu);
4842                 return;
4843         }
4844
4845         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4846         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4847         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4848 }
4849
4850 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4851 {
4852         struct vcpu_vmx *vmx = to_vmx(vcpu);
4853         uint32_t intr;
4854         int irq = vcpu->arch.interrupt.nr;
4855
4856         trace_kvm_inj_virq(irq);
4857
4858         ++vcpu->stat.irq_injections;
4859         if (vmx->rmode.vm86_active) {
4860                 int inc_eip = 0;
4861                 if (vcpu->arch.interrupt.soft)
4862                         inc_eip = vcpu->arch.event_exit_inst_len;
4863                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4864                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4865                 return;
4866         }
4867         intr = irq | INTR_INFO_VALID_MASK;
4868         if (vcpu->arch.interrupt.soft) {
4869                 intr |= INTR_TYPE_SOFT_INTR;
4870                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4871                              vmx->vcpu.arch.event_exit_inst_len);
4872         } else
4873                 intr |= INTR_TYPE_EXT_INTR;
4874         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4875 }
4876
4877 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4878 {
4879         struct vcpu_vmx *vmx = to_vmx(vcpu);
4880
4881         if (is_guest_mode(vcpu))
4882                 return;
4883
4884         if (!cpu_has_virtual_nmis()) {
4885                 /*
4886                  * Tracking the NMI-blocked state in software is built upon
4887                  * finding the next open IRQ window. This, in turn, depends on
4888                  * well-behaving guests: They have to keep IRQs disabled at
4889                  * least as long as the NMI handler runs. Otherwise we may
4890                  * cause NMI nesting, maybe breaking the guest. But as this is
4891                  * highly unlikely, we can live with the residual risk.
4892                  */
4893                 vmx->soft_vnmi_blocked = 1;
4894                 vmx->vnmi_blocked_time = 0;
4895         }
4896
4897         ++vcpu->stat.nmi_injections;
4898         vmx->nmi_known_unmasked = false;
4899         if (vmx->rmode.vm86_active) {
4900                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4901                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4902                 return;
4903         }
4904         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4905                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4906 }
4907
4908 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4909 {
4910         if (!cpu_has_virtual_nmis())
4911                 return to_vmx(vcpu)->soft_vnmi_blocked;
4912         if (to_vmx(vcpu)->nmi_known_unmasked)
4913                 return false;
4914         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4915 }
4916
4917 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4918 {
4919         struct vcpu_vmx *vmx = to_vmx(vcpu);
4920
4921         if (!cpu_has_virtual_nmis()) {
4922                 if (vmx->soft_vnmi_blocked != masked) {
4923                         vmx->soft_vnmi_blocked = masked;
4924                         vmx->vnmi_blocked_time = 0;
4925                 }
4926         } else {
4927                 vmx->nmi_known_unmasked = !masked;
4928                 if (masked)
4929                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4930                                       GUEST_INTR_STATE_NMI);
4931                 else
4932                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4933                                         GUEST_INTR_STATE_NMI);
4934         }
4935 }
4936
4937 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4938 {
4939         if (to_vmx(vcpu)->nested.nested_run_pending)
4940                 return 0;
4941
4942         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4943                 return 0;
4944
4945         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4946                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4947                    | GUEST_INTR_STATE_NMI));
4948 }
4949
4950 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4951 {
4952         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4953                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4954                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4955                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4956 }
4957
4958 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4959 {
4960         int ret;
4961         struct kvm_userspace_memory_region tss_mem = {
4962                 .slot = TSS_PRIVATE_MEMSLOT,
4963                 .guest_phys_addr = addr,
4964                 .memory_size = PAGE_SIZE * 3,
4965                 .flags = 0,
4966         };
4967
4968         ret = kvm_set_memory_region(kvm, &tss_mem);
4969         if (ret)
4970                 return ret;
4971         kvm->arch.tss_addr = addr;
4972         return init_rmode_tss(kvm);
4973 }
4974
4975 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4976 {
4977         switch (vec) {
4978         case BP_VECTOR:
4979                 /*
4980                  * Update instruction length as we may reinject the exception
4981                  * from user space while in guest debugging mode.
4982                  */
4983                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4984                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4985                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4986                         return false;
4987                 /* fall through */
4988         case DB_VECTOR:
4989                 if (vcpu->guest_debug &
4990                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4991                         return false;
4992                 /* fall through */
4993         case DE_VECTOR:
4994         case OF_VECTOR:
4995         case BR_VECTOR:
4996         case UD_VECTOR:
4997         case DF_VECTOR:
4998         case SS_VECTOR:
4999         case GP_VECTOR:
5000         case MF_VECTOR:
5001                 return true;
5002         break;
5003         }
5004         return false;
5005 }
5006
5007 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5008                                   int vec, u32 err_code)
5009 {
5010         /*
5011          * Instruction with address size override prefix opcode 0x67
5012          * Cause the #SS fault with 0 error code in VM86 mode.
5013          */
5014         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5015                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5016                         if (vcpu->arch.halt_request) {
5017                                 vcpu->arch.halt_request = 0;
5018                                 return kvm_vcpu_halt(vcpu);
5019                         }
5020                         return 1;
5021                 }
5022                 return 0;
5023         }
5024
5025         /*
5026          * Forward all other exceptions that are valid in real mode.
5027          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5028          *        the required debugging infrastructure rework.
5029          */
5030         kvm_queue_exception(vcpu, vec);
5031         return 1;
5032 }
5033
5034 /*
5035  * Trigger machine check on the host. We assume all the MSRs are already set up
5036  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5037  * We pass a fake environment to the machine check handler because we want
5038  * the guest to be always treated like user space, no matter what context
5039  * it used internally.
5040  */
5041 static void kvm_machine_check(void)
5042 {
5043 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5044         struct pt_regs regs = {
5045                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5046                 .flags = X86_EFLAGS_IF,
5047         };
5048
5049         do_machine_check(&regs, 0);
5050 #endif
5051 }
5052
5053 static int handle_machine_check(struct kvm_vcpu *vcpu)
5054 {
5055         /* already handled by vcpu_run */
5056         return 1;
5057 }
5058
5059 static int handle_exception(struct kvm_vcpu *vcpu)
5060 {
5061         struct vcpu_vmx *vmx = to_vmx(vcpu);
5062         struct kvm_run *kvm_run = vcpu->run;
5063         u32 intr_info, ex_no, error_code;
5064         unsigned long cr2, rip, dr6;
5065         u32 vect_info;
5066         enum emulation_result er;
5067
5068         vect_info = vmx->idt_vectoring_info;
5069         intr_info = vmx->exit_intr_info;
5070
5071         if (is_machine_check(intr_info))
5072                 return handle_machine_check(vcpu);
5073
5074         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5075                 return 1;  /* already handled by vmx_vcpu_run() */
5076
5077         if (is_no_device(intr_info)) {
5078                 vmx_fpu_activate(vcpu);
5079                 return 1;
5080         }
5081
5082         if (is_invalid_opcode(intr_info)) {
5083                 if (is_guest_mode(vcpu)) {
5084                         kvm_queue_exception(vcpu, UD_VECTOR);
5085                         return 1;
5086                 }
5087                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5088                 if (er != EMULATE_DONE)
5089                         kvm_queue_exception(vcpu, UD_VECTOR);
5090                 return 1;
5091         }
5092
5093         error_code = 0;
5094         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5095                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5096
5097         /*
5098          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5099          * MMIO, it is better to report an internal error.
5100          * See the comments in vmx_handle_exit.
5101          */
5102         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5103             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5104                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5105                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5106                 vcpu->run->internal.ndata = 3;
5107                 vcpu->run->internal.data[0] = vect_info;
5108                 vcpu->run->internal.data[1] = intr_info;
5109                 vcpu->run->internal.data[2] = error_code;
5110                 return 0;
5111         }
5112
5113         if (is_page_fault(intr_info)) {
5114                 /* EPT won't cause page fault directly */
5115                 BUG_ON(enable_ept);
5116                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5117                 trace_kvm_page_fault(cr2, error_code);
5118
5119                 if (kvm_event_needs_reinjection(vcpu))
5120                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5121                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5122         }
5123
5124         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5125
5126         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5127                 return handle_rmode_exception(vcpu, ex_no, error_code);
5128
5129         switch (ex_no) {
5130         case DB_VECTOR:
5131                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5132                 if (!(vcpu->guest_debug &
5133                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5134                         vcpu->arch.dr6 &= ~15;
5135                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5136                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5137                                 skip_emulated_instruction(vcpu);
5138
5139                         kvm_queue_exception(vcpu, DB_VECTOR);
5140                         return 1;
5141                 }
5142                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5143                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5144                 /* fall through */
5145         case BP_VECTOR:
5146                 /*
5147                  * Update instruction length as we may reinject #BP from
5148                  * user space while in guest debugging mode. Reading it for
5149                  * #DB as well causes no harm, it is not used in that case.
5150                  */
5151                 vmx->vcpu.arch.event_exit_inst_len =
5152                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5153                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5154                 rip = kvm_rip_read(vcpu);
5155                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5156                 kvm_run->debug.arch.exception = ex_no;
5157                 break;
5158         default:
5159                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5160                 kvm_run->ex.exception = ex_no;
5161                 kvm_run->ex.error_code = error_code;
5162                 break;
5163         }
5164         return 0;
5165 }
5166
5167 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5168 {
5169         ++vcpu->stat.irq_exits;
5170         return 1;
5171 }
5172
5173 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5174 {
5175         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5176         return 0;
5177 }
5178
5179 static int handle_io(struct kvm_vcpu *vcpu)
5180 {
5181         unsigned long exit_qualification;
5182         int size, in, string;
5183         unsigned port;
5184
5185         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5186         string = (exit_qualification & 16) != 0;
5187         in = (exit_qualification & 8) != 0;
5188
5189         ++vcpu->stat.io_exits;
5190
5191         if (string || in)
5192                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5193
5194         port = exit_qualification >> 16;
5195         size = (exit_qualification & 7) + 1;
5196         skip_emulated_instruction(vcpu);
5197
5198         return kvm_fast_pio_out(vcpu, size, port);
5199 }
5200
5201 static void
5202 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5203 {
5204         /*
5205          * Patch in the VMCALL instruction:
5206          */
5207         hypercall[0] = 0x0f;
5208         hypercall[1] = 0x01;
5209         hypercall[2] = 0xc1;
5210 }
5211
5212 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5213 {
5214         unsigned long always_on = VMXON_CR0_ALWAYSON;
5215         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5216
5217         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5218                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5219             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5220                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5221         return (val & always_on) == always_on;
5222 }
5223
5224 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5225 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5226 {
5227         if (is_guest_mode(vcpu)) {
5228                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5229                 unsigned long orig_val = val;
5230
5231                 /*
5232                  * We get here when L2 changed cr0 in a way that did not change
5233                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5234                  * but did change L0 shadowed bits. So we first calculate the
5235                  * effective cr0 value that L1 would like to write into the
5236                  * hardware. It consists of the L2-owned bits from the new
5237                  * value combined with the L1-owned bits from L1's guest_cr0.
5238                  */
5239                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5240                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5241
5242                 if (!nested_cr0_valid(vcpu, val))
5243                         return 1;
5244
5245                 if (kvm_set_cr0(vcpu, val))
5246                         return 1;
5247                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5248                 return 0;
5249         } else {
5250                 if (to_vmx(vcpu)->nested.vmxon &&
5251                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5252                         return 1;
5253                 return kvm_set_cr0(vcpu, val);
5254         }
5255 }
5256
5257 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5258 {
5259         if (is_guest_mode(vcpu)) {
5260                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5261                 unsigned long orig_val = val;
5262
5263                 /* analogously to handle_set_cr0 */
5264                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5265                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5266                 if (kvm_set_cr4(vcpu, val))
5267                         return 1;
5268                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5269                 return 0;
5270         } else
5271                 return kvm_set_cr4(vcpu, val);
5272 }
5273
5274 /* called to set cr0 as approriate for clts instruction exit. */
5275 static void handle_clts(struct kvm_vcpu *vcpu)
5276 {
5277         if (is_guest_mode(vcpu)) {
5278                 /*
5279                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5280                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5281                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5282                  */
5283                 vmcs_writel(CR0_READ_SHADOW,
5284                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5285                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5286         } else
5287                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5288 }
5289
5290 static int handle_cr(struct kvm_vcpu *vcpu)
5291 {
5292         unsigned long exit_qualification, val;
5293         int cr;
5294         int reg;
5295         int err;
5296
5297         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5298         cr = exit_qualification & 15;
5299         reg = (exit_qualification >> 8) & 15;
5300         switch ((exit_qualification >> 4) & 3) {
5301         case 0: /* mov to cr */
5302                 val = kvm_register_readl(vcpu, reg);
5303                 trace_kvm_cr_write(cr, val);
5304                 switch (cr) {
5305                 case 0:
5306                         err = handle_set_cr0(vcpu, val);
5307                         kvm_complete_insn_gp(vcpu, err);
5308                         return 1;
5309                 case 3:
5310                         err = kvm_set_cr3(vcpu, val);
5311                         kvm_complete_insn_gp(vcpu, err);
5312                         return 1;
5313                 case 4:
5314                         err = handle_set_cr4(vcpu, val);
5315                         kvm_complete_insn_gp(vcpu, err);
5316                         return 1;
5317                 case 8: {
5318                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5319                                 u8 cr8 = (u8)val;
5320                                 err = kvm_set_cr8(vcpu, cr8);
5321                                 kvm_complete_insn_gp(vcpu, err);
5322                                 if (irqchip_in_kernel(vcpu->kvm))
5323                                         return 1;
5324                                 if (cr8_prev <= cr8)
5325                                         return 1;
5326                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5327                                 return 0;
5328                         }
5329                 }
5330                 break;
5331         case 2: /* clts */
5332                 handle_clts(vcpu);
5333                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5334                 skip_emulated_instruction(vcpu);
5335                 vmx_fpu_activate(vcpu);
5336                 return 1;
5337         case 1: /*mov from cr*/
5338                 switch (cr) {
5339                 case 3:
5340                         val = kvm_read_cr3(vcpu);
5341                         kvm_register_write(vcpu, reg, val);
5342                         trace_kvm_cr_read(cr, val);
5343                         skip_emulated_instruction(vcpu);
5344                         return 1;
5345                 case 8:
5346                         val = kvm_get_cr8(vcpu);
5347                         kvm_register_write(vcpu, reg, val);
5348                         trace_kvm_cr_read(cr, val);
5349                         skip_emulated_instruction(vcpu);
5350                         return 1;
5351                 }
5352                 break;
5353         case 3: /* lmsw */
5354                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5355                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5356                 kvm_lmsw(vcpu, val);
5357
5358                 skip_emulated_instruction(vcpu);
5359                 return 1;
5360         default:
5361                 break;
5362         }
5363         vcpu->run->exit_reason = 0;
5364         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5365                (int)(exit_qualification >> 4) & 3, cr);
5366         return 0;
5367 }
5368
5369 static int handle_dr(struct kvm_vcpu *vcpu)
5370 {
5371         unsigned long exit_qualification;
5372         int dr, dr7, reg;
5373
5374         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5375         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5376
5377         /* First, if DR does not exist, trigger UD */
5378         if (!kvm_require_dr(vcpu, dr))
5379                 return 1;
5380
5381         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5382         if (!kvm_require_cpl(vcpu, 0))
5383                 return 1;
5384         dr7 = vmcs_readl(GUEST_DR7);
5385         if (dr7 & DR7_GD) {
5386                 /*
5387                  * As the vm-exit takes precedence over the debug trap, we
5388                  * need to emulate the latter, either for the host or the
5389                  * guest debugging itself.
5390                  */
5391                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5392                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5393                         vcpu->run->debug.arch.dr7 = dr7;
5394                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5395                         vcpu->run->debug.arch.exception = DB_VECTOR;
5396                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5397                         return 0;
5398                 } else {
5399                         vcpu->arch.dr6 &= ~15;
5400                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5401                         kvm_queue_exception(vcpu, DB_VECTOR);
5402                         return 1;
5403                 }
5404         }
5405
5406         if (vcpu->guest_debug == 0) {
5407                 u32 cpu_based_vm_exec_control;
5408
5409                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5410                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5411                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5412
5413                 /*
5414                  * No more DR vmexits; force a reload of the debug registers
5415                  * and reenter on this instruction.  The next vmexit will
5416                  * retrieve the full state of the debug registers.
5417                  */
5418                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5419                 return 1;
5420         }
5421
5422         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5423         if (exit_qualification & TYPE_MOV_FROM_DR) {
5424                 unsigned long val;
5425
5426                 if (kvm_get_dr(vcpu, dr, &val))
5427                         return 1;
5428                 kvm_register_write(vcpu, reg, val);
5429         } else
5430                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5431                         return 1;
5432
5433         skip_emulated_instruction(vcpu);
5434         return 1;
5435 }
5436
5437 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5438 {
5439         return vcpu->arch.dr6;
5440 }
5441
5442 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5443 {
5444 }
5445
5446 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5447 {
5448         u32 cpu_based_vm_exec_control;
5449
5450         get_debugreg(vcpu->arch.db[0], 0);
5451         get_debugreg(vcpu->arch.db[1], 1);
5452         get_debugreg(vcpu->arch.db[2], 2);
5453         get_debugreg(vcpu->arch.db[3], 3);
5454         get_debugreg(vcpu->arch.dr6, 6);
5455         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5456
5457         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5458
5459         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5460         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5461         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5462 }
5463
5464 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5465 {
5466         vmcs_writel(GUEST_DR7, val);
5467 }
5468
5469 static int handle_cpuid(struct kvm_vcpu *vcpu)
5470 {
5471         kvm_emulate_cpuid(vcpu);
5472         return 1;
5473 }
5474
5475 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5476 {
5477         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5478         u64 data;
5479
5480         if (vmx_get_msr(vcpu, ecx, &data)) {
5481                 trace_kvm_msr_read_ex(ecx);
5482                 kvm_inject_gp(vcpu, 0);
5483                 return 1;
5484         }
5485
5486         trace_kvm_msr_read(ecx, data);
5487
5488         /* FIXME: handling of bits 32:63 of rax, rdx */
5489         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5490         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5491         skip_emulated_instruction(vcpu);
5492         return 1;
5493 }
5494
5495 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5496 {
5497         struct msr_data msr;
5498         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5499         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5500                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5501
5502         msr.data = data;
5503         msr.index = ecx;
5504         msr.host_initiated = false;
5505         if (kvm_set_msr(vcpu, &msr) != 0) {
5506                 trace_kvm_msr_write_ex(ecx, data);
5507                 kvm_inject_gp(vcpu, 0);
5508                 return 1;
5509         }
5510
5511         trace_kvm_msr_write(ecx, data);
5512         skip_emulated_instruction(vcpu);
5513         return 1;
5514 }
5515
5516 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5517 {
5518         kvm_make_request(KVM_REQ_EVENT, vcpu);
5519         return 1;
5520 }
5521
5522 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5523 {
5524         u32 cpu_based_vm_exec_control;
5525
5526         /* clear pending irq */
5527         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5528         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5529         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5530
5531         kvm_make_request(KVM_REQ_EVENT, vcpu);
5532
5533         ++vcpu->stat.irq_window_exits;
5534
5535         /*
5536          * If the user space waits to inject interrupts, exit as soon as
5537          * possible
5538          */
5539         if (!irqchip_in_kernel(vcpu->kvm) &&
5540             vcpu->run->request_interrupt_window &&
5541             !kvm_cpu_has_interrupt(vcpu)) {
5542                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5543                 return 0;
5544         }
5545         return 1;
5546 }
5547
5548 static int handle_halt(struct kvm_vcpu *vcpu)
5549 {
5550         return kvm_emulate_halt(vcpu);
5551 }
5552
5553 static int handle_vmcall(struct kvm_vcpu *vcpu)
5554 {
5555         kvm_emulate_hypercall(vcpu);
5556         return 1;
5557 }
5558
5559 static int handle_invd(struct kvm_vcpu *vcpu)
5560 {
5561         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5562 }
5563
5564 static int handle_invlpg(struct kvm_vcpu *vcpu)
5565 {
5566         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5567
5568         kvm_mmu_invlpg(vcpu, exit_qualification);
5569         skip_emulated_instruction(vcpu);
5570         return 1;
5571 }
5572
5573 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5574 {
5575         int err;
5576
5577         err = kvm_rdpmc(vcpu);
5578         kvm_complete_insn_gp(vcpu, err);
5579
5580         return 1;
5581 }
5582
5583 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5584 {
5585         kvm_emulate_wbinvd(vcpu);
5586         return 1;
5587 }
5588
5589 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5590 {
5591         u64 new_bv = kvm_read_edx_eax(vcpu);
5592         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5593
5594         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5595                 skip_emulated_instruction(vcpu);
5596         return 1;
5597 }
5598
5599 static int handle_xsaves(struct kvm_vcpu *vcpu)
5600 {
5601         skip_emulated_instruction(vcpu);
5602         WARN(1, "this should never happen\n");
5603         return 1;
5604 }
5605
5606 static int handle_xrstors(struct kvm_vcpu *vcpu)
5607 {
5608         skip_emulated_instruction(vcpu);
5609         WARN(1, "this should never happen\n");
5610         return 1;
5611 }
5612
5613 static int handle_apic_access(struct kvm_vcpu *vcpu)
5614 {
5615         if (likely(fasteoi)) {
5616                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5617                 int access_type, offset;
5618
5619                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5620                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5621                 /*
5622                  * Sane guest uses MOV to write EOI, with written value
5623                  * not cared. So make a short-circuit here by avoiding
5624                  * heavy instruction emulation.
5625                  */
5626                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5627                     (offset == APIC_EOI)) {
5628                         kvm_lapic_set_eoi(vcpu);
5629                         skip_emulated_instruction(vcpu);
5630                         return 1;
5631                 }
5632         }
5633         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5634 }
5635
5636 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5637 {
5638         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5639         int vector = exit_qualification & 0xff;
5640
5641         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5642         kvm_apic_set_eoi_accelerated(vcpu, vector);
5643         return 1;
5644 }
5645
5646 static int handle_apic_write(struct kvm_vcpu *vcpu)
5647 {
5648         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5649         u32 offset = exit_qualification & 0xfff;
5650
5651         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5652         kvm_apic_write_nodecode(vcpu, offset);
5653         return 1;
5654 }
5655
5656 static int handle_task_switch(struct kvm_vcpu *vcpu)
5657 {
5658         struct vcpu_vmx *vmx = to_vmx(vcpu);
5659         unsigned long exit_qualification;
5660         bool has_error_code = false;
5661         u32 error_code = 0;
5662         u16 tss_selector;
5663         int reason, type, idt_v, idt_index;
5664
5665         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5666         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5667         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5668
5669         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5670
5671         reason = (u32)exit_qualification >> 30;
5672         if (reason == TASK_SWITCH_GATE && idt_v) {
5673                 switch (type) {
5674                 case INTR_TYPE_NMI_INTR:
5675                         vcpu->arch.nmi_injected = false;
5676                         vmx_set_nmi_mask(vcpu, true);
5677                         break;
5678                 case INTR_TYPE_EXT_INTR:
5679                 case INTR_TYPE_SOFT_INTR:
5680                         kvm_clear_interrupt_queue(vcpu);
5681                         break;
5682                 case INTR_TYPE_HARD_EXCEPTION:
5683                         if (vmx->idt_vectoring_info &
5684                             VECTORING_INFO_DELIVER_CODE_MASK) {
5685                                 has_error_code = true;
5686                                 error_code =
5687                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5688                         }
5689                         /* fall through */
5690                 case INTR_TYPE_SOFT_EXCEPTION:
5691                         kvm_clear_exception_queue(vcpu);
5692                         break;
5693                 default:
5694                         break;
5695                 }
5696         }
5697         tss_selector = exit_qualification;
5698
5699         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5700                        type != INTR_TYPE_EXT_INTR &&
5701                        type != INTR_TYPE_NMI_INTR))
5702                 skip_emulated_instruction(vcpu);
5703
5704         if (kvm_task_switch(vcpu, tss_selector,
5705                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5706                             has_error_code, error_code) == EMULATE_FAIL) {
5707                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5708                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5709                 vcpu->run->internal.ndata = 0;
5710                 return 0;
5711         }
5712
5713         /* clear all local breakpoint enable flags */
5714         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5715
5716         /*
5717          * TODO: What about debug traps on tss switch?
5718          *       Are we supposed to inject them and update dr6?
5719          */
5720
5721         return 1;
5722 }
5723
5724 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5725 {
5726         unsigned long exit_qualification;
5727         gpa_t gpa;
5728         u32 error_code;
5729         int gla_validity;
5730
5731         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5732
5733         gla_validity = (exit_qualification >> 7) & 0x3;
5734         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5735                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5736                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5737                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5738                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5739                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5740                         (long unsigned int)exit_qualification);
5741                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5742                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5743                 return 0;
5744         }
5745
5746         /*
5747          * EPT violation happened while executing iret from NMI,
5748          * "blocked by NMI" bit has to be set before next VM entry.
5749          * There are errata that may cause this bit to not be set:
5750          * AAK134, BY25.
5751          */
5752         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5753                         cpu_has_virtual_nmis() &&
5754                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5755                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5756
5757         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5758         trace_kvm_page_fault(gpa, exit_qualification);
5759
5760         /* It is a write fault? */
5761         error_code = exit_qualification & PFERR_WRITE_MASK;
5762         /* It is a fetch fault? */
5763         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5764         /* ept page table is present? */
5765         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5766
5767         vcpu->arch.exit_qualification = exit_qualification;
5768
5769         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5770 }
5771
5772 static u64 ept_rsvd_mask(u64 spte, int level)
5773 {
5774         int i;
5775         u64 mask = 0;
5776
5777         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5778                 mask |= (1ULL << i);
5779
5780         if (level == 4)
5781                 /* bits 7:3 reserved */
5782                 mask |= 0xf8;
5783         else if (spte & (1ULL << 7))
5784                 /*
5785                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5786                  * level == 1 if the hypervisor is using the ignored bit 7.
5787                  */
5788                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5789         else if (level > 1)
5790                 /* bits 6:3 reserved */
5791                 mask |= 0x78;
5792
5793         return mask;
5794 }
5795
5796 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5797                                        int level)
5798 {
5799         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5800
5801         /* 010b (write-only) */
5802         WARN_ON((spte & 0x7) == 0x2);
5803
5804         /* 110b (write/execute) */
5805         WARN_ON((spte & 0x7) == 0x6);
5806
5807         /* 100b (execute-only) and value not supported by logical processor */
5808         if (!cpu_has_vmx_ept_execute_only())
5809                 WARN_ON((spte & 0x7) == 0x4);
5810
5811         /* not 000b */
5812         if ((spte & 0x7)) {
5813                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5814
5815                 if (rsvd_bits != 0) {
5816                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5817                                          __func__, rsvd_bits);
5818                         WARN_ON(1);
5819                 }
5820
5821                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5822                 if ((rsvd_bits & 0x38) == 0) {
5823                         u64 ept_mem_type = (spte & 0x38) >> 3;
5824
5825                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5826                             ept_mem_type == 7) {
5827                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5828                                                 __func__, ept_mem_type);
5829                                 WARN_ON(1);
5830                         }
5831                 }
5832         }
5833 }
5834
5835 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5836 {
5837         u64 sptes[4];
5838         int nr_sptes, i, ret;
5839         gpa_t gpa;
5840
5841         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5842         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5843                 skip_emulated_instruction(vcpu);
5844                 return 1;
5845         }
5846
5847         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5848         if (likely(ret == RET_MMIO_PF_EMULATE))
5849                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5850                                               EMULATE_DONE;
5851
5852         if (unlikely(ret == RET_MMIO_PF_INVALID))
5853                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5854
5855         if (unlikely(ret == RET_MMIO_PF_RETRY))
5856                 return 1;
5857
5858         /* It is the real ept misconfig */
5859         printk(KERN_ERR "EPT: Misconfiguration.\n");
5860         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5861
5862         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5863
5864         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5865                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5866
5867         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5868         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5869
5870         return 0;
5871 }
5872
5873 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5874 {
5875         u32 cpu_based_vm_exec_control;
5876
5877         /* clear pending NMI */
5878         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5879         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5880         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5881         ++vcpu->stat.nmi_window_exits;
5882         kvm_make_request(KVM_REQ_EVENT, vcpu);
5883
5884         return 1;
5885 }
5886
5887 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5888 {
5889         struct vcpu_vmx *vmx = to_vmx(vcpu);
5890         enum emulation_result err = EMULATE_DONE;
5891         int ret = 1;
5892         u32 cpu_exec_ctrl;
5893         bool intr_window_requested;
5894         unsigned count = 130;
5895
5896         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5897         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5898
5899         while (vmx->emulation_required && count-- != 0) {
5900                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5901                         return handle_interrupt_window(&vmx->vcpu);
5902
5903                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5904                         return 1;
5905
5906                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5907
5908                 if (err == EMULATE_USER_EXIT) {
5909                         ++vcpu->stat.mmio_exits;
5910                         ret = 0;
5911                         goto out;
5912                 }
5913
5914                 if (err != EMULATE_DONE) {
5915                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5916                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5917                         vcpu->run->internal.ndata = 0;
5918                         return 0;
5919                 }
5920
5921                 if (vcpu->arch.halt_request) {
5922                         vcpu->arch.halt_request = 0;
5923                         ret = kvm_vcpu_halt(vcpu);
5924                         goto out;
5925                 }
5926
5927                 if (signal_pending(current))
5928                         goto out;
5929                 if (need_resched())
5930                         schedule();
5931         }
5932
5933 out:
5934         return ret;
5935 }
5936
5937 static int __grow_ple_window(int val)
5938 {
5939         if (ple_window_grow < 1)
5940                 return ple_window;
5941
5942         val = min(val, ple_window_actual_max);
5943
5944         if (ple_window_grow < ple_window)
5945                 val *= ple_window_grow;
5946         else
5947                 val += ple_window_grow;
5948
5949         return val;
5950 }
5951
5952 static int __shrink_ple_window(int val, int modifier, int minimum)
5953 {
5954         if (modifier < 1)
5955                 return ple_window;
5956
5957         if (modifier < ple_window)
5958                 val /= modifier;
5959         else
5960                 val -= modifier;
5961
5962         return max(val, minimum);
5963 }
5964
5965 static void grow_ple_window(struct kvm_vcpu *vcpu)
5966 {
5967         struct vcpu_vmx *vmx = to_vmx(vcpu);
5968         int old = vmx->ple_window;
5969
5970         vmx->ple_window = __grow_ple_window(old);
5971
5972         if (vmx->ple_window != old)
5973                 vmx->ple_window_dirty = true;
5974
5975         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5976 }
5977
5978 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5979 {
5980         struct vcpu_vmx *vmx = to_vmx(vcpu);
5981         int old = vmx->ple_window;
5982
5983         vmx->ple_window = __shrink_ple_window(old,
5984                                               ple_window_shrink, ple_window);
5985
5986         if (vmx->ple_window != old)
5987                 vmx->ple_window_dirty = true;
5988
5989         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5990 }
5991
5992 /*
5993  * ple_window_actual_max is computed to be one grow_ple_window() below
5994  * ple_window_max. (See __grow_ple_window for the reason.)
5995  * This prevents overflows, because ple_window_max is int.
5996  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5997  * this process.
5998  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5999  */
6000 static void update_ple_window_actual_max(void)
6001 {
6002         ple_window_actual_max =
6003                         __shrink_ple_window(max(ple_window_max, ple_window),
6004                                             ple_window_grow, INT_MIN);
6005 }
6006
6007 static __init int hardware_setup(void)
6008 {
6009         int r = -ENOMEM, i, msr;
6010
6011         rdmsrl_safe(MSR_EFER, &host_efer);
6012
6013         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6014                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6015
6016         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6017         if (!vmx_io_bitmap_a)
6018                 return r;
6019
6020         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6021         if (!vmx_io_bitmap_b)
6022                 goto out;
6023
6024         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6025         if (!vmx_msr_bitmap_legacy)
6026                 goto out1;
6027
6028         vmx_msr_bitmap_legacy_x2apic =
6029                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6030         if (!vmx_msr_bitmap_legacy_x2apic)
6031                 goto out2;
6032
6033         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6034         if (!vmx_msr_bitmap_longmode)
6035                 goto out3;
6036
6037         vmx_msr_bitmap_longmode_x2apic =
6038                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6039         if (!vmx_msr_bitmap_longmode_x2apic)
6040                 goto out4;
6041
6042         if (nested) {
6043                 vmx_msr_bitmap_nested =
6044                         (unsigned long *)__get_free_page(GFP_KERNEL);
6045                 if (!vmx_msr_bitmap_nested)
6046                         goto out5;
6047         }
6048
6049         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6050         if (!vmx_vmread_bitmap)
6051                 goto out6;
6052
6053         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6054         if (!vmx_vmwrite_bitmap)
6055                 goto out7;
6056
6057         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6058         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6059
6060         /*
6061          * Allow direct access to the PC debug port (it is often used for I/O
6062          * delays, but the vmexits simply slow things down).
6063          */
6064         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6065         clear_bit(0x80, vmx_io_bitmap_a);
6066
6067         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6068
6069         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6070         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6071         if (nested)
6072                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6073
6074         if (setup_vmcs_config(&vmcs_config) < 0) {
6075                 r = -EIO;
6076                 goto out8;
6077         }
6078
6079         if (boot_cpu_has(X86_FEATURE_NX))
6080                 kvm_enable_efer_bits(EFER_NX);
6081
6082         if (!cpu_has_vmx_vpid())
6083                 enable_vpid = 0;
6084         if (!cpu_has_vmx_shadow_vmcs())
6085                 enable_shadow_vmcs = 0;
6086         if (enable_shadow_vmcs)
6087                 init_vmcs_shadow_fields();
6088
6089         if (!cpu_has_vmx_ept() ||
6090             !cpu_has_vmx_ept_4levels()) {
6091                 enable_ept = 0;
6092                 enable_unrestricted_guest = 0;
6093                 enable_ept_ad_bits = 0;
6094         }
6095
6096         if (!cpu_has_vmx_ept_ad_bits())
6097                 enable_ept_ad_bits = 0;
6098
6099         if (!cpu_has_vmx_unrestricted_guest())
6100                 enable_unrestricted_guest = 0;
6101
6102         if (!cpu_has_vmx_flexpriority())
6103                 flexpriority_enabled = 0;
6104
6105         /*
6106          * set_apic_access_page_addr() is used to reload apic access
6107          * page upon invalidation.  No need to do anything if not
6108          * using the APIC_ACCESS_ADDR VMCS field.
6109          */
6110         if (!flexpriority_enabled)
6111                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6112
6113         if (!cpu_has_vmx_tpr_shadow())
6114                 kvm_x86_ops->update_cr8_intercept = NULL;
6115
6116         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6117                 kvm_disable_largepages();
6118
6119         if (!cpu_has_vmx_ple())
6120                 ple_gap = 0;
6121
6122         if (!cpu_has_vmx_apicv())
6123                 enable_apicv = 0;
6124
6125         if (enable_apicv)
6126                 kvm_x86_ops->update_cr8_intercept = NULL;
6127         else {
6128                 kvm_x86_ops->hwapic_irr_update = NULL;
6129                 kvm_x86_ops->hwapic_isr_update = NULL;
6130                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6131                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6132         }
6133
6134         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6135         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6136         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6137         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6138         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6139         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6140         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6141
6142         memcpy(vmx_msr_bitmap_legacy_x2apic,
6143                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6144         memcpy(vmx_msr_bitmap_longmode_x2apic,
6145                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6146
6147         if (enable_apicv) {
6148                 for (msr = 0x800; msr <= 0x8ff; msr++)
6149                         vmx_disable_intercept_msr_read_x2apic(msr);
6150
6151                 /* According SDM, in x2apic mode, the whole id reg is used.
6152                  * But in KVM, it only use the highest eight bits. Need to
6153                  * intercept it */
6154                 vmx_enable_intercept_msr_read_x2apic(0x802);
6155                 /* TMCCT */
6156                 vmx_enable_intercept_msr_read_x2apic(0x839);
6157                 /* TPR */
6158                 vmx_disable_intercept_msr_write_x2apic(0x808);
6159                 /* EOI */
6160                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6161                 /* SELF-IPI */
6162                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6163         }
6164
6165         if (enable_ept) {
6166                 kvm_mmu_set_mask_ptes(0ull,
6167                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6168                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6169                         0ull, VMX_EPT_EXECUTABLE_MASK);
6170                 ept_set_mmio_spte_mask();
6171                 kvm_enable_tdp();
6172         } else
6173                 kvm_disable_tdp();
6174
6175         update_ple_window_actual_max();
6176
6177         /*
6178          * Only enable PML when hardware supports PML feature, and both EPT
6179          * and EPT A/D bit features are enabled -- PML depends on them to work.
6180          */
6181         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6182                 enable_pml = 0;
6183
6184         if (!enable_pml) {
6185                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6186                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6187                 kvm_x86_ops->flush_log_dirty = NULL;
6188                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6189         }
6190
6191         return alloc_kvm_area();
6192
6193 out8:
6194         free_page((unsigned long)vmx_vmwrite_bitmap);
6195 out7:
6196         free_page((unsigned long)vmx_vmread_bitmap);
6197 out6:
6198         if (nested)
6199                 free_page((unsigned long)vmx_msr_bitmap_nested);
6200 out5:
6201         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6202 out4:
6203         free_page((unsigned long)vmx_msr_bitmap_longmode);
6204 out3:
6205         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6206 out2:
6207         free_page((unsigned long)vmx_msr_bitmap_legacy);
6208 out1:
6209         free_page((unsigned long)vmx_io_bitmap_b);
6210 out:
6211         free_page((unsigned long)vmx_io_bitmap_a);
6212
6213     return r;
6214 }
6215
6216 static __exit void hardware_unsetup(void)
6217 {
6218         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6219         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6220         free_page((unsigned long)vmx_msr_bitmap_legacy);
6221         free_page((unsigned long)vmx_msr_bitmap_longmode);
6222         free_page((unsigned long)vmx_io_bitmap_b);
6223         free_page((unsigned long)vmx_io_bitmap_a);
6224         free_page((unsigned long)vmx_vmwrite_bitmap);
6225         free_page((unsigned long)vmx_vmread_bitmap);
6226         if (nested)
6227                 free_page((unsigned long)vmx_msr_bitmap_nested);
6228
6229         free_kvm_area();
6230 }
6231
6232 /*
6233  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6234  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6235  */
6236 static int handle_pause(struct kvm_vcpu *vcpu)
6237 {
6238         if (ple_gap)
6239                 grow_ple_window(vcpu);
6240
6241         skip_emulated_instruction(vcpu);
6242         kvm_vcpu_on_spin(vcpu);
6243
6244         return 1;
6245 }
6246
6247 static int handle_nop(struct kvm_vcpu *vcpu)
6248 {
6249         skip_emulated_instruction(vcpu);
6250         return 1;
6251 }
6252
6253 static int handle_mwait(struct kvm_vcpu *vcpu)
6254 {
6255         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6256         return handle_nop(vcpu);
6257 }
6258
6259 static int handle_monitor(struct kvm_vcpu *vcpu)
6260 {
6261         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6262         return handle_nop(vcpu);
6263 }
6264
6265 /*
6266  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6267  * We could reuse a single VMCS for all the L2 guests, but we also want the
6268  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6269  * allows keeping them loaded on the processor, and in the future will allow
6270  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6271  * every entry if they never change.
6272  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6273  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6274  *
6275  * The following functions allocate and free a vmcs02 in this pool.
6276  */
6277
6278 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6279 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6280 {
6281         struct vmcs02_list *item;
6282         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6283                 if (item->vmptr == vmx->nested.current_vmptr) {
6284                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6285                         return &item->vmcs02;
6286                 }
6287
6288         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6289                 /* Recycle the least recently used VMCS. */
6290                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6291                         struct vmcs02_list, list);
6292                 item->vmptr = vmx->nested.current_vmptr;
6293                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6294                 return &item->vmcs02;
6295         }
6296
6297         /* Create a new VMCS */
6298         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6299         if (!item)
6300                 return NULL;
6301         item->vmcs02.vmcs = alloc_vmcs();
6302         if (!item->vmcs02.vmcs) {
6303                 kfree(item);
6304                 return NULL;
6305         }
6306         loaded_vmcs_init(&item->vmcs02);
6307         item->vmptr = vmx->nested.current_vmptr;
6308         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6309         vmx->nested.vmcs02_num++;
6310         return &item->vmcs02;
6311 }
6312
6313 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6314 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6315 {
6316         struct vmcs02_list *item;
6317         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6318                 if (item->vmptr == vmptr) {
6319                         free_loaded_vmcs(&item->vmcs02);
6320                         list_del(&item->list);
6321                         kfree(item);
6322                         vmx->nested.vmcs02_num--;
6323                         return;
6324                 }
6325 }
6326
6327 /*
6328  * Free all VMCSs saved for this vcpu, except the one pointed by
6329  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6330  * must be &vmx->vmcs01.
6331  */
6332 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6333 {
6334         struct vmcs02_list *item, *n;
6335
6336         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6337         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6338                 /*
6339                  * Something will leak if the above WARN triggers.  Better than
6340                  * a use-after-free.
6341                  */
6342                 if (vmx->loaded_vmcs == &item->vmcs02)
6343                         continue;
6344
6345                 free_loaded_vmcs(&item->vmcs02);
6346                 list_del(&item->list);
6347                 kfree(item);
6348                 vmx->nested.vmcs02_num--;
6349         }
6350 }
6351
6352 /*
6353  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6354  * set the success or error code of an emulated VMX instruction, as specified
6355  * by Vol 2B, VMX Instruction Reference, "Conventions".
6356  */
6357 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6358 {
6359         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6360                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6361                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6362 }
6363
6364 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6365 {
6366         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6367                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6368                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6369                         | X86_EFLAGS_CF);
6370 }
6371
6372 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6373                                         u32 vm_instruction_error)
6374 {
6375         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6376                 /*
6377                  * failValid writes the error number to the current VMCS, which
6378                  * can't be done there isn't a current VMCS.
6379                  */
6380                 nested_vmx_failInvalid(vcpu);
6381                 return;
6382         }
6383         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6384                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6385                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6386                         | X86_EFLAGS_ZF);
6387         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6388         /*
6389          * We don't need to force a shadow sync because
6390          * VM_INSTRUCTION_ERROR is not shadowed
6391          */
6392 }
6393
6394 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6395 {
6396         /* TODO: not to reset guest simply here. */
6397         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6398         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6399 }
6400
6401 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6402 {
6403         struct vcpu_vmx *vmx =
6404                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6405
6406         vmx->nested.preemption_timer_expired = true;
6407         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6408         kvm_vcpu_kick(&vmx->vcpu);
6409
6410         return HRTIMER_NORESTART;
6411 }
6412
6413 /*
6414  * Decode the memory-address operand of a vmx instruction, as recorded on an
6415  * exit caused by such an instruction (run by a guest hypervisor).
6416  * On success, returns 0. When the operand is invalid, returns 1 and throws
6417  * #UD or #GP.
6418  */
6419 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6420                                  unsigned long exit_qualification,
6421                                  u32 vmx_instruction_info, gva_t *ret)
6422 {
6423         /*
6424          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6425          * Execution", on an exit, vmx_instruction_info holds most of the
6426          * addressing components of the operand. Only the displacement part
6427          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6428          * For how an actual address is calculated from all these components,
6429          * refer to Vol. 1, "Operand Addressing".
6430          */
6431         int  scaling = vmx_instruction_info & 3;
6432         int  addr_size = (vmx_instruction_info >> 7) & 7;
6433         bool is_reg = vmx_instruction_info & (1u << 10);
6434         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6435         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6436         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6437         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6438         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6439
6440         if (is_reg) {
6441                 kvm_queue_exception(vcpu, UD_VECTOR);
6442                 return 1;
6443         }
6444
6445         /* Addr = segment_base + offset */
6446         /* offset = base + [index * scale] + displacement */
6447         *ret = vmx_get_segment_base(vcpu, seg_reg);
6448         if (base_is_valid)
6449                 *ret += kvm_register_read(vcpu, base_reg);
6450         if (index_is_valid)
6451                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6452         *ret += exit_qualification; /* holds the displacement */
6453
6454         if (addr_size == 1) /* 32 bit */
6455                 *ret &= 0xffffffff;
6456
6457         /*
6458          * TODO: throw #GP (and return 1) in various cases that the VM*
6459          * instructions require it - e.g., offset beyond segment limit,
6460          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6461          * address, and so on. Currently these are not checked.
6462          */
6463         return 0;
6464 }
6465
6466 /*
6467  * This function performs the various checks including
6468  * - if it's 4KB aligned
6469  * - No bits beyond the physical address width are set
6470  * - Returns 0 on success or else 1
6471  * (Intel SDM Section 30.3)
6472  */
6473 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6474                                   gpa_t *vmpointer)
6475 {
6476         gva_t gva;
6477         gpa_t vmptr;
6478         struct x86_exception e;
6479         struct page *page;
6480         struct vcpu_vmx *vmx = to_vmx(vcpu);
6481         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6482
6483         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6484                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6485                 return 1;
6486
6487         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6488                                 sizeof(vmptr), &e)) {
6489                 kvm_inject_page_fault(vcpu, &e);
6490                 return 1;
6491         }
6492
6493         switch (exit_reason) {
6494         case EXIT_REASON_VMON:
6495                 /*
6496                  * SDM 3: 24.11.5
6497                  * The first 4 bytes of VMXON region contain the supported
6498                  * VMCS revision identifier
6499                  *
6500                  * Note - IA32_VMX_BASIC[48] will never be 1
6501                  * for the nested case;
6502                  * which replaces physical address width with 32
6503                  *
6504                  */
6505                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6506                         nested_vmx_failInvalid(vcpu);
6507                         skip_emulated_instruction(vcpu);
6508                         return 1;
6509                 }
6510
6511                 page = nested_get_page(vcpu, vmptr);
6512                 if (page == NULL ||
6513                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6514                         nested_vmx_failInvalid(vcpu);
6515                         kunmap(page);
6516                         skip_emulated_instruction(vcpu);
6517                         return 1;
6518                 }
6519                 kunmap(page);
6520                 vmx->nested.vmxon_ptr = vmptr;
6521                 break;
6522         case EXIT_REASON_VMCLEAR:
6523                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6524                         nested_vmx_failValid(vcpu,
6525                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6526                         skip_emulated_instruction(vcpu);
6527                         return 1;
6528                 }
6529
6530                 if (vmptr == vmx->nested.vmxon_ptr) {
6531                         nested_vmx_failValid(vcpu,
6532                                              VMXERR_VMCLEAR_VMXON_POINTER);
6533                         skip_emulated_instruction(vcpu);
6534                         return 1;
6535                 }
6536                 break;
6537         case EXIT_REASON_VMPTRLD:
6538                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6539                         nested_vmx_failValid(vcpu,
6540                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6541                         skip_emulated_instruction(vcpu);
6542                         return 1;
6543                 }
6544
6545                 if (vmptr == vmx->nested.vmxon_ptr) {
6546                         nested_vmx_failValid(vcpu,
6547                                              VMXERR_VMCLEAR_VMXON_POINTER);
6548                         skip_emulated_instruction(vcpu);
6549                         return 1;
6550                 }
6551                 break;
6552         default:
6553                 return 1; /* shouldn't happen */
6554         }
6555
6556         if (vmpointer)
6557                 *vmpointer = vmptr;
6558         return 0;
6559 }
6560
6561 /*
6562  * Emulate the VMXON instruction.
6563  * Currently, we just remember that VMX is active, and do not save or even
6564  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6565  * do not currently need to store anything in that guest-allocated memory
6566  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6567  * argument is different from the VMXON pointer (which the spec says they do).
6568  */
6569 static int handle_vmon(struct kvm_vcpu *vcpu)
6570 {
6571         struct kvm_segment cs;
6572         struct vcpu_vmx *vmx = to_vmx(vcpu);
6573         struct vmcs *shadow_vmcs;
6574         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6575                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6576
6577         /* The Intel VMX Instruction Reference lists a bunch of bits that
6578          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6579          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6580          * Otherwise, we should fail with #UD. We test these now:
6581          */
6582         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6583             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6584             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6585                 kvm_queue_exception(vcpu, UD_VECTOR);
6586                 return 1;
6587         }
6588
6589         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6590         if (is_long_mode(vcpu) && !cs.l) {
6591                 kvm_queue_exception(vcpu, UD_VECTOR);
6592                 return 1;
6593         }
6594
6595         if (vmx_get_cpl(vcpu)) {
6596                 kvm_inject_gp(vcpu, 0);
6597                 return 1;
6598         }
6599
6600         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6601                 return 1;
6602
6603         if (vmx->nested.vmxon) {
6604                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6605                 skip_emulated_instruction(vcpu);
6606                 return 1;
6607         }
6608
6609         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6610                         != VMXON_NEEDED_FEATURES) {
6611                 kvm_inject_gp(vcpu, 0);
6612                 return 1;
6613         }
6614
6615         if (enable_shadow_vmcs) {
6616                 shadow_vmcs = alloc_vmcs();
6617                 if (!shadow_vmcs)
6618                         return -ENOMEM;
6619                 /* mark vmcs as shadow */
6620                 shadow_vmcs->revision_id |= (1u << 31);
6621                 /* init shadow vmcs */
6622                 vmcs_clear(shadow_vmcs);
6623                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6624         }
6625
6626         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6627         vmx->nested.vmcs02_num = 0;
6628
6629         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6630                      HRTIMER_MODE_REL);
6631         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6632
6633         vmx->nested.vmxon = true;
6634
6635         skip_emulated_instruction(vcpu);
6636         nested_vmx_succeed(vcpu);
6637         return 1;
6638 }
6639
6640 /*
6641  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6642  * for running VMX instructions (except VMXON, whose prerequisites are
6643  * slightly different). It also specifies what exception to inject otherwise.
6644  */
6645 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6646 {
6647         struct kvm_segment cs;
6648         struct vcpu_vmx *vmx = to_vmx(vcpu);
6649
6650         if (!vmx->nested.vmxon) {
6651                 kvm_queue_exception(vcpu, UD_VECTOR);
6652                 return 0;
6653         }
6654
6655         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6656         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6657             (is_long_mode(vcpu) && !cs.l)) {
6658                 kvm_queue_exception(vcpu, UD_VECTOR);
6659                 return 0;
6660         }
6661
6662         if (vmx_get_cpl(vcpu)) {
6663                 kvm_inject_gp(vcpu, 0);
6664                 return 0;
6665         }
6666
6667         return 1;
6668 }
6669
6670 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6671 {
6672         u32 exec_control;
6673         if (vmx->nested.current_vmptr == -1ull)
6674                 return;
6675
6676         /* current_vmptr and current_vmcs12 are always set/reset together */
6677         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6678                 return;
6679
6680         if (enable_shadow_vmcs) {
6681                 /* copy to memory all shadowed fields in case
6682                    they were modified */
6683                 copy_shadow_to_vmcs12(vmx);
6684                 vmx->nested.sync_shadow_vmcs = false;
6685                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6686                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6687                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6688                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6689         }
6690         vmx->nested.posted_intr_nv = -1;
6691         kunmap(vmx->nested.current_vmcs12_page);
6692         nested_release_page(vmx->nested.current_vmcs12_page);
6693         vmx->nested.current_vmptr = -1ull;
6694         vmx->nested.current_vmcs12 = NULL;
6695 }
6696
6697 /*
6698  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6699  * just stops using VMX.
6700  */
6701 static void free_nested(struct vcpu_vmx *vmx)
6702 {
6703         if (!vmx->nested.vmxon)
6704                 return;
6705
6706         vmx->nested.vmxon = false;
6707         nested_release_vmcs12(vmx);
6708         if (enable_shadow_vmcs)
6709                 free_vmcs(vmx->nested.current_shadow_vmcs);
6710         /* Unpin physical memory we referred to in current vmcs02 */
6711         if (vmx->nested.apic_access_page) {
6712                 nested_release_page(vmx->nested.apic_access_page);
6713                 vmx->nested.apic_access_page = NULL;
6714         }
6715         if (vmx->nested.virtual_apic_page) {
6716                 nested_release_page(vmx->nested.virtual_apic_page);
6717                 vmx->nested.virtual_apic_page = NULL;
6718         }
6719         if (vmx->nested.pi_desc_page) {
6720                 kunmap(vmx->nested.pi_desc_page);
6721                 nested_release_page(vmx->nested.pi_desc_page);
6722                 vmx->nested.pi_desc_page = NULL;
6723                 vmx->nested.pi_desc = NULL;
6724         }
6725
6726         nested_free_all_saved_vmcss(vmx);
6727 }
6728
6729 /* Emulate the VMXOFF instruction */
6730 static int handle_vmoff(struct kvm_vcpu *vcpu)
6731 {
6732         if (!nested_vmx_check_permission(vcpu))
6733                 return 1;
6734         free_nested(to_vmx(vcpu));
6735         skip_emulated_instruction(vcpu);
6736         nested_vmx_succeed(vcpu);
6737         return 1;
6738 }
6739
6740 /* Emulate the VMCLEAR instruction */
6741 static int handle_vmclear(struct kvm_vcpu *vcpu)
6742 {
6743         struct vcpu_vmx *vmx = to_vmx(vcpu);
6744         gpa_t vmptr;
6745         struct vmcs12 *vmcs12;
6746         struct page *page;
6747
6748         if (!nested_vmx_check_permission(vcpu))
6749                 return 1;
6750
6751         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6752                 return 1;
6753
6754         if (vmptr == vmx->nested.current_vmptr)
6755                 nested_release_vmcs12(vmx);
6756
6757         page = nested_get_page(vcpu, vmptr);
6758         if (page == NULL) {
6759                 /*
6760                  * For accurate processor emulation, VMCLEAR beyond available
6761                  * physical memory should do nothing at all. However, it is
6762                  * possible that a nested vmx bug, not a guest hypervisor bug,
6763                  * resulted in this case, so let's shut down before doing any
6764                  * more damage:
6765                  */
6766                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6767                 return 1;
6768         }
6769         vmcs12 = kmap(page);
6770         vmcs12->launch_state = 0;
6771         kunmap(page);
6772         nested_release_page(page);
6773
6774         nested_free_vmcs02(vmx, vmptr);
6775
6776         skip_emulated_instruction(vcpu);
6777         nested_vmx_succeed(vcpu);
6778         return 1;
6779 }
6780
6781 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6782
6783 /* Emulate the VMLAUNCH instruction */
6784 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6785 {
6786         return nested_vmx_run(vcpu, true);
6787 }
6788
6789 /* Emulate the VMRESUME instruction */
6790 static int handle_vmresume(struct kvm_vcpu *vcpu)
6791 {
6792
6793         return nested_vmx_run(vcpu, false);
6794 }
6795
6796 enum vmcs_field_type {
6797         VMCS_FIELD_TYPE_U16 = 0,
6798         VMCS_FIELD_TYPE_U64 = 1,
6799         VMCS_FIELD_TYPE_U32 = 2,
6800         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6801 };
6802
6803 static inline int vmcs_field_type(unsigned long field)
6804 {
6805         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6806                 return VMCS_FIELD_TYPE_U32;
6807         return (field >> 13) & 0x3 ;
6808 }
6809
6810 static inline int vmcs_field_readonly(unsigned long field)
6811 {
6812         return (((field >> 10) & 0x3) == 1);
6813 }
6814
6815 /*
6816  * Read a vmcs12 field. Since these can have varying lengths and we return
6817  * one type, we chose the biggest type (u64) and zero-extend the return value
6818  * to that size. Note that the caller, handle_vmread, might need to use only
6819  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6820  * 64-bit fields are to be returned).
6821  */
6822 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6823                                   unsigned long field, u64 *ret)
6824 {
6825         short offset = vmcs_field_to_offset(field);
6826         char *p;
6827
6828         if (offset < 0)
6829                 return offset;
6830
6831         p = ((char *)(get_vmcs12(vcpu))) + offset;
6832
6833         switch (vmcs_field_type(field)) {
6834         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6835                 *ret = *((natural_width *)p);
6836                 return 0;
6837         case VMCS_FIELD_TYPE_U16:
6838                 *ret = *((u16 *)p);
6839                 return 0;
6840         case VMCS_FIELD_TYPE_U32:
6841                 *ret = *((u32 *)p);
6842                 return 0;
6843         case VMCS_FIELD_TYPE_U64:
6844                 *ret = *((u64 *)p);
6845                 return 0;
6846         default:
6847                 WARN_ON(1);
6848                 return -ENOENT;
6849         }
6850 }
6851
6852
6853 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6854                                    unsigned long field, u64 field_value){
6855         short offset = vmcs_field_to_offset(field);
6856         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6857         if (offset < 0)
6858                 return offset;
6859
6860         switch (vmcs_field_type(field)) {
6861         case VMCS_FIELD_TYPE_U16:
6862                 *(u16 *)p = field_value;
6863                 return 0;
6864         case VMCS_FIELD_TYPE_U32:
6865                 *(u32 *)p = field_value;
6866                 return 0;
6867         case VMCS_FIELD_TYPE_U64:
6868                 *(u64 *)p = field_value;
6869                 return 0;
6870         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6871                 *(natural_width *)p = field_value;
6872                 return 0;
6873         default:
6874                 WARN_ON(1);
6875                 return -ENOENT;
6876         }
6877
6878 }
6879
6880 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6881 {
6882         int i;
6883         unsigned long field;
6884         u64 field_value;
6885         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6886         const unsigned long *fields = shadow_read_write_fields;
6887         const int num_fields = max_shadow_read_write_fields;
6888
6889         preempt_disable();
6890
6891         vmcs_load(shadow_vmcs);
6892
6893         for (i = 0; i < num_fields; i++) {
6894                 field = fields[i];
6895                 switch (vmcs_field_type(field)) {
6896                 case VMCS_FIELD_TYPE_U16:
6897                         field_value = vmcs_read16(field);
6898                         break;
6899                 case VMCS_FIELD_TYPE_U32:
6900                         field_value = vmcs_read32(field);
6901                         break;
6902                 case VMCS_FIELD_TYPE_U64:
6903                         field_value = vmcs_read64(field);
6904                         break;
6905                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6906                         field_value = vmcs_readl(field);
6907                         break;
6908                 default:
6909                         WARN_ON(1);
6910                         continue;
6911                 }
6912                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6913         }
6914
6915         vmcs_clear(shadow_vmcs);
6916         vmcs_load(vmx->loaded_vmcs->vmcs);
6917
6918         preempt_enable();
6919 }
6920
6921 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6922 {
6923         const unsigned long *fields[] = {
6924                 shadow_read_write_fields,
6925                 shadow_read_only_fields
6926         };
6927         const int max_fields[] = {
6928                 max_shadow_read_write_fields,
6929                 max_shadow_read_only_fields
6930         };
6931         int i, q;
6932         unsigned long field;
6933         u64 field_value = 0;
6934         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6935
6936         vmcs_load(shadow_vmcs);
6937
6938         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6939                 for (i = 0; i < max_fields[q]; i++) {
6940                         field = fields[q][i];
6941                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6942
6943                         switch (vmcs_field_type(field)) {
6944                         case VMCS_FIELD_TYPE_U16:
6945                                 vmcs_write16(field, (u16)field_value);
6946                                 break;
6947                         case VMCS_FIELD_TYPE_U32:
6948                                 vmcs_write32(field, (u32)field_value);
6949                                 break;
6950                         case VMCS_FIELD_TYPE_U64:
6951                                 vmcs_write64(field, (u64)field_value);
6952                                 break;
6953                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6954                                 vmcs_writel(field, (long)field_value);
6955                                 break;
6956                         default:
6957                                 WARN_ON(1);
6958                                 break;
6959                         }
6960                 }
6961         }
6962
6963         vmcs_clear(shadow_vmcs);
6964         vmcs_load(vmx->loaded_vmcs->vmcs);
6965 }
6966
6967 /*
6968  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6969  * used before) all generate the same failure when it is missing.
6970  */
6971 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6972 {
6973         struct vcpu_vmx *vmx = to_vmx(vcpu);
6974         if (vmx->nested.current_vmptr == -1ull) {
6975                 nested_vmx_failInvalid(vcpu);
6976                 skip_emulated_instruction(vcpu);
6977                 return 0;
6978         }
6979         return 1;
6980 }
6981
6982 static int handle_vmread(struct kvm_vcpu *vcpu)
6983 {
6984         unsigned long field;
6985         u64 field_value;
6986         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6987         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6988         gva_t gva = 0;
6989
6990         if (!nested_vmx_check_permission(vcpu) ||
6991             !nested_vmx_check_vmcs12(vcpu))
6992                 return 1;
6993
6994         /* Decode instruction info and find the field to read */
6995         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6996         /* Read the field, zero-extended to a u64 field_value */
6997         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6998                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6999                 skip_emulated_instruction(vcpu);
7000                 return 1;
7001         }
7002         /*
7003          * Now copy part of this value to register or memory, as requested.
7004          * Note that the number of bits actually copied is 32 or 64 depending
7005          * on the guest's mode (32 or 64 bit), not on the given field's length.
7006          */
7007         if (vmx_instruction_info & (1u << 10)) {
7008                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7009                         field_value);
7010         } else {
7011                 if (get_vmx_mem_address(vcpu, exit_qualification,
7012                                 vmx_instruction_info, &gva))
7013                         return 1;
7014                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7015                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7016                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7017         }
7018
7019         nested_vmx_succeed(vcpu);
7020         skip_emulated_instruction(vcpu);
7021         return 1;
7022 }
7023
7024
7025 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7026 {
7027         unsigned long field;
7028         gva_t gva;
7029         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7030         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7031         /* The value to write might be 32 or 64 bits, depending on L1's long
7032          * mode, and eventually we need to write that into a field of several
7033          * possible lengths. The code below first zero-extends the value to 64
7034          * bit (field_value), and then copies only the approriate number of
7035          * bits into the vmcs12 field.
7036          */
7037         u64 field_value = 0;
7038         struct x86_exception e;
7039
7040         if (!nested_vmx_check_permission(vcpu) ||
7041             !nested_vmx_check_vmcs12(vcpu))
7042                 return 1;
7043
7044         if (vmx_instruction_info & (1u << 10))
7045                 field_value = kvm_register_readl(vcpu,
7046                         (((vmx_instruction_info) >> 3) & 0xf));
7047         else {
7048                 if (get_vmx_mem_address(vcpu, exit_qualification,
7049                                 vmx_instruction_info, &gva))
7050                         return 1;
7051                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7052                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7053                         kvm_inject_page_fault(vcpu, &e);
7054                         return 1;
7055                 }
7056         }
7057
7058
7059         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7060         if (vmcs_field_readonly(field)) {
7061                 nested_vmx_failValid(vcpu,
7062                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7063                 skip_emulated_instruction(vcpu);
7064                 return 1;
7065         }
7066
7067         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7068                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7069                 skip_emulated_instruction(vcpu);
7070                 return 1;
7071         }
7072
7073         nested_vmx_succeed(vcpu);
7074         skip_emulated_instruction(vcpu);
7075         return 1;
7076 }
7077
7078 /* Emulate the VMPTRLD instruction */
7079 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7080 {
7081         struct vcpu_vmx *vmx = to_vmx(vcpu);
7082         gpa_t vmptr;
7083         u32 exec_control;
7084
7085         if (!nested_vmx_check_permission(vcpu))
7086                 return 1;
7087
7088         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7089                 return 1;
7090
7091         if (vmx->nested.current_vmptr != vmptr) {
7092                 struct vmcs12 *new_vmcs12;
7093                 struct page *page;
7094                 page = nested_get_page(vcpu, vmptr);
7095                 if (page == NULL) {
7096                         nested_vmx_failInvalid(vcpu);
7097                         skip_emulated_instruction(vcpu);
7098                         return 1;
7099                 }
7100                 new_vmcs12 = kmap(page);
7101                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7102                         kunmap(page);
7103                         nested_release_page_clean(page);
7104                         nested_vmx_failValid(vcpu,
7105                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7106                         skip_emulated_instruction(vcpu);
7107                         return 1;
7108                 }
7109
7110                 nested_release_vmcs12(vmx);
7111                 vmx->nested.current_vmptr = vmptr;
7112                 vmx->nested.current_vmcs12 = new_vmcs12;
7113                 vmx->nested.current_vmcs12_page = page;
7114                 if (enable_shadow_vmcs) {
7115                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7116                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7117                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7118                         vmcs_write64(VMCS_LINK_POINTER,
7119                                      __pa(vmx->nested.current_shadow_vmcs));
7120                         vmx->nested.sync_shadow_vmcs = true;
7121                 }
7122         }
7123
7124         nested_vmx_succeed(vcpu);
7125         skip_emulated_instruction(vcpu);
7126         return 1;
7127 }
7128
7129 /* Emulate the VMPTRST instruction */
7130 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7131 {
7132         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7133         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7134         gva_t vmcs_gva;
7135         struct x86_exception e;
7136
7137         if (!nested_vmx_check_permission(vcpu))
7138                 return 1;
7139
7140         if (get_vmx_mem_address(vcpu, exit_qualification,
7141                         vmx_instruction_info, &vmcs_gva))
7142                 return 1;
7143         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7144         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7145                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7146                                  sizeof(u64), &e)) {
7147                 kvm_inject_page_fault(vcpu, &e);
7148                 return 1;
7149         }
7150         nested_vmx_succeed(vcpu);
7151         skip_emulated_instruction(vcpu);
7152         return 1;
7153 }
7154
7155 /* Emulate the INVEPT instruction */
7156 static int handle_invept(struct kvm_vcpu *vcpu)
7157 {
7158         struct vcpu_vmx *vmx = to_vmx(vcpu);
7159         u32 vmx_instruction_info, types;
7160         unsigned long type;
7161         gva_t gva;
7162         struct x86_exception e;
7163         struct {
7164                 u64 eptp, gpa;
7165         } operand;
7166
7167         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7168               SECONDARY_EXEC_ENABLE_EPT) ||
7169             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7170                 kvm_queue_exception(vcpu, UD_VECTOR);
7171                 return 1;
7172         }
7173
7174         if (!nested_vmx_check_permission(vcpu))
7175                 return 1;
7176
7177         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7178                 kvm_queue_exception(vcpu, UD_VECTOR);
7179                 return 1;
7180         }
7181
7182         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7183         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7184
7185         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7186
7187         if (!(types & (1UL << type))) {
7188                 nested_vmx_failValid(vcpu,
7189                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7190                 return 1;
7191         }
7192
7193         /* According to the Intel VMX instruction reference, the memory
7194          * operand is read even if it isn't needed (e.g., for type==global)
7195          */
7196         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7197                         vmx_instruction_info, &gva))
7198                 return 1;
7199         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7200                                 sizeof(operand), &e)) {
7201                 kvm_inject_page_fault(vcpu, &e);
7202                 return 1;
7203         }
7204
7205         switch (type) {
7206         case VMX_EPT_EXTENT_GLOBAL:
7207                 kvm_mmu_sync_roots(vcpu);
7208                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7209                 nested_vmx_succeed(vcpu);
7210                 break;
7211         default:
7212                 /* Trap single context invalidation invept calls */
7213                 BUG_ON(1);
7214                 break;
7215         }
7216
7217         skip_emulated_instruction(vcpu);
7218         return 1;
7219 }
7220
7221 static int handle_invvpid(struct kvm_vcpu *vcpu)
7222 {
7223         kvm_queue_exception(vcpu, UD_VECTOR);
7224         return 1;
7225 }
7226
7227 static int handle_pml_full(struct kvm_vcpu *vcpu)
7228 {
7229         unsigned long exit_qualification;
7230
7231         trace_kvm_pml_full(vcpu->vcpu_id);
7232
7233         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7234
7235         /*
7236          * PML buffer FULL happened while executing iret from NMI,
7237          * "blocked by NMI" bit has to be set before next VM entry.
7238          */
7239         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7240                         cpu_has_virtual_nmis() &&
7241                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7242                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7243                                 GUEST_INTR_STATE_NMI);
7244
7245         /*
7246          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7247          * here.., and there's no userspace involvement needed for PML.
7248          */
7249         return 1;
7250 }
7251
7252 /*
7253  * The exit handlers return 1 if the exit was handled fully and guest execution
7254  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7255  * to be done to userspace and return 0.
7256  */
7257 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7258         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7259         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7260         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7261         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7262         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7263         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7264         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7265         [EXIT_REASON_CPUID]                   = handle_cpuid,
7266         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7267         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7268         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7269         [EXIT_REASON_HLT]                     = handle_halt,
7270         [EXIT_REASON_INVD]                    = handle_invd,
7271         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7272         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7273         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7274         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7275         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7276         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7277         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7278         [EXIT_REASON_VMREAD]                  = handle_vmread,
7279         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7280         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7281         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7282         [EXIT_REASON_VMON]                    = handle_vmon,
7283         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7284         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7285         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7286         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7287         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7288         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7289         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7290         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7291         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7292         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7293         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7294         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7295         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7296         [EXIT_REASON_INVEPT]                  = handle_invept,
7297         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7298         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7299         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7300         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7301 };
7302
7303 static const int kvm_vmx_max_exit_handlers =
7304         ARRAY_SIZE(kvm_vmx_exit_handlers);
7305
7306 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7307                                        struct vmcs12 *vmcs12)
7308 {
7309         unsigned long exit_qualification;
7310         gpa_t bitmap, last_bitmap;
7311         unsigned int port;
7312         int size;
7313         u8 b;
7314
7315         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7316                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7317
7318         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7319
7320         port = exit_qualification >> 16;
7321         size = (exit_qualification & 7) + 1;
7322
7323         last_bitmap = (gpa_t)-1;
7324         b = -1;
7325
7326         while (size > 0) {
7327                 if (port < 0x8000)
7328                         bitmap = vmcs12->io_bitmap_a;
7329                 else if (port < 0x10000)
7330                         bitmap = vmcs12->io_bitmap_b;
7331                 else
7332                         return true;
7333                 bitmap += (port & 0x7fff) / 8;
7334
7335                 if (last_bitmap != bitmap)
7336                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7337                                 return true;
7338                 if (b & (1 << (port & 7)))
7339                         return true;
7340
7341                 port++;
7342                 size--;
7343                 last_bitmap = bitmap;
7344         }
7345
7346         return false;
7347 }
7348
7349 /*
7350  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7351  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7352  * disinterest in the current event (read or write a specific MSR) by using an
7353  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7354  */
7355 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7356         struct vmcs12 *vmcs12, u32 exit_reason)
7357 {
7358         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7359         gpa_t bitmap;
7360
7361         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7362                 return true;
7363
7364         /*
7365          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7366          * for the four combinations of read/write and low/high MSR numbers.
7367          * First we need to figure out which of the four to use:
7368          */
7369         bitmap = vmcs12->msr_bitmap;
7370         if (exit_reason == EXIT_REASON_MSR_WRITE)
7371                 bitmap += 2048;
7372         if (msr_index >= 0xc0000000) {
7373                 msr_index -= 0xc0000000;
7374                 bitmap += 1024;
7375         }
7376
7377         /* Then read the msr_index'th bit from this bitmap: */
7378         if (msr_index < 1024*8) {
7379                 unsigned char b;
7380                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7381                         return true;
7382                 return 1 & (b >> (msr_index & 7));
7383         } else
7384                 return true; /* let L1 handle the wrong parameter */
7385 }
7386
7387 /*
7388  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7389  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7390  * intercept (via guest_host_mask etc.) the current event.
7391  */
7392 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7393         struct vmcs12 *vmcs12)
7394 {
7395         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7396         int cr = exit_qualification & 15;
7397         int reg = (exit_qualification >> 8) & 15;
7398         unsigned long val = kvm_register_readl(vcpu, reg);
7399
7400         switch ((exit_qualification >> 4) & 3) {
7401         case 0: /* mov to cr */
7402                 switch (cr) {
7403                 case 0:
7404                         if (vmcs12->cr0_guest_host_mask &
7405                             (val ^ vmcs12->cr0_read_shadow))
7406                                 return true;
7407                         break;
7408                 case 3:
7409                         if ((vmcs12->cr3_target_count >= 1 &&
7410                                         vmcs12->cr3_target_value0 == val) ||
7411                                 (vmcs12->cr3_target_count >= 2 &&
7412                                         vmcs12->cr3_target_value1 == val) ||
7413                                 (vmcs12->cr3_target_count >= 3 &&
7414                                         vmcs12->cr3_target_value2 == val) ||
7415                                 (vmcs12->cr3_target_count >= 4 &&
7416                                         vmcs12->cr3_target_value3 == val))
7417                                 return false;
7418                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7419                                 return true;
7420                         break;
7421                 case 4:
7422                         if (vmcs12->cr4_guest_host_mask &
7423                             (vmcs12->cr4_read_shadow ^ val))
7424                                 return true;
7425                         break;
7426                 case 8:
7427                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7428                                 return true;
7429                         break;
7430                 }
7431                 break;
7432         case 2: /* clts */
7433                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7434                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7435                         return true;
7436                 break;
7437         case 1: /* mov from cr */
7438                 switch (cr) {
7439                 case 3:
7440                         if (vmcs12->cpu_based_vm_exec_control &
7441                             CPU_BASED_CR3_STORE_EXITING)
7442                                 return true;
7443                         break;
7444                 case 8:
7445                         if (vmcs12->cpu_based_vm_exec_control &
7446                             CPU_BASED_CR8_STORE_EXITING)
7447                                 return true;
7448                         break;
7449                 }
7450                 break;
7451         case 3: /* lmsw */
7452                 /*
7453                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7454                  * cr0. Other attempted changes are ignored, with no exit.
7455                  */
7456                 if (vmcs12->cr0_guest_host_mask & 0xe &
7457                     (val ^ vmcs12->cr0_read_shadow))
7458                         return true;
7459                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7460                     !(vmcs12->cr0_read_shadow & 0x1) &&
7461                     (val & 0x1))
7462                         return true;
7463                 break;
7464         }
7465         return false;
7466 }
7467
7468 /*
7469  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7470  * should handle it ourselves in L0 (and then continue L2). Only call this
7471  * when in is_guest_mode (L2).
7472  */
7473 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7474 {
7475         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7476         struct vcpu_vmx *vmx = to_vmx(vcpu);
7477         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7478         u32 exit_reason = vmx->exit_reason;
7479
7480         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7481                                 vmcs_readl(EXIT_QUALIFICATION),
7482                                 vmx->idt_vectoring_info,
7483                                 intr_info,
7484                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7485                                 KVM_ISA_VMX);
7486
7487         if (vmx->nested.nested_run_pending)
7488                 return false;
7489
7490         if (unlikely(vmx->fail)) {
7491                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7492                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7493                 return true;
7494         }
7495
7496         switch (exit_reason) {
7497         case EXIT_REASON_EXCEPTION_NMI:
7498                 if (!is_exception(intr_info))
7499                         return false;
7500                 else if (is_page_fault(intr_info))
7501                         return enable_ept;
7502                 else if (is_no_device(intr_info) &&
7503                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7504                         return false;
7505                 return vmcs12->exception_bitmap &
7506                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7507         case EXIT_REASON_EXTERNAL_INTERRUPT:
7508                 return false;
7509         case EXIT_REASON_TRIPLE_FAULT:
7510                 return true;
7511         case EXIT_REASON_PENDING_INTERRUPT:
7512                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7513         case EXIT_REASON_NMI_WINDOW:
7514                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7515         case EXIT_REASON_TASK_SWITCH:
7516                 return true;
7517         case EXIT_REASON_CPUID:
7518                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7519                         return false;
7520                 return true;
7521         case EXIT_REASON_HLT:
7522                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7523         case EXIT_REASON_INVD:
7524                 return true;
7525         case EXIT_REASON_INVLPG:
7526                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7527         case EXIT_REASON_RDPMC:
7528                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7529         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7530                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7531         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7532         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7533         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7534         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7535         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7536         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7537                 /*
7538                  * VMX instructions trap unconditionally. This allows L1 to
7539                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7540                  */
7541                 return true;
7542         case EXIT_REASON_CR_ACCESS:
7543                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7544         case EXIT_REASON_DR_ACCESS:
7545                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7546         case EXIT_REASON_IO_INSTRUCTION:
7547                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7548         case EXIT_REASON_MSR_READ:
7549         case EXIT_REASON_MSR_WRITE:
7550                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7551         case EXIT_REASON_INVALID_STATE:
7552                 return true;
7553         case EXIT_REASON_MWAIT_INSTRUCTION:
7554                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7555         case EXIT_REASON_MONITOR_INSTRUCTION:
7556                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7557         case EXIT_REASON_PAUSE_INSTRUCTION:
7558                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7559                         nested_cpu_has2(vmcs12,
7560                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7561         case EXIT_REASON_MCE_DURING_VMENTRY:
7562                 return false;
7563         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7564                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7565         case EXIT_REASON_APIC_ACCESS:
7566                 return nested_cpu_has2(vmcs12,
7567                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7568         case EXIT_REASON_APIC_WRITE:
7569         case EXIT_REASON_EOI_INDUCED:
7570                 /* apic_write and eoi_induced should exit unconditionally. */
7571                 return true;
7572         case EXIT_REASON_EPT_VIOLATION:
7573                 /*
7574                  * L0 always deals with the EPT violation. If nested EPT is
7575                  * used, and the nested mmu code discovers that the address is
7576                  * missing in the guest EPT table (EPT12), the EPT violation
7577                  * will be injected with nested_ept_inject_page_fault()
7578                  */
7579                 return false;
7580         case EXIT_REASON_EPT_MISCONFIG:
7581                 /*
7582                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7583                  * table (shadow on EPT) or a merged EPT table that L0 built
7584                  * (EPT on EPT). So any problems with the structure of the
7585                  * table is L0's fault.
7586                  */
7587                 return false;
7588         case EXIT_REASON_WBINVD:
7589                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7590         case EXIT_REASON_XSETBV:
7591                 return true;
7592         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7593                 /*
7594                  * This should never happen, since it is not possible to
7595                  * set XSS to a non-zero value---neither in L1 nor in L2.
7596                  * If if it were, XSS would have to be checked against
7597                  * the XSS exit bitmap in vmcs12.
7598                  */
7599                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7600         default:
7601                 return true;
7602         }
7603 }
7604
7605 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7606 {
7607         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7608         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7609 }
7610
7611 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7612 {
7613         struct page *pml_pg;
7614         u32 exec_control;
7615
7616         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7617         if (!pml_pg)
7618                 return -ENOMEM;
7619
7620         vmx->pml_pg = pml_pg;
7621
7622         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7623         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7624
7625         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7626         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7627         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7628
7629         return 0;
7630 }
7631
7632 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7633 {
7634         u32 exec_control;
7635
7636         ASSERT(vmx->pml_pg);
7637         __free_page(vmx->pml_pg);
7638         vmx->pml_pg = NULL;
7639
7640         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7641         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7642         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7643 }
7644
7645 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7646 {
7647         struct kvm *kvm = vmx->vcpu.kvm;
7648         u64 *pml_buf;
7649         u16 pml_idx;
7650
7651         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7652
7653         /* Do nothing if PML buffer is empty */
7654         if (pml_idx == (PML_ENTITY_NUM - 1))
7655                 return;
7656
7657         /* PML index always points to next available PML buffer entity */
7658         if (pml_idx >= PML_ENTITY_NUM)
7659                 pml_idx = 0;
7660         else
7661                 pml_idx++;
7662
7663         pml_buf = page_address(vmx->pml_pg);
7664         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7665                 u64 gpa;
7666
7667                 gpa = pml_buf[pml_idx];
7668                 WARN_ON(gpa & (PAGE_SIZE - 1));
7669                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7670         }
7671
7672         /* reset PML index */
7673         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7674 }
7675
7676 /*
7677  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7678  * Called before reporting dirty_bitmap to userspace.
7679  */
7680 static void kvm_flush_pml_buffers(struct kvm *kvm)
7681 {
7682         int i;
7683         struct kvm_vcpu *vcpu;
7684         /*
7685          * We only need to kick vcpu out of guest mode here, as PML buffer
7686          * is flushed at beginning of all VMEXITs, and it's obvious that only
7687          * vcpus running in guest are possible to have unflushed GPAs in PML
7688          * buffer.
7689          */
7690         kvm_for_each_vcpu(i, vcpu, kvm)
7691                 kvm_vcpu_kick(vcpu);
7692 }
7693
7694 /*
7695  * The guest has exited.  See if we can fix it or if we need userspace
7696  * assistance.
7697  */
7698 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7699 {
7700         struct vcpu_vmx *vmx = to_vmx(vcpu);
7701         u32 exit_reason = vmx->exit_reason;
7702         u32 vectoring_info = vmx->idt_vectoring_info;
7703
7704         /*
7705          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7706          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7707          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7708          * mode as if vcpus is in root mode, the PML buffer must has been
7709          * flushed already.
7710          */
7711         if (enable_pml)
7712                 vmx_flush_pml_buffer(vmx);
7713
7714         /* If guest state is invalid, start emulating */
7715         if (vmx->emulation_required)
7716                 return handle_invalid_guest_state(vcpu);
7717
7718         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7719                 nested_vmx_vmexit(vcpu, exit_reason,
7720                                   vmcs_read32(VM_EXIT_INTR_INFO),
7721                                   vmcs_readl(EXIT_QUALIFICATION));
7722                 return 1;
7723         }
7724
7725         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7726                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7727                 vcpu->run->fail_entry.hardware_entry_failure_reason
7728                         = exit_reason;
7729                 return 0;
7730         }
7731
7732         if (unlikely(vmx->fail)) {
7733                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7734                 vcpu->run->fail_entry.hardware_entry_failure_reason
7735                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7736                 return 0;
7737         }
7738
7739         /*
7740          * Note:
7741          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7742          * delivery event since it indicates guest is accessing MMIO.
7743          * The vm-exit can be triggered again after return to guest that
7744          * will cause infinite loop.
7745          */
7746         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7747                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7748                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7749                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7750                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7751                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7752                 vcpu->run->internal.ndata = 2;
7753                 vcpu->run->internal.data[0] = vectoring_info;
7754                 vcpu->run->internal.data[1] = exit_reason;
7755                 return 0;
7756         }
7757
7758         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7759             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7760                                         get_vmcs12(vcpu))))) {
7761                 if (vmx_interrupt_allowed(vcpu)) {
7762                         vmx->soft_vnmi_blocked = 0;
7763                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7764                            vcpu->arch.nmi_pending) {
7765                         /*
7766                          * This CPU don't support us in finding the end of an
7767                          * NMI-blocked window if the guest runs with IRQs
7768                          * disabled. So we pull the trigger after 1 s of
7769                          * futile waiting, but inform the user about this.
7770                          */
7771                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7772                                "state on VCPU %d after 1 s timeout\n",
7773                                __func__, vcpu->vcpu_id);
7774                         vmx->soft_vnmi_blocked = 0;
7775                 }
7776         }
7777
7778         if (exit_reason < kvm_vmx_max_exit_handlers
7779             && kvm_vmx_exit_handlers[exit_reason])
7780                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7781         else {
7782                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7783                 kvm_queue_exception(vcpu, UD_VECTOR);
7784                 return 1;
7785         }
7786 }
7787
7788 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7789 {
7790         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7791
7792         if (is_guest_mode(vcpu) &&
7793                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7794                 return;
7795
7796         if (irr == -1 || tpr < irr) {
7797                 vmcs_write32(TPR_THRESHOLD, 0);
7798                 return;
7799         }
7800
7801         vmcs_write32(TPR_THRESHOLD, irr);
7802 }
7803
7804 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7805 {
7806         u32 sec_exec_control;
7807
7808         /*
7809          * There is not point to enable virtualize x2apic without enable
7810          * apicv
7811          */
7812         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7813                                 !vmx_vm_has_apicv(vcpu->kvm))
7814                 return;
7815
7816         if (!vm_need_tpr_shadow(vcpu->kvm))
7817                 return;
7818
7819         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7820
7821         if (set) {
7822                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7823                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7824         } else {
7825                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7826                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7827         }
7828         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7829
7830         vmx_set_msr_bitmap(vcpu);
7831 }
7832
7833 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7834 {
7835         struct vcpu_vmx *vmx = to_vmx(vcpu);
7836
7837         /*
7838          * Currently we do not handle the nested case where L2 has an
7839          * APIC access page of its own; that page is still pinned.
7840          * Hence, we skip the case where the VCPU is in guest mode _and_
7841          * L1 prepared an APIC access page for L2.
7842          *
7843          * For the case where L1 and L2 share the same APIC access page
7844          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7845          * in the vmcs12), this function will only update either the vmcs01
7846          * or the vmcs02.  If the former, the vmcs02 will be updated by
7847          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7848          * the next L2->L1 exit.
7849          */
7850         if (!is_guest_mode(vcpu) ||
7851             !nested_cpu_has2(vmx->nested.current_vmcs12,
7852                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7853                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7854 }
7855
7856 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7857 {
7858         u16 status;
7859         u8 old;
7860
7861         if (isr == -1)
7862                 isr = 0;
7863
7864         status = vmcs_read16(GUEST_INTR_STATUS);
7865         old = status >> 8;
7866         if (isr != old) {
7867                 status &= 0xff;
7868                 status |= isr << 8;
7869                 vmcs_write16(GUEST_INTR_STATUS, status);
7870         }
7871 }
7872
7873 static void vmx_set_rvi(int vector)
7874 {
7875         u16 status;
7876         u8 old;
7877
7878         if (vector == -1)
7879                 vector = 0;
7880
7881         status = vmcs_read16(GUEST_INTR_STATUS);
7882         old = (u8)status & 0xff;
7883         if ((u8)vector != old) {
7884                 status &= ~0xff;
7885                 status |= (u8)vector;
7886                 vmcs_write16(GUEST_INTR_STATUS, status);
7887         }
7888 }
7889
7890 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7891 {
7892         if (!is_guest_mode(vcpu)) {
7893                 vmx_set_rvi(max_irr);
7894                 return;
7895         }
7896
7897         if (max_irr == -1)
7898                 return;
7899
7900         /*
7901          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7902          * handles it.
7903          */
7904         if (nested_exit_on_intr(vcpu))
7905                 return;
7906
7907         /*
7908          * Else, fall back to pre-APICv interrupt injection since L2
7909          * is run without virtual interrupt delivery.
7910          */
7911         if (!kvm_event_needs_reinjection(vcpu) &&
7912             vmx_interrupt_allowed(vcpu)) {
7913                 kvm_queue_interrupt(vcpu, max_irr, false);
7914                 vmx_inject_irq(vcpu);
7915         }
7916 }
7917
7918 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7919 {
7920         if (!vmx_vm_has_apicv(vcpu->kvm))
7921                 return;
7922
7923         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7924         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7925         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7926         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7927 }
7928
7929 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7930 {
7931         u32 exit_intr_info;
7932
7933         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7934               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7935                 return;
7936
7937         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7938         exit_intr_info = vmx->exit_intr_info;
7939
7940         /* Handle machine checks before interrupts are enabled */
7941         if (is_machine_check(exit_intr_info))
7942                 kvm_machine_check();
7943
7944         /* We need to handle NMIs before interrupts are enabled */
7945         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7946             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7947                 kvm_before_handle_nmi(&vmx->vcpu);
7948                 asm("int $2");
7949                 kvm_after_handle_nmi(&vmx->vcpu);
7950         }
7951 }
7952
7953 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7954 {
7955         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7956
7957         /*
7958          * If external interrupt exists, IF bit is set in rflags/eflags on the
7959          * interrupt stack frame, and interrupt will be enabled on a return
7960          * from interrupt handler.
7961          */
7962         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7963                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7964                 unsigned int vector;
7965                 unsigned long entry;
7966                 gate_desc *desc;
7967                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7968 #ifdef CONFIG_X86_64
7969                 unsigned long tmp;
7970 #endif
7971
7972                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7973                 desc = (gate_desc *)vmx->host_idt_base + vector;
7974                 entry = gate_offset(*desc);
7975                 asm volatile(
7976 #ifdef CONFIG_X86_64
7977                         "mov %%" _ASM_SP ", %[sp]\n\t"
7978                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7979                         "push $%c[ss]\n\t"
7980                         "push %[sp]\n\t"
7981 #endif
7982                         "pushf\n\t"
7983                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7984                         __ASM_SIZE(push) " $%c[cs]\n\t"
7985                         "call *%[entry]\n\t"
7986                         :
7987 #ifdef CONFIG_X86_64
7988                         [sp]"=&r"(tmp)
7989 #endif
7990                         :
7991                         [entry]"r"(entry),
7992                         [ss]"i"(__KERNEL_DS),
7993                         [cs]"i"(__KERNEL_CS)
7994                         );
7995         } else
7996                 local_irq_enable();
7997 }
7998
7999 static bool vmx_mpx_supported(void)
8000 {
8001         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8002                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8003 }
8004
8005 static bool vmx_xsaves_supported(void)
8006 {
8007         return vmcs_config.cpu_based_2nd_exec_ctrl &
8008                 SECONDARY_EXEC_XSAVES;
8009 }
8010
8011 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8012 {
8013         u32 exit_intr_info;
8014         bool unblock_nmi;
8015         u8 vector;
8016         bool idtv_info_valid;
8017
8018         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8019
8020         if (cpu_has_virtual_nmis()) {
8021                 if (vmx->nmi_known_unmasked)
8022                         return;
8023                 /*
8024                  * Can't use vmx->exit_intr_info since we're not sure what
8025                  * the exit reason is.
8026                  */
8027                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8028                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8029                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8030                 /*
8031                  * SDM 3: 27.7.1.2 (September 2008)
8032                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8033                  * a guest IRET fault.
8034                  * SDM 3: 23.2.2 (September 2008)
8035                  * Bit 12 is undefined in any of the following cases:
8036                  *  If the VM exit sets the valid bit in the IDT-vectoring
8037                  *   information field.
8038                  *  If the VM exit is due to a double fault.
8039                  */
8040                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8041                     vector != DF_VECTOR && !idtv_info_valid)
8042                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8043                                       GUEST_INTR_STATE_NMI);
8044                 else
8045                         vmx->nmi_known_unmasked =
8046                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8047                                   & GUEST_INTR_STATE_NMI);
8048         } else if (unlikely(vmx->soft_vnmi_blocked))
8049                 vmx->vnmi_blocked_time +=
8050                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8051 }
8052
8053 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8054                                       u32 idt_vectoring_info,
8055                                       int instr_len_field,
8056                                       int error_code_field)
8057 {
8058         u8 vector;
8059         int type;
8060         bool idtv_info_valid;
8061
8062         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8063
8064         vcpu->arch.nmi_injected = false;
8065         kvm_clear_exception_queue(vcpu);
8066         kvm_clear_interrupt_queue(vcpu);
8067
8068         if (!idtv_info_valid)
8069                 return;
8070
8071         kvm_make_request(KVM_REQ_EVENT, vcpu);
8072
8073         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8074         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8075
8076         switch (type) {
8077         case INTR_TYPE_NMI_INTR:
8078                 vcpu->arch.nmi_injected = true;
8079                 /*
8080                  * SDM 3: 27.7.1.2 (September 2008)
8081                  * Clear bit "block by NMI" before VM entry if a NMI
8082                  * delivery faulted.
8083                  */
8084                 vmx_set_nmi_mask(vcpu, false);
8085                 break;
8086         case INTR_TYPE_SOFT_EXCEPTION:
8087                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8088                 /* fall through */
8089         case INTR_TYPE_HARD_EXCEPTION:
8090                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8091                         u32 err = vmcs_read32(error_code_field);
8092                         kvm_requeue_exception_e(vcpu, vector, err);
8093                 } else
8094                         kvm_requeue_exception(vcpu, vector);
8095                 break;
8096         case INTR_TYPE_SOFT_INTR:
8097                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8098                 /* fall through */
8099         case INTR_TYPE_EXT_INTR:
8100                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8101                 break;
8102         default:
8103                 break;
8104         }
8105 }
8106
8107 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8108 {
8109         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8110                                   VM_EXIT_INSTRUCTION_LEN,
8111                                   IDT_VECTORING_ERROR_CODE);
8112 }
8113
8114 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8115 {
8116         __vmx_complete_interrupts(vcpu,
8117                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8118                                   VM_ENTRY_INSTRUCTION_LEN,
8119                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8120
8121         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8122 }
8123
8124 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8125 {
8126         int i, nr_msrs;
8127         struct perf_guest_switch_msr *msrs;
8128
8129         msrs = perf_guest_get_msrs(&nr_msrs);
8130
8131         if (!msrs)
8132                 return;
8133
8134         for (i = 0; i < nr_msrs; i++)
8135                 if (msrs[i].host == msrs[i].guest)
8136                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8137                 else
8138                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8139                                         msrs[i].host);
8140 }
8141
8142 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8143 {
8144         struct vcpu_vmx *vmx = to_vmx(vcpu);
8145         unsigned long debugctlmsr, cr4;
8146
8147         /* Record the guest's net vcpu time for enforced NMI injections. */
8148         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8149                 vmx->entry_time = ktime_get();
8150
8151         /* Don't enter VMX if guest state is invalid, let the exit handler
8152            start emulation until we arrive back to a valid state */
8153         if (vmx->emulation_required)
8154                 return;
8155
8156         if (vmx->ple_window_dirty) {
8157                 vmx->ple_window_dirty = false;
8158                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8159         }
8160
8161         if (vmx->nested.sync_shadow_vmcs) {
8162                 copy_vmcs12_to_shadow(vmx);
8163                 vmx->nested.sync_shadow_vmcs = false;
8164         }
8165
8166         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8167                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8168         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8169                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8170
8171         cr4 = cr4_read_shadow();
8172         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8173                 vmcs_writel(HOST_CR4, cr4);
8174                 vmx->host_state.vmcs_host_cr4 = cr4;
8175         }
8176
8177         /* When single-stepping over STI and MOV SS, we must clear the
8178          * corresponding interruptibility bits in the guest state. Otherwise
8179          * vmentry fails as it then expects bit 14 (BS) in pending debug
8180          * exceptions being set, but that's not correct for the guest debugging
8181          * case. */
8182         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8183                 vmx_set_interrupt_shadow(vcpu, 0);
8184
8185         atomic_switch_perf_msrs(vmx);
8186         debugctlmsr = get_debugctlmsr();
8187
8188         vmx->__launched = vmx->loaded_vmcs->launched;
8189         asm(
8190                 /* Store host registers */
8191                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8192                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8193                 "push %%" _ASM_CX " \n\t"
8194                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8195                 "je 1f \n\t"
8196                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8197                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8198                 "1: \n\t"
8199                 /* Reload cr2 if changed */
8200                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8201                 "mov %%cr2, %%" _ASM_DX " \n\t"
8202                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8203                 "je 2f \n\t"
8204                 "mov %%" _ASM_AX", %%cr2 \n\t"
8205                 "2: \n\t"
8206                 /* Check if vmlaunch of vmresume is needed */
8207                 "cmpl $0, %c[launched](%0) \n\t"
8208                 /* Load guest registers.  Don't clobber flags. */
8209                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8210                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8211                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8212                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8213                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8214                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8215 #ifdef CONFIG_X86_64
8216                 "mov %c[r8](%0),  %%r8  \n\t"
8217                 "mov %c[r9](%0),  %%r9  \n\t"
8218                 "mov %c[r10](%0), %%r10 \n\t"
8219                 "mov %c[r11](%0), %%r11 \n\t"
8220                 "mov %c[r12](%0), %%r12 \n\t"
8221                 "mov %c[r13](%0), %%r13 \n\t"
8222                 "mov %c[r14](%0), %%r14 \n\t"
8223                 "mov %c[r15](%0), %%r15 \n\t"
8224 #endif
8225                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8226
8227                 /* Enter guest mode */
8228                 "jne 1f \n\t"
8229                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8230                 "jmp 2f \n\t"
8231                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8232                 "2: "
8233                 /* Save guest registers, load host registers, keep flags */
8234                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8235                 "pop %0 \n\t"
8236                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8237                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8238                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8239                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8240                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8241                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8242                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8243 #ifdef CONFIG_X86_64
8244                 "mov %%r8,  %c[r8](%0) \n\t"
8245                 "mov %%r9,  %c[r9](%0) \n\t"
8246                 "mov %%r10, %c[r10](%0) \n\t"
8247                 "mov %%r11, %c[r11](%0) \n\t"
8248                 "mov %%r12, %c[r12](%0) \n\t"
8249                 "mov %%r13, %c[r13](%0) \n\t"
8250                 "mov %%r14, %c[r14](%0) \n\t"
8251                 "mov %%r15, %c[r15](%0) \n\t"
8252 #endif
8253                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8254                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8255
8256                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8257                 "setbe %c[fail](%0) \n\t"
8258                 ".pushsection .rodata \n\t"
8259                 ".global vmx_return \n\t"
8260                 "vmx_return: " _ASM_PTR " 2b \n\t"
8261                 ".popsection"
8262               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8263                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8264                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8265                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8266                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8267                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8268                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8269                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8270                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8271                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8272                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8273 #ifdef CONFIG_X86_64
8274                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8275                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8276                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8277                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8278                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8279                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8280                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8281                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8282 #endif
8283                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8284                 [wordsize]"i"(sizeof(ulong))
8285               : "cc", "memory"
8286 #ifdef CONFIG_X86_64
8287                 , "rax", "rbx", "rdi", "rsi"
8288                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8289 #else
8290                 , "eax", "ebx", "edi", "esi"
8291 #endif
8292               );
8293
8294         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8295         if (debugctlmsr)
8296                 update_debugctlmsr(debugctlmsr);
8297
8298 #ifndef CONFIG_X86_64
8299         /*
8300          * The sysexit path does not restore ds/es, so we must set them to
8301          * a reasonable value ourselves.
8302          *
8303          * We can't defer this to vmx_load_host_state() since that function
8304          * may be executed in interrupt context, which saves and restore segments
8305          * around it, nullifying its effect.
8306          */
8307         loadsegment(ds, __USER_DS);
8308         loadsegment(es, __USER_DS);
8309 #endif
8310
8311         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8312                                   | (1 << VCPU_EXREG_RFLAGS)
8313                                   | (1 << VCPU_EXREG_PDPTR)
8314                                   | (1 << VCPU_EXREG_SEGMENTS)
8315                                   | (1 << VCPU_EXREG_CR3));
8316         vcpu->arch.regs_dirty = 0;
8317
8318         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8319
8320         vmx->loaded_vmcs->launched = 1;
8321
8322         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8323         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8324
8325         /*
8326          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8327          * we did not inject a still-pending event to L1 now because of
8328          * nested_run_pending, we need to re-enable this bit.
8329          */
8330         if (vmx->nested.nested_run_pending)
8331                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8332
8333         vmx->nested.nested_run_pending = 0;
8334
8335         vmx_complete_atomic_exit(vmx);
8336         vmx_recover_nmi_blocking(vmx);
8337         vmx_complete_interrupts(vmx);
8338 }
8339
8340 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8341 {
8342         struct vcpu_vmx *vmx = to_vmx(vcpu);
8343         int cpu;
8344
8345         if (vmx->loaded_vmcs == &vmx->vmcs01)
8346                 return;
8347
8348         cpu = get_cpu();
8349         vmx->loaded_vmcs = &vmx->vmcs01;
8350         vmx_vcpu_put(vcpu);
8351         vmx_vcpu_load(vcpu, cpu);
8352         vcpu->cpu = cpu;
8353         put_cpu();
8354 }
8355
8356 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8357 {
8358         struct vcpu_vmx *vmx = to_vmx(vcpu);
8359
8360         if (enable_pml)
8361                 vmx_disable_pml(vmx);
8362         free_vpid(vmx);
8363         leave_guest_mode(vcpu);
8364         vmx_load_vmcs01(vcpu);
8365         free_nested(vmx);
8366         free_loaded_vmcs(vmx->loaded_vmcs);
8367         kfree(vmx->guest_msrs);
8368         kvm_vcpu_uninit(vcpu);
8369         kmem_cache_free(kvm_vcpu_cache, vmx);
8370 }
8371
8372 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8373 {
8374         int err;
8375         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8376         int cpu;
8377
8378         if (!vmx)
8379                 return ERR_PTR(-ENOMEM);
8380
8381         allocate_vpid(vmx);
8382
8383         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8384         if (err)
8385                 goto free_vcpu;
8386
8387         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8388         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8389                      > PAGE_SIZE);
8390
8391         err = -ENOMEM;
8392         if (!vmx->guest_msrs) {
8393                 goto uninit_vcpu;
8394         }
8395
8396         vmx->loaded_vmcs = &vmx->vmcs01;
8397         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8398         if (!vmx->loaded_vmcs->vmcs)
8399                 goto free_msrs;
8400         if (!vmm_exclusive)
8401                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8402         loaded_vmcs_init(vmx->loaded_vmcs);
8403         if (!vmm_exclusive)
8404                 kvm_cpu_vmxoff();
8405
8406         cpu = get_cpu();
8407         vmx_vcpu_load(&vmx->vcpu, cpu);
8408         vmx->vcpu.cpu = cpu;
8409         err = vmx_vcpu_setup(vmx);
8410         vmx_vcpu_put(&vmx->vcpu);
8411         put_cpu();
8412         if (err)
8413                 goto free_vmcs;
8414         if (vm_need_virtualize_apic_accesses(kvm)) {
8415                 err = alloc_apic_access_page(kvm);
8416                 if (err)
8417                         goto free_vmcs;
8418         }
8419
8420         if (enable_ept) {
8421                 if (!kvm->arch.ept_identity_map_addr)
8422                         kvm->arch.ept_identity_map_addr =
8423                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8424                 err = init_rmode_identity_map(kvm);
8425                 if (err)
8426                         goto free_vmcs;
8427         }
8428
8429         if (nested)
8430                 nested_vmx_setup_ctls_msrs(vmx);
8431
8432         vmx->nested.posted_intr_nv = -1;
8433         vmx->nested.current_vmptr = -1ull;
8434         vmx->nested.current_vmcs12 = NULL;
8435
8436         /*
8437          * If PML is turned on, failure on enabling PML just results in failure
8438          * of creating the vcpu, therefore we can simplify PML logic (by
8439          * avoiding dealing with cases, such as enabling PML partially on vcpus
8440          * for the guest, etc.
8441          */
8442         if (enable_pml) {
8443                 err = vmx_enable_pml(vmx);
8444                 if (err)
8445                         goto free_vmcs;
8446         }
8447
8448         return &vmx->vcpu;
8449
8450 free_vmcs:
8451         free_loaded_vmcs(vmx->loaded_vmcs);
8452 free_msrs:
8453         kfree(vmx->guest_msrs);
8454 uninit_vcpu:
8455         kvm_vcpu_uninit(&vmx->vcpu);
8456 free_vcpu:
8457         free_vpid(vmx);
8458         kmem_cache_free(kvm_vcpu_cache, vmx);
8459         return ERR_PTR(err);
8460 }
8461
8462 static void __init vmx_check_processor_compat(void *rtn)
8463 {
8464         struct vmcs_config vmcs_conf;
8465
8466         *(int *)rtn = 0;
8467         if (setup_vmcs_config(&vmcs_conf) < 0)
8468                 *(int *)rtn = -EIO;
8469         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8470                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8471                                 smp_processor_id());
8472                 *(int *)rtn = -EIO;
8473         }
8474 }
8475
8476 static int get_ept_level(void)
8477 {
8478         return VMX_EPT_DEFAULT_GAW + 1;
8479 }
8480
8481 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8482 {
8483         u64 ret;
8484
8485         /* For VT-d and EPT combination
8486          * 1. MMIO: always map as UC
8487          * 2. EPT with VT-d:
8488          *   a. VT-d without snooping control feature: can't guarantee the
8489          *      result, try to trust guest.
8490          *   b. VT-d with snooping control feature: snooping control feature of
8491          *      VT-d engine can guarantee the cache correctness. Just set it
8492          *      to WB to keep consistent with host. So the same as item 3.
8493          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8494          *    consistent with host MTRR
8495          */
8496         if (is_mmio)
8497                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8498         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8499                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8500                       VMX_EPT_MT_EPTE_SHIFT;
8501         else
8502                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8503                         | VMX_EPT_IPAT_BIT;
8504
8505         return ret;
8506 }
8507
8508 static int vmx_get_lpage_level(void)
8509 {
8510         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8511                 return PT_DIRECTORY_LEVEL;
8512         else
8513                 /* For shadow and EPT supported 1GB page */
8514                 return PT_PDPE_LEVEL;
8515 }
8516
8517 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8518 {
8519         struct kvm_cpuid_entry2 *best;
8520         struct vcpu_vmx *vmx = to_vmx(vcpu);
8521         u32 exec_control;
8522
8523         vmx->rdtscp_enabled = false;
8524         if (vmx_rdtscp_supported()) {
8525                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8526                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8527                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8528                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8529                                 vmx->rdtscp_enabled = true;
8530                         else {
8531                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8532                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8533                                                 exec_control);
8534                         }
8535                 }
8536                 if (nested && !vmx->rdtscp_enabled)
8537                         vmx->nested.nested_vmx_secondary_ctls_high &=
8538                                 ~SECONDARY_EXEC_RDTSCP;
8539         }
8540
8541         /* Exposing INVPCID only when PCID is exposed */
8542         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8543         if (vmx_invpcid_supported() &&
8544             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8545             guest_cpuid_has_pcid(vcpu)) {
8546                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8547                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8548                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8549                              exec_control);
8550         } else {
8551                 if (cpu_has_secondary_exec_ctrls()) {
8552                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8553                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8554                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8555                                      exec_control);
8556                 }
8557                 if (best)
8558                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8559         }
8560 }
8561
8562 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8563 {
8564         if (func == 1 && nested)
8565                 entry->ecx |= bit(X86_FEATURE_VMX);
8566 }
8567
8568 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8569                 struct x86_exception *fault)
8570 {
8571         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8572         u32 exit_reason;
8573
8574         if (fault->error_code & PFERR_RSVD_MASK)
8575                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8576         else
8577                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8578         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8579         vmcs12->guest_physical_address = fault->address;
8580 }
8581
8582 /* Callbacks for nested_ept_init_mmu_context: */
8583
8584 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8585 {
8586         /* return the page table to be shadowed - in our case, EPT12 */
8587         return get_vmcs12(vcpu)->ept_pointer;
8588 }
8589
8590 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8591 {
8592         WARN_ON(mmu_is_nested(vcpu));
8593         kvm_init_shadow_ept_mmu(vcpu,
8594                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8595                         VMX_EPT_EXECUTE_ONLY_BIT);
8596         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8597         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8598         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8599
8600         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8601 }
8602
8603 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8604 {
8605         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8606 }
8607
8608 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8609                                             u16 error_code)
8610 {
8611         bool inequality, bit;
8612
8613         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8614         inequality =
8615                 (error_code & vmcs12->page_fault_error_code_mask) !=
8616                  vmcs12->page_fault_error_code_match;
8617         return inequality ^ bit;
8618 }
8619
8620 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8621                 struct x86_exception *fault)
8622 {
8623         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8624
8625         WARN_ON(!is_guest_mode(vcpu));
8626
8627         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8628                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8629                                   vmcs_read32(VM_EXIT_INTR_INFO),
8630                                   vmcs_readl(EXIT_QUALIFICATION));
8631         else
8632                 kvm_inject_page_fault(vcpu, fault);
8633 }
8634
8635 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8636                                         struct vmcs12 *vmcs12)
8637 {
8638         struct vcpu_vmx *vmx = to_vmx(vcpu);
8639         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8640
8641         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8642                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8643                     vmcs12->apic_access_addr >> maxphyaddr)
8644                         return false;
8645
8646                 /*
8647                  * Translate L1 physical address to host physical
8648                  * address for vmcs02. Keep the page pinned, so this
8649                  * physical address remains valid. We keep a reference
8650                  * to it so we can release it later.
8651                  */
8652                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8653                         nested_release_page(vmx->nested.apic_access_page);
8654                 vmx->nested.apic_access_page =
8655                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8656         }
8657
8658         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8659                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8660                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
8661                         return false;
8662
8663                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8664                         nested_release_page(vmx->nested.virtual_apic_page);
8665                 vmx->nested.virtual_apic_page =
8666                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8667
8668                 /*
8669                  * Failing the vm entry is _not_ what the processor does
8670                  * but it's basically the only possibility we have.
8671                  * We could still enter the guest if CR8 load exits are
8672                  * enabled, CR8 store exits are enabled, and virtualize APIC
8673                  * access is disabled; in this case the processor would never
8674                  * use the TPR shadow and we could simply clear the bit from
8675                  * the execution control.  But such a configuration is useless,
8676                  * so let's keep the code simple.
8677                  */
8678                 if (!vmx->nested.virtual_apic_page)
8679                         return false;
8680         }
8681
8682         if (nested_cpu_has_posted_intr(vmcs12)) {
8683                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8684                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
8685                         return false;
8686
8687                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8688                         kunmap(vmx->nested.pi_desc_page);
8689                         nested_release_page(vmx->nested.pi_desc_page);
8690                 }
8691                 vmx->nested.pi_desc_page =
8692                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8693                 if (!vmx->nested.pi_desc_page)
8694                         return false;
8695
8696                 vmx->nested.pi_desc =
8697                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8698                 if (!vmx->nested.pi_desc) {
8699                         nested_release_page_clean(vmx->nested.pi_desc_page);
8700                         return false;
8701                 }
8702                 vmx->nested.pi_desc =
8703                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8704                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8705                         (PAGE_SIZE - 1)));
8706         }
8707
8708         return true;
8709 }
8710
8711 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8712 {
8713         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8714         struct vcpu_vmx *vmx = to_vmx(vcpu);
8715
8716         if (vcpu->arch.virtual_tsc_khz == 0)
8717                 return;
8718
8719         /* Make sure short timeouts reliably trigger an immediate vmexit.
8720          * hrtimer_start does not guarantee this. */
8721         if (preemption_timeout <= 1) {
8722                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8723                 return;
8724         }
8725
8726         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8727         preemption_timeout *= 1000000;
8728         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8729         hrtimer_start(&vmx->nested.preemption_timer,
8730                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8731 }
8732
8733 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8734                                                 struct vmcs12 *vmcs12)
8735 {
8736         int maxphyaddr;
8737         u64 addr;
8738
8739         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8740                 return 0;
8741
8742         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8743                 WARN_ON(1);
8744                 return -EINVAL;
8745         }
8746         maxphyaddr = cpuid_maxphyaddr(vcpu);
8747
8748         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8749            ((addr + PAGE_SIZE) >> maxphyaddr))
8750                 return -EINVAL;
8751
8752         return 0;
8753 }
8754
8755 /*
8756  * Merge L0's and L1's MSR bitmap, return false to indicate that
8757  * we do not use the hardware.
8758  */
8759 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8760                                                struct vmcs12 *vmcs12)
8761 {
8762         int msr;
8763         struct page *page;
8764         unsigned long *msr_bitmap;
8765
8766         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8767                 return false;
8768
8769         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8770         if (!page) {
8771                 WARN_ON(1);
8772                 return false;
8773         }
8774         msr_bitmap = (unsigned long *)kmap(page);
8775         if (!msr_bitmap) {
8776                 nested_release_page_clean(page);
8777                 WARN_ON(1);
8778                 return false;
8779         }
8780
8781         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8782                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8783                         for (msr = 0x800; msr <= 0x8ff; msr++)
8784                                 nested_vmx_disable_intercept_for_msr(
8785                                         msr_bitmap,
8786                                         vmx_msr_bitmap_nested,
8787                                         msr, MSR_TYPE_R);
8788                 /* TPR is allowed */
8789                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8790                                 vmx_msr_bitmap_nested,
8791                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8792                                 MSR_TYPE_R | MSR_TYPE_W);
8793                 if (nested_cpu_has_vid(vmcs12)) {
8794                         /* EOI and self-IPI are allowed */
8795                         nested_vmx_disable_intercept_for_msr(
8796                                 msr_bitmap,
8797                                 vmx_msr_bitmap_nested,
8798                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8799                                 MSR_TYPE_W);
8800                         nested_vmx_disable_intercept_for_msr(
8801                                 msr_bitmap,
8802                                 vmx_msr_bitmap_nested,
8803                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8804                                 MSR_TYPE_W);
8805                 }
8806         } else {
8807                 /*
8808                  * Enable reading intercept of all the x2apic
8809                  * MSRs. We should not rely on vmcs12 to do any
8810                  * optimizations here, it may have been modified
8811                  * by L1.
8812                  */
8813                 for (msr = 0x800; msr <= 0x8ff; msr++)
8814                         __vmx_enable_intercept_for_msr(
8815                                 vmx_msr_bitmap_nested,
8816                                 msr,
8817                                 MSR_TYPE_R);
8818
8819                 __vmx_enable_intercept_for_msr(
8820                                 vmx_msr_bitmap_nested,
8821                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8822                                 MSR_TYPE_W);
8823                 __vmx_enable_intercept_for_msr(
8824                                 vmx_msr_bitmap_nested,
8825                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8826                                 MSR_TYPE_W);
8827                 __vmx_enable_intercept_for_msr(
8828                                 vmx_msr_bitmap_nested,
8829                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8830                                 MSR_TYPE_W);
8831         }
8832         kunmap(page);
8833         nested_release_page_clean(page);
8834
8835         return true;
8836 }
8837
8838 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8839                                            struct vmcs12 *vmcs12)
8840 {
8841         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8842             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8843             !nested_cpu_has_vid(vmcs12) &&
8844             !nested_cpu_has_posted_intr(vmcs12))
8845                 return 0;
8846
8847         /*
8848          * If virtualize x2apic mode is enabled,
8849          * virtualize apic access must be disabled.
8850          */
8851         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8852             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8853                 return -EINVAL;
8854
8855         /*
8856          * If virtual interrupt delivery is enabled,
8857          * we must exit on external interrupts.
8858          */
8859         if (nested_cpu_has_vid(vmcs12) &&
8860            !nested_exit_on_intr(vcpu))
8861                 return -EINVAL;
8862
8863         /*
8864          * bits 15:8 should be zero in posted_intr_nv,
8865          * the descriptor address has been already checked
8866          * in nested_get_vmcs12_pages.
8867          */
8868         if (nested_cpu_has_posted_intr(vmcs12) &&
8869            (!nested_cpu_has_vid(vmcs12) ||
8870             !nested_exit_intr_ack_set(vcpu) ||
8871             vmcs12->posted_intr_nv & 0xff00))
8872                 return -EINVAL;
8873
8874         /* tpr shadow is needed by all apicv features. */
8875         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8876                 return -EINVAL;
8877
8878         return 0;
8879 }
8880
8881 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8882                                        unsigned long count_field,
8883                                        unsigned long addr_field)
8884 {
8885         int maxphyaddr;
8886         u64 count, addr;
8887
8888         if (vmcs12_read_any(vcpu, count_field, &count) ||
8889             vmcs12_read_any(vcpu, addr_field, &addr)) {
8890                 WARN_ON(1);
8891                 return -EINVAL;
8892         }
8893         if (count == 0)
8894                 return 0;
8895         maxphyaddr = cpuid_maxphyaddr(vcpu);
8896         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8897             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8898                 pr_warn_ratelimited(
8899                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8900                         addr_field, maxphyaddr, count, addr);
8901                 return -EINVAL;
8902         }
8903         return 0;
8904 }
8905
8906 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8907                                                 struct vmcs12 *vmcs12)
8908 {
8909         if (vmcs12->vm_exit_msr_load_count == 0 &&
8910             vmcs12->vm_exit_msr_store_count == 0 &&
8911             vmcs12->vm_entry_msr_load_count == 0)
8912                 return 0; /* Fast path */
8913         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8914                                         VM_EXIT_MSR_LOAD_ADDR) ||
8915             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8916                                         VM_EXIT_MSR_STORE_ADDR) ||
8917             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8918                                         VM_ENTRY_MSR_LOAD_ADDR))
8919                 return -EINVAL;
8920         return 0;
8921 }
8922
8923 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8924                                        struct vmx_msr_entry *e)
8925 {
8926         /* x2APIC MSR accesses are not allowed */
8927         if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8928                 return -EINVAL;
8929         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8930             e->index == MSR_IA32_UCODE_REV)
8931                 return -EINVAL;
8932         if (e->reserved != 0)
8933                 return -EINVAL;
8934         return 0;
8935 }
8936
8937 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8938                                      struct vmx_msr_entry *e)
8939 {
8940         if (e->index == MSR_FS_BASE ||
8941             e->index == MSR_GS_BASE ||
8942             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8943             nested_vmx_msr_check_common(vcpu, e))
8944                 return -EINVAL;
8945         return 0;
8946 }
8947
8948 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8949                                       struct vmx_msr_entry *e)
8950 {
8951         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8952             nested_vmx_msr_check_common(vcpu, e))
8953                 return -EINVAL;
8954         return 0;
8955 }
8956
8957 /*
8958  * Load guest's/host's msr at nested entry/exit.
8959  * return 0 for success, entry index for failure.
8960  */
8961 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8962 {
8963         u32 i;
8964         struct vmx_msr_entry e;
8965         struct msr_data msr;
8966
8967         msr.host_initiated = false;
8968         for (i = 0; i < count; i++) {
8969                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8970                                    &e, sizeof(e))) {
8971                         pr_warn_ratelimited(
8972                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8973                                 __func__, i, gpa + i * sizeof(e));
8974                         goto fail;
8975                 }
8976                 if (nested_vmx_load_msr_check(vcpu, &e)) {
8977                         pr_warn_ratelimited(
8978                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8979                                 __func__, i, e.index, e.reserved);
8980                         goto fail;
8981                 }
8982                 msr.index = e.index;
8983                 msr.data = e.value;
8984                 if (kvm_set_msr(vcpu, &msr)) {
8985                         pr_warn_ratelimited(
8986                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8987                                 __func__, i, e.index, e.value);
8988                         goto fail;
8989                 }
8990         }
8991         return 0;
8992 fail:
8993         return i + 1;
8994 }
8995
8996 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8997 {
8998         u32 i;
8999         struct vmx_msr_entry e;
9000
9001         for (i = 0; i < count; i++) {
9002                 if (kvm_read_guest(vcpu->kvm,
9003                                    gpa + i * sizeof(e),
9004                                    &e, 2 * sizeof(u32))) {
9005                         pr_warn_ratelimited(
9006                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9007                                 __func__, i, gpa + i * sizeof(e));
9008                         return -EINVAL;
9009                 }
9010                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9011                         pr_warn_ratelimited(
9012                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9013                                 __func__, i, e.index, e.reserved);
9014                         return -EINVAL;
9015                 }
9016                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9017                         pr_warn_ratelimited(
9018                                 "%s cannot read MSR (%u, 0x%x)\n",
9019                                 __func__, i, e.index);
9020                         return -EINVAL;
9021                 }
9022                 if (kvm_write_guest(vcpu->kvm,
9023                                     gpa + i * sizeof(e) +
9024                                         offsetof(struct vmx_msr_entry, value),
9025                                     &e.value, sizeof(e.value))) {
9026                         pr_warn_ratelimited(
9027                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9028                                 __func__, i, e.index, e.value);
9029                         return -EINVAL;
9030                 }
9031         }
9032         return 0;
9033 }
9034
9035 /*
9036  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9037  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9038  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9039  * guest in a way that will both be appropriate to L1's requests, and our
9040  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9041  * function also has additional necessary side-effects, like setting various
9042  * vcpu->arch fields.
9043  */
9044 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9045 {
9046         struct vcpu_vmx *vmx = to_vmx(vcpu);
9047         u32 exec_control;
9048
9049         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9050         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9051         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9052         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9053         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9054         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9055         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9056         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9057         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9058         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9059         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9060         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9061         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9062         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9063         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9064         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9065         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9066         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9067         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9068         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9069         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9070         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9071         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9072         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9073         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9074         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9075         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9076         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9077         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9078         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9079         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9080         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9081         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9082         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9083         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9084         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9085
9086         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9087                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9088                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9089         } else {
9090                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9091                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9092         }
9093         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9094                 vmcs12->vm_entry_intr_info_field);
9095         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9096                 vmcs12->vm_entry_exception_error_code);
9097         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9098                 vmcs12->vm_entry_instruction_len);
9099         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9100                 vmcs12->guest_interruptibility_info);
9101         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9102         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9103         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9104                 vmcs12->guest_pending_dbg_exceptions);
9105         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9106         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9107
9108         if (nested_cpu_has_xsaves(vmcs12))
9109                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9110         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9111
9112         exec_control = vmcs12->pin_based_vm_exec_control;
9113         exec_control |= vmcs_config.pin_based_exec_ctrl;
9114         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9115
9116         if (nested_cpu_has_posted_intr(vmcs12)) {
9117                 /*
9118                  * Note that we use L0's vector here and in
9119                  * vmx_deliver_nested_posted_interrupt.
9120                  */
9121                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9122                 vmx->nested.pi_pending = false;
9123                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9124                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9125                         page_to_phys(vmx->nested.pi_desc_page) +
9126                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9127                         (PAGE_SIZE - 1)));
9128         } else
9129                 exec_control &= ~PIN_BASED_POSTED_INTR;
9130
9131         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9132
9133         vmx->nested.preemption_timer_expired = false;
9134         if (nested_cpu_has_preemption_timer(vmcs12))
9135                 vmx_start_preemption_timer(vcpu);
9136
9137         /*
9138          * Whether page-faults are trapped is determined by a combination of
9139          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9140          * If enable_ept, L0 doesn't care about page faults and we should
9141          * set all of these to L1's desires. However, if !enable_ept, L0 does
9142          * care about (at least some) page faults, and because it is not easy
9143          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9144          * to exit on each and every L2 page fault. This is done by setting
9145          * MASK=MATCH=0 and (see below) EB.PF=1.
9146          * Note that below we don't need special code to set EB.PF beyond the
9147          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9148          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9149          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9150          *
9151          * A problem with this approach (when !enable_ept) is that L1 may be
9152          * injected with more page faults than it asked for. This could have
9153          * caused problems, but in practice existing hypervisors don't care.
9154          * To fix this, we will need to emulate the PFEC checking (on the L1
9155          * page tables), using walk_addr(), when injecting PFs to L1.
9156          */
9157         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9158                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9159         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9160                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9161
9162         if (cpu_has_secondary_exec_ctrls()) {
9163                 exec_control = vmx_secondary_exec_control(vmx);
9164                 if (!vmx->rdtscp_enabled)
9165                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9166                 /* Take the following fields only from vmcs12 */
9167                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9168                                   SECONDARY_EXEC_RDTSCP |
9169                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9170                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9171                 if (nested_cpu_has(vmcs12,
9172                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9173                         exec_control |= vmcs12->secondary_vm_exec_control;
9174
9175                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9176                         /*
9177                          * If translation failed, no matter: This feature asks
9178                          * to exit when accessing the given address, and if it
9179                          * can never be accessed, this feature won't do
9180                          * anything anyway.
9181                          */
9182                         if (!vmx->nested.apic_access_page)
9183                                 exec_control &=
9184                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9185                         else
9186                                 vmcs_write64(APIC_ACCESS_ADDR,
9187                                   page_to_phys(vmx->nested.apic_access_page));
9188                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9189                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9190                         exec_control |=
9191                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9192                         kvm_vcpu_reload_apic_access_page(vcpu);
9193                 }
9194
9195                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9196                         vmcs_write64(EOI_EXIT_BITMAP0,
9197                                 vmcs12->eoi_exit_bitmap0);
9198                         vmcs_write64(EOI_EXIT_BITMAP1,
9199                                 vmcs12->eoi_exit_bitmap1);
9200                         vmcs_write64(EOI_EXIT_BITMAP2,
9201                                 vmcs12->eoi_exit_bitmap2);
9202                         vmcs_write64(EOI_EXIT_BITMAP3,
9203                                 vmcs12->eoi_exit_bitmap3);
9204                         vmcs_write16(GUEST_INTR_STATUS,
9205                                 vmcs12->guest_intr_status);
9206                 }
9207
9208                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9209         }
9210
9211
9212         /*
9213          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9214          * Some constant fields are set here by vmx_set_constant_host_state().
9215          * Other fields are different per CPU, and will be set later when
9216          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9217          */
9218         vmx_set_constant_host_state(vmx);
9219
9220         /*
9221          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9222          * entry, but only if the current (host) sp changed from the value
9223          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9224          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9225          * here we just force the write to happen on entry.
9226          */
9227         vmx->host_rsp = 0;
9228
9229         exec_control = vmx_exec_control(vmx); /* L0's desires */
9230         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9231         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9232         exec_control &= ~CPU_BASED_TPR_SHADOW;
9233         exec_control |= vmcs12->cpu_based_vm_exec_control;
9234
9235         if (exec_control & CPU_BASED_TPR_SHADOW) {
9236                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9237                                 page_to_phys(vmx->nested.virtual_apic_page));
9238                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9239         }
9240
9241         if (cpu_has_vmx_msr_bitmap() &&
9242             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9243                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9244                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9245         } else
9246                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9247
9248         /*
9249          * Merging of IO bitmap not currently supported.
9250          * Rather, exit every time.
9251          */
9252         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9253         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9254
9255         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9256
9257         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9258          * bitwise-or of what L1 wants to trap for L2, and what we want to
9259          * trap. Note that CR0.TS also needs updating - we do this later.
9260          */
9261         update_exception_bitmap(vcpu);
9262         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9263         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9264
9265         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9266          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9267          * bits are further modified by vmx_set_efer() below.
9268          */
9269         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9270
9271         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9272          * emulated by vmx_set_efer(), below.
9273          */
9274         vm_entry_controls_init(vmx,
9275                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9276                         ~VM_ENTRY_IA32E_MODE) |
9277                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9278
9279         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9280                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9281                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9282         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9283                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9284
9285
9286         set_cr4_guest_host_mask(vmx);
9287
9288         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9289                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9290
9291         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9292                 vmcs_write64(TSC_OFFSET,
9293                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9294         else
9295                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9296
9297         if (enable_vpid) {
9298                 /*
9299                  * Trivially support vpid by letting L2s share their parent
9300                  * L1's vpid. TODO: move to a more elaborate solution, giving
9301                  * each L2 its own vpid and exposing the vpid feature to L1.
9302                  */
9303                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9304                 vmx_flush_tlb(vcpu);
9305         }
9306
9307         if (nested_cpu_has_ept(vmcs12)) {
9308                 kvm_mmu_unload(vcpu);
9309                 nested_ept_init_mmu_context(vcpu);
9310         }
9311
9312         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9313                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9314         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9315                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9316         else
9317                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9318         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9319         vmx_set_efer(vcpu, vcpu->arch.efer);
9320
9321         /*
9322          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9323          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9324          * The CR0_READ_SHADOW is what L2 should have expected to read given
9325          * the specifications by L1; It's not enough to take
9326          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9327          * have more bits than L1 expected.
9328          */
9329         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9330         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9331
9332         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9333         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9334
9335         /* shadow page tables on either EPT or shadow page tables */
9336         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9337         kvm_mmu_reset_context(vcpu);
9338
9339         if (!enable_ept)
9340                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9341
9342         /*
9343          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9344          */
9345         if (enable_ept) {
9346                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9347                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9348                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9349                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9350         }
9351
9352         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9353         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9354 }
9355
9356 /*
9357  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9358  * for running an L2 nested guest.
9359  */
9360 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9361 {
9362         struct vmcs12 *vmcs12;
9363         struct vcpu_vmx *vmx = to_vmx(vcpu);
9364         int cpu;
9365         struct loaded_vmcs *vmcs02;
9366         bool ia32e;
9367         u32 msr_entry_idx;
9368
9369         if (!nested_vmx_check_permission(vcpu) ||
9370             !nested_vmx_check_vmcs12(vcpu))
9371                 return 1;
9372
9373         skip_emulated_instruction(vcpu);
9374         vmcs12 = get_vmcs12(vcpu);
9375
9376         if (enable_shadow_vmcs)
9377                 copy_shadow_to_vmcs12(vmx);
9378
9379         /*
9380          * The nested entry process starts with enforcing various prerequisites
9381          * on vmcs12 as required by the Intel SDM, and act appropriately when
9382          * they fail: As the SDM explains, some conditions should cause the
9383          * instruction to fail, while others will cause the instruction to seem
9384          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9385          * To speed up the normal (success) code path, we should avoid checking
9386          * for misconfigurations which will anyway be caught by the processor
9387          * when using the merged vmcs02.
9388          */
9389         if (vmcs12->launch_state == launch) {
9390                 nested_vmx_failValid(vcpu,
9391                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9392                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9393                 return 1;
9394         }
9395
9396         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9397             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9398                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9399                 return 1;
9400         }
9401
9402         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9403                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9404                 return 1;
9405         }
9406
9407         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9408                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9409                 return 1;
9410         }
9411
9412         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9413                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9414                 return 1;
9415         }
9416
9417         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9418                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9419                 return 1;
9420         }
9421
9422         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9423                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9424                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9425             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9426                                 vmx->nested.nested_vmx_secondary_ctls_low,
9427                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9428             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9429                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9430                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9431             !vmx_control_verify(vmcs12->vm_exit_controls,
9432                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9433                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9434             !vmx_control_verify(vmcs12->vm_entry_controls,
9435                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9436                                 vmx->nested.nested_vmx_entry_ctls_high))
9437         {
9438                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9439                 return 1;
9440         }
9441
9442         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9443             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9444                 nested_vmx_failValid(vcpu,
9445                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9446                 return 1;
9447         }
9448
9449         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9450             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9451                 nested_vmx_entry_failure(vcpu, vmcs12,
9452                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9453                 return 1;
9454         }
9455         if (vmcs12->vmcs_link_pointer != -1ull) {
9456                 nested_vmx_entry_failure(vcpu, vmcs12,
9457                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9458                 return 1;
9459         }
9460
9461         /*
9462          * If the load IA32_EFER VM-entry control is 1, the following checks
9463          * are performed on the field for the IA32_EFER MSR:
9464          * - Bits reserved in the IA32_EFER MSR must be 0.
9465          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9466          *   the IA-32e mode guest VM-exit control. It must also be identical
9467          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9468          *   CR0.PG) is 1.
9469          */
9470         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9471                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9472                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9473                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9474                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9475                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9476                         nested_vmx_entry_failure(vcpu, vmcs12,
9477                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9478                         return 1;
9479                 }
9480         }
9481
9482         /*
9483          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9484          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9485          * the values of the LMA and LME bits in the field must each be that of
9486          * the host address-space size VM-exit control.
9487          */
9488         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9489                 ia32e = (vmcs12->vm_exit_controls &
9490                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9491                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9492                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9493                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9494                         nested_vmx_entry_failure(vcpu, vmcs12,
9495                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9496                         return 1;
9497                 }
9498         }
9499
9500         /*
9501          * We're finally done with prerequisite checking, and can start with
9502          * the nested entry.
9503          */
9504
9505         vmcs02 = nested_get_current_vmcs02(vmx);
9506         if (!vmcs02)
9507                 return -ENOMEM;
9508
9509         enter_guest_mode(vcpu);
9510
9511         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9512
9513         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9514                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9515
9516         cpu = get_cpu();
9517         vmx->loaded_vmcs = vmcs02;
9518         vmx_vcpu_put(vcpu);
9519         vmx_vcpu_load(vcpu, cpu);
9520         vcpu->cpu = cpu;
9521         put_cpu();
9522
9523         vmx_segment_cache_clear(vmx);
9524
9525         prepare_vmcs02(vcpu, vmcs12);
9526
9527         msr_entry_idx = nested_vmx_load_msr(vcpu,
9528                                             vmcs12->vm_entry_msr_load_addr,
9529                                             vmcs12->vm_entry_msr_load_count);
9530         if (msr_entry_idx) {
9531                 leave_guest_mode(vcpu);
9532                 vmx_load_vmcs01(vcpu);
9533                 nested_vmx_entry_failure(vcpu, vmcs12,
9534                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9535                 return 1;
9536         }
9537
9538         vmcs12->launch_state = 1;
9539
9540         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9541                 return kvm_vcpu_halt(vcpu);
9542
9543         vmx->nested.nested_run_pending = 1;
9544
9545         /*
9546          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9547          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9548          * returned as far as L1 is concerned. It will only return (and set
9549          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9550          */
9551         return 1;
9552 }
9553
9554 /*
9555  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9556  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9557  * This function returns the new value we should put in vmcs12.guest_cr0.
9558  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9559  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9560  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9561  *     didn't trap the bit, because if L1 did, so would L0).
9562  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9563  *     been modified by L2, and L1 knows it. So just leave the old value of
9564  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9565  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9566  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9567  *     changed these bits, and therefore they need to be updated, but L0
9568  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9569  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9570  */
9571 static inline unsigned long
9572 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9573 {
9574         return
9575         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9576         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9577         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9578                         vcpu->arch.cr0_guest_owned_bits));
9579 }
9580
9581 static inline unsigned long
9582 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9583 {
9584         return
9585         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9586         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9587         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9588                         vcpu->arch.cr4_guest_owned_bits));
9589 }
9590
9591 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9592                                        struct vmcs12 *vmcs12)
9593 {
9594         u32 idt_vectoring;
9595         unsigned int nr;
9596
9597         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9598                 nr = vcpu->arch.exception.nr;
9599                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9600
9601                 if (kvm_exception_is_soft(nr)) {
9602                         vmcs12->vm_exit_instruction_len =
9603                                 vcpu->arch.event_exit_inst_len;
9604                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9605                 } else
9606                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9607
9608                 if (vcpu->arch.exception.has_error_code) {
9609                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9610                         vmcs12->idt_vectoring_error_code =
9611                                 vcpu->arch.exception.error_code;
9612                 }
9613
9614                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9615         } else if (vcpu->arch.nmi_injected) {
9616                 vmcs12->idt_vectoring_info_field =
9617                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9618         } else if (vcpu->arch.interrupt.pending) {
9619                 nr = vcpu->arch.interrupt.nr;
9620                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9621
9622                 if (vcpu->arch.interrupt.soft) {
9623                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9624                         vmcs12->vm_entry_instruction_len =
9625                                 vcpu->arch.event_exit_inst_len;
9626                 } else
9627                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9628
9629                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9630         }
9631 }
9632
9633 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9634 {
9635         struct vcpu_vmx *vmx = to_vmx(vcpu);
9636
9637         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9638             vmx->nested.preemption_timer_expired) {
9639                 if (vmx->nested.nested_run_pending)
9640                         return -EBUSY;
9641                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9642                 return 0;
9643         }
9644
9645         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9646                 if (vmx->nested.nested_run_pending ||
9647                     vcpu->arch.interrupt.pending)
9648                         return -EBUSY;
9649                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9650                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9651                                   INTR_INFO_VALID_MASK, 0);
9652                 /*
9653                  * The NMI-triggered VM exit counts as injection:
9654                  * clear this one and block further NMIs.
9655                  */
9656                 vcpu->arch.nmi_pending = 0;
9657                 vmx_set_nmi_mask(vcpu, true);
9658                 return 0;
9659         }
9660
9661         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9662             nested_exit_on_intr(vcpu)) {
9663                 if (vmx->nested.nested_run_pending)
9664                         return -EBUSY;
9665                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9666                 return 0;
9667         }
9668
9669         return vmx_complete_nested_posted_interrupt(vcpu);
9670 }
9671
9672 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9673 {
9674         ktime_t remaining =
9675                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9676         u64 value;
9677
9678         if (ktime_to_ns(remaining) <= 0)
9679                 return 0;
9680
9681         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9682         do_div(value, 1000000);
9683         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9684 }
9685
9686 /*
9687  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9688  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9689  * and this function updates it to reflect the changes to the guest state while
9690  * L2 was running (and perhaps made some exits which were handled directly by L0
9691  * without going back to L1), and to reflect the exit reason.
9692  * Note that we do not have to copy here all VMCS fields, just those that
9693  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9694  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9695  * which already writes to vmcs12 directly.
9696  */
9697 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9698                            u32 exit_reason, u32 exit_intr_info,
9699                            unsigned long exit_qualification)
9700 {
9701         /* update guest state fields: */
9702         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9703         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9704
9705         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9706         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9707         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9708
9709         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9710         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9711         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9712         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9713         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9714         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9715         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9716         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9717         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9718         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9719         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9720         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9721         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9722         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9723         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9724         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9725         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9726         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9727         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9728         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9729         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9730         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9731         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9732         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9733         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9734         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9735         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9736         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9737         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9738         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9739         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9740         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9741         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9742         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9743         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9744         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9745
9746         vmcs12->guest_interruptibility_info =
9747                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9748         vmcs12->guest_pending_dbg_exceptions =
9749                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9750         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9751                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9752         else
9753                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9754
9755         if (nested_cpu_has_preemption_timer(vmcs12)) {
9756                 if (vmcs12->vm_exit_controls &
9757                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9758                         vmcs12->vmx_preemption_timer_value =
9759                                 vmx_get_preemption_timer_value(vcpu);
9760                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9761         }
9762
9763         /*
9764          * In some cases (usually, nested EPT), L2 is allowed to change its
9765          * own CR3 without exiting. If it has changed it, we must keep it.
9766          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9767          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9768          *
9769          * Additionally, restore L2's PDPTR to vmcs12.
9770          */
9771         if (enable_ept) {
9772                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9773                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9774                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9775                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9776                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9777         }
9778
9779         if (nested_cpu_has_vid(vmcs12))
9780                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9781
9782         vmcs12->vm_entry_controls =
9783                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9784                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9785
9786         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9787                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9788                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9789         }
9790
9791         /* TODO: These cannot have changed unless we have MSR bitmaps and
9792          * the relevant bit asks not to trap the change */
9793         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9794                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9795         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9796                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9797         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9798         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9799         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9800         if (vmx_mpx_supported())
9801                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9802         if (nested_cpu_has_xsaves(vmcs12))
9803                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9804
9805         /* update exit information fields: */
9806
9807         vmcs12->vm_exit_reason = exit_reason;
9808         vmcs12->exit_qualification = exit_qualification;
9809
9810         vmcs12->vm_exit_intr_info = exit_intr_info;
9811         if ((vmcs12->vm_exit_intr_info &
9812              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9813             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9814                 vmcs12->vm_exit_intr_error_code =
9815                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9816         vmcs12->idt_vectoring_info_field = 0;
9817         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9818         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9819
9820         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9821                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9822                  * instead of reading the real value. */
9823                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9824
9825                 /*
9826                  * Transfer the event that L0 or L1 may wanted to inject into
9827                  * L2 to IDT_VECTORING_INFO_FIELD.
9828                  */
9829                 vmcs12_save_pending_event(vcpu, vmcs12);
9830         }
9831
9832         /*
9833          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9834          * preserved above and would only end up incorrectly in L1.
9835          */
9836         vcpu->arch.nmi_injected = false;
9837         kvm_clear_exception_queue(vcpu);
9838         kvm_clear_interrupt_queue(vcpu);
9839 }
9840
9841 /*
9842  * A part of what we need to when the nested L2 guest exits and we want to
9843  * run its L1 parent, is to reset L1's guest state to the host state specified
9844  * in vmcs12.
9845  * This function is to be called not only on normal nested exit, but also on
9846  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9847  * Failures During or After Loading Guest State").
9848  * This function should be called when the active VMCS is L1's (vmcs01).
9849  */
9850 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9851                                    struct vmcs12 *vmcs12)
9852 {
9853         struct kvm_segment seg;
9854
9855         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9856                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9857         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9858                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9859         else
9860                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9861         vmx_set_efer(vcpu, vcpu->arch.efer);
9862
9863         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9864         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9865         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9866         /*
9867          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9868          * actually changed, because it depends on the current state of
9869          * fpu_active (which may have changed).
9870          * Note that vmx_set_cr0 refers to efer set above.
9871          */
9872         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9873         /*
9874          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9875          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9876          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9877          */
9878         update_exception_bitmap(vcpu);
9879         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9880         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9881
9882         /*
9883          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9884          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9885          */
9886         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9887         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9888
9889         nested_ept_uninit_mmu_context(vcpu);
9890
9891         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9892         kvm_mmu_reset_context(vcpu);
9893
9894         if (!enable_ept)
9895                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9896
9897         if (enable_vpid) {
9898                 /*
9899                  * Trivially support vpid by letting L2s share their parent
9900                  * L1's vpid. TODO: move to a more elaborate solution, giving
9901                  * each L2 its own vpid and exposing the vpid feature to L1.
9902                  */
9903                 vmx_flush_tlb(vcpu);
9904         }
9905
9906
9907         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9908         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9909         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9910         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9911         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9912
9913         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9914         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9915                 vmcs_write64(GUEST_BNDCFGS, 0);
9916
9917         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9918                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9919                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9920         }
9921         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9922                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9923                         vmcs12->host_ia32_perf_global_ctrl);
9924
9925         /* Set L1 segment info according to Intel SDM
9926             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9927         seg = (struct kvm_segment) {
9928                 .base = 0,
9929                 .limit = 0xFFFFFFFF,
9930                 .selector = vmcs12->host_cs_selector,
9931                 .type = 11,
9932                 .present = 1,
9933                 .s = 1,
9934                 .g = 1
9935         };
9936         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9937                 seg.l = 1;
9938         else
9939                 seg.db = 1;
9940         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9941         seg = (struct kvm_segment) {
9942                 .base = 0,
9943                 .limit = 0xFFFFFFFF,
9944                 .type = 3,
9945                 .present = 1,
9946                 .s = 1,
9947                 .db = 1,
9948                 .g = 1
9949         };
9950         seg.selector = vmcs12->host_ds_selector;
9951         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9952         seg.selector = vmcs12->host_es_selector;
9953         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9954         seg.selector = vmcs12->host_ss_selector;
9955         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9956         seg.selector = vmcs12->host_fs_selector;
9957         seg.base = vmcs12->host_fs_base;
9958         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9959         seg.selector = vmcs12->host_gs_selector;
9960         seg.base = vmcs12->host_gs_base;
9961         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9962         seg = (struct kvm_segment) {
9963                 .base = vmcs12->host_tr_base,
9964                 .limit = 0x67,
9965                 .selector = vmcs12->host_tr_selector,
9966                 .type = 11,
9967                 .present = 1
9968         };
9969         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9970
9971         kvm_set_dr(vcpu, 7, 0x400);
9972         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9973
9974         if (cpu_has_vmx_msr_bitmap())
9975                 vmx_set_msr_bitmap(vcpu);
9976
9977         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9978                                 vmcs12->vm_exit_msr_load_count))
9979                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9980 }
9981
9982 /*
9983  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9984  * and modify vmcs12 to make it see what it would expect to see there if
9985  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9986  */
9987 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9988                               u32 exit_intr_info,
9989                               unsigned long exit_qualification)
9990 {
9991         struct vcpu_vmx *vmx = to_vmx(vcpu);
9992         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9993
9994         /* trying to cancel vmlaunch/vmresume is a bug */
9995         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9996
9997         leave_guest_mode(vcpu);
9998         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9999                        exit_qualification);
10000
10001         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10002                                  vmcs12->vm_exit_msr_store_count))
10003                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10004
10005         vmx_load_vmcs01(vcpu);
10006
10007         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10008             && nested_exit_intr_ack_set(vcpu)) {
10009                 int irq = kvm_cpu_get_interrupt(vcpu);
10010                 WARN_ON(irq < 0);
10011                 vmcs12->vm_exit_intr_info = irq |
10012                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10013         }
10014
10015         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10016                                        vmcs12->exit_qualification,
10017                                        vmcs12->idt_vectoring_info_field,
10018                                        vmcs12->vm_exit_intr_info,
10019                                        vmcs12->vm_exit_intr_error_code,
10020                                        KVM_ISA_VMX);
10021
10022         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10023         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10024         vmx_segment_cache_clear(vmx);
10025
10026         /* if no vmcs02 cache requested, remove the one we used */
10027         if (VMCS02_POOL_SIZE == 0)
10028                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10029
10030         load_vmcs12_host_state(vcpu, vmcs12);
10031
10032         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10033         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10034
10035         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10036         vmx->host_rsp = 0;
10037
10038         /* Unpin physical memory we referred to in vmcs02 */
10039         if (vmx->nested.apic_access_page) {
10040                 nested_release_page(vmx->nested.apic_access_page);
10041                 vmx->nested.apic_access_page = NULL;
10042         }
10043         if (vmx->nested.virtual_apic_page) {
10044                 nested_release_page(vmx->nested.virtual_apic_page);
10045                 vmx->nested.virtual_apic_page = NULL;
10046         }
10047         if (vmx->nested.pi_desc_page) {
10048                 kunmap(vmx->nested.pi_desc_page);
10049                 nested_release_page(vmx->nested.pi_desc_page);
10050                 vmx->nested.pi_desc_page = NULL;
10051                 vmx->nested.pi_desc = NULL;
10052         }
10053
10054         /*
10055          * We are now running in L2, mmu_notifier will force to reload the
10056          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10057          */
10058         kvm_vcpu_reload_apic_access_page(vcpu);
10059
10060         /*
10061          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10062          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10063          * success or failure flag accordingly.
10064          */
10065         if (unlikely(vmx->fail)) {
10066                 vmx->fail = 0;
10067                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10068         } else
10069                 nested_vmx_succeed(vcpu);
10070         if (enable_shadow_vmcs)
10071                 vmx->nested.sync_shadow_vmcs = true;
10072
10073         /* in case we halted in L2 */
10074         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10075 }
10076
10077 /*
10078  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10079  */
10080 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10081 {
10082         if (is_guest_mode(vcpu))
10083                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10084         free_nested(to_vmx(vcpu));
10085 }
10086
10087 /*
10088  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10089  * 23.7 "VM-entry failures during or after loading guest state" (this also
10090  * lists the acceptable exit-reason and exit-qualification parameters).
10091  * It should only be called before L2 actually succeeded to run, and when
10092  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10093  */
10094 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10095                         struct vmcs12 *vmcs12,
10096                         u32 reason, unsigned long qualification)
10097 {
10098         load_vmcs12_host_state(vcpu, vmcs12);
10099         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10100         vmcs12->exit_qualification = qualification;
10101         nested_vmx_succeed(vcpu);
10102         if (enable_shadow_vmcs)
10103                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10104 }
10105
10106 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10107                                struct x86_instruction_info *info,
10108                                enum x86_intercept_stage stage)
10109 {
10110         return X86EMUL_CONTINUE;
10111 }
10112
10113 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10114 {
10115         if (ple_gap)
10116                 shrink_ple_window(vcpu);
10117 }
10118
10119 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10120                                      struct kvm_memory_slot *slot)
10121 {
10122         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10123         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10124 }
10125
10126 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10127                                        struct kvm_memory_slot *slot)
10128 {
10129         kvm_mmu_slot_set_dirty(kvm, slot);
10130 }
10131
10132 static void vmx_flush_log_dirty(struct kvm *kvm)
10133 {
10134         kvm_flush_pml_buffers(kvm);
10135 }
10136
10137 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10138                                            struct kvm_memory_slot *memslot,
10139                                            gfn_t offset, unsigned long mask)
10140 {
10141         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10142 }
10143
10144 static struct kvm_x86_ops vmx_x86_ops = {
10145         .cpu_has_kvm_support = cpu_has_kvm_support,
10146         .disabled_by_bios = vmx_disabled_by_bios,
10147         .hardware_setup = hardware_setup,
10148         .hardware_unsetup = hardware_unsetup,
10149         .check_processor_compatibility = vmx_check_processor_compat,
10150         .hardware_enable = hardware_enable,
10151         .hardware_disable = hardware_disable,
10152         .cpu_has_accelerated_tpr = report_flexpriority,
10153
10154         .vcpu_create = vmx_create_vcpu,
10155         .vcpu_free = vmx_free_vcpu,
10156         .vcpu_reset = vmx_vcpu_reset,
10157
10158         .prepare_guest_switch = vmx_save_host_state,
10159         .vcpu_load = vmx_vcpu_load,
10160         .vcpu_put = vmx_vcpu_put,
10161
10162         .update_db_bp_intercept = update_exception_bitmap,
10163         .get_msr = vmx_get_msr,
10164         .set_msr = vmx_set_msr,
10165         .get_segment_base = vmx_get_segment_base,
10166         .get_segment = vmx_get_segment,
10167         .set_segment = vmx_set_segment,
10168         .get_cpl = vmx_get_cpl,
10169         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10170         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10171         .decache_cr3 = vmx_decache_cr3,
10172         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10173         .set_cr0 = vmx_set_cr0,
10174         .set_cr3 = vmx_set_cr3,
10175         .set_cr4 = vmx_set_cr4,
10176         .set_efer = vmx_set_efer,
10177         .get_idt = vmx_get_idt,
10178         .set_idt = vmx_set_idt,
10179         .get_gdt = vmx_get_gdt,
10180         .set_gdt = vmx_set_gdt,
10181         .get_dr6 = vmx_get_dr6,
10182         .set_dr6 = vmx_set_dr6,
10183         .set_dr7 = vmx_set_dr7,
10184         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10185         .cache_reg = vmx_cache_reg,
10186         .get_rflags = vmx_get_rflags,
10187         .set_rflags = vmx_set_rflags,
10188         .fpu_activate = vmx_fpu_activate,
10189         .fpu_deactivate = vmx_fpu_deactivate,
10190
10191         .tlb_flush = vmx_flush_tlb,
10192
10193         .run = vmx_vcpu_run,
10194         .handle_exit = vmx_handle_exit,
10195         .skip_emulated_instruction = skip_emulated_instruction,
10196         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10197         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10198         .patch_hypercall = vmx_patch_hypercall,
10199         .set_irq = vmx_inject_irq,
10200         .set_nmi = vmx_inject_nmi,
10201         .queue_exception = vmx_queue_exception,
10202         .cancel_injection = vmx_cancel_injection,
10203         .interrupt_allowed = vmx_interrupt_allowed,
10204         .nmi_allowed = vmx_nmi_allowed,
10205         .get_nmi_mask = vmx_get_nmi_mask,
10206         .set_nmi_mask = vmx_set_nmi_mask,
10207         .enable_nmi_window = enable_nmi_window,
10208         .enable_irq_window = enable_irq_window,
10209         .update_cr8_intercept = update_cr8_intercept,
10210         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10211         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10212         .vm_has_apicv = vmx_vm_has_apicv,
10213         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10214         .hwapic_irr_update = vmx_hwapic_irr_update,
10215         .hwapic_isr_update = vmx_hwapic_isr_update,
10216         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10217         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10218
10219         .set_tss_addr = vmx_set_tss_addr,
10220         .get_tdp_level = get_ept_level,
10221         .get_mt_mask = vmx_get_mt_mask,
10222
10223         .get_exit_info = vmx_get_exit_info,
10224
10225         .get_lpage_level = vmx_get_lpage_level,
10226
10227         .cpuid_update = vmx_cpuid_update,
10228
10229         .rdtscp_supported = vmx_rdtscp_supported,
10230         .invpcid_supported = vmx_invpcid_supported,
10231
10232         .set_supported_cpuid = vmx_set_supported_cpuid,
10233
10234         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10235
10236         .set_tsc_khz = vmx_set_tsc_khz,
10237         .read_tsc_offset = vmx_read_tsc_offset,
10238         .write_tsc_offset = vmx_write_tsc_offset,
10239         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10240         .compute_tsc_offset = vmx_compute_tsc_offset,
10241         .read_l1_tsc = vmx_read_l1_tsc,
10242
10243         .set_tdp_cr3 = vmx_set_cr3,
10244
10245         .check_intercept = vmx_check_intercept,
10246         .handle_external_intr = vmx_handle_external_intr,
10247         .mpx_supported = vmx_mpx_supported,
10248         .xsaves_supported = vmx_xsaves_supported,
10249
10250         .check_nested_events = vmx_check_nested_events,
10251
10252         .sched_in = vmx_sched_in,
10253
10254         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10255         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10256         .flush_log_dirty = vmx_flush_log_dirty,
10257         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10258 };
10259
10260 static int __init vmx_init(void)
10261 {
10262         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10263                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10264         if (r)
10265                 return r;
10266
10267 #ifdef CONFIG_KEXEC
10268         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10269                            crash_vmclear_local_loaded_vmcss);
10270 #endif
10271
10272         return 0;
10273 }
10274
10275 static void __exit vmx_exit(void)
10276 {
10277 #ifdef CONFIG_KEXEC
10278         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10279         synchronize_rcu();
10280 #endif
10281
10282         kvm_exit();
10283 }
10284
10285 module_init(vmx_init)
10286 module_exit(vmx_exit)