kernel/arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         /* L2 must run next, and mustn't decide to exit to L1. */
 412         bool nested_run_pending;
 413         /*
 414          * Guest pages referred to in vmcs02 with host-physical pointers, so
 415          * we must keep them pinned while L2 runs.
 416          */
 417         struct page *apic_access_page;
 418         struct page *virtual_apic_page;
 419         struct page *pi_desc_page;
 420         struct pi_desc *pi_desc;
 421         bool pi_pending;
 422         u16 posted_intr_nv;
 423         u64 msr_ia32_feature_control;
 424
 425         struct hrtimer preemption_timer;
 426         bool preemption_timer_expired;
 427
 428         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 429         u64 vmcs01_debugctl;
 430
 431         u16 vpid02;
 432         u16 last_vpid;
 433
 434         u32 nested_vmx_procbased_ctls_low;
 435         u32 nested_vmx_procbased_ctls_high;
 436         u32 nested_vmx_true_procbased_ctls_low;
 437         u32 nested_vmx_secondary_ctls_low;
 438         u32 nested_vmx_secondary_ctls_high;
 439         u32 nested_vmx_pinbased_ctls_low;
 440         u32 nested_vmx_pinbased_ctls_high;
 441         u32 nested_vmx_exit_ctls_low;
 442         u32 nested_vmx_exit_ctls_high;
 443         u32 nested_vmx_true_exit_ctls_low;
 444         u32 nested_vmx_entry_ctls_low;
 445         u32 nested_vmx_entry_ctls_high;
 446         u32 nested_vmx_true_entry_ctls_low;
 447         u32 nested_vmx_misc_low;
 448         u32 nested_vmx_misc_high;
 449         u32 nested_vmx_ept_caps;
 450         u32 nested_vmx_vpid_caps;
 451 };
 452
 453 #define POSTED_INTR_ON  0
 454 #define POSTED_INTR_SN  1
 455
 456 /* Posted-Interrupt Descriptor */
 457 struct pi_desc {
 458         u32 pir[8];     /* Posted interrupt requested */
 459         union {
 460                 struct {
 461                                 /* bit 256 - Outstanding Notification */
 462                         u16     on      : 1,
 463                                 /* bit 257 - Suppress Notification */
 464                                 sn      : 1,
 465                                 /* bit 271:258 - Reserved */
 466                                 rsvd_1  : 14;
 467                                 /* bit 279:272 - Notification Vector */
 468                         u8      nv;
 469                                 /* bit 287:280 - Reserved */
 470                         u8      rsvd_2;
 471                                 /* bit 319:288 - Notification Destination */
 472                         u32     ndst;
 473                 };
 474                 u64 control;
 475         };
 476         u32 rsvd[6];
 477 } __aligned(64);
 478
 479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 480 {
 481         return test_and_set_bit(POSTED_INTR_ON,
 482                         (unsigned long *)&pi_desc->control);
 483 }
 484
 485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 486 {
 487         return test_and_clear_bit(POSTED_INTR_ON,
 488                         (unsigned long *)&pi_desc->control);
 489 }
 490
 491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 492 {
 493         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 494 }
 495
 496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 497 {
 498         return clear_bit(POSTED_INTR_SN,
 499                         (unsigned long *)&pi_desc->control);
 500 }
 501
 502 static inline void pi_set_sn(struct pi_desc *pi_desc)
 503 {
 504         return set_bit(POSTED_INTR_SN,
 505                         (unsigned long *)&pi_desc->control);
 506 }
 507
 508 static inline int pi_test_on(struct pi_desc *pi_desc)
 509 {
 510         return test_bit(POSTED_INTR_ON,
 511                         (unsigned long *)&pi_desc->control);
 512 }
 513
 514 static inline int pi_test_sn(struct pi_desc *pi_desc)
 515 {
 516         return test_bit(POSTED_INTR_SN,
 517                         (unsigned long *)&pi_desc->control);
 518 }
 519
 520 struct vcpu_vmx {
 521         struct kvm_vcpu       vcpu;
 522         unsigned long         host_rsp;
 523         u8                    fail;
 524         bool                  nmi_known_unmasked;
 525         u32                   exit_intr_info;
 526         u32                   idt_vectoring_info;
 527         ulong                 rflags;
 528         struct shared_msr_entry *guest_msrs;
 529         int                   nmsrs;
 530         int                   save_nmsrs;
 531         unsigned long         host_idt_base;
 532 #ifdef CONFIG_X86_64
 533         u64                   msr_host_kernel_gs_base;
 534         u64                   msr_guest_kernel_gs_base;
 535 #endif
 536         u32 vm_entry_controls_shadow;
 537         u32 vm_exit_controls_shadow;
 538         /*
 539          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 540          * non-nested (L1) guest, it always points to vmcs01. For a nested
 541          * guest (L2), it points to a different VMCS.
 542          */
 543         struct loaded_vmcs    vmcs01;
 544         struct loaded_vmcs   *loaded_vmcs;
 545         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 546         struct msr_autoload {
 547                 unsigned nr;
 548                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 549                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 550         } msr_autoload;
 551         struct {
 552                 int           loaded;
 553                 u16           fs_sel, gs_sel, ldt_sel;
 554 #ifdef CONFIG_X86_64
 555                 u16           ds_sel, es_sel;
 556 #endif
 557                 int           gs_ldt_reload_needed;
 558                 int           fs_reload_needed;
 559                 u64           msr_host_bndcfgs;
 560                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 561         } host_state;
 562         struct {
 563                 int vm86_active;
 564                 ulong save_rflags;
 565                 struct kvm_segment segs[8];
 566         } rmode;
 567         struct {
 568                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 569                 struct kvm_save_segment {
 570                         u16 selector;
 571                         unsigned long base;
 572                         u32 limit;
 573                         u32 ar;
 574                 } seg[8];
 575         } segment_cache;
 576         int vpid;
 577         bool emulation_required;
 578
 579         /* Support for vnmi-less CPUs */
 580         int soft_vnmi_blocked;
 581         ktime_t entry_time;
 582         s64 vnmi_blocked_time;
 583         u32 exit_reason;
 584
 585         /* Posted interrupt descriptor */
 586         struct pi_desc pi_desc;
 587
 588         /* Support for a guest hypervisor (nested VMX) */
 589         struct nested_vmx nested;
 590
 591         /* Dynamic PLE window. */
 592         int ple_window;
 593         bool ple_window_dirty;
 594
 595         /* Support for PML */
 596 #define PML_ENTITY_NUM          512
 597         struct page *pml_pg;
 598
 599         u64 current_tsc_ratio;
 600 };
 601
 602 enum segment_cache_field {
 603         SEG_FIELD_SEL = 0,
 604         SEG_FIELD_BASE = 1,
 605         SEG_FIELD_LIMIT = 2,
 606         SEG_FIELD_AR = 3,
 607
 608         SEG_FIELD_NR = 4
 609 };
 610
 611 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 612 {
 613         return container_of(vcpu, struct vcpu_vmx, vcpu);
 614 }
 615
 616 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 617 {
 618         return &(to_vmx(vcpu)->pi_desc);
 619 }
 620
 621 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 622 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 623 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 624                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 625
 626
 627 static unsigned long shadow_read_only_fields[] = {
 628         /*
 629          * We do NOT shadow fields that are modified when L0
 630          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 631          * VMXON...) executed by L1.
 632          * For example, VM_INSTRUCTION_ERROR is read
 633          * by L1 if a vmx instruction fails (part of the error path).
 634          * Note the code assumes this logic. If for some reason
 635          * we start shadowing these fields then we need to
 636          * force a shadow sync when L0 emulates vmx instructions
 637          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 638          * by nested_vmx_failValid)
 639          */
 640         VM_EXIT_REASON,
 641         VM_EXIT_INTR_INFO,
 642         VM_EXIT_INSTRUCTION_LEN,
 643         IDT_VECTORING_INFO_FIELD,
 644         IDT_VECTORING_ERROR_CODE,
 645         VM_EXIT_INTR_ERROR_CODE,
 646         EXIT_QUALIFICATION,
 647         GUEST_LINEAR_ADDRESS,
 648         GUEST_PHYSICAL_ADDRESS
 649 };
 650 static int max_shadow_read_only_fields =
 651         ARRAY_SIZE(shadow_read_only_fields);
 652
 653 static unsigned long shadow_read_write_fields[] = {
 654         TPR_THRESHOLD,
 655         GUEST_RIP,
 656         GUEST_RSP,
 657         GUEST_CR0,
 658         GUEST_CR3,
 659         GUEST_CR4,
 660         GUEST_INTERRUPTIBILITY_INFO,
 661         GUEST_RFLAGS,
 662         GUEST_CS_SELECTOR,
 663         GUEST_CS_AR_BYTES,
 664         GUEST_CS_LIMIT,
 665         GUEST_CS_BASE,
 666         GUEST_ES_BASE,
 667         GUEST_BNDCFGS,
 668         CR0_GUEST_HOST_MASK,
 669         CR0_READ_SHADOW,
 670         CR4_READ_SHADOW,
 671         TSC_OFFSET,
 672         EXCEPTION_BITMAP,
 673         CPU_BASED_VM_EXEC_CONTROL,
 674         VM_ENTRY_EXCEPTION_ERROR_CODE,
 675         VM_ENTRY_INTR_INFO_FIELD,
 676         VM_ENTRY_INSTRUCTION_LEN,
 677         VM_ENTRY_EXCEPTION_ERROR_CODE,
 678         HOST_FS_BASE,
 679         HOST_GS_BASE,
 680         HOST_FS_SELECTOR,
 681         HOST_GS_SELECTOR
 682 };
 683 static int max_shadow_read_write_fields =
 684         ARRAY_SIZE(shadow_read_write_fields);
 685
 686 static const unsigned short vmcs_field_to_offset_table[] = {
 687         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 688         FIELD(POSTED_INTR_NV, posted_intr_nv),
 689         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 690         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 691         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 692         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 693         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 694         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 695         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 696         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 697         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 698         FIELD(HOST_ES_SELECTOR, host_es_selector),
 699         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 700         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 701         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 702         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 703         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 704         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 705         FIELD64(IO_BITMAP_A, io_bitmap_a),
 706         FIELD64(IO_BITMAP_B, io_bitmap_b),
 707         FIELD64(MSR_BITMAP, msr_bitmap),
 708         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 709         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 710         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 711         FIELD64(TSC_OFFSET, tsc_offset),
 712         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 713         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 714         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 715         FIELD64(EPT_POINTER, ept_pointer),
 716         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 717         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 718         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 719         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 720         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 721         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 722         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 723         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 724         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 725         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 726         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 727         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 728         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 729         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 730         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 731         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 732         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 733         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 734         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 735         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 736         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 737         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 740         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 741         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 742         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 743         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 744         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 745         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 746         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 747         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 748         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 749         FIELD(TPR_THRESHOLD, tpr_threshold),
 750         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 751         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 752         FIELD(VM_EXIT_REASON, vm_exit_reason),
 753         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 754         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 755         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 756         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 757         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 758         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 759         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 760         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 761         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 762         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 763         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 764         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 765         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 766         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 767         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 768         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 769         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 770         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 771         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 772         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 773         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 774         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 775         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 776         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 777         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 778         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 779         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 780         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 781         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 782         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 783         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 784         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 785         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 786         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 787         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 788         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 789         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 790         FIELD(EXIT_QUALIFICATION, exit_qualification),
 791         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 792         FIELD(GUEST_CR0, guest_cr0),
 793         FIELD(GUEST_CR3, guest_cr3),
 794         FIELD(GUEST_CR4, guest_cr4),
 795         FIELD(GUEST_ES_BASE, guest_es_base),
 796         FIELD(GUEST_CS_BASE, guest_cs_base),
 797         FIELD(GUEST_SS_BASE, guest_ss_base),
 798         FIELD(GUEST_DS_BASE, guest_ds_base),
 799         FIELD(GUEST_FS_BASE, guest_fs_base),
 800         FIELD(GUEST_GS_BASE, guest_gs_base),
 801         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 802         FIELD(GUEST_TR_BASE, guest_tr_base),
 803         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 804         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 805         FIELD(GUEST_DR7, guest_dr7),
 806         FIELD(GUEST_RSP, guest_rsp),
 807         FIELD(GUEST_RIP, guest_rip),
 808         FIELD(GUEST_RFLAGS, guest_rflags),
 809         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 810         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 811         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 812         FIELD(HOST_CR0, host_cr0),
 813         FIELD(HOST_CR3, host_cr3),
 814         FIELD(HOST_CR4, host_cr4),
 815         FIELD(HOST_FS_BASE, host_fs_base),
 816         FIELD(HOST_GS_BASE, host_gs_base),
 817         FIELD(HOST_TR_BASE, host_tr_base),
 818         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 819         FIELD(HOST_IDTR_BASE, host_idtr_base),
 820         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 821         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 822         FIELD(HOST_RSP, host_rsp),
 823         FIELD(HOST_RIP, host_rip),
 824 };
 825
 826 static inline short vmcs_field_to_offset(unsigned long field)
 827 {
 828         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 829
 830         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 831             vmcs_field_to_offset_table[field] == 0)
 832                 return -ENOENT;
 833
 834         return vmcs_field_to_offset_table[field];
 835 }
 836
 837 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 838 {
 839         return to_vmx(vcpu)->nested.current_vmcs12;
 840 }
 841
 842 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 843 {
 844         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 845         if (is_error_page(page))
 846                 return NULL;
 847
 848         return page;
 849 }
 850
 851 static void nested_release_page(struct page *page)
 852 {
 853         kvm_release_page_dirty(page);
 854 }
 855
 856 static void nested_release_page_clean(struct page *page)
 857 {
 858         kvm_release_page_clean(page);
 859 }
 860
 861 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 862 static u64 construct_eptp(unsigned long root_hpa);
 863 static void kvm_cpu_vmxon(u64 addr);
 864 static void kvm_cpu_vmxoff(void);
 865 static bool vmx_mpx_supported(void);
 866 static bool vmx_xsaves_supported(void);
 867 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 876 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 877 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 878 static int alloc_identity_pagetable(struct kvm *kvm);
 879
 880 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 881 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 882 /*
 883  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 884  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 885  */
 886 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 887 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 888
 889 /*
 890  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 891  * can find which vCPU should be waken up.
 892  */
 893 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 894 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 895
 896 static unsigned long *vmx_io_bitmap_a;
 897 static unsigned long *vmx_io_bitmap_b;
 898 static unsigned long *vmx_msr_bitmap_legacy;
 899 static unsigned long *vmx_msr_bitmap_longmode;
 900 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 901 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 902 static unsigned long *vmx_msr_bitmap_nested;
 903 static unsigned long *vmx_vmread_bitmap;
 904 static unsigned long *vmx_vmwrite_bitmap;
 905
 906 static bool cpu_has_load_ia32_efer;
 907 static bool cpu_has_load_perf_global_ctrl;
 908
 909 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 910 static DEFINE_SPINLOCK(vmx_vpid_lock);
 911
 912 static struct vmcs_config {
 913         int size;
 914         int order;
 915         u32 revision_id;
 916         u32 pin_based_exec_ctrl;
 917         u32 cpu_based_exec_ctrl;
 918         u32 cpu_based_2nd_exec_ctrl;
 919         u32 vmexit_ctrl;
 920         u32 vmentry_ctrl;
 921 } vmcs_config;
 922
 923 static struct vmx_capability {
 924         u32 ept;
 925         u32 vpid;
 926 } vmx_capability;
 927
 928 #define VMX_SEGMENT_FIELD(seg)                                  \
 929         [VCPU_SREG_##seg] = {                                   \
 930                 .selector = GUEST_##seg##_SELECTOR,             \
 931                 .base = GUEST_##seg##_BASE,                     \
 932                 .limit = GUEST_##seg##_LIMIT,                   \
 933                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 934         }
 935
 936 static const struct kvm_vmx_segment_field {
 937         unsigned selector;
 938         unsigned base;
 939         unsigned limit;
 940         unsigned ar_bytes;
 941 } kvm_vmx_segment_fields[] = {
 942         VMX_SEGMENT_FIELD(CS),
 943         VMX_SEGMENT_FIELD(DS),
 944         VMX_SEGMENT_FIELD(ES),
 945         VMX_SEGMENT_FIELD(FS),
 946         VMX_SEGMENT_FIELD(GS),
 947         VMX_SEGMENT_FIELD(SS),
 948         VMX_SEGMENT_FIELD(TR),
 949         VMX_SEGMENT_FIELD(LDTR),
 950 };
 951
 952 static u64 host_efer;
 953
 954 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 955
 956 /*
 957  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 958  * away by decrementing the array size.
 959  */
 960 static const u32 vmx_msr_index[] = {
 961 #ifdef CONFIG_X86_64
 962         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 963 #endif
 964         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 965 };
 966
 967 static inline bool is_page_fault(u32 intr_info)
 968 {
 969         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 970                              INTR_INFO_VALID_MASK)) ==
 971                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 972 }
 973
 974 static inline bool is_no_device(u32 intr_info)
 975 {
 976         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 977                              INTR_INFO_VALID_MASK)) ==
 978                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 979 }
 980
 981 static inline bool is_invalid_opcode(u32 intr_info)
 982 {
 983         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 984                              INTR_INFO_VALID_MASK)) ==
 985                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 986 }
 987
 988 static inline bool is_external_interrupt(u32 intr_info)
 989 {
 990         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 991                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 992 }
 993
 994 static inline bool is_machine_check(u32 intr_info)
 995 {
 996         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 997                              INTR_INFO_VALID_MASK)) ==
 998                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1002 {
1003         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 }
1005
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1007 {
1008         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 }
1010
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1012 {
1013         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 }
1015
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1017 {
1018         return vmcs_config.cpu_based_exec_ctrl &
1019                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 }
1021
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1023 {
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 }
1027
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1029 {
1030         return vmcs_config.cpu_based_2nd_exec_ctrl &
1031                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 }
1033
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1035 {
1036         return vmcs_config.cpu_based_2nd_exec_ctrl &
1037                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 }
1039
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1041 {
1042         return vmcs_config.cpu_based_2nd_exec_ctrl &
1043                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 }
1045
1046 static inline bool cpu_has_vmx_posted_intr(void)
1047 {
1048         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1049                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 }
1051
1052 static inline bool cpu_has_vmx_apicv(void)
1053 {
1054         return cpu_has_vmx_apic_register_virt() &&
1055                 cpu_has_vmx_virtual_intr_delivery() &&
1056                 cpu_has_vmx_posted_intr();
1057 }
1058
1059 static inline bool cpu_has_vmx_flexpriority(void)
1060 {
1061         return cpu_has_vmx_tpr_shadow() &&
1062                 cpu_has_vmx_virtualize_apic_accesses();
1063 }
1064
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1066 {
1067         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 }
1069
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1071 {
1072         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 }
1074
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1076 {
1077         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 }
1079
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1081 {
1082         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 }
1084
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1086 {
1087         return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 }
1089
1090 static inline bool cpu_has_vmx_invept_context(void)
1091 {
1092         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 }
1094
1095 static inline bool cpu_has_vmx_invept_global(void)
1096 {
1097         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 }
1099
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1101 {
1102         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 }
1104
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1106 {
1107         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 }
1109
1110 static inline bool cpu_has_vmx_ept(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_ENABLE_EPT;
1114 }
1115
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 }
1121
1122 static inline bool cpu_has_vmx_ple(void)
1123 {
1124         return vmcs_config.cpu_based_2nd_exec_ctrl &
1125                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 }
1127
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1129 {
1130         return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 }
1132
1133 static inline bool cpu_has_vmx_vpid(void)
1134 {
1135         return vmcs_config.cpu_based_2nd_exec_ctrl &
1136                 SECONDARY_EXEC_ENABLE_VPID;
1137 }
1138
1139 static inline bool cpu_has_vmx_rdtscp(void)
1140 {
1141         return vmcs_config.cpu_based_2nd_exec_ctrl &
1142                 SECONDARY_EXEC_RDTSCP;
1143 }
1144
1145 static inline bool cpu_has_vmx_invpcid(void)
1146 {
1147         return vmcs_config.cpu_based_2nd_exec_ctrl &
1148                 SECONDARY_EXEC_ENABLE_INVPCID;
1149 }
1150
1151 static inline bool cpu_has_virtual_nmis(void)
1152 {
1153         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 }
1155
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1157 {
1158         return vmcs_config.cpu_based_2nd_exec_ctrl &
1159                 SECONDARY_EXEC_WBINVD_EXITING;
1160 }
1161
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 {
1164         u64 vmx_msr;
1165         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1166         /* check if the cpu supports writing r/o exit information fields */
1167         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168                 return false;
1169
1170         return vmcs_config.cpu_based_2nd_exec_ctrl &
1171                 SECONDARY_EXEC_SHADOW_VMCS;
1172 }
1173
1174 static inline bool cpu_has_vmx_pml(void)
1175 {
1176         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 }
1178
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1180 {
1181         return vmcs_config.cpu_based_2nd_exec_ctrl &
1182                 SECONDARY_EXEC_TSC_SCALING;
1183 }
1184
1185 static inline bool report_flexpriority(void)
1186 {
1187         return flexpriority_enabled;
1188 }
1189
1190 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1191 {
1192         return vmcs12->cpu_based_vm_exec_control & bit;
1193 }
1194
1195 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1196 {
1197         return (vmcs12->cpu_based_vm_exec_control &
1198                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1199                 (vmcs12->secondary_vm_exec_control & bit);
1200 }
1201
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1203 {
1204         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 }
1206
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1208 {
1209         return vmcs12->pin_based_vm_exec_control &
1210                 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 }
1212
1213 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1214 {
1215         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 }
1217
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1219 {
1220         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1221                 vmx_xsaves_supported();
1222 }
1223
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1225 {
1226         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 }
1228
1229 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1230 {
1231         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 }
1233
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1235 {
1236         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 }
1238
1239 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1240 {
1241         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 }
1243
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1245 {
1246         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 }
1248
1249 static inline bool is_exception(u32 intr_info)
1250 {
1251         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1252                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1253 }
1254
1255 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1256                               u32 exit_intr_info,
1257                               unsigned long exit_qualification);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1259                         struct vmcs12 *vmcs12,
1260                         u32 reason, unsigned long qualification);
1261
1262 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1263 {
1264         int i;
1265
1266         for (i = 0; i < vmx->nmsrs; ++i)
1267                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1268                         return i;
1269         return -1;
1270 }
1271
1272 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1273 {
1274     struct {
1275         u64 vpid : 16;
1276         u64 rsvd : 48;
1277         u64 gva;
1278     } operand = { vpid, 0, gva };
1279
1280     asm volatile (__ex(ASM_VMX_INVVPID)
1281                   /* CF==1 or ZF==1 --> rc = -1 */
1282                   "; ja 1f ; ud2 ; 1:"
1283                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 }
1285
1286 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1287 {
1288         struct {
1289                 u64 eptp, gpa;
1290         } operand = {eptp, gpa};
1291
1292         asm volatile (__ex(ASM_VMX_INVEPT)
1293                         /* CF==1 or ZF==1 --> rc = -1 */
1294                         "; ja 1f ; ud2 ; 1:\n"
1295                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 }
1297
1298 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1299 {
1300         int i;
1301
1302         i = __find_msr_index(vmx, msr);
1303         if (i >= 0)
1304                 return &vmx->guest_msrs[i];
1305         return NULL;
1306 }
1307
1308 static void vmcs_clear(struct vmcs *vmcs)
1309 {
1310         u64 phys_addr = __pa(vmcs);
1311         u8 error;
1312
1313         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1314                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315                       : "cc", "memory");
1316         if (error)
1317                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1318                        vmcs, phys_addr);
1319 }
1320
1321 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1322 {
1323         vmcs_clear(loaded_vmcs->vmcs);
1324         loaded_vmcs->cpu = -1;
1325         loaded_vmcs->launched = 0;
1326 }
1327
1328 static void vmcs_load(struct vmcs *vmcs)
1329 {
1330         u64 phys_addr = __pa(vmcs);
1331         u8 error;
1332
1333         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1334                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335                         : "cc", "memory");
1336         if (error)
1337                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1338                        vmcs, phys_addr);
1339 }
1340
1341 #ifdef CONFIG_KEXEC_CORE
1342 /*
1343  * This bitmap is used to indicate whether the vmclear
1344  * operation is enabled on all cpus. All disabled by
1345  * default.
1346  */
1347 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1348
1349 static inline void crash_enable_local_vmclear(int cpu)
1350 {
1351         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 }
1353
1354 static inline void crash_disable_local_vmclear(int cpu)
1355 {
1356         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 }
1358
1359 static inline int crash_local_vmclear_enabled(int cpu)
1360 {
1361         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 }
1363
1364 static void crash_vmclear_local_loaded_vmcss(void)
1365 {
1366         int cpu = raw_smp_processor_id();
1367         struct loaded_vmcs *v;
1368
1369         if (!crash_local_vmclear_enabled(cpu))
1370                 return;
1371
1372         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1373                             loaded_vmcss_on_cpu_link)
1374                 vmcs_clear(v->vmcs);
1375 }
1376 #else
1377 static inline void crash_enable_local_vmclear(int cpu) { }
1378 static inline void crash_disable_local_vmclear(int cpu) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1380
1381 static void __loaded_vmcs_clear(void *arg)
1382 {
1383         struct loaded_vmcs *loaded_vmcs = arg;
1384         int cpu = raw_smp_processor_id();
1385
1386         if (loaded_vmcs->cpu != cpu)
1387                 return; /* vcpu migration can race with cpu offline */
1388         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1389                 per_cpu(current_vmcs, cpu) = NULL;
1390         crash_disable_local_vmclear(cpu);
1391         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392
1393         /*
1394          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395          * is before setting loaded_vmcs->vcpu to -1 which is done in
1396          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397          * then adds the vmcs into percpu list before it is deleted.
1398          */
1399         smp_wmb();
1400
1401         loaded_vmcs_init(loaded_vmcs);
1402         crash_enable_local_vmclear(cpu);
1403 }
1404
1405 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1406 {
1407         int cpu = loaded_vmcs->cpu;
1408
1409         if (cpu != -1)
1410                 smp_call_function_single(cpu,
1411                          __loaded_vmcs_clear, loaded_vmcs, 1);
1412 }
1413
1414 static inline void vpid_sync_vcpu_single(int vpid)
1415 {
1416         if (vpid == 0)
1417                 return;
1418
1419         if (cpu_has_vmx_invvpid_single())
1420                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 }
1422
1423 static inline void vpid_sync_vcpu_global(void)
1424 {
1425         if (cpu_has_vmx_invvpid_global())
1426                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 }
1428
1429 static inline void vpid_sync_context(int vpid)
1430 {
1431         if (cpu_has_vmx_invvpid_single())
1432                 vpid_sync_vcpu_single(vpid);
1433         else
1434                 vpid_sync_vcpu_global();
1435 }
1436
1437 static inline void ept_sync_global(void)
1438 {
1439         if (cpu_has_vmx_invept_global())
1440                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 }
1442
1443 static inline void ept_sync_context(u64 eptp)
1444 {
1445         if (enable_ept) {
1446                 if (cpu_has_vmx_invept_context())
1447                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1448                 else
1449                         ept_sync_global();
1450         }
1451 }
1452
1453 static __always_inline unsigned long vmcs_readl(unsigned long field)
1454 {
1455         unsigned long value;
1456
1457         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1458                       : "=a"(value) : "d"(field) : "cc");
1459         return value;
1460 }
1461
1462 static __always_inline u16 vmcs_read16(unsigned long field)
1463 {
1464         return vmcs_readl(field);
1465 }
1466
1467 static __always_inline u32 vmcs_read32(unsigned long field)
1468 {
1469         return vmcs_readl(field);
1470 }
1471
1472 static __always_inline u64 vmcs_read64(unsigned long field)
1473 {
1474 #ifdef CONFIG_X86_64
1475         return vmcs_readl(field);
1476 #else
1477         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1478 #endif
1479 }
1480
1481 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1482 {
1483         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1484                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1485         dump_stack();
1486 }
1487
1488 static void vmcs_writel(unsigned long field, unsigned long value)
1489 {
1490         u8 error;
1491
1492         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1493                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1494         if (unlikely(error))
1495                 vmwrite_error(field, value);
1496 }
1497
1498 static void vmcs_write16(unsigned long field, u16 value)
1499 {
1500         vmcs_writel(field, value);
1501 }
1502
1503 static void vmcs_write32(unsigned long field, u32 value)
1504 {
1505         vmcs_writel(field, value);
1506 }
1507
1508 static void vmcs_write64(unsigned long field, u64 value)
1509 {
1510         vmcs_writel(field, value);
1511 #ifndef CONFIG_X86_64
1512         asm volatile ("");
1513         vmcs_writel(field+1, value >> 32);
1514 #endif
1515 }
1516
1517 static void vmcs_clear_bits(unsigned long field, u32 mask)
1518 {
1519         vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 }
1521
1522 static void vmcs_set_bits(unsigned long field, u32 mask)
1523 {
1524         vmcs_writel(field, vmcs_readl(field) | mask);
1525 }
1526
1527 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1528 {
1529         vmcs_write32(VM_ENTRY_CONTROLS, val);
1530         vmx->vm_entry_controls_shadow = val;
1531 }
1532
1533 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1534 {
1535         if (vmx->vm_entry_controls_shadow != val)
1536                 vm_entry_controls_init(vmx, val);
1537 }
1538
1539 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1540 {
1541         return vmx->vm_entry_controls_shadow;
1542 }
1543
1544
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1546 {
1547         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 }
1549
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1551 {
1552         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 }
1554
1555 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1556 {
1557         vmcs_write32(VM_EXIT_CONTROLS, val);
1558         vmx->vm_exit_controls_shadow = val;
1559 }
1560
1561 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1562 {
1563         if (vmx->vm_exit_controls_shadow != val)
1564                 vm_exit_controls_init(vmx, val);
1565 }
1566
1567 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1568 {
1569         return vmx->vm_exit_controls_shadow;
1570 }
1571
1572
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1574 {
1575         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 }
1577
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1579 {
1580         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 }
1582
1583 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1584 {
1585         vmx->segment_cache.bitmask = 0;
1586 }
1587
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1589                                        unsigned field)
1590 {
1591         bool ret;
1592         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1593
1594         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1595                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1596                 vmx->segment_cache.bitmask = 0;
1597         }
1598         ret = vmx->segment_cache.bitmask & mask;
1599         vmx->segment_cache.bitmask |= mask;
1600         return ret;
1601 }
1602
1603 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1604 {
1605         u16 *p = &vmx->segment_cache.seg[seg].selector;
1606
1607         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1608                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1609         return *p;
1610 }
1611
1612 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1613 {
1614         ulong *p = &vmx->segment_cache.seg[seg].base;
1615
1616         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1617                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1618         return *p;
1619 }
1620
1621 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1622 {
1623         u32 *p = &vmx->segment_cache.seg[seg].limit;
1624
1625         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1626                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1627         return *p;
1628 }
1629
1630 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1631 {
1632         u32 *p = &vmx->segment_cache.seg[seg].ar;
1633
1634         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1635                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1636         return *p;
1637 }
1638
1639 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1640 {
1641         u32 eb;
1642
1643         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1644              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1645         if ((vcpu->guest_debug &
1646              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1647             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1648                 eb |= 1u << BP_VECTOR;
1649         if (to_vmx(vcpu)->rmode.vm86_active)
1650                 eb = ~0;
1651         if (enable_ept)
1652                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1653         if (vcpu->fpu_active)
1654                 eb &= ~(1u << NM_VECTOR);
1655
1656         /* When we are running a nested L2 guest and L1 specified for it a
1657          * certain exception bitmap, we must trap the same exceptions and pass
1658          * them to L1. When running L2, we will only handle the exceptions
1659          * specified above if L1 did not want them.
1660          */
1661         if (is_guest_mode(vcpu))
1662                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1663
1664         vmcs_write32(EXCEPTION_BITMAP, eb);
1665 }
1666
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1668                 unsigned long entry, unsigned long exit)
1669 {
1670         vm_entry_controls_clearbit(vmx, entry);
1671         vm_exit_controls_clearbit(vmx, exit);
1672 }
1673
1674 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 {
1676         unsigned i;
1677         struct msr_autoload *m = &vmx->msr_autoload;
1678
1679         switch (msr) {
1680         case MSR_EFER:
1681                 if (cpu_has_load_ia32_efer) {
1682                         clear_atomic_switch_msr_special(vmx,
1683                                         VM_ENTRY_LOAD_IA32_EFER,
1684                                         VM_EXIT_LOAD_IA32_EFER);
1685                         return;
1686                 }
1687                 break;
1688         case MSR_CORE_PERF_GLOBAL_CTRL:
1689                 if (cpu_has_load_perf_global_ctrl) {
1690                         clear_atomic_switch_msr_special(vmx,
1691                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1692                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1693                         return;
1694                 }
1695                 break;
1696         }
1697
1698         for (i = 0; i < m->nr; ++i)
1699                 if (m->guest[i].index == msr)
1700                         break;
1701
1702         if (i == m->nr)
1703                 return;
1704         --m->nr;
1705         m->guest[i] = m->guest[m->nr];
1706         m->host[i] = m->host[m->nr];
1707         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1708         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 }
1710
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1712                 unsigned long entry, unsigned long exit,
1713                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1714                 u64 guest_val, u64 host_val)
1715 {
1716         vmcs_write64(guest_val_vmcs, guest_val);
1717         vmcs_write64(host_val_vmcs, host_val);
1718         vm_entry_controls_setbit(vmx, entry);
1719         vm_exit_controls_setbit(vmx, exit);
1720 }
1721
1722 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1723                                   u64 guest_val, u64 host_val)
1724 {
1725         unsigned i;
1726         struct msr_autoload *m = &vmx->msr_autoload;
1727
1728         switch (msr) {
1729         case MSR_EFER:
1730                 if (cpu_has_load_ia32_efer) {
1731                         add_atomic_switch_msr_special(vmx,
1732                                         VM_ENTRY_LOAD_IA32_EFER,
1733                                         VM_EXIT_LOAD_IA32_EFER,
1734                                         GUEST_IA32_EFER,
1735                                         HOST_IA32_EFER,
1736                                         guest_val, host_val);
1737                         return;
1738                 }
1739                 break;
1740         case MSR_CORE_PERF_GLOBAL_CTRL:
1741                 if (cpu_has_load_perf_global_ctrl) {
1742                         add_atomic_switch_msr_special(vmx,
1743                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1744                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1746                                         HOST_IA32_PERF_GLOBAL_CTRL,
1747                                         guest_val, host_val);
1748                         return;
1749                 }
1750                 break;
1751         case MSR_IA32_PEBS_ENABLE:
1752                 /* PEBS needs a quiescent period after being disabled (to write
1753                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1754                  * provide that period, so a CPU could write host's record into
1755                  * guest's memory.
1756                  */
1757                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1758         }
1759
1760         for (i = 0; i < m->nr; ++i)
1761                 if (m->guest[i].index == msr)
1762                         break;
1763
1764         if (i == NR_AUTOLOAD_MSRS) {
1765                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1766                                 "Can't add msr %x\n", msr);
1767                 return;
1768         } else if (i == m->nr) {
1769                 ++m->nr;
1770                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1771                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1772         }
1773
1774         m->guest[i].index = msr;
1775         m->guest[i].value = guest_val;
1776         m->host[i].index = msr;
1777         m->host[i].value = host_val;
1778 }
1779
1780 static void reload_tss(void)
1781 {
1782         /*
1783          * VT restores TR but not its size.  Useless.
1784          */
1785         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1786         struct desc_struct *descs;
1787
1788         descs = (void *)gdt->address;
1789         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1790         load_TR_desc();
1791 }
1792
1793 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1794 {
1795         u64 guest_efer = vmx->vcpu.arch.efer;
1796         u64 ignore_bits = 0;
1797
1798         if (!enable_ept) {
1799                 /*
1800                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1801                  * host CPUID is more efficient than testing guest CPUID
1802                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1803                  */
1804                 if (boot_cpu_has(X86_FEATURE_SMEP))
1805                         guest_efer |= EFER_NX;
1806                 else if (!(guest_efer & EFER_NX))
1807                         ignore_bits |= EFER_NX;
1808         }
1809
1810         /*
1811          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1812          */
1813         ignore_bits |= EFER_SCE;
1814 #ifdef CONFIG_X86_64
1815         ignore_bits |= EFER_LMA | EFER_LME;
1816         /* SCE is meaningful only in long mode on Intel */
1817         if (guest_efer & EFER_LMA)
1818                 ignore_bits &= ~(u64)EFER_SCE;
1819 #endif
1820
1821         clear_atomic_switch_msr(vmx, MSR_EFER);
1822
1823         /*
1824          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1825          * On CPUs that support "load IA32_EFER", always switch EFER
1826          * atomically, since it's faster than switching it manually.
1827          */
1828         if (cpu_has_load_ia32_efer ||
1829             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1830                 if (!(guest_efer & EFER_LMA))
1831                         guest_efer &= ~EFER_LME;
1832                 if (guest_efer != host_efer)
1833                         add_atomic_switch_msr(vmx, MSR_EFER,
1834                                               guest_efer, host_efer);
1835                 return false;
1836         } else {
1837                 guest_efer &= ~ignore_bits;
1838                 guest_efer |= host_efer & ignore_bits;
1839
1840                 vmx->guest_msrs[efer_offset].data = guest_efer;
1841                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1842
1843                 return true;
1844         }
1845 }
1846
1847 static unsigned long segment_base(u16 selector)
1848 {
1849         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1850         struct desc_struct *d;
1851         unsigned long table_base;
1852         unsigned long v;
1853
1854         if (!(selector & ~3))
1855                 return 0;
1856
1857         table_base = gdt->address;
1858
1859         if (selector & 4) {           /* from ldt */
1860                 u16 ldt_selector = kvm_read_ldt();
1861
1862                 if (!(ldt_selector & ~3))
1863                         return 0;
1864
1865                 table_base = segment_base(ldt_selector);
1866         }
1867         d = (struct desc_struct *)(table_base + (selector & ~7));
1868         v = get_desc_base(d);
1869 #ifdef CONFIG_X86_64
1870        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1871                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1872 #endif
1873         return v;
1874 }
1875
1876 static inline unsigned long kvm_read_tr_base(void)
1877 {
1878         u16 tr;
1879         asm("str %0" : "=g"(tr));
1880         return segment_base(tr);
1881 }
1882
1883 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1884 {
1885         struct vcpu_vmx *vmx = to_vmx(vcpu);
1886         int i;
1887
1888         if (vmx->host_state.loaded)
1889                 return;
1890
1891         vmx->host_state.loaded = 1;
1892         /*
1893          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1894          * allow segment selectors with cpl > 0 or ti == 1.
1895          */
1896         vmx->host_state.ldt_sel = kvm_read_ldt();
1897         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1898         savesegment(fs, vmx->host_state.fs_sel);
1899         if (!(vmx->host_state.fs_sel & 7)) {
1900                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1901                 vmx->host_state.fs_reload_needed = 0;
1902         } else {
1903                 vmcs_write16(HOST_FS_SELECTOR, 0);
1904                 vmx->host_state.fs_reload_needed = 1;
1905         }
1906         savesegment(gs, vmx->host_state.gs_sel);
1907         if (!(vmx->host_state.gs_sel & 7))
1908                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1909         else {
1910                 vmcs_write16(HOST_GS_SELECTOR, 0);
1911                 vmx->host_state.gs_ldt_reload_needed = 1;
1912         }
1913
1914 #ifdef CONFIG_X86_64
1915         savesegment(ds, vmx->host_state.ds_sel);
1916         savesegment(es, vmx->host_state.es_sel);
1917 #endif
1918
1919 #ifdef CONFIG_X86_64
1920         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1921         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1922 #else
1923         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1924         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1925 #endif
1926
1927 #ifdef CONFIG_X86_64
1928         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1929         if (is_long_mode(&vmx->vcpu))
1930                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1931 #endif
1932         if (boot_cpu_has(X86_FEATURE_MPX))
1933                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1934         for (i = 0; i < vmx->save_nmsrs; ++i)
1935                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1936                                    vmx->guest_msrs[i].data,
1937                                    vmx->guest_msrs[i].mask);
1938 }
1939
1940 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1941 {
1942         if (!vmx->host_state.loaded)
1943                 return;
1944
1945         ++vmx->vcpu.stat.host_state_reload;
1946         vmx->host_state.loaded = 0;
1947 #ifdef CONFIG_X86_64
1948         if (is_long_mode(&vmx->vcpu))
1949                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1950 #endif
1951         if (vmx->host_state.gs_ldt_reload_needed) {
1952                 kvm_load_ldt(vmx->host_state.ldt_sel);
1953 #ifdef CONFIG_X86_64
1954                 load_gs_index(vmx->host_state.gs_sel);
1955 #else
1956                 loadsegment(gs, vmx->host_state.gs_sel);
1957 #endif
1958         }
1959         if (vmx->host_state.fs_reload_needed)
1960                 loadsegment(fs, vmx->host_state.fs_sel);
1961 #ifdef CONFIG_X86_64
1962         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1963                 loadsegment(ds, vmx->host_state.ds_sel);
1964                 loadsegment(es, vmx->host_state.es_sel);
1965         }
1966 #endif
1967         reload_tss();
1968 #ifdef CONFIG_X86_64
1969         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1970 #endif
1971         if (vmx->host_state.msr_host_bndcfgs)
1972                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1973         /*
1974          * If the FPU is not active (through the host task or
1975          * the guest vcpu), then restore the cr0.TS bit.
1976          */
1977         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1978                 stts();
1979         load_gdt(this_cpu_ptr(&host_gdt));
1980 }
1981
1982 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1983 {
1984         preempt_disable();
1985         __vmx_load_host_state(vmx);
1986         preempt_enable();
1987 }
1988
1989 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1990 {
1991         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1992         struct pi_desc old, new;
1993         unsigned int dest;
1994
1995         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1996                 !irq_remapping_cap(IRQ_POSTING_CAP))
1997                 return;
1998
1999         do {
2000                 old.control = new.control = pi_desc->control;
2001
2002                 /*
2003                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2004                  * are two possible cases:
2005                  * 1. After running 'pre_block', context switch
2006                  *    happened. For this case, 'sn' was set in
2007                  *    vmx_vcpu_put(), so we need to clear it here.
2008                  * 2. After running 'pre_block', we were blocked,
2009                  *    and woken up by some other guy. For this case,
2010                  *    we don't need to do anything, 'pi_post_block'
2011                  *    will do everything for us. However, we cannot
2012                  *    check whether it is case #1 or case #2 here
2013                  *    (maybe, not needed), so we also clear sn here,
2014                  *    I think it is not a big deal.
2015                  */
2016                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2017                         if (vcpu->cpu != cpu) {
2018                                 dest = cpu_physical_id(cpu);
2019
2020                                 if (x2apic_enabled())
2021                                         new.ndst = dest;
2022                                 else
2023                                         new.ndst = (dest << 8) & 0xFF00;
2024                         }
2025
2026                         /* set 'NV' to 'notification vector' */
2027                         new.nv = POSTED_INTR_VECTOR;
2028                 }
2029
2030                 /* Allow posting non-urgent interrupts */
2031                 new.sn = 0;
2032         } while (cmpxchg(&pi_desc->control, old.control,
2033                         new.control) != old.control);
2034 }
2035 /*
2036  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2037  * vcpu mutex is already taken.
2038  */
2039 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2040 {
2041         struct vcpu_vmx *vmx = to_vmx(vcpu);
2042         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2043
2044         if (!vmm_exclusive)
2045                 kvm_cpu_vmxon(phys_addr);
2046         else if (vmx->loaded_vmcs->cpu != cpu)
2047                 loaded_vmcs_clear(vmx->loaded_vmcs);
2048
2049         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2050                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2051                 vmcs_load(vmx->loaded_vmcs->vmcs);
2052         }
2053
2054         if (vmx->loaded_vmcs->cpu != cpu) {
2055                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2056                 unsigned long sysenter_esp;
2057
2058                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2059                 local_irq_disable();
2060                 crash_disable_local_vmclear(cpu);
2061
2062                 /*
2063                  * Read loaded_vmcs->cpu should be before fetching
2064                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2065                  * See the comments in __loaded_vmcs_clear().
2066                  */
2067                 smp_rmb();
2068
2069                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2070                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2071                 crash_enable_local_vmclear(cpu);
2072                 local_irq_enable();
2073
2074                 /*
2075                  * Linux uses per-cpu TSS and GDT, so set these when switching
2076                  * processors.
2077                  */
2078                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2079                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2080
2081                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2082                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2083
2084                 vmx->loaded_vmcs->cpu = cpu;
2085         }
2086
2087         /* Setup TSC multiplier */
2088         if (kvm_has_tsc_control &&
2089             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2090                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2091                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2092         }
2093
2094         vmx_vcpu_pi_load(vcpu, cpu);
2095 }
2096
2097 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2098 {
2099         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2100
2101         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2102                 !irq_remapping_cap(IRQ_POSTING_CAP))
2103                 return;
2104
2105         /* Set SN when the vCPU is preempted */
2106         if (vcpu->preempted)
2107                 pi_set_sn(pi_desc);
2108 }
2109
2110 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2111 {
2112         vmx_vcpu_pi_put(vcpu);
2113
2114         __vmx_load_host_state(to_vmx(vcpu));
2115         if (!vmm_exclusive) {
2116                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2117                 vcpu->cpu = -1;
2118                 kvm_cpu_vmxoff();
2119         }
2120 }
2121
2122 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2123 {
2124         ulong cr0;
2125
2126         if (vcpu->fpu_active)
2127                 return;
2128         vcpu->fpu_active = 1;
2129         cr0 = vmcs_readl(GUEST_CR0);
2130         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2131         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2132         vmcs_writel(GUEST_CR0, cr0);
2133         update_exception_bitmap(vcpu);
2134         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2135         if (is_guest_mode(vcpu))
2136                 vcpu->arch.cr0_guest_owned_bits &=
2137                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2138         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2139 }
2140
2141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2142
2143 /*
2144  * Return the cr0 value that a nested guest would read. This is a combination
2145  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2146  * its hypervisor (cr0_read_shadow).
2147  */
2148 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2149 {
2150         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2151                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2152 }
2153 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2154 {
2155         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2156                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2157 }
2158
2159 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2160 {
2161         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2162          * set this *before* calling this function.
2163          */
2164         vmx_decache_cr0_guest_bits(vcpu);
2165         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2166         update_exception_bitmap(vcpu);
2167         vcpu->arch.cr0_guest_owned_bits = 0;
2168         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2169         if (is_guest_mode(vcpu)) {
2170                 /*
2171                  * L1's specified read shadow might not contain the TS bit,
2172                  * so now that we turned on shadowing of this bit, we need to
2173                  * set this bit of the shadow. Like in nested_vmx_run we need
2174                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2175                  * up-to-date here because we just decached cr0.TS (and we'll
2176                  * only update vmcs12->guest_cr0 on nested exit).
2177                  */
2178                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2179                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2180                         (vcpu->arch.cr0 & X86_CR0_TS);
2181                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2182         } else
2183                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2184 }
2185
2186 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2187 {
2188         unsigned long rflags, save_rflags;
2189
2190         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2191                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2192                 rflags = vmcs_readl(GUEST_RFLAGS);
2193                 if (to_vmx(vcpu)->rmode.vm86_active) {
2194                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2195                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2196                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2197                 }
2198                 to_vmx(vcpu)->rflags = rflags;
2199         }
2200         return to_vmx(vcpu)->rflags;
2201 }
2202
2203 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2204 {
2205         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2206         to_vmx(vcpu)->rflags = rflags;
2207         if (to_vmx(vcpu)->rmode.vm86_active) {
2208                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2209                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2210         }
2211         vmcs_writel(GUEST_RFLAGS, rflags);
2212 }
2213
2214 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2215 {
2216         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2217         int ret = 0;
2218
2219         if (interruptibility & GUEST_INTR_STATE_STI)
2220                 ret |= KVM_X86_SHADOW_INT_STI;
2221         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2222                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2223
2224         return ret;
2225 }
2226
2227 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2228 {
2229         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2230         u32 interruptibility = interruptibility_old;
2231
2232         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2233
2234         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2235                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2236         else if (mask & KVM_X86_SHADOW_INT_STI)
2237                 interruptibility |= GUEST_INTR_STATE_STI;
2238
2239         if ((interruptibility != interruptibility_old))
2240                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2241 }
2242
2243 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2244 {
2245         unsigned long rip;
2246
2247         rip = kvm_rip_read(vcpu);
2248         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2249         kvm_rip_write(vcpu, rip);
2250
2251         /* skipping an emulated instruction also counts */
2252         vmx_set_interrupt_shadow(vcpu, 0);
2253 }
2254
2255 /*
2256  * KVM wants to inject page-faults which it got to the guest. This function
2257  * checks whether in a nested guest, we need to inject them to L1 or L2.
2258  */
2259 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2260 {
2261         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2262
2263         if (!(vmcs12->exception_bitmap & (1u << nr)))
2264                 return 0;
2265
2266         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2267                           vmcs_read32(VM_EXIT_INTR_INFO),
2268                           vmcs_readl(EXIT_QUALIFICATION));
2269         return 1;
2270 }
2271
2272 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2273                                 bool has_error_code, u32 error_code,
2274                                 bool reinject)
2275 {
2276         struct vcpu_vmx *vmx = to_vmx(vcpu);
2277         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2278
2279         if (!reinject && is_guest_mode(vcpu) &&
2280             nested_vmx_check_exception(vcpu, nr))
2281                 return;
2282
2283         if (has_error_code) {
2284                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2285                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2286         }
2287
2288         if (vmx->rmode.vm86_active) {
2289                 int inc_eip = 0;
2290                 if (kvm_exception_is_soft(nr))
2291                         inc_eip = vcpu->arch.event_exit_inst_len;
2292                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2293                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2294                 return;
2295         }
2296
2297         if (kvm_exception_is_soft(nr)) {
2298                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2299                              vmx->vcpu.arch.event_exit_inst_len);
2300                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2301         } else
2302                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2303
2304         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2305 }
2306
2307 static bool vmx_rdtscp_supported(void)
2308 {
2309         return cpu_has_vmx_rdtscp();
2310 }
2311
2312 static bool vmx_invpcid_supported(void)
2313 {
2314         return cpu_has_vmx_invpcid() && enable_ept;
2315 }
2316
2317 /*
2318  * Swap MSR entry in host/guest MSR entry array.
2319  */
2320 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2321 {
2322         struct shared_msr_entry tmp;
2323
2324         tmp = vmx->guest_msrs[to];
2325         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2326         vmx->guest_msrs[from] = tmp;
2327 }
2328
2329 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2330 {
2331         unsigned long *msr_bitmap;
2332
2333         if (is_guest_mode(vcpu))
2334                 msr_bitmap = vmx_msr_bitmap_nested;
2335         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2336                 if (is_long_mode(vcpu))
2337                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2338                 else
2339                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2340         } else {
2341                 if (is_long_mode(vcpu))
2342                         msr_bitmap = vmx_msr_bitmap_longmode;
2343                 else
2344                         msr_bitmap = vmx_msr_bitmap_legacy;
2345         }
2346
2347         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2348 }
2349
2350 /*
2351  * Set up the vmcs to automatically save and restore system
2352  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2353  * mode, as fiddling with msrs is very expensive.
2354  */
2355 static void setup_msrs(struct vcpu_vmx *vmx)
2356 {
2357         int save_nmsrs, index;
2358
2359         save_nmsrs = 0;
2360 #ifdef CONFIG_X86_64
2361         if (is_long_mode(&vmx->vcpu)) {
2362                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2363                 if (index >= 0)
2364                         move_msr_up(vmx, index, save_nmsrs++);
2365                 index = __find_msr_index(vmx, MSR_LSTAR);
2366                 if (index >= 0)
2367                         move_msr_up(vmx, index, save_nmsrs++);
2368                 index = __find_msr_index(vmx, MSR_CSTAR);
2369                 if (index >= 0)
2370                         move_msr_up(vmx, index, save_nmsrs++);
2371                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2372                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2373                         move_msr_up(vmx, index, save_nmsrs++);
2374                 /*
2375                  * MSR_STAR is only needed on long mode guests, and only
2376                  * if efer.sce is enabled.
2377                  */
2378                 index = __find_msr_index(vmx, MSR_STAR);
2379                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2380                         move_msr_up(vmx, index, save_nmsrs++);
2381         }
2382 #endif
2383         index = __find_msr_index(vmx, MSR_EFER);
2384         if (index >= 0 && update_transition_efer(vmx, index))
2385                 move_msr_up(vmx, index, save_nmsrs++);
2386
2387         vmx->save_nmsrs = save_nmsrs;
2388
2389         if (cpu_has_vmx_msr_bitmap())
2390                 vmx_set_msr_bitmap(&vmx->vcpu);
2391 }
2392
2393 /*
2394  * reads and returns guest's timestamp counter "register"
2395  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2396  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2397  */
2398 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2399 {
2400         u64 host_tsc, tsc_offset;
2401
2402         host_tsc = rdtsc();
2403         tsc_offset = vmcs_read64(TSC_OFFSET);
2404         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2405 }
2406
2407 /*
2408  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2409  * counter, even if a nested guest (L2) is currently running.
2410  */
2411 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2412 {
2413         u64 tsc_offset;
2414
2415         tsc_offset = is_guest_mode(vcpu) ?
2416                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2417                 vmcs_read64(TSC_OFFSET);
2418         return host_tsc + tsc_offset;
2419 }
2420
2421 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2422 {
2423         return vmcs_read64(TSC_OFFSET);
2424 }
2425
2426 /*
2427  * writes 'offset' into guest's timestamp counter offset register
2428  */
2429 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2430 {
2431         if (is_guest_mode(vcpu)) {
2432                 /*
2433                  * We're here if L1 chose not to trap WRMSR to TSC. According
2434                  * to the spec, this should set L1's TSC; The offset that L1
2435                  * set for L2 remains unchanged, and still needs to be added
2436                  * to the newly set TSC to get L2's TSC.
2437                  */
2438                 struct vmcs12 *vmcs12;
2439                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2440                 /* recalculate vmcs02.TSC_OFFSET: */
2441                 vmcs12 = get_vmcs12(vcpu);
2442                 vmcs_write64(TSC_OFFSET, offset +
2443                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2444                          vmcs12->tsc_offset : 0));
2445         } else {
2446                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2447                                            vmcs_read64(TSC_OFFSET), offset);
2448                 vmcs_write64(TSC_OFFSET, offset);
2449         }
2450 }
2451
2452 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2453 {
2454         u64 offset = vmcs_read64(TSC_OFFSET);
2455
2456         vmcs_write64(TSC_OFFSET, offset + adjustment);
2457         if (is_guest_mode(vcpu)) {
2458                 /* Even when running L2, the adjustment needs to apply to L1 */
2459                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2460         } else
2461                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2462                                            offset + adjustment);
2463 }
2464
2465 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2466 {
2467         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2468         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2469 }
2470
2471 /*
2472  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2473  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2474  * all guests if the "nested" module option is off, and can also be disabled
2475  * for a single guest by disabling its VMX cpuid bit.
2476  */
2477 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2478 {
2479         return nested && guest_cpuid_has_vmx(vcpu);
2480 }
2481
2482 /*
2483  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2484  * returned for the various VMX controls MSRs when nested VMX is enabled.
2485  * The same values should also be used to verify that vmcs12 control fields are
2486  * valid during nested entry from L1 to L2.
2487  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2488  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2489  * bit in the high half is on if the corresponding bit in the control field
2490  * may be on. See also vmx_control_verify().
2491  */
2492 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2493 {
2494         /*
2495          * Note that as a general rule, the high half of the MSRs (bits in
2496          * the control fields which may be 1) should be initialized by the
2497          * intersection of the underlying hardware's MSR (i.e., features which
2498          * can be supported) and the list of features we want to expose -
2499          * because they are known to be properly supported in our code.
2500          * Also, usually, the low half of the MSRs (bits which must be 1) can
2501          * be set to 0, meaning that L1 may turn off any of these bits. The
2502          * reason is that if one of these bits is necessary, it will appear
2503          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2504          * fields of vmcs01 and vmcs02, will turn these bits off - and
2505          * nested_vmx_exit_handled() will not pass related exits to L1.
2506          * These rules have exceptions below.
2507          */
2508
2509         /* pin-based controls */
2510         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2511                 vmx->nested.nested_vmx_pinbased_ctls_low,
2512                 vmx->nested.nested_vmx_pinbased_ctls_high);
2513         vmx->nested.nested_vmx_pinbased_ctls_low |=
2514                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2515         vmx->nested.nested_vmx_pinbased_ctls_high &=
2516                 PIN_BASED_EXT_INTR_MASK |
2517                 PIN_BASED_NMI_EXITING |
2518                 PIN_BASED_VIRTUAL_NMIS;
2519         vmx->nested.nested_vmx_pinbased_ctls_high |=
2520                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2521                 PIN_BASED_VMX_PREEMPTION_TIMER;
2522         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2523                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2524                         PIN_BASED_POSTED_INTR;
2525
2526         /* exit controls */
2527         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2528                 vmx->nested.nested_vmx_exit_ctls_low,
2529                 vmx->nested.nested_vmx_exit_ctls_high);
2530         vmx->nested.nested_vmx_exit_ctls_low =
2531                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2532
2533         vmx->nested.nested_vmx_exit_ctls_high &=
2534 #ifdef CONFIG_X86_64
2535                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2536 #endif
2537                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2538         vmx->nested.nested_vmx_exit_ctls_high |=
2539                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2540                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2541                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2542
2543         if (vmx_mpx_supported())
2544                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2545
2546         /* We support free control of debug control saving. */
2547         vmx->nested.nested_vmx_true_exit_ctls_low =
2548                 vmx->nested.nested_vmx_exit_ctls_low &
2549                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2550
2551         /* entry controls */
2552         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2553                 vmx->nested.nested_vmx_entry_ctls_low,
2554                 vmx->nested.nested_vmx_entry_ctls_high);
2555         vmx->nested.nested_vmx_entry_ctls_low =
2556                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2557         vmx->nested.nested_vmx_entry_ctls_high &=
2558 #ifdef CONFIG_X86_64
2559                 VM_ENTRY_IA32E_MODE |
2560 #endif
2561                 VM_ENTRY_LOAD_IA32_PAT;
2562         vmx->nested.nested_vmx_entry_ctls_high |=
2563                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2564         if (vmx_mpx_supported())
2565                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2566
2567         /* We support free control of debug control loading. */
2568         vmx->nested.nested_vmx_true_entry_ctls_low =
2569                 vmx->nested.nested_vmx_entry_ctls_low &
2570                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2571
2572         /* cpu-based controls */
2573         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2574                 vmx->nested.nested_vmx_procbased_ctls_low,
2575                 vmx->nested.nested_vmx_procbased_ctls_high);
2576         vmx->nested.nested_vmx_procbased_ctls_low =
2577                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2578         vmx->nested.nested_vmx_procbased_ctls_high &=
2579                 CPU_BASED_VIRTUAL_INTR_PENDING |
2580                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2581                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2582                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2583                 CPU_BASED_CR3_STORE_EXITING |
2584 #ifdef CONFIG_X86_64
2585                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2586 #endif
2587                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2588                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2589                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2590                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2591                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2592         /*
2593          * We can allow some features even when not supported by the
2594          * hardware. For example, L1 can specify an MSR bitmap - and we
2595          * can use it to avoid exits to L1 - even when L0 runs L2
2596          * without MSR bitmaps.
2597          */
2598         vmx->nested.nested_vmx_procbased_ctls_high |=
2599                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2600                 CPU_BASED_USE_MSR_BITMAPS;
2601
2602         /* We support free control of CR3 access interception. */
2603         vmx->nested.nested_vmx_true_procbased_ctls_low =
2604                 vmx->nested.nested_vmx_procbased_ctls_low &
2605                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2606
2607         /* secondary cpu-based controls */
2608         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2609                 vmx->nested.nested_vmx_secondary_ctls_low,
2610                 vmx->nested.nested_vmx_secondary_ctls_high);
2611         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2612         vmx->nested.nested_vmx_secondary_ctls_high &=
2613                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2614                 SECONDARY_EXEC_RDTSCP |
2615                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2616                 SECONDARY_EXEC_ENABLE_VPID |
2617                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2618                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2619                 SECONDARY_EXEC_WBINVD_EXITING |
2620                 SECONDARY_EXEC_XSAVES |
2621                 SECONDARY_EXEC_PCOMMIT;
2622
2623         if (enable_ept) {
2624                 /* nested EPT: emulate EPT also to L1 */
2625                 vmx->nested.nested_vmx_secondary_ctls_high |=
2626                         SECONDARY_EXEC_ENABLE_EPT;
2627                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2628                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2629                          VMX_EPT_INVEPT_BIT;
2630                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2631                 /*
2632                  * For nested guests, we don't do anything specific
2633                  * for single context invalidation. Hence, only advertise
2634                  * support for global context invalidation.
2635                  */
2636                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2637         } else
2638                 vmx->nested.nested_vmx_ept_caps = 0;
2639
2640         if (enable_vpid)
2641                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2642                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2643         else
2644                 vmx->nested.nested_vmx_vpid_caps = 0;
2645
2646         if (enable_unrestricted_guest)
2647                 vmx->nested.nested_vmx_secondary_ctls_high |=
2648                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2649
2650         /* miscellaneous data */
2651         rdmsr(MSR_IA32_VMX_MISC,
2652                 vmx->nested.nested_vmx_misc_low,
2653                 vmx->nested.nested_vmx_misc_high);
2654         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2655         vmx->nested.nested_vmx_misc_low |=
2656                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2657                 VMX_MISC_ACTIVITY_HLT;
2658         vmx->nested.nested_vmx_misc_high = 0;
2659 }
2660
2661 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2662 {
2663         /*
2664          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2665          */
2666         return ((control & high) | low) == control;
2667 }
2668
2669 static inline u64 vmx_control_msr(u32 low, u32 high)
2670 {
2671         return low | ((u64)high << 32);
2672 }
2673
2674 /* Returns 0 on success, non-0 otherwise. */
2675 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2676 {
2677         struct vcpu_vmx *vmx = to_vmx(vcpu);
2678
2679         switch (msr_index) {
2680         case MSR_IA32_VMX_BASIC:
2681                 /*
2682                  * This MSR reports some information about VMX support. We
2683                  * should return information about the VMX we emulate for the
2684                  * guest, and the VMCS structure we give it - not about the
2685                  * VMX support of the underlying hardware.
2686                  */
2687                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2688                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2689                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2690                 break;
2691         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2692         case MSR_IA32_VMX_PINBASED_CTLS:
2693                 *pdata = vmx_control_msr(
2694                         vmx->nested.nested_vmx_pinbased_ctls_low,
2695                         vmx->nested.nested_vmx_pinbased_ctls_high);
2696                 break;
2697         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2698                 *pdata = vmx_control_msr(
2699                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2700                         vmx->nested.nested_vmx_procbased_ctls_high);
2701                 break;
2702         case MSR_IA32_VMX_PROCBASED_CTLS:
2703                 *pdata = vmx_control_msr(
2704                         vmx->nested.nested_vmx_procbased_ctls_low,
2705                         vmx->nested.nested_vmx_procbased_ctls_high);
2706                 break;
2707         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2708                 *pdata = vmx_control_msr(
2709                         vmx->nested.nested_vmx_true_exit_ctls_low,
2710                         vmx->nested.nested_vmx_exit_ctls_high);
2711                 break;
2712         case MSR_IA32_VMX_EXIT_CTLS:
2713                 *pdata = vmx_control_msr(
2714                         vmx->nested.nested_vmx_exit_ctls_low,
2715                         vmx->nested.nested_vmx_exit_ctls_high);
2716                 break;
2717         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2718                 *pdata = vmx_control_msr(
2719                         vmx->nested.nested_vmx_true_entry_ctls_low,
2720                         vmx->nested.nested_vmx_entry_ctls_high);
2721                 break;
2722         case MSR_IA32_VMX_ENTRY_CTLS:
2723                 *pdata = vmx_control_msr(
2724                         vmx->nested.nested_vmx_entry_ctls_low,
2725                         vmx->nested.nested_vmx_entry_ctls_high);
2726                 break;
2727         case MSR_IA32_VMX_MISC:
2728                 *pdata = vmx_control_msr(
2729                         vmx->nested.nested_vmx_misc_low,
2730                         vmx->nested.nested_vmx_misc_high);
2731                 break;
2732         /*
2733          * These MSRs specify bits which the guest must keep fixed (on or off)
2734          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2735          * We picked the standard core2 setting.
2736          */
2737 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2738 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2739         case MSR_IA32_VMX_CR0_FIXED0:
2740                 *pdata = VMXON_CR0_ALWAYSON;
2741                 break;
2742         case MSR_IA32_VMX_CR0_FIXED1:
2743                 *pdata = -1ULL;
2744                 break;
2745         case MSR_IA32_VMX_CR4_FIXED0:
2746                 *pdata = VMXON_CR4_ALWAYSON;
2747                 break;
2748         case MSR_IA32_VMX_CR4_FIXED1:
2749                 *pdata = -1ULL;
2750                 break;
2751         case MSR_IA32_VMX_VMCS_ENUM:
2752                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2753                 break;
2754         case MSR_IA32_VMX_PROCBASED_CTLS2:
2755                 *pdata = vmx_control_msr(
2756                         vmx->nested.nested_vmx_secondary_ctls_low,
2757                         vmx->nested.nested_vmx_secondary_ctls_high);
2758                 break;
2759         case MSR_IA32_VMX_EPT_VPID_CAP:
2760                 /* Currently, no nested vpid support */
2761                 *pdata = vmx->nested.nested_vmx_ept_caps |
2762                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2763                 break;
2764         default:
2765                 return 1;
2766         }
2767
2768         return 0;
2769 }
2770
2771 /*
2772  * Reads an msr value (of 'msr_index') into 'pdata'.
2773  * Returns 0 on success, non-0 otherwise.
2774  * Assumes vcpu_load() was already called.
2775  */
2776 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2777 {
2778         struct shared_msr_entry *msr;
2779
2780         switch (msr_info->index) {
2781 #ifdef CONFIG_X86_64
2782         case MSR_FS_BASE:
2783                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2784                 break;
2785         case MSR_GS_BASE:
2786                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2787                 break;
2788         case MSR_KERNEL_GS_BASE:
2789                 vmx_load_host_state(to_vmx(vcpu));
2790                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2791                 break;
2792 #endif
2793         case MSR_EFER:
2794                 return kvm_get_msr_common(vcpu, msr_info);
2795         case MSR_IA32_TSC:
2796                 msr_info->data = guest_read_tsc(vcpu);
2797                 break;
2798         case MSR_IA32_SYSENTER_CS:
2799                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2800                 break;
2801         case MSR_IA32_SYSENTER_EIP:
2802                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2803                 break;
2804         case MSR_IA32_SYSENTER_ESP:
2805                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2806                 break;
2807         case MSR_IA32_BNDCFGS:
2808                 if (!vmx_mpx_supported())
2809                         return 1;
2810                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2811                 break;
2812         case MSR_IA32_FEATURE_CONTROL:
2813                 if (!nested_vmx_allowed(vcpu))
2814                         return 1;
2815                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2816                 break;
2817         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2818                 if (!nested_vmx_allowed(vcpu))
2819                         return 1;
2820                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2821         case MSR_IA32_XSS:
2822                 if (!vmx_xsaves_supported())
2823                         return 1;
2824                 msr_info->data = vcpu->arch.ia32_xss;
2825                 break;
2826         case MSR_TSC_AUX:
2827                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2828                         return 1;
2829                 /* Otherwise falls through */
2830         default:
2831                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2832                 if (msr) {
2833                         msr_info->data = msr->data;
2834                         break;
2835                 }
2836                 return kvm_get_msr_common(vcpu, msr_info);
2837         }
2838
2839         return 0;
2840 }
2841
2842 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2843
2844 /*
2845  * Writes msr value into into the appropriate "register".
2846  * Returns 0 on success, non-0 otherwise.
2847  * Assumes vcpu_load() was already called.
2848  */
2849 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2850 {
2851         struct vcpu_vmx *vmx = to_vmx(vcpu);
2852         struct shared_msr_entry *msr;
2853         int ret = 0;
2854         u32 msr_index = msr_info->index;
2855         u64 data = msr_info->data;
2856
2857         switch (msr_index) {
2858         case MSR_EFER:
2859                 ret = kvm_set_msr_common(vcpu, msr_info);
2860                 break;
2861 #ifdef CONFIG_X86_64
2862         case MSR_FS_BASE:
2863                 vmx_segment_cache_clear(vmx);
2864                 vmcs_writel(GUEST_FS_BASE, data);
2865                 break;
2866         case MSR_GS_BASE:
2867                 vmx_segment_cache_clear(vmx);
2868                 vmcs_writel(GUEST_GS_BASE, data);
2869                 break;
2870         case MSR_KERNEL_GS_BASE:
2871                 vmx_load_host_state(vmx);
2872                 vmx->msr_guest_kernel_gs_base = data;
2873                 break;
2874 #endif
2875         case MSR_IA32_SYSENTER_CS:
2876                 vmcs_write32(GUEST_SYSENTER_CS, data);
2877                 break;
2878         case MSR_IA32_SYSENTER_EIP:
2879                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2880                 break;
2881         case MSR_IA32_SYSENTER_ESP:
2882                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2883                 break;
2884         case MSR_IA32_BNDCFGS:
2885                 if (!vmx_mpx_supported())
2886                         return 1;
2887                 vmcs_write64(GUEST_BNDCFGS, data);
2888                 break;
2889         case MSR_IA32_TSC:
2890                 kvm_write_tsc(vcpu, msr_info);
2891                 break;
2892         case MSR_IA32_CR_PAT:
2893                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2894                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2895                                 return 1;
2896                         vmcs_write64(GUEST_IA32_PAT, data);
2897                         vcpu->arch.pat = data;
2898                         break;
2899                 }
2900                 ret = kvm_set_msr_common(vcpu, msr_info);
2901                 break;
2902         case MSR_IA32_TSC_ADJUST:
2903                 ret = kvm_set_msr_common(vcpu, msr_info);
2904                 break;
2905         case MSR_IA32_FEATURE_CONTROL:
2906                 if (!nested_vmx_allowed(vcpu) ||
2907                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2908                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2909                         return 1;
2910                 vmx->nested.msr_ia32_feature_control = data;
2911                 if (msr_info->host_initiated && data == 0)
2912                         vmx_leave_nested(vcpu);
2913                 break;
2914         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2915                 return 1; /* they are read-only */
2916         case MSR_IA32_XSS:
2917                 if (!vmx_xsaves_supported())
2918                         return 1;
2919                 /*
2920                  * The only supported bit as of Skylake is bit 8, but
2921                  * it is not supported on KVM.
2922                  */
2923                 if (data != 0)
2924                         return 1;
2925                 vcpu->arch.ia32_xss = data;
2926                 if (vcpu->arch.ia32_xss != host_xss)
2927                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2928                                 vcpu->arch.ia32_xss, host_xss);
2929                 else
2930                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2931                 break;
2932         case MSR_TSC_AUX:
2933                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2934                         return 1;
2935                 /* Check reserved bit, higher 32 bits should be zero */
2936                 if ((data >> 32) != 0)
2937                         return 1;
2938                 /* Otherwise falls through */
2939         default:
2940                 msr = find_msr_entry(vmx, msr_index);
2941                 if (msr) {
2942                         u64 old_msr_data = msr->data;
2943                         msr->data = data;
2944                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2945                                 preempt_disable();
2946                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2947                                                          msr->mask);
2948                                 preempt_enable();
2949                                 if (ret)
2950                                         msr->data = old_msr_data;
2951                         }
2952                         break;
2953                 }
2954                 ret = kvm_set_msr_common(vcpu, msr_info);
2955         }
2956
2957         return ret;
2958 }
2959
2960 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2961 {
2962         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2963         switch (reg) {
2964         case VCPU_REGS_RSP:
2965                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2966                 break;
2967         case VCPU_REGS_RIP:
2968                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2969                 break;
2970         case VCPU_EXREG_PDPTR:
2971                 if (enable_ept)
2972                         ept_save_pdptrs(vcpu);
2973                 break;
2974         default:
2975                 break;
2976         }
2977 }
2978
2979 static __init int cpu_has_kvm_support(void)
2980 {
2981         return cpu_has_vmx();
2982 }
2983
2984 static __init int vmx_disabled_by_bios(void)
2985 {
2986         u64 msr;
2987
2988         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2989         if (msr & FEATURE_CONTROL_LOCKED) {
2990                 /* launched w/ TXT and VMX disabled */
2991                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2992                         && tboot_enabled())
2993                         return 1;
2994                 /* launched w/o TXT and VMX only enabled w/ TXT */
2995                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2996                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2997                         && !tboot_enabled()) {
2998                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2999                                 "activate TXT before enabling KVM\n");
3000                         return 1;
3001                 }
3002                 /* launched w/o TXT and VMX disabled */
3003                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3004                         && !tboot_enabled())
3005                         return 1;
3006         }
3007
3008         return 0;
3009 }
3010
3011 static void kvm_cpu_vmxon(u64 addr)
3012 {
3013         asm volatile (ASM_VMX_VMXON_RAX
3014                         : : "a"(&addr), "m"(addr)
3015                         : "memory", "cc");
3016 }
3017
3018 static int hardware_enable(void)
3019 {
3020         int cpu = raw_smp_processor_id();
3021         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3022         u64 old, test_bits;
3023
3024         if (cr4_read_shadow() & X86_CR4_VMXE)
3025                 return -EBUSY;
3026
3027         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3028         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3029         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3030
3031         /*
3032          * Now we can enable the vmclear operation in kdump
3033          * since the loaded_vmcss_on_cpu list on this cpu
3034          * has been initialized.
3035          *
3036          * Though the cpu is not in VMX operation now, there
3037          * is no problem to enable the vmclear operation
3038          * for the loaded_vmcss_on_cpu list is empty!
3039          */
3040         crash_enable_local_vmclear(cpu);
3041
3042         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3043
3044         test_bits = FEATURE_CONTROL_LOCKED;
3045         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3046         if (tboot_enabled())
3047                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3048
3049         if ((old & test_bits) != test_bits) {
3050                 /* enable and lock */
3051                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3052         }
3053         cr4_set_bits(X86_CR4_VMXE);
3054
3055         if (vmm_exclusive) {
3056                 kvm_cpu_vmxon(phys_addr);
3057                 ept_sync_global();
3058         }
3059
3060         native_store_gdt(this_cpu_ptr(&host_gdt));
3061
3062         return 0;
3063 }
3064
3065 static void vmclear_local_loaded_vmcss(void)
3066 {
3067         int cpu = raw_smp_processor_id();
3068         struct loaded_vmcs *v, *n;
3069
3070         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3071                                  loaded_vmcss_on_cpu_link)
3072                 __loaded_vmcs_clear(v);
3073 }
3074
3075
3076 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3077  * tricks.
3078  */
3079 static void kvm_cpu_vmxoff(void)
3080 {
3081         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3082 }
3083
3084 static void hardware_disable(void)
3085 {
3086         if (vmm_exclusive) {
3087                 vmclear_local_loaded_vmcss();
3088                 kvm_cpu_vmxoff();
3089         }
3090         cr4_clear_bits(X86_CR4_VMXE);
3091 }
3092
3093 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3094                                       u32 msr, u32 *result)
3095 {
3096         u32 vmx_msr_low, vmx_msr_high;
3097         u32 ctl = ctl_min | ctl_opt;
3098
3099         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3100
3101         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3102         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3103
3104         /* Ensure minimum (required) set of control bits are supported. */
3105         if (ctl_min & ~ctl)
3106                 return -EIO;
3107
3108         *result = ctl;
3109         return 0;
3110 }
3111
3112 static __init bool allow_1_setting(u32 msr, u32 ctl)
3113 {
3114         u32 vmx_msr_low, vmx_msr_high;
3115
3116         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3117         return vmx_msr_high & ctl;
3118 }
3119
3120 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3121 {
3122         u32 vmx_msr_low, vmx_msr_high;
3123         u32 min, opt, min2, opt2;
3124         u32 _pin_based_exec_control = 0;
3125         u32 _cpu_based_exec_control = 0;
3126         u32 _cpu_based_2nd_exec_control = 0;
3127         u32 _vmexit_control = 0;
3128         u32 _vmentry_control = 0;
3129
3130         min = CPU_BASED_HLT_EXITING |
3131 #ifdef CONFIG_X86_64
3132               CPU_BASED_CR8_LOAD_EXITING |
3133               CPU_BASED_CR8_STORE_EXITING |
3134 #endif
3135               CPU_BASED_CR3_LOAD_EXITING |
3136               CPU_BASED_CR3_STORE_EXITING |
3137               CPU_BASED_USE_IO_BITMAPS |
3138               CPU_BASED_MOV_DR_EXITING |
3139               CPU_BASED_USE_TSC_OFFSETING |
3140               CPU_BASED_MWAIT_EXITING |
3141               CPU_BASED_MONITOR_EXITING |
3142               CPU_BASED_INVLPG_EXITING |
3143               CPU_BASED_RDPMC_EXITING;
3144
3145         opt = CPU_BASED_TPR_SHADOW |
3146               CPU_BASED_USE_MSR_BITMAPS |
3147               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3148         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3149                                 &_cpu_based_exec_control) < 0)
3150                 return -EIO;
3151 #ifdef CONFIG_X86_64
3152         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3153                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3154                                            ~CPU_BASED_CR8_STORE_EXITING;
3155 #endif
3156         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3157                 min2 = 0;
3158                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3159                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3160                         SECONDARY_EXEC_WBINVD_EXITING |
3161                         SECONDARY_EXEC_ENABLE_VPID |
3162                         SECONDARY_EXEC_ENABLE_EPT |
3163                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3164                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3165                         SECONDARY_EXEC_RDTSCP |
3166                         SECONDARY_EXEC_ENABLE_INVPCID |
3167                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3168                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3169                         SECONDARY_EXEC_SHADOW_VMCS |
3170                         SECONDARY_EXEC_XSAVES |
3171                         SECONDARY_EXEC_ENABLE_PML |
3172                         SECONDARY_EXEC_PCOMMIT |
3173                         SECONDARY_EXEC_TSC_SCALING;
3174                 if (adjust_vmx_controls(min2, opt2,
3175                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3176                                         &_cpu_based_2nd_exec_control) < 0)
3177                         return -EIO;
3178         }
3179 #ifndef CONFIG_X86_64
3180         if (!(_cpu_based_2nd_exec_control &
3181                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3182                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3183 #endif
3184
3185         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3186                 _cpu_based_2nd_exec_control &= ~(
3187                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3188                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3189                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3190
3191         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3192                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3193                    enabled */
3194                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3195                                              CPU_BASED_CR3_STORE_EXITING |
3196                                              CPU_BASED_INVLPG_EXITING);
3197                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3198                       vmx_capability.ept, vmx_capability.vpid);
3199         }
3200
3201         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3202 #ifdef CONFIG_X86_64
3203         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3204 #endif
3205         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3206                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3207         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3208                                 &_vmexit_control) < 0)
3209                 return -EIO;
3210
3211         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3212         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3213         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3214                                 &_pin_based_exec_control) < 0)
3215                 return -EIO;
3216
3217         if (!(_cpu_based_2nd_exec_control &
3218                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3219                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3220                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3221
3222         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3223         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3224         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3225                                 &_vmentry_control) < 0)
3226                 return -EIO;
3227
3228         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3229
3230         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3231         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3232                 return -EIO;
3233
3234 #ifdef CONFIG_X86_64
3235         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3236         if (vmx_msr_high & (1u<<16))
3237                 return -EIO;
3238 #endif
3239
3240         /* Require Write-Back (WB) memory type for VMCS accesses. */
3241         if (((vmx_msr_high >> 18) & 15) != 6)
3242                 return -EIO;
3243
3244         vmcs_conf->size = vmx_msr_high & 0x1fff;
3245         vmcs_conf->order = get_order(vmcs_config.size);
3246         vmcs_conf->revision_id = vmx_msr_low;
3247
3248         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3249         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3250         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3251         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3252         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3253
3254         cpu_has_load_ia32_efer =
3255                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3256                                 VM_ENTRY_LOAD_IA32_EFER)
3257                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3258                                    VM_EXIT_LOAD_IA32_EFER);
3259
3260         cpu_has_load_perf_global_ctrl =
3261                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3262                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3263                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3264                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3265
3266         /*
3267          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3268          * but due to arrata below it can't be used. Workaround is to use
3269          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3270          *
3271          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3272          *
3273          * AAK155             (model 26)
3274          * AAP115             (model 30)
3275          * AAT100             (model 37)
3276          * BC86,AAY89,BD102   (model 44)
3277          * BA97               (model 46)
3278          *
3279          */
3280         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3281                 switch (boot_cpu_data.x86_model) {
3282                 case 26:
3283                 case 30:
3284                 case 37:
3285                 case 44:
3286                 case 46:
3287                         cpu_has_load_perf_global_ctrl = false;
3288                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3289                                         "does not work properly. Using workaround\n");
3290                         break;
3291                 default:
3292                         break;
3293                 }
3294         }
3295
3296         if (cpu_has_xsaves)
3297                 rdmsrl(MSR_IA32_XSS, host_xss);
3298
3299         return 0;
3300 }
3301
3302 static struct vmcs *alloc_vmcs_cpu(int cpu)
3303 {
3304         int node = cpu_to_node(cpu);
3305         struct page *pages;
3306         struct vmcs *vmcs;
3307
3308         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3309         if (!pages)
3310                 return NULL;
3311         vmcs = page_address(pages);
3312         memset(vmcs, 0, vmcs_config.size);
3313         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3314         return vmcs;
3315 }
3316
3317 static struct vmcs *alloc_vmcs(void)
3318 {
3319         return alloc_vmcs_cpu(raw_smp_processor_id());
3320 }
3321
3322 static void free_vmcs(struct vmcs *vmcs)
3323 {
3324         free_pages((unsigned long)vmcs, vmcs_config.order);
3325 }
3326
3327 /*
3328  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3329  */
3330 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3331 {
3332         if (!loaded_vmcs->vmcs)
3333                 return;
3334         loaded_vmcs_clear(loaded_vmcs);
3335         free_vmcs(loaded_vmcs->vmcs);
3336         loaded_vmcs->vmcs = NULL;
3337 }
3338
3339 static void free_kvm_area(void)
3340 {
3341         int cpu;
3342
3343         for_each_possible_cpu(cpu) {
3344                 free_vmcs(per_cpu(vmxarea, cpu));
3345                 per_cpu(vmxarea, cpu) = NULL;
3346         }
3347 }
3348
3349 static void init_vmcs_shadow_fields(void)
3350 {
3351         int i, j;
3352
3353         /* No checks for read only fields yet */
3354
3355         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3356                 switch (shadow_read_write_fields[i]) {
3357                 case GUEST_BNDCFGS:
3358                         if (!vmx_mpx_supported())
3359                                 continue;
3360                         break;
3361                 default:
3362                         break;
3363                 }
3364
3365                 if (j < i)
3366                         shadow_read_write_fields[j] =
3367                                 shadow_read_write_fields[i];
3368                 j++;
3369         }
3370         max_shadow_read_write_fields = j;
3371
3372         /* shadowed fields guest access without vmexit */
3373         for (i = 0; i < max_shadow_read_write_fields; i++) {
3374                 clear_bit(shadow_read_write_fields[i],
3375                           vmx_vmwrite_bitmap);
3376                 clear_bit(shadow_read_write_fields[i],
3377                           vmx_vmread_bitmap);
3378         }
3379         for (i = 0; i < max_shadow_read_only_fields; i++)
3380                 clear_bit(shadow_read_only_fields[i],
3381                           vmx_vmread_bitmap);
3382 }
3383
3384 static __init int alloc_kvm_area(void)
3385 {
3386         int cpu;
3387
3388         for_each_possible_cpu(cpu) {
3389                 struct vmcs *vmcs;
3390
3391                 vmcs = alloc_vmcs_cpu(cpu);
3392                 if (!vmcs) {
3393                         free_kvm_area();
3394                         return -ENOMEM;
3395                 }
3396
3397                 per_cpu(vmxarea, cpu) = vmcs;
3398         }
3399         return 0;
3400 }
3401
3402 static bool emulation_required(struct kvm_vcpu *vcpu)
3403 {
3404         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3405 }
3406
3407 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3408                 struct kvm_segment *save)
3409 {
3410         if (!emulate_invalid_guest_state) {
3411                 /*
3412                  * CS and SS RPL should be equal during guest entry according
3413                  * to VMX spec, but in reality it is not always so. Since vcpu
3414                  * is in the middle of the transition from real mode to
3415                  * protected mode it is safe to assume that RPL 0 is a good
3416                  * default value.
3417                  */
3418                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3419                         save->selector &= ~SEGMENT_RPL_MASK;
3420                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3421                 save->s = 1;
3422         }
3423         vmx_set_segment(vcpu, save, seg);
3424 }
3425
3426 static void enter_pmode(struct kvm_vcpu *vcpu)
3427 {
3428         unsigned long flags;
3429         struct vcpu_vmx *vmx = to_vmx(vcpu);
3430
3431         /*
3432          * Update real mode segment cache. It may be not up-to-date if sement
3433          * register was written while vcpu was in a guest mode.
3434          */
3435         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3436         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3437         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3438         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3439         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3440         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3441
3442         vmx->rmode.vm86_active = 0;
3443
3444         vmx_segment_cache_clear(vmx);
3445
3446         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3447
3448         flags = vmcs_readl(GUEST_RFLAGS);
3449         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3450         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3451         vmcs_writel(GUEST_RFLAGS, flags);
3452
3453         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3454                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3455
3456         update_exception_bitmap(vcpu);
3457
3458         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3459         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3460         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3461         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3462         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3463         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3464 }
3465
3466 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3467 {
3468         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3469         struct kvm_segment var = *save;
3470
3471         var.dpl = 0x3;
3472         if (seg == VCPU_SREG_CS)
3473                 var.type = 0x3;
3474
3475         if (!emulate_invalid_guest_state) {
3476                 var.selector = var.base >> 4;
3477                 var.base = var.base & 0xffff0;
3478                 var.limit = 0xffff;
3479                 var.g = 0;
3480                 var.db = 0;
3481                 var.present = 1;
3482                 var.s = 1;
3483                 var.l = 0;
3484                 var.unusable = 0;
3485                 var.type = 0x3;
3486                 var.avl = 0;
3487                 if (save->base & 0xf)
3488                         printk_once(KERN_WARNING "kvm: segment base is not "
3489                                         "paragraph aligned when entering "
3490                                         "protected mode (seg=%d)", seg);
3491         }
3492
3493         vmcs_write16(sf->selector, var.selector);
3494         vmcs_write32(sf->base, var.base);
3495         vmcs_write32(sf->limit, var.limit);
3496         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3497 }
3498
3499 static void enter_rmode(struct kvm_vcpu *vcpu)
3500 {
3501         unsigned long flags;
3502         struct vcpu_vmx *vmx = to_vmx(vcpu);
3503
3504         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3505         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3506         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3507         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3508         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3509         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3510         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3511
3512         vmx->rmode.vm86_active = 1;
3513
3514         /*
3515          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3516          * vcpu. Warn the user that an update is overdue.
3517          */
3518         if (!vcpu->kvm->arch.tss_addr)
3519                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3520                              "called before entering vcpu\n");
3521
3522         vmx_segment_cache_clear(vmx);
3523
3524         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3525         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3526         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3527
3528         flags = vmcs_readl(GUEST_RFLAGS);
3529         vmx->rmode.save_rflags = flags;
3530
3531         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3532
3533         vmcs_writel(GUEST_RFLAGS, flags);
3534         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3535         update_exception_bitmap(vcpu);
3536
3537         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3538         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3539         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3540         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3541         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3542         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3543
3544         kvm_mmu_reset_context(vcpu);
3545 }
3546
3547 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3548 {
3549         struct vcpu_vmx *vmx = to_vmx(vcpu);
3550         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3551
3552         if (!msr)
3553                 return;
3554
3555         /*
3556          * Force kernel_gs_base reloading before EFER changes, as control
3557          * of this msr depends on is_long_mode().
3558          */
3559         vmx_load_host_state(to_vmx(vcpu));
3560         vcpu->arch.efer = efer;
3561         if (efer & EFER_LMA) {
3562                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3563                 msr->data = efer;
3564         } else {
3565                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3566
3567                 msr->data = efer & ~EFER_LME;
3568         }
3569         setup_msrs(vmx);
3570 }
3571
3572 #ifdef CONFIG_X86_64
3573
3574 static void enter_lmode(struct kvm_vcpu *vcpu)
3575 {
3576         u32 guest_tr_ar;
3577
3578         vmx_segment_cache_clear(to_vmx(vcpu));
3579
3580         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3581         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3582                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3583                                      __func__);
3584                 vmcs_write32(GUEST_TR_AR_BYTES,
3585                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3586                              | VMX_AR_TYPE_BUSY_64_TSS);
3587         }
3588         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3589 }
3590
3591 static void exit_lmode(struct kvm_vcpu *vcpu)
3592 {
3593         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3594         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3595 }
3596
3597 #endif
3598
3599 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3600 {
3601         vpid_sync_context(vpid);
3602         if (enable_ept) {
3603                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3604                         return;
3605                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3606         }
3607 }
3608
3609 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3610 {
3611         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3612 }
3613
3614 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3615 {
3616         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3617
3618         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3619         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3620 }
3621
3622 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3623 {
3624         if (enable_ept && is_paging(vcpu))
3625                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3626         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3627 }
3628
3629 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3630 {
3631         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3632
3633         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3634         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3635 }
3636
3637 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3638 {
3639         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3640
3641         if (!test_bit(VCPU_EXREG_PDPTR,
3642                       (unsigned long *)&vcpu->arch.regs_dirty))
3643                 return;
3644
3645         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3646                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3647                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3648                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3649                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3650         }
3651 }
3652
3653 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3654 {
3655         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3656
3657         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3658                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3659                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3660                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3661                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3662         }
3663
3664         __set_bit(VCPU_EXREG_PDPTR,
3665                   (unsigned long *)&vcpu->arch.regs_avail);
3666         __set_bit(VCPU_EXREG_PDPTR,
3667                   (unsigned long *)&vcpu->arch.regs_dirty);
3668 }
3669
3670 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3671
3672 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3673                                         unsigned long cr0,
3674                                         struct kvm_vcpu *vcpu)
3675 {
3676         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3677                 vmx_decache_cr3(vcpu);
3678         if (!(cr0 & X86_CR0_PG)) {
3679                 /* From paging/starting to nonpaging */
3680                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3681                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3682                              (CPU_BASED_CR3_LOAD_EXITING |
3683                               CPU_BASED_CR3_STORE_EXITING));
3684                 vcpu->arch.cr0 = cr0;
3685                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3686         } else if (!is_paging(vcpu)) {
3687                 /* From nonpaging to paging */
3688                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3689                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3690                              ~(CPU_BASED_CR3_LOAD_EXITING |
3691                                CPU_BASED_CR3_STORE_EXITING));
3692                 vcpu->arch.cr0 = cr0;
3693                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3694         }
3695
3696         if (!(cr0 & X86_CR0_WP))
3697                 *hw_cr0 &= ~X86_CR0_WP;
3698 }
3699
3700 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3701 {
3702         struct vcpu_vmx *vmx = to_vmx(vcpu);
3703         unsigned long hw_cr0;
3704
3705         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3706         if (enable_unrestricted_guest)
3707                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3708         else {
3709                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3710
3711                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3712                         enter_pmode(vcpu);
3713
3714                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3715                         enter_rmode(vcpu);
3716         }
3717
3718 #ifdef CONFIG_X86_64
3719         if (vcpu->arch.efer & EFER_LME) {
3720                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3721                         enter_lmode(vcpu);
3722                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3723                         exit_lmode(vcpu);
3724         }
3725 #endif
3726
3727         if (enable_ept)
3728                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3729
3730         if (!vcpu->fpu_active)
3731                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3732
3733         vmcs_writel(CR0_READ_SHADOW, cr0);
3734         vmcs_writel(GUEST_CR0, hw_cr0);
3735         vcpu->arch.cr0 = cr0;
3736
3737         /* depends on vcpu->arch.cr0 to be set to a new value */
3738         vmx->emulation_required = emulation_required(vcpu);
3739 }
3740
3741 static u64 construct_eptp(unsigned long root_hpa)
3742 {
3743         u64 eptp;
3744
3745         /* TODO write the value reading from MSR */
3746         eptp = VMX_EPT_DEFAULT_MT |
3747                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3748         if (enable_ept_ad_bits)
3749                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3750         eptp |= (root_hpa & PAGE_MASK);
3751
3752         return eptp;
3753 }
3754
3755 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3756 {
3757         unsigned long guest_cr3;
3758         u64 eptp;
3759
3760         guest_cr3 = cr3;
3761         if (enable_ept) {
3762                 eptp = construct_eptp(cr3);
3763                 vmcs_write64(EPT_POINTER, eptp);
3764                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3765                         guest_cr3 = kvm_read_cr3(vcpu);
3766                 else
3767                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3768                 ept_load_pdptrs(vcpu);
3769         }
3770
3771         vmx_flush_tlb(vcpu);
3772         vmcs_writel(GUEST_CR3, guest_cr3);
3773 }
3774
3775 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3776 {
3777         /*
3778          * Pass through host's Machine Check Enable value to hw_cr4, which
3779          * is in force while we are in guest mode.  Do not let guests control
3780          * this bit, even if host CR4.MCE == 0.
3781          */
3782         unsigned long hw_cr4 =
3783                 (cr4_read_shadow() & X86_CR4_MCE) |
3784                 (cr4 & ~X86_CR4_MCE) |
3785                 (to_vmx(vcpu)->rmode.vm86_active ?
3786                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3787
3788         if (cr4 & X86_CR4_VMXE) {
3789                 /*
3790                  * To use VMXON (and later other VMX instructions), a guest
3791                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3792                  * So basically the check on whether to allow nested VMX
3793                  * is here.
3794                  */
3795                 if (!nested_vmx_allowed(vcpu))
3796                         return 1;
3797         }
3798         if (to_vmx(vcpu)->nested.vmxon &&
3799             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3800                 return 1;
3801
3802         vcpu->arch.cr4 = cr4;
3803         if (enable_ept) {
3804                 if (!is_paging(vcpu)) {
3805                         hw_cr4 &= ~X86_CR4_PAE;
3806                         hw_cr4 |= X86_CR4_PSE;
3807                 } else if (!(cr4 & X86_CR4_PAE)) {
3808                         hw_cr4 &= ~X86_CR4_PAE;
3809                 }
3810         }
3811
3812         if (!enable_unrestricted_guest && !is_paging(vcpu))
3813                 /*
3814                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3815                  * hardware.  However KVM always uses paging mode without
3816                  * unrestricted guest.
3817                  * To emulate this behavior, SMEP/SMAP needs to be manually
3818                  * disabled when guest switches to non-paging mode.
3819                  */
3820                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3821
3822         vmcs_writel(CR4_READ_SHADOW, cr4);
3823         vmcs_writel(GUEST_CR4, hw_cr4);
3824         return 0;
3825 }
3826
3827 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3828                             struct kvm_segment *var, int seg)
3829 {
3830         struct vcpu_vmx *vmx = to_vmx(vcpu);
3831         u32 ar;
3832
3833         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3834                 *var = vmx->rmode.segs[seg];
3835                 if (seg == VCPU_SREG_TR
3836                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3837                         return;
3838                 var->base = vmx_read_guest_seg_base(vmx, seg);
3839                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3840                 return;
3841         }
3842         var->base = vmx_read_guest_seg_base(vmx, seg);
3843         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3844         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3845         ar = vmx_read_guest_seg_ar(vmx, seg);
3846         var->unusable = (ar >> 16) & 1;
3847         var->type = ar & 15;
3848         var->s = (ar >> 4) & 1;
3849         var->dpl = (ar >> 5) & 3;
3850         /*
3851          * Some userspaces do not preserve unusable property. Since usable
3852          * segment has to be present according to VMX spec we can use present
3853          * property to amend userspace bug by making unusable segment always
3854          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3855          * segment as unusable.
3856          */
3857         var->present = !var->unusable;
3858         var->avl = (ar >> 12) & 1;
3859         var->l = (ar >> 13) & 1;
3860         var->db = (ar >> 14) & 1;
3861         var->g = (ar >> 15) & 1;
3862 }
3863
3864 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3865 {
3866         struct kvm_segment s;
3867
3868         if (to_vmx(vcpu)->rmode.vm86_active) {
3869                 vmx_get_segment(vcpu, &s, seg);
3870                 return s.base;
3871         }
3872         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3873 }
3874
3875 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3876 {
3877         struct vcpu_vmx *vmx = to_vmx(vcpu);
3878
3879         if (unlikely(vmx->rmode.vm86_active))
3880                 return 0;
3881         else {
3882                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3883                 return VMX_AR_DPL(ar);
3884         }
3885 }
3886
3887 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3888 {
3889         u32 ar;
3890
3891         if (var->unusable || !var->present)
3892                 ar = 1 << 16;
3893         else {
3894                 ar = var->type & 15;
3895                 ar |= (var->s & 1) << 4;
3896                 ar |= (var->dpl & 3) << 5;
3897                 ar |= (var->present & 1) << 7;
3898                 ar |= (var->avl & 1) << 12;
3899                 ar |= (var->l & 1) << 13;
3900                 ar |= (var->db & 1) << 14;
3901                 ar |= (var->g & 1) << 15;
3902         }
3903
3904         return ar;
3905 }
3906
3907 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3908                             struct kvm_segment *var, int seg)
3909 {
3910         struct vcpu_vmx *vmx = to_vmx(vcpu);
3911         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3912
3913         vmx_segment_cache_clear(vmx);
3914
3915         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3916                 vmx->rmode.segs[seg] = *var;
3917                 if (seg == VCPU_SREG_TR)
3918                         vmcs_write16(sf->selector, var->selector);
3919                 else if (var->s)
3920                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3921                 goto out;
3922         }
3923
3924         vmcs_writel(sf->base, var->base);
3925         vmcs_write32(sf->limit, var->limit);
3926         vmcs_write16(sf->selector, var->selector);
3927
3928         /*
3929          *   Fix the "Accessed" bit in AR field of segment registers for older
3930          * qemu binaries.
3931          *   IA32 arch specifies that at the time of processor reset the
3932          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3933          * is setting it to 0 in the userland code. This causes invalid guest
3934          * state vmexit when "unrestricted guest" mode is turned on.
3935          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3936          * tree. Newer qemu binaries with that qemu fix would not need this
3937          * kvm hack.
3938          */
3939         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3940                 var->type |= 0x1; /* Accessed */
3941
3942         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3943
3944 out:
3945         vmx->emulation_required = emulation_required(vcpu);
3946 }
3947
3948 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3949 {
3950         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3951
3952         *db = (ar >> 14) & 1;
3953         *l = (ar >> 13) & 1;
3954 }
3955
3956 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3957 {
3958         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3959         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3960 }
3961
3962 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3963 {
3964         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3965         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3966 }
3967
3968 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3969 {
3970         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3971         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3972 }
3973
3974 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3975 {
3976         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3977         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3978 }
3979
3980 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3981 {
3982         struct kvm_segment var;
3983         u32 ar;
3984
3985         vmx_get_segment(vcpu, &var, seg);
3986         var.dpl = 0x3;
3987         if (seg == VCPU_SREG_CS)
3988                 var.type = 0x3;
3989         ar = vmx_segment_access_rights(&var);
3990
3991         if (var.base != (var.selector << 4))
3992                 return false;
3993         if (var.limit != 0xffff)
3994                 return false;
3995         if (ar != 0xf3)
3996                 return false;
3997
3998         return true;
3999 }
4000
4001 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4002 {
4003         struct kvm_segment cs;
4004         unsigned int cs_rpl;
4005
4006         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4007         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4008
4009         if (cs.unusable)
4010                 return false;
4011         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4012                 return false;
4013         if (!cs.s)
4014                 return false;
4015         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4016                 if (cs.dpl > cs_rpl)
4017                         return false;
4018         } else {
4019                 if (cs.dpl != cs_rpl)
4020                         return false;
4021         }
4022         if (!cs.present)
4023                 return false;
4024
4025         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4026         return true;
4027 }
4028
4029 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4030 {
4031         struct kvm_segment ss;
4032         unsigned int ss_rpl;
4033
4034         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4035         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4036
4037         if (ss.unusable)
4038                 return true;
4039         if (ss.type != 3 && ss.type != 7)
4040                 return false;
4041         if (!ss.s)
4042                 return false;
4043         if (ss.dpl != ss_rpl) /* DPL != RPL */
4044                 return false;
4045         if (!ss.present)
4046                 return false;
4047
4048         return true;
4049 }
4050
4051 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4052 {
4053         struct kvm_segment var;
4054         unsigned int rpl;
4055
4056         vmx_get_segment(vcpu, &var, seg);
4057         rpl = var.selector & SEGMENT_RPL_MASK;
4058
4059         if (var.unusable)
4060                 return true;
4061         if (!var.s)
4062                 return false;
4063         if (!var.present)
4064                 return false;
4065         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4066                 if (var.dpl < rpl) /* DPL < RPL */
4067                         return false;
4068         }
4069
4070         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4071          * rights flags
4072          */
4073         return true;
4074 }
4075
4076 static bool tr_valid(struct kvm_vcpu *vcpu)
4077 {
4078         struct kvm_segment tr;
4079
4080         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4081
4082         if (tr.unusable)
4083                 return false;
4084         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4085                 return false;
4086         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4087                 return false;
4088         if (!tr.present)
4089                 return false;
4090
4091         return true;
4092 }
4093
4094 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4095 {
4096         struct kvm_segment ldtr;
4097
4098         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4099
4100         if (ldtr.unusable)
4101                 return true;
4102         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4103                 return false;
4104         if (ldtr.type != 2)
4105                 return false;
4106         if (!ldtr.present)
4107                 return false;
4108
4109         return true;
4110 }
4111
4112 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4113 {
4114         struct kvm_segment cs, ss;
4115
4116         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4117         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4118
4119         return ((cs.selector & SEGMENT_RPL_MASK) ==
4120                  (ss.selector & SEGMENT_RPL_MASK));
4121 }
4122
4123 /*
4124  * Check if guest state is valid. Returns true if valid, false if
4125  * not.
4126  * We assume that registers are always usable
4127  */
4128 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4129 {
4130         if (enable_unrestricted_guest)
4131                 return true;
4132
4133         /* real mode guest state checks */
4134         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4135                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4136                         return false;
4137                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4138                         return false;
4139                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4140                         return false;
4141                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4142                         return false;
4143                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4144                         return false;
4145                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4146                         return false;
4147         } else {
4148         /* protected mode guest state checks */
4149                 if (!cs_ss_rpl_check(vcpu))
4150                         return false;
4151                 if (!code_segment_valid(vcpu))
4152                         return false;
4153                 if (!stack_segment_valid(vcpu))
4154                         return false;
4155                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4156                         return false;
4157                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4158                         return false;
4159                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4160                         return false;
4161                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4162                         return false;
4163                 if (!tr_valid(vcpu))
4164                         return false;
4165                 if (!ldtr_valid(vcpu))
4166                         return false;
4167         }
4168         /* TODO:
4169          * - Add checks on RIP
4170          * - Add checks on RFLAGS
4171          */
4172
4173         return true;
4174 }
4175
4176 static int init_rmode_tss(struct kvm *kvm)
4177 {
4178         gfn_t fn;
4179         u16 data = 0;
4180         int idx, r;
4181
4182         idx = srcu_read_lock(&kvm->srcu);
4183         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4184         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4185         if (r < 0)
4186                 goto out;
4187         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4188         r = kvm_write_guest_page(kvm, fn++, &data,
4189                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4190         if (r < 0)
4191                 goto out;
4192         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4193         if (r < 0)
4194                 goto out;
4195         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4196         if (r < 0)
4197                 goto out;
4198         data = ~0;
4199         r = kvm_write_guest_page(kvm, fn, &data,
4200                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4201                                  sizeof(u8));
4202 out:
4203         srcu_read_unlock(&kvm->srcu, idx);
4204         return r;
4205 }
4206
4207 static int init_rmode_identity_map(struct kvm *kvm)
4208 {
4209         int i, idx, r = 0;
4210         pfn_t identity_map_pfn;
4211         u32 tmp;
4212
4213         if (!enable_ept)
4214                 return 0;
4215
4216         /* Protect kvm->arch.ept_identity_pagetable_done. */
4217         mutex_lock(&kvm->slots_lock);
4218
4219         if (likely(kvm->arch.ept_identity_pagetable_done))
4220                 goto out2;
4221
4222         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4223
4224         r = alloc_identity_pagetable(kvm);
4225         if (r < 0)
4226                 goto out2;
4227
4228         idx = srcu_read_lock(&kvm->srcu);
4229         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4230         if (r < 0)
4231                 goto out;
4232         /* Set up identity-mapping pagetable for EPT in real mode */
4233         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4234                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4235                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4236                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4237                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4238                 if (r < 0)
4239                         goto out;
4240         }
4241         kvm->arch.ept_identity_pagetable_done = true;
4242
4243 out:
4244         srcu_read_unlock(&kvm->srcu, idx);
4245
4246 out2:
4247         mutex_unlock(&kvm->slots_lock);
4248         return r;
4249 }
4250
4251 static void seg_setup(int seg)
4252 {
4253         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4254         unsigned int ar;
4255
4256         vmcs_write16(sf->selector, 0);
4257         vmcs_writel(sf->base, 0);
4258         vmcs_write32(sf->limit, 0xffff);
4259         ar = 0x93;
4260         if (seg == VCPU_SREG_CS)
4261                 ar |= 0x08; /* code segment */
4262
4263         vmcs_write32(sf->ar_bytes, ar);
4264 }
4265
4266 static int alloc_apic_access_page(struct kvm *kvm)
4267 {
4268         struct page *page;
4269         int r = 0;
4270
4271         mutex_lock(&kvm->slots_lock);
4272         if (kvm->arch.apic_access_page_done)
4273                 goto out;
4274         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4275                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4276         if (r)
4277                 goto out;
4278
4279         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4280         if (is_error_page(page)) {
4281                 r = -EFAULT;
4282                 goto out;
4283         }
4284
4285         /*
4286          * Do not pin the page in memory, so that memory hot-unplug
4287          * is able to migrate it.
4288          */
4289         put_page(page);
4290         kvm->arch.apic_access_page_done = true;
4291 out:
4292         mutex_unlock(&kvm->slots_lock);
4293         return r;
4294 }
4295
4296 static int alloc_identity_pagetable(struct kvm *kvm)
4297 {
4298         /* Called with kvm->slots_lock held. */
4299
4300         int r = 0;
4301
4302         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4303
4304         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4305                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4306
4307         return r;
4308 }
4309
4310 static int allocate_vpid(void)
4311 {
4312         int vpid;
4313
4314         if (!enable_vpid)
4315                 return 0;
4316         spin_lock(&vmx_vpid_lock);
4317         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4318         if (vpid < VMX_NR_VPIDS)
4319                 __set_bit(vpid, vmx_vpid_bitmap);
4320         else
4321                 vpid = 0;
4322         spin_unlock(&vmx_vpid_lock);
4323         return vpid;
4324 }
4325
4326 static void free_vpid(int vpid)
4327 {
4328         if (!enable_vpid || vpid == 0)
4329                 return;
4330         spin_lock(&vmx_vpid_lock);
4331         __clear_bit(vpid, vmx_vpid_bitmap);
4332         spin_unlock(&vmx_vpid_lock);
4333 }
4334
4335 #define MSR_TYPE_R      1
4336 #define MSR_TYPE_W      2
4337 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4338                                                 u32 msr, int type)
4339 {
4340         int f = sizeof(unsigned long);
4341
4342         if (!cpu_has_vmx_msr_bitmap())
4343                 return;
4344
4345         /*
4346          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4347          * have the write-low and read-high bitmap offsets the wrong way round.
4348          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4349          */
4350         if (msr <= 0x1fff) {
4351                 if (type & MSR_TYPE_R)
4352                         /* read-low */
4353                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4354
4355                 if (type & MSR_TYPE_W)
4356                         /* write-low */
4357                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4358
4359         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4360                 msr &= 0x1fff;
4361                 if (type & MSR_TYPE_R)
4362                         /* read-high */
4363                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4364
4365                 if (type & MSR_TYPE_W)
4366                         /* write-high */
4367                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4368
4369         }
4370 }
4371
4372 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4373                                                 u32 msr, int type)
4374 {
4375         int f = sizeof(unsigned long);
4376
4377         if (!cpu_has_vmx_msr_bitmap())
4378                 return;
4379
4380         /*
4381          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4382          * have the write-low and read-high bitmap offsets the wrong way round.
4383          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4384          */
4385         if (msr <= 0x1fff) {
4386                 if (type & MSR_TYPE_R)
4387                         /* read-low */
4388                         __set_bit(msr, msr_bitmap + 0x000 / f);
4389
4390                 if (type & MSR_TYPE_W)
4391                         /* write-low */
4392                         __set_bit(msr, msr_bitmap + 0x800 / f);
4393
4394         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4395                 msr &= 0x1fff;
4396                 if (type & MSR_TYPE_R)
4397                         /* read-high */
4398                         __set_bit(msr, msr_bitmap + 0x400 / f);
4399
4400                 if (type & MSR_TYPE_W)
4401                         /* write-high */
4402                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4403
4404         }
4405 }
4406
4407 /*
4408  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4409  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4410  */
4411 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4412                                                unsigned long *msr_bitmap_nested,
4413                                                u32 msr, int type)
4414 {
4415         int f = sizeof(unsigned long);
4416
4417         if (!cpu_has_vmx_msr_bitmap()) {
4418                 WARN_ON(1);
4419                 return;
4420         }
4421
4422         /*
4423          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4424          * have the write-low and read-high bitmap offsets the wrong way round.
4425          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4426          */
4427         if (msr <= 0x1fff) {
4428                 if (type & MSR_TYPE_R &&
4429                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4430                         /* read-low */
4431                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4432
4433                 if (type & MSR_TYPE_W &&
4434                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4435                         /* write-low */
4436                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4437
4438         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4439                 msr &= 0x1fff;
4440                 if (type & MSR_TYPE_R &&
4441                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4442                         /* read-high */
4443                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4444
4445                 if (type & MSR_TYPE_W &&
4446                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4447                         /* write-high */
4448                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4449
4450         }
4451 }
4452
4453 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4454 {
4455         if (!longmode_only)
4456                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4457                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4458         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4459                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4460 }
4461
4462 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4463 {
4464         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4465                         msr, MSR_TYPE_R);
4466         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4467                         msr, MSR_TYPE_R);
4468 }
4469
4470 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4471 {
4472         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4473                         msr, MSR_TYPE_R);
4474         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4475                         msr, MSR_TYPE_R);
4476 }
4477
4478 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4479 {
4480         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4481                         msr, MSR_TYPE_W);
4482         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4483                         msr, MSR_TYPE_W);
4484 }
4485
4486 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4487 {
4488         return enable_apicv && lapic_in_kernel(vcpu);
4489 }
4490
4491 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4492 {
4493         struct vcpu_vmx *vmx = to_vmx(vcpu);
4494         int max_irr;
4495         void *vapic_page;
4496         u16 status;
4497
4498         if (vmx->nested.pi_desc &&
4499             vmx->nested.pi_pending) {
4500                 vmx->nested.pi_pending = false;
4501                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4502                         return 0;
4503
4504                 max_irr = find_last_bit(
4505                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4506
4507                 if (max_irr == 256)
4508                         return 0;
4509
4510                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4511                 if (!vapic_page) {
4512                         WARN_ON(1);
4513                         return -ENOMEM;
4514                 }
4515                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4516                 kunmap(vmx->nested.virtual_apic_page);
4517
4518                 status = vmcs_read16(GUEST_INTR_STATUS);
4519                 if ((u8)max_irr > ((u8)status & 0xff)) {
4520                         status &= ~0xff;
4521                         status |= (u8)max_irr;
4522                         vmcs_write16(GUEST_INTR_STATUS, status);
4523                 }
4524         }
4525         return 0;
4526 }
4527
4528 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4529 {
4530 #ifdef CONFIG_SMP
4531         if (vcpu->mode == IN_GUEST_MODE) {
4532                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4533
4534                 /*
4535                  * Currently, we don't support urgent interrupt,
4536                  * all interrupts are recognized as non-urgent
4537                  * interrupt, so we cannot post interrupts when
4538                  * 'SN' is set.
4539                  *
4540                  * If the vcpu is in guest mode, it means it is
4541                  * running instead of being scheduled out and
4542                  * waiting in the run queue, and that's the only
4543                  * case when 'SN' is set currently, warning if
4544                  * 'SN' is set.
4545                  */
4546                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4547
4548                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4549                                 POSTED_INTR_VECTOR);
4550                 return true;
4551         }
4552 #endif
4553         return false;
4554 }
4555
4556 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4557                                                 int vector)
4558 {
4559         struct vcpu_vmx *vmx = to_vmx(vcpu);
4560
4561         if (is_guest_mode(vcpu) &&
4562             vector == vmx->nested.posted_intr_nv) {
4563                 /* the PIR and ON have been set by L1. */
4564                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4565                 /*
4566                  * If a posted intr is not recognized by hardware,
4567                  * we will accomplish it in the next vmentry.
4568                  */
4569                 vmx->nested.pi_pending = true;
4570                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4571                 return 0;
4572         }
4573         return -1;
4574 }
4575 /*
4576  * Send interrupt to vcpu via posted interrupt way.
4577  * 1. If target vcpu is running(non-root mode), send posted interrupt
4578  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4579  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4580  * interrupt from PIR in next vmentry.
4581  */
4582 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4583 {
4584         struct vcpu_vmx *vmx = to_vmx(vcpu);
4585         int r;
4586
4587         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4588         if (!r)
4589                 return;
4590
4591         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4592                 return;
4593
4594         r = pi_test_and_set_on(&vmx->pi_desc);
4595         kvm_make_request(KVM_REQ_EVENT, vcpu);
4596         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4597                 kvm_vcpu_kick(vcpu);
4598 }
4599
4600 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4601 {
4602         struct vcpu_vmx *vmx = to_vmx(vcpu);
4603
4604         if (!pi_test_and_clear_on(&vmx->pi_desc))
4605                 return;
4606
4607         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4608 }
4609
4610 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4611 {
4612         return;
4613 }
4614
4615 /*
4616  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4617  * will not change in the lifetime of the guest.
4618  * Note that host-state that does change is set elsewhere. E.g., host-state
4619  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4620  */
4621 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4622 {
4623         u32 low32, high32;
4624         unsigned long tmpl;
4625         struct desc_ptr dt;
4626         unsigned long cr4;
4627
4628         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4629         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4630
4631         /* Save the most likely value for this task's CR4 in the VMCS. */
4632         cr4 = cr4_read_shadow();
4633         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4634         vmx->host_state.vmcs_host_cr4 = cr4;
4635
4636         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4637 #ifdef CONFIG_X86_64
4638         /*
4639          * Load null selectors, so we can avoid reloading them in
4640          * __vmx_load_host_state(), in case userspace uses the null selectors
4641          * too (the expected case).
4642          */
4643         vmcs_write16(HOST_DS_SELECTOR, 0);
4644         vmcs_write16(HOST_ES_SELECTOR, 0);
4645 #else
4646         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4647         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4648 #endif
4649         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4650         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4651
4652         native_store_idt(&dt);
4653         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4654         vmx->host_idt_base = dt.address;
4655
4656         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4657
4658         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4659         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4660         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4661         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4662
4663         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4664                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4665                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4666         }
4667 }
4668
4669 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4670 {
4671         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4672         if (enable_ept)
4673                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4674         if (is_guest_mode(&vmx->vcpu))
4675                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4676                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4677         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4678 }
4679
4680 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4681 {
4682         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4683
4684         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4685                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4686         return pin_based_exec_ctrl;
4687 }
4688
4689 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4690 {
4691         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4692
4693         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4694                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4695
4696         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4697                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4698 #ifdef CONFIG_X86_64
4699                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4700                                 CPU_BASED_CR8_LOAD_EXITING;
4701 #endif
4702         }
4703         if (!enable_ept)
4704                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4705                                 CPU_BASED_CR3_LOAD_EXITING  |
4706                                 CPU_BASED_INVLPG_EXITING;
4707         return exec_control;
4708 }
4709
4710 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4711 {
4712         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4713         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4714                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4715         if (vmx->vpid == 0)
4716                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4717         if (!enable_ept) {
4718                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4719                 enable_unrestricted_guest = 0;
4720                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4721                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4722         }
4723         if (!enable_unrestricted_guest)
4724                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4725         if (!ple_gap)
4726                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4727         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4728                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4729                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4730         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4731         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4732            (handle_vmptrld).
4733            We can NOT enable shadow_vmcs here because we don't have yet
4734            a current VMCS12
4735         */
4736         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4737
4738         if (!enable_pml)
4739                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4740
4741         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4742         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4743
4744         return exec_control;
4745 }
4746
4747 static void ept_set_mmio_spte_mask(void)
4748 {
4749         /*
4750          * EPT Misconfigurations can be generated if the value of bits 2:0
4751          * of an EPT paging-structure entry is 110b (write/execute).
4752          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4753          * spte.
4754          */
4755         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4756 }
4757
4758 #define VMX_XSS_EXIT_BITMAP 0
4759 /*
4760  * Sets up the vmcs for emulated real mode.
4761  */
4762 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4763 {
4764 #ifdef CONFIG_X86_64
4765         unsigned long a;
4766 #endif
4767         int i;
4768
4769         /* I/O */
4770         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4771         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4772
4773         if (enable_shadow_vmcs) {
4774                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4775                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4776         }
4777         if (cpu_has_vmx_msr_bitmap())
4778                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4779
4780         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4781
4782         /* Control */
4783         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4784
4785         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4786
4787         if (cpu_has_secondary_exec_ctrls())
4788                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4789                                 vmx_secondary_exec_control(vmx));
4790
4791         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4792                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4793                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4794                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4795                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4796
4797                 vmcs_write16(GUEST_INTR_STATUS, 0);
4798
4799                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4800                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4801         }
4802
4803         if (ple_gap) {
4804                 vmcs_write32(PLE_GAP, ple_gap);
4805                 vmx->ple_window = ple_window;
4806                 vmx->ple_window_dirty = true;
4807         }
4808
4809         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4810         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4811         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4812
4813         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4814         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4815         vmx_set_constant_host_state(vmx);
4816 #ifdef CONFIG_X86_64
4817         rdmsrl(MSR_FS_BASE, a);
4818         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4819         rdmsrl(MSR_GS_BASE, a);
4820         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4821 #else
4822         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4823         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4824 #endif
4825
4826         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4827         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4828         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4829         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4830         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4831
4832         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4833                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4834
4835         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4836                 u32 index = vmx_msr_index[i];
4837                 u32 data_low, data_high;
4838                 int j = vmx->nmsrs;
4839
4840                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4841                         continue;
4842                 if (wrmsr_safe(index, data_low, data_high) < 0)
4843                         continue;
4844                 vmx->guest_msrs[j].index = i;
4845                 vmx->guest_msrs[j].data = 0;
4846                 vmx->guest_msrs[j].mask = -1ull;
4847                 ++vmx->nmsrs;
4848         }
4849
4850
4851         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4852
4853         /* 22.2.1, 20.8.1 */
4854         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4855
4856         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4857         set_cr4_guest_host_mask(vmx);
4858
4859         if (vmx_xsaves_supported())
4860                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4861
4862         return 0;
4863 }
4864
4865 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4866 {
4867         struct vcpu_vmx *vmx = to_vmx(vcpu);
4868         struct msr_data apic_base_msr;
4869         u64 cr0;
4870
4871         vmx->rmode.vm86_active = 0;
4872
4873         vmx->soft_vnmi_blocked = 0;
4874
4875         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4876         kvm_set_cr8(vcpu, 0);
4877
4878         if (!init_event) {
4879                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4880                                      MSR_IA32_APICBASE_ENABLE;
4881                 if (kvm_vcpu_is_reset_bsp(vcpu))
4882                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4883                 apic_base_msr.host_initiated = true;
4884                 kvm_set_apic_base(vcpu, &apic_base_msr);
4885         }
4886
4887         vmx_segment_cache_clear(vmx);
4888
4889         seg_setup(VCPU_SREG_CS);
4890         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4891         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4892
4893         seg_setup(VCPU_SREG_DS);
4894         seg_setup(VCPU_SREG_ES);
4895         seg_setup(VCPU_SREG_FS);
4896         seg_setup(VCPU_SREG_GS);
4897         seg_setup(VCPU_SREG_SS);
4898
4899         vmcs_write16(GUEST_TR_SELECTOR, 0);
4900         vmcs_writel(GUEST_TR_BASE, 0);
4901         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4902         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4903
4904         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4905         vmcs_writel(GUEST_LDTR_BASE, 0);
4906         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4907         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4908
4909         if (!init_event) {
4910                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4911                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4912                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4913                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4914         }
4915
4916         vmcs_writel(GUEST_RFLAGS, 0x02);
4917         kvm_rip_write(vcpu, 0xfff0);
4918
4919         vmcs_writel(GUEST_GDTR_BASE, 0);
4920         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4921
4922         vmcs_writel(GUEST_IDTR_BASE, 0);
4923         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4924
4925         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4926         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4927         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4928
4929         setup_msrs(vmx);
4930
4931         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4932
4933         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4934                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4935                 if (cpu_need_tpr_shadow(vcpu))
4936                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4937                                      __pa(vcpu->arch.apic->regs));
4938                 vmcs_write32(TPR_THRESHOLD, 0);
4939         }
4940
4941         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4942
4943         if (vmx_cpu_uses_apicv(vcpu))
4944                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4945
4946         if (vmx->vpid != 0)
4947                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4948
4949         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4950         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4951         vmx->vcpu.arch.cr0 = cr0;
4952         vmx_set_cr4(vcpu, 0);
4953         vmx_set_efer(vcpu, 0);
4954         vmx_fpu_activate(vcpu);
4955         update_exception_bitmap(vcpu);
4956
4957         vpid_sync_context(vmx->vpid);
4958 }
4959
4960 /*
4961  * In nested virtualization, check if L1 asked to exit on external interrupts.
4962  * For most existing hypervisors, this will always return true.
4963  */
4964 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4965 {
4966         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4967                 PIN_BASED_EXT_INTR_MASK;
4968 }
4969
4970 /*
4971  * In nested virtualization, check if L1 has set
4972  * VM_EXIT_ACK_INTR_ON_EXIT
4973  */
4974 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4975 {
4976         return get_vmcs12(vcpu)->vm_exit_controls &
4977                 VM_EXIT_ACK_INTR_ON_EXIT;
4978 }
4979
4980 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4981 {
4982         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4983                 PIN_BASED_NMI_EXITING;
4984 }
4985
4986 static void enable_irq_window(struct kvm_vcpu *vcpu)
4987 {
4988         u32 cpu_based_vm_exec_control;
4989
4990         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4991         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4992         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4993 }
4994
4995 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4996 {
4997         u32 cpu_based_vm_exec_control;
4998
4999         if (!cpu_has_virtual_nmis() ||
5000             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5001                 enable_irq_window(vcpu);
5002                 return;
5003         }
5004
5005         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5006         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5007         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5008 }
5009
5010 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5011 {
5012         struct vcpu_vmx *vmx = to_vmx(vcpu);
5013         uint32_t intr;
5014         int irq = vcpu->arch.interrupt.nr;
5015
5016         trace_kvm_inj_virq(irq);
5017
5018         ++vcpu->stat.irq_injections;
5019         if (vmx->rmode.vm86_active) {
5020                 int inc_eip = 0;
5021                 if (vcpu->arch.interrupt.soft)
5022                         inc_eip = vcpu->arch.event_exit_inst_len;
5023                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5024                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5025                 return;
5026         }
5027         intr = irq | INTR_INFO_VALID_MASK;
5028         if (vcpu->arch.interrupt.soft) {
5029                 intr |= INTR_TYPE_SOFT_INTR;
5030                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5031                              vmx->vcpu.arch.event_exit_inst_len);
5032         } else
5033                 intr |= INTR_TYPE_EXT_INTR;
5034         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5035 }
5036
5037 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5038 {
5039         struct vcpu_vmx *vmx = to_vmx(vcpu);
5040
5041         if (is_guest_mode(vcpu))
5042                 return;
5043
5044         if (!cpu_has_virtual_nmis()) {
5045                 /*
5046                  * Tracking the NMI-blocked state in software is built upon
5047                  * finding the next open IRQ window. This, in turn, depends on
5048                  * well-behaving guests: They have to keep IRQs disabled at
5049                  * least as long as the NMI handler runs. Otherwise we may
5050                  * cause NMI nesting, maybe breaking the guest. But as this is
5051                  * highly unlikely, we can live with the residual risk.
5052                  */
5053                 vmx->soft_vnmi_blocked = 1;
5054                 vmx->vnmi_blocked_time = 0;
5055         }
5056
5057         ++vcpu->stat.nmi_injections;
5058         vmx->nmi_known_unmasked = false;
5059         if (vmx->rmode.vm86_active) {
5060                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5061                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5062                 return;
5063         }
5064         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5065                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5066 }
5067
5068 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5069 {
5070         if (!cpu_has_virtual_nmis())
5071                 return to_vmx(vcpu)->soft_vnmi_blocked;
5072         if (to_vmx(vcpu)->nmi_known_unmasked)
5073                 return false;
5074         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5075 }
5076
5077 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5078 {
5079         struct vcpu_vmx *vmx = to_vmx(vcpu);
5080
5081         if (!cpu_has_virtual_nmis()) {
5082                 if (vmx->soft_vnmi_blocked != masked) {
5083                         vmx->soft_vnmi_blocked = masked;
5084                         vmx->vnmi_blocked_time = 0;
5085                 }
5086         } else {
5087                 vmx->nmi_known_unmasked = !masked;
5088                 if (masked)
5089                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5090                                       GUEST_INTR_STATE_NMI);
5091                 else
5092                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5093                                         GUEST_INTR_STATE_NMI);
5094         }
5095 }
5096
5097 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5098 {
5099         if (to_vmx(vcpu)->nested.nested_run_pending)
5100                 return 0;
5101
5102         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5103                 return 0;
5104
5105         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5106                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5107                    | GUEST_INTR_STATE_NMI));
5108 }
5109
5110 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5111 {
5112         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5113                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5114                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5115                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5116 }
5117
5118 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5119 {
5120         int ret;
5121
5122         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5123                                     PAGE_SIZE * 3);
5124         if (ret)
5125                 return ret;
5126         kvm->arch.tss_addr = addr;
5127         return init_rmode_tss(kvm);
5128 }
5129
5130 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5131 {
5132         switch (vec) {
5133         case BP_VECTOR:
5134                 /*
5135                  * Update instruction length as we may reinject the exception
5136                  * from user space while in guest debugging mode.
5137                  */
5138                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5139                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5140                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5141                         return false;
5142                 /* fall through */
5143         case DB_VECTOR:
5144                 if (vcpu->guest_debug &
5145                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5146                         return false;
5147                 /* fall through */
5148         case DE_VECTOR:
5149         case OF_VECTOR:
5150         case BR_VECTOR:
5151         case UD_VECTOR:
5152         case DF_VECTOR:
5153         case SS_VECTOR:
5154         case GP_VECTOR:
5155         case MF_VECTOR:
5156                 return true;
5157         break;
5158         }
5159         return false;
5160 }
5161
5162 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5163                                   int vec, u32 err_code)
5164 {
5165         /*
5166          * Instruction with address size override prefix opcode 0x67
5167          * Cause the #SS fault with 0 error code in VM86 mode.
5168          */
5169         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5170                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5171                         if (vcpu->arch.halt_request) {
5172                                 vcpu->arch.halt_request = 0;
5173                                 return kvm_vcpu_halt(vcpu);
5174                         }
5175                         return 1;
5176                 }
5177                 return 0;
5178         }
5179
5180         /*
5181          * Forward all other exceptions that are valid in real mode.
5182          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5183          *        the required debugging infrastructure rework.
5184          */
5185         kvm_queue_exception(vcpu, vec);
5186         return 1;
5187 }
5188
5189 /*
5190  * Trigger machine check on the host. We assume all the MSRs are already set up
5191  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5192  * We pass a fake environment to the machine check handler because we want
5193  * the guest to be always treated like user space, no matter what context
5194  * it used internally.
5195  */
5196 static void kvm_machine_check(void)
5197 {
5198 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5199         struct pt_regs regs = {
5200                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5201                 .flags = X86_EFLAGS_IF,
5202         };
5203
5204         do_machine_check(&regs, 0);
5205 #endif
5206 }
5207
5208 static int handle_machine_check(struct kvm_vcpu *vcpu)
5209 {
5210         /* already handled by vcpu_run */
5211         return 1;
5212 }
5213
5214 static int handle_exception(struct kvm_vcpu *vcpu)
5215 {
5216         struct vcpu_vmx *vmx = to_vmx(vcpu);
5217         struct kvm_run *kvm_run = vcpu->run;
5218         u32 intr_info, ex_no, error_code;
5219         unsigned long cr2, rip, dr6;
5220         u32 vect_info;
5221         enum emulation_result er;
5222
5223         vect_info = vmx->idt_vectoring_info;
5224         intr_info = vmx->exit_intr_info;
5225
5226         if (is_machine_check(intr_info))
5227                 return handle_machine_check(vcpu);
5228
5229         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5230                 return 1;  /* already handled by vmx_vcpu_run() */
5231
5232         if (is_no_device(intr_info)) {
5233                 vmx_fpu_activate(vcpu);
5234                 return 1;
5235         }
5236
5237         if (is_invalid_opcode(intr_info)) {
5238                 if (is_guest_mode(vcpu)) {
5239                         kvm_queue_exception(vcpu, UD_VECTOR);
5240                         return 1;
5241                 }
5242                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5243                 if (er != EMULATE_DONE)
5244                         kvm_queue_exception(vcpu, UD_VECTOR);
5245                 return 1;
5246         }
5247
5248         error_code = 0;
5249         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5250                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5251
5252         /*
5253          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5254          * MMIO, it is better to report an internal error.
5255          * See the comments in vmx_handle_exit.
5256          */
5257         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5258             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5259                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5260                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5261                 vcpu->run->internal.ndata = 3;
5262                 vcpu->run->internal.data[0] = vect_info;
5263                 vcpu->run->internal.data[1] = intr_info;
5264                 vcpu->run->internal.data[2] = error_code;
5265                 return 0;
5266         }
5267
5268         if (is_page_fault(intr_info)) {
5269                 /* EPT won't cause page fault directly */
5270                 BUG_ON(enable_ept);
5271                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5272                 trace_kvm_page_fault(cr2, error_code);
5273
5274                 if (kvm_event_needs_reinjection(vcpu))
5275                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5276                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5277         }
5278
5279         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5280
5281         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5282                 return handle_rmode_exception(vcpu, ex_no, error_code);
5283
5284         switch (ex_no) {
5285         case AC_VECTOR:
5286                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5287                 return 1;
5288         case DB_VECTOR:
5289                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5290                 if (!(vcpu->guest_debug &
5291                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5292                         vcpu->arch.dr6 &= ~15;
5293                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5294                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5295                                 skip_emulated_instruction(vcpu);
5296
5297                         kvm_queue_exception(vcpu, DB_VECTOR);
5298                         return 1;
5299                 }
5300                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5301                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5302                 /* fall through */
5303         case BP_VECTOR:
5304                 /*
5305                  * Update instruction length as we may reinject #BP from
5306                  * user space while in guest debugging mode. Reading it for
5307                  * #DB as well causes no harm, it is not used in that case.
5308                  */
5309                 vmx->vcpu.arch.event_exit_inst_len =
5310                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5311                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5312                 rip = kvm_rip_read(vcpu);
5313                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5314                 kvm_run->debug.arch.exception = ex_no;
5315                 break;
5316         default:
5317                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5318                 kvm_run->ex.exception = ex_no;
5319                 kvm_run->ex.error_code = error_code;
5320                 break;
5321         }
5322         return 0;
5323 }
5324
5325 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5326 {
5327         ++vcpu->stat.irq_exits;
5328         return 1;
5329 }
5330
5331 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5332 {
5333         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5334         return 0;
5335 }
5336
5337 static int handle_io(struct kvm_vcpu *vcpu)
5338 {
5339         unsigned long exit_qualification;
5340         int size, in, string;
5341         unsigned port;
5342
5343         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5344         string = (exit_qualification & 16) != 0;
5345         in = (exit_qualification & 8) != 0;
5346
5347         ++vcpu->stat.io_exits;
5348
5349         if (string || in)
5350                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5351
5352         port = exit_qualification >> 16;
5353         size = (exit_qualification & 7) + 1;
5354         skip_emulated_instruction(vcpu);
5355
5356         return kvm_fast_pio_out(vcpu, size, port);
5357 }
5358
5359 static void
5360 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5361 {
5362         /*
5363          * Patch in the VMCALL instruction:
5364          */
5365         hypercall[0] = 0x0f;
5366         hypercall[1] = 0x01;
5367         hypercall[2] = 0xc1;
5368 }
5369
5370 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5371 {
5372         unsigned long always_on = VMXON_CR0_ALWAYSON;
5373         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5374
5375         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5376                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5377             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5378                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5379         return (val & always_on) == always_on;
5380 }
5381
5382 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5383 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5384 {
5385         if (is_guest_mode(vcpu)) {
5386                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5387                 unsigned long orig_val = val;
5388
5389                 /*
5390                  * We get here when L2 changed cr0 in a way that did not change
5391                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5392                  * but did change L0 shadowed bits. So we first calculate the
5393                  * effective cr0 value that L1 would like to write into the
5394                  * hardware. It consists of the L2-owned bits from the new
5395                  * value combined with the L1-owned bits from L1's guest_cr0.
5396                  */
5397                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5398                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5399
5400                 if (!nested_cr0_valid(vcpu, val))
5401                         return 1;
5402
5403                 if (kvm_set_cr0(vcpu, val))
5404                         return 1;
5405                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5406                 return 0;
5407         } else {
5408                 if (to_vmx(vcpu)->nested.vmxon &&
5409                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5410                         return 1;
5411                 return kvm_set_cr0(vcpu, val);
5412         }
5413 }
5414
5415 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5416 {
5417         if (is_guest_mode(vcpu)) {
5418                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5419                 unsigned long orig_val = val;
5420
5421                 /* analogously to handle_set_cr0 */
5422                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5423                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5424                 if (kvm_set_cr4(vcpu, val))
5425                         return 1;
5426                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5427                 return 0;
5428         } else
5429                 return kvm_set_cr4(vcpu, val);
5430 }
5431
5432 /* called to set cr0 as approriate for clts instruction exit. */
5433 static void handle_clts(struct kvm_vcpu *vcpu)
5434 {
5435         if (is_guest_mode(vcpu)) {
5436                 /*
5437                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5438                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5439                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5440                  */
5441                 vmcs_writel(CR0_READ_SHADOW,
5442                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5443                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5444         } else
5445                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5446 }
5447
5448 static int handle_cr(struct kvm_vcpu *vcpu)
5449 {
5450         unsigned long exit_qualification, val;
5451         int cr;
5452         int reg;
5453         int err;
5454
5455         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5456         cr = exit_qualification & 15;
5457         reg = (exit_qualification >> 8) & 15;
5458         switch ((exit_qualification >> 4) & 3) {
5459         case 0: /* mov to cr */
5460                 val = kvm_register_readl(vcpu, reg);
5461                 trace_kvm_cr_write(cr, val);
5462                 switch (cr) {
5463                 case 0:
5464                         err = handle_set_cr0(vcpu, val);
5465                         kvm_complete_insn_gp(vcpu, err);
5466                         return 1;
5467                 case 3:
5468                         err = kvm_set_cr3(vcpu, val);
5469                         kvm_complete_insn_gp(vcpu, err);
5470                         return 1;
5471                 case 4:
5472                         err = handle_set_cr4(vcpu, val);
5473                         kvm_complete_insn_gp(vcpu, err);
5474                         return 1;
5475                 case 8: {
5476                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5477                                 u8 cr8 = (u8)val;
5478                                 err = kvm_set_cr8(vcpu, cr8);
5479                                 kvm_complete_insn_gp(vcpu, err);
5480                                 if (lapic_in_kernel(vcpu))
5481                                         return 1;
5482                                 if (cr8_prev <= cr8)
5483                                         return 1;
5484                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5485                                 return 0;
5486                         }
5487                 }
5488                 break;
5489         case 2: /* clts */
5490                 handle_clts(vcpu);
5491                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5492                 skip_emulated_instruction(vcpu);
5493                 vmx_fpu_activate(vcpu);
5494                 return 1;
5495         case 1: /*mov from cr*/
5496                 switch (cr) {
5497                 case 3:
5498                         val = kvm_read_cr3(vcpu);
5499                         kvm_register_write(vcpu, reg, val);
5500                         trace_kvm_cr_read(cr, val);
5501                         skip_emulated_instruction(vcpu);
5502                         return 1;
5503                 case 8:
5504                         val = kvm_get_cr8(vcpu);
5505                         kvm_register_write(vcpu, reg, val);
5506                         trace_kvm_cr_read(cr, val);
5507                         skip_emulated_instruction(vcpu);
5508                         return 1;
5509                 }
5510                 break;
5511         case 3: /* lmsw */
5512                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5513                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5514                 kvm_lmsw(vcpu, val);
5515
5516                 skip_emulated_instruction(vcpu);
5517                 return 1;
5518         default:
5519                 break;
5520         }
5521         vcpu->run->exit_reason = 0;
5522         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5523                (int)(exit_qualification >> 4) & 3, cr);
5524         return 0;
5525 }
5526
5527 static int handle_dr(struct kvm_vcpu *vcpu)
5528 {
5529         unsigned long exit_qualification;
5530         int dr, dr7, reg;
5531
5532         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5533         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5534
5535         /* First, if DR does not exist, trigger UD */
5536         if (!kvm_require_dr(vcpu, dr))
5537                 return 1;
5538
5539         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5540         if (!kvm_require_cpl(vcpu, 0))
5541                 return 1;
5542         dr7 = vmcs_readl(GUEST_DR7);
5543         if (dr7 & DR7_GD) {
5544                 /*
5545                  * As the vm-exit takes precedence over the debug trap, we
5546                  * need to emulate the latter, either for the host or the
5547                  * guest debugging itself.
5548                  */
5549                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5550                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5551                         vcpu->run->debug.arch.dr7 = dr7;
5552                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5553                         vcpu->run->debug.arch.exception = DB_VECTOR;
5554                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5555                         return 0;
5556                 } else {
5557                         vcpu->arch.dr6 &= ~15;
5558                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5559                         kvm_queue_exception(vcpu, DB_VECTOR);
5560                         return 1;
5561                 }
5562         }
5563
5564         if (vcpu->guest_debug == 0) {
5565                 u32 cpu_based_vm_exec_control;
5566
5567                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5568                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5569                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5570
5571                 /*
5572                  * No more DR vmexits; force a reload of the debug registers
5573                  * and reenter on this instruction.  The next vmexit will
5574                  * retrieve the full state of the debug registers.
5575                  */
5576                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5577                 return 1;
5578         }
5579
5580         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5581         if (exit_qualification & TYPE_MOV_FROM_DR) {
5582                 unsigned long val;
5583
5584                 if (kvm_get_dr(vcpu, dr, &val))
5585                         return 1;
5586                 kvm_register_write(vcpu, reg, val);
5587         } else
5588                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5589                         return 1;
5590
5591         skip_emulated_instruction(vcpu);
5592         return 1;
5593 }
5594
5595 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5596 {
5597         return vcpu->arch.dr6;
5598 }
5599
5600 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5601 {
5602 }
5603
5604 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5605 {
5606         u32 cpu_based_vm_exec_control;
5607
5608         get_debugreg(vcpu->arch.db[0], 0);
5609         get_debugreg(vcpu->arch.db[1], 1);
5610         get_debugreg(vcpu->arch.db[2], 2);
5611         get_debugreg(vcpu->arch.db[3], 3);
5612         get_debugreg(vcpu->arch.dr6, 6);
5613         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5614
5615         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5616
5617         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5618         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5619         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5620 }
5621
5622 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5623 {
5624         vmcs_writel(GUEST_DR7, val);
5625 }
5626
5627 static int handle_cpuid(struct kvm_vcpu *vcpu)
5628 {
5629         kvm_emulate_cpuid(vcpu);
5630         return 1;
5631 }
5632
5633 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5634 {
5635         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5636         struct msr_data msr_info;
5637
5638         msr_info.index = ecx;
5639         msr_info.host_initiated = false;
5640         if (vmx_get_msr(vcpu, &msr_info)) {
5641                 trace_kvm_msr_read_ex(ecx);
5642                 kvm_inject_gp(vcpu, 0);
5643                 return 1;
5644         }
5645
5646         trace_kvm_msr_read(ecx, msr_info.data);
5647
5648         /* FIXME: handling of bits 32:63 of rax, rdx */
5649         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5650         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5651         skip_emulated_instruction(vcpu);
5652         return 1;
5653 }
5654
5655 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5656 {
5657         struct msr_data msr;
5658         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5659         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5660                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5661
5662         msr.data = data;
5663         msr.index = ecx;
5664         msr.host_initiated = false;
5665         if (kvm_set_msr(vcpu, &msr) != 0) {
5666                 trace_kvm_msr_write_ex(ecx, data);
5667                 kvm_inject_gp(vcpu, 0);
5668                 return 1;
5669         }
5670
5671         trace_kvm_msr_write(ecx, data);
5672         skip_emulated_instruction(vcpu);
5673         return 1;
5674 }
5675
5676 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5677 {
5678         kvm_make_request(KVM_REQ_EVENT, vcpu);
5679         return 1;
5680 }
5681
5682 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5683 {
5684         u32 cpu_based_vm_exec_control;
5685
5686         /* clear pending irq */
5687         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5688         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5689         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5690
5691         kvm_make_request(KVM_REQ_EVENT, vcpu);
5692
5693         ++vcpu->stat.irq_window_exits;
5694         return 1;
5695 }
5696
5697 static int handle_halt(struct kvm_vcpu *vcpu)
5698 {
5699         return kvm_emulate_halt(vcpu);
5700 }
5701
5702 static int handle_vmcall(struct kvm_vcpu *vcpu)
5703 {
5704         kvm_emulate_hypercall(vcpu);
5705         return 1;
5706 }
5707
5708 static int handle_invd(struct kvm_vcpu *vcpu)
5709 {
5710         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5711 }
5712
5713 static int handle_invlpg(struct kvm_vcpu *vcpu)
5714 {
5715         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5716
5717         kvm_mmu_invlpg(vcpu, exit_qualification);
5718         skip_emulated_instruction(vcpu);
5719         return 1;
5720 }
5721
5722 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5723 {
5724         int err;
5725
5726         err = kvm_rdpmc(vcpu);
5727         kvm_complete_insn_gp(vcpu, err);
5728
5729         return 1;
5730 }
5731
5732 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5733 {
5734         kvm_emulate_wbinvd(vcpu);
5735         return 1;
5736 }
5737
5738 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5739 {
5740         u64 new_bv = kvm_read_edx_eax(vcpu);
5741         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5742
5743         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5744                 skip_emulated_instruction(vcpu);
5745         return 1;
5746 }
5747
5748 static int handle_xsaves(struct kvm_vcpu *vcpu)
5749 {
5750         skip_emulated_instruction(vcpu);
5751         WARN(1, "this should never happen\n");
5752         return 1;
5753 }
5754
5755 static int handle_xrstors(struct kvm_vcpu *vcpu)
5756 {
5757         skip_emulated_instruction(vcpu);
5758         WARN(1, "this should never happen\n");
5759         return 1;
5760 }
5761
5762 static int handle_apic_access(struct kvm_vcpu *vcpu)
5763 {
5764         if (likely(fasteoi)) {
5765                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5766                 int access_type, offset;
5767
5768                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5769                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5770                 /*
5771                  * Sane guest uses MOV to write EOI, with written value
5772                  * not cared. So make a short-circuit here by avoiding
5773                  * heavy instruction emulation.
5774                  */
5775                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5776                     (offset == APIC_EOI)) {
5777                         kvm_lapic_set_eoi(vcpu);
5778                         skip_emulated_instruction(vcpu);
5779                         return 1;
5780                 }
5781         }
5782         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5783 }
5784
5785 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5786 {
5787         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5788         int vector = exit_qualification & 0xff;
5789
5790         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5791         kvm_apic_set_eoi_accelerated(vcpu, vector);
5792         return 1;
5793 }
5794
5795 static int handle_apic_write(struct kvm_vcpu *vcpu)
5796 {
5797         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5798         u32 offset = exit_qualification & 0xfff;
5799
5800         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5801         kvm_apic_write_nodecode(vcpu, offset);
5802         return 1;
5803 }
5804
5805 static int handle_task_switch(struct kvm_vcpu *vcpu)
5806 {
5807         struct vcpu_vmx *vmx = to_vmx(vcpu);
5808         unsigned long exit_qualification;
5809         bool has_error_code = false;
5810         u32 error_code = 0;
5811         u16 tss_selector;
5812         int reason, type, idt_v, idt_index;
5813
5814         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5815         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5816         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5817
5818         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5819
5820         reason = (u32)exit_qualification >> 30;
5821         if (reason == TASK_SWITCH_GATE && idt_v) {
5822                 switch (type) {
5823                 case INTR_TYPE_NMI_INTR:
5824                         vcpu->arch.nmi_injected = false;
5825                         vmx_set_nmi_mask(vcpu, true);
5826                         break;
5827                 case INTR_TYPE_EXT_INTR:
5828                 case INTR_TYPE_SOFT_INTR:
5829                         kvm_clear_interrupt_queue(vcpu);
5830                         break;
5831                 case INTR_TYPE_HARD_EXCEPTION:
5832                         if (vmx->idt_vectoring_info &
5833                             VECTORING_INFO_DELIVER_CODE_MASK) {
5834                                 has_error_code = true;
5835                                 error_code =
5836                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5837                         }
5838                         /* fall through */
5839                 case INTR_TYPE_SOFT_EXCEPTION:
5840                         kvm_clear_exception_queue(vcpu);
5841                         break;
5842                 default:
5843                         break;
5844                 }
5845         }
5846         tss_selector = exit_qualification;
5847
5848         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5849                        type != INTR_TYPE_EXT_INTR &&
5850                        type != INTR_TYPE_NMI_INTR))
5851                 skip_emulated_instruction(vcpu);
5852
5853         if (kvm_task_switch(vcpu, tss_selector,
5854                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5855                             has_error_code, error_code) == EMULATE_FAIL) {
5856                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5857                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5858                 vcpu->run->internal.ndata = 0;
5859                 return 0;
5860         }
5861
5862         /*
5863          * TODO: What about debug traps on tss switch?
5864          *       Are we supposed to inject them and update dr6?
5865          */
5866
5867         return 1;
5868 }
5869
5870 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5871 {
5872         unsigned long exit_qualification;
5873         gpa_t gpa;
5874         u32 error_code;
5875         int gla_validity;
5876
5877         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5878
5879         gla_validity = (exit_qualification >> 7) & 0x3;
5880         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5881                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5882                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5883                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5884                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5885                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5886                         (long unsigned int)exit_qualification);
5887                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5888                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5889                 return 0;
5890         }
5891
5892         /*
5893          * EPT violation happened while executing iret from NMI,
5894          * "blocked by NMI" bit has to be set before next VM entry.
5895          * There are errata that may cause this bit to not be set:
5896          * AAK134, BY25.
5897          */
5898         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5899                         cpu_has_virtual_nmis() &&
5900                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5901                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5902
5903         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5904         trace_kvm_page_fault(gpa, exit_qualification);
5905
5906         /* It is a write fault? */
5907         error_code = exit_qualification & PFERR_WRITE_MASK;
5908         /* It is a fetch fault? */
5909         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5910         /* ept page table is present? */
5911         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5912
5913         vcpu->arch.exit_qualification = exit_qualification;
5914
5915         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5916 }
5917
5918 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5919 {
5920         int ret;
5921         gpa_t gpa;
5922
5923         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5924         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5925                 skip_emulated_instruction(vcpu);
5926                 trace_kvm_fast_mmio(gpa);
5927                 return 1;
5928         }
5929
5930         ret = handle_mmio_page_fault(vcpu, gpa, true);
5931         if (likely(ret == RET_MMIO_PF_EMULATE))
5932                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5933                                               EMULATE_DONE;
5934
5935         if (unlikely(ret == RET_MMIO_PF_INVALID))
5936                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5937
5938         if (unlikely(ret == RET_MMIO_PF_RETRY))
5939                 return 1;
5940
5941         /* It is the real ept misconfig */
5942         WARN_ON(1);
5943
5944         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5945         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5946
5947         return 0;
5948 }
5949
5950 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5951 {
5952         u32 cpu_based_vm_exec_control;
5953
5954         /* clear pending NMI */
5955         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5956         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5957         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5958         ++vcpu->stat.nmi_window_exits;
5959         kvm_make_request(KVM_REQ_EVENT, vcpu);
5960
5961         return 1;
5962 }
5963
5964 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5965 {
5966         struct vcpu_vmx *vmx = to_vmx(vcpu);
5967         enum emulation_result err = EMULATE_DONE;
5968         int ret = 1;
5969         u32 cpu_exec_ctrl;
5970         bool intr_window_requested;
5971         unsigned count = 130;
5972
5973         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5974         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5975
5976         while (vmx->emulation_required && count-- != 0) {
5977                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5978                         return handle_interrupt_window(&vmx->vcpu);
5979
5980                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5981                         return 1;
5982
5983                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5984
5985                 if (err == EMULATE_USER_EXIT) {
5986                         ++vcpu->stat.mmio_exits;
5987                         ret = 0;
5988                         goto out;
5989                 }
5990
5991                 if (err != EMULATE_DONE) {
5992                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5993                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5994                         vcpu->run->internal.ndata = 0;
5995                         return 0;
5996                 }
5997
5998                 if (vcpu->arch.halt_request) {
5999                         vcpu->arch.halt_request = 0;
6000                         ret = kvm_vcpu_halt(vcpu);
6001                         goto out;
6002                 }
6003
6004                 if (signal_pending(current))
6005                         goto out;
6006                 if (need_resched())
6007                         schedule();
6008         }
6009
6010 out:
6011         return ret;
6012 }
6013
6014 static int __grow_ple_window(int val)
6015 {
6016         if (ple_window_grow < 1)
6017                 return ple_window;
6018
6019         val = min(val, ple_window_actual_max);
6020
6021         if (ple_window_grow < ple_window)
6022                 val *= ple_window_grow;
6023         else
6024                 val += ple_window_grow;
6025
6026         return val;
6027 }
6028
6029 static int __shrink_ple_window(int val, int modifier, int minimum)
6030 {
6031         if (modifier < 1)
6032                 return ple_window;
6033
6034         if (modifier < ple_window)
6035                 val /= modifier;
6036         else
6037                 val -= modifier;
6038
6039         return max(val, minimum);
6040 }
6041
6042 static void grow_ple_window(struct kvm_vcpu *vcpu)
6043 {
6044         struct vcpu_vmx *vmx = to_vmx(vcpu);
6045         int old = vmx->ple_window;
6046
6047         vmx->ple_window = __grow_ple_window(old);
6048
6049         if (vmx->ple_window != old)
6050                 vmx->ple_window_dirty = true;
6051
6052         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6053 }
6054
6055 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6056 {
6057         struct vcpu_vmx *vmx = to_vmx(vcpu);
6058         int old = vmx->ple_window;
6059
6060         vmx->ple_window = __shrink_ple_window(old,
6061                                               ple_window_shrink, ple_window);
6062
6063         if (vmx->ple_window != old)
6064                 vmx->ple_window_dirty = true;
6065
6066         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6067 }
6068
6069 /*
6070  * ple_window_actual_max is computed to be one grow_ple_window() below
6071  * ple_window_max. (See __grow_ple_window for the reason.)
6072  * This prevents overflows, because ple_window_max is int.
6073  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6074  * this process.
6075  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6076  */
6077 static void update_ple_window_actual_max(void)
6078 {
6079         ple_window_actual_max =
6080                         __shrink_ple_window(max(ple_window_max, ple_window),
6081                                             ple_window_grow, INT_MIN);
6082 }
6083
6084 /*
6085  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6086  */
6087 static void wakeup_handler(void)
6088 {
6089         struct kvm_vcpu *vcpu;
6090         int cpu = smp_processor_id();
6091
6092         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6093         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6094                         blocked_vcpu_list) {
6095                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6096
6097                 if (pi_test_on(pi_desc) == 1)
6098                         kvm_vcpu_kick(vcpu);
6099         }
6100         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6101 }
6102
6103 static __init int hardware_setup(void)
6104 {
6105         int r = -ENOMEM, i, msr;
6106
6107         rdmsrl_safe(MSR_EFER, &host_efer);
6108
6109         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6110                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6111
6112         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6113         if (!vmx_io_bitmap_a)
6114                 return r;
6115
6116         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6117         if (!vmx_io_bitmap_b)
6118                 goto out;
6119
6120         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6121         if (!vmx_msr_bitmap_legacy)
6122                 goto out1;
6123
6124         vmx_msr_bitmap_legacy_x2apic =
6125                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6126         if (!vmx_msr_bitmap_legacy_x2apic)
6127                 goto out2;
6128
6129         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6130         if (!vmx_msr_bitmap_longmode)
6131                 goto out3;
6132
6133         vmx_msr_bitmap_longmode_x2apic =
6134                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6135         if (!vmx_msr_bitmap_longmode_x2apic)
6136                 goto out4;
6137
6138         if (nested) {
6139                 vmx_msr_bitmap_nested =
6140                         (unsigned long *)__get_free_page(GFP_KERNEL);
6141                 if (!vmx_msr_bitmap_nested)
6142                         goto out5;
6143         }
6144
6145         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6146         if (!vmx_vmread_bitmap)
6147                 goto out6;
6148
6149         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6150         if (!vmx_vmwrite_bitmap)
6151                 goto out7;
6152
6153         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6154         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6155
6156         /*
6157          * Allow direct access to the PC debug port (it is often used for I/O
6158          * delays, but the vmexits simply slow things down).
6159          */
6160         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6161         clear_bit(0x80, vmx_io_bitmap_a);
6162
6163         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6164
6165         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6166         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6167         if (nested)
6168                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6169
6170         if (setup_vmcs_config(&vmcs_config) < 0) {
6171                 r = -EIO;
6172                 goto out8;
6173         }
6174
6175         if (boot_cpu_has(X86_FEATURE_NX))
6176                 kvm_enable_efer_bits(EFER_NX);
6177
6178         if (!cpu_has_vmx_vpid())
6179                 enable_vpid = 0;
6180         if (!cpu_has_vmx_shadow_vmcs())
6181                 enable_shadow_vmcs = 0;
6182         if (enable_shadow_vmcs)
6183                 init_vmcs_shadow_fields();
6184
6185         if (!cpu_has_vmx_ept() ||
6186             !cpu_has_vmx_ept_4levels()) {
6187                 enable_ept = 0;
6188                 enable_unrestricted_guest = 0;
6189                 enable_ept_ad_bits = 0;
6190         }
6191
6192         if (!cpu_has_vmx_ept_ad_bits())
6193                 enable_ept_ad_bits = 0;
6194
6195         if (!cpu_has_vmx_unrestricted_guest())
6196                 enable_unrestricted_guest = 0;
6197
6198         if (!cpu_has_vmx_flexpriority())
6199                 flexpriority_enabled = 0;
6200
6201         /*
6202          * set_apic_access_page_addr() is used to reload apic access
6203          * page upon invalidation.  No need to do anything if not
6204          * using the APIC_ACCESS_ADDR VMCS field.
6205          */
6206         if (!flexpriority_enabled)
6207                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6208
6209         if (!cpu_has_vmx_tpr_shadow())
6210                 kvm_x86_ops->update_cr8_intercept = NULL;
6211
6212         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6213                 kvm_disable_largepages();
6214
6215         if (!cpu_has_vmx_ple())
6216                 ple_gap = 0;
6217
6218         if (!cpu_has_vmx_apicv())
6219                 enable_apicv = 0;
6220
6221         if (cpu_has_vmx_tsc_scaling()) {
6222                 kvm_has_tsc_control = true;
6223                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6224                 kvm_tsc_scaling_ratio_frac_bits = 48;
6225         }
6226
6227         if (enable_apicv)
6228                 kvm_x86_ops->update_cr8_intercept = NULL;
6229         else {
6230                 kvm_x86_ops->hwapic_irr_update = NULL;
6231                 kvm_x86_ops->hwapic_isr_update = NULL;
6232                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6233                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6234         }
6235
6236         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6237         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6238         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6239         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6240         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6241         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6242         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6243
6244         memcpy(vmx_msr_bitmap_legacy_x2apic,
6245                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6246         memcpy(vmx_msr_bitmap_longmode_x2apic,
6247                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6248
6249         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6250
6251         if (enable_apicv) {
6252                 for (msr = 0x800; msr <= 0x8ff; msr++)
6253                         vmx_disable_intercept_msr_read_x2apic(msr);
6254
6255                 /* According SDM, in x2apic mode, the whole id reg is used.
6256                  * But in KVM, it only use the highest eight bits. Need to
6257                  * intercept it */
6258                 vmx_enable_intercept_msr_read_x2apic(0x802);
6259                 /* TMCCT */
6260                 vmx_enable_intercept_msr_read_x2apic(0x839);
6261                 /* TPR */
6262                 vmx_disable_intercept_msr_write_x2apic(0x808);
6263                 /* EOI */
6264                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6265                 /* SELF-IPI */
6266                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6267         }
6268
6269         if (enable_ept) {
6270                 kvm_mmu_set_mask_ptes(0ull,
6271                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6272                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6273                         0ull, VMX_EPT_EXECUTABLE_MASK);
6274                 ept_set_mmio_spte_mask();
6275                 kvm_enable_tdp();
6276         } else
6277                 kvm_disable_tdp();
6278
6279         update_ple_window_actual_max();
6280
6281         /*
6282          * Only enable PML when hardware supports PML feature, and both EPT
6283          * and EPT A/D bit features are enabled -- PML depends on them to work.
6284          */
6285         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6286                 enable_pml = 0;
6287
6288         if (!enable_pml) {
6289                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6290                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6291                 kvm_x86_ops->flush_log_dirty = NULL;
6292                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6293         }
6294
6295         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6296
6297         return alloc_kvm_area();
6298
6299 out8:
6300         free_page((unsigned long)vmx_vmwrite_bitmap);
6301 out7:
6302         free_page((unsigned long)vmx_vmread_bitmap);
6303 out6:
6304         if (nested)
6305                 free_page((unsigned long)vmx_msr_bitmap_nested);
6306 out5:
6307         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6308 out4:
6309         free_page((unsigned long)vmx_msr_bitmap_longmode);
6310 out3:
6311         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6312 out2:
6313         free_page((unsigned long)vmx_msr_bitmap_legacy);
6314 out1:
6315         free_page((unsigned long)vmx_io_bitmap_b);
6316 out:
6317         free_page((unsigned long)vmx_io_bitmap_a);
6318
6319     return r;
6320 }
6321
6322 static __exit void hardware_unsetup(void)
6323 {
6324         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6325         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6326         free_page((unsigned long)vmx_msr_bitmap_legacy);
6327         free_page((unsigned long)vmx_msr_bitmap_longmode);
6328         free_page((unsigned long)vmx_io_bitmap_b);
6329         free_page((unsigned long)vmx_io_bitmap_a);
6330         free_page((unsigned long)vmx_vmwrite_bitmap);
6331         free_page((unsigned long)vmx_vmread_bitmap);
6332         if (nested)
6333                 free_page((unsigned long)vmx_msr_bitmap_nested);
6334
6335         free_kvm_area();
6336 }
6337
6338 /*
6339  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6340  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6341  */
6342 static int handle_pause(struct kvm_vcpu *vcpu)
6343 {
6344         if (ple_gap)
6345                 grow_ple_window(vcpu);
6346
6347         skip_emulated_instruction(vcpu);
6348         kvm_vcpu_on_spin(vcpu);
6349
6350         return 1;
6351 }
6352
6353 static int handle_nop(struct kvm_vcpu *vcpu)
6354 {
6355         skip_emulated_instruction(vcpu);
6356         return 1;
6357 }
6358
6359 static int handle_mwait(struct kvm_vcpu *vcpu)
6360 {
6361         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6362         return handle_nop(vcpu);
6363 }
6364
6365 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6366 {
6367         return 1;
6368 }
6369
6370 static int handle_monitor(struct kvm_vcpu *vcpu)
6371 {
6372         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6373         return handle_nop(vcpu);
6374 }
6375
6376 /*
6377  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6378  * We could reuse a single VMCS for all the L2 guests, but we also want the
6379  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6380  * allows keeping them loaded on the processor, and in the future will allow
6381  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6382  * every entry if they never change.
6383  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6384  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6385  *
6386  * The following functions allocate and free a vmcs02 in this pool.
6387  */
6388
6389 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6390 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6391 {
6392         struct vmcs02_list *item;
6393         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6394                 if (item->vmptr == vmx->nested.current_vmptr) {
6395                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6396                         return &item->vmcs02;
6397                 }
6398
6399         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6400                 /* Recycle the least recently used VMCS. */
6401                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6402                         struct vmcs02_list, list);
6403                 item->vmptr = vmx->nested.current_vmptr;
6404                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6405                 return &item->vmcs02;
6406         }
6407
6408         /* Create a new VMCS */
6409         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6410         if (!item)
6411                 return NULL;
6412         item->vmcs02.vmcs = alloc_vmcs();
6413         if (!item->vmcs02.vmcs) {
6414                 kfree(item);
6415                 return NULL;
6416         }
6417         loaded_vmcs_init(&item->vmcs02);
6418         item->vmptr = vmx->nested.current_vmptr;
6419         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6420         vmx->nested.vmcs02_num++;
6421         return &item->vmcs02;
6422 }
6423
6424 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6425 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6426 {
6427         struct vmcs02_list *item;
6428         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6429                 if (item->vmptr == vmptr) {
6430                         free_loaded_vmcs(&item->vmcs02);
6431                         list_del(&item->list);
6432                         kfree(item);
6433                         vmx->nested.vmcs02_num--;
6434                         return;
6435                 }
6436 }
6437
6438 /*
6439  * Free all VMCSs saved for this vcpu, except the one pointed by
6440  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6441  * must be &vmx->vmcs01.
6442  */
6443 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6444 {
6445         struct vmcs02_list *item, *n;
6446
6447         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6448         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6449                 /*
6450                  * Something will leak if the above WARN triggers.  Better than
6451                  * a use-after-free.
6452                  */
6453                 if (vmx->loaded_vmcs == &item->vmcs02)
6454                         continue;
6455
6456                 free_loaded_vmcs(&item->vmcs02);
6457                 list_del(&item->list);
6458                 kfree(item);
6459                 vmx->nested.vmcs02_num--;
6460         }
6461 }
6462
6463 /*
6464  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6465  * set the success or error code of an emulated VMX instruction, as specified
6466  * by Vol 2B, VMX Instruction Reference, "Conventions".
6467  */
6468 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6469 {
6470         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6471                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6472                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6473 }
6474
6475 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6476 {
6477         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6478                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6479                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6480                         | X86_EFLAGS_CF);
6481 }
6482
6483 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6484                                         u32 vm_instruction_error)
6485 {
6486         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6487                 /*
6488                  * failValid writes the error number to the current VMCS, which
6489                  * can't be done there isn't a current VMCS.
6490                  */
6491                 nested_vmx_failInvalid(vcpu);
6492                 return;
6493         }
6494         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6495                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6496                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6497                         | X86_EFLAGS_ZF);
6498         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6499         /*
6500          * We don't need to force a shadow sync because
6501          * VM_INSTRUCTION_ERROR is not shadowed
6502          */
6503 }
6504
6505 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6506 {
6507         /* TODO: not to reset guest simply here. */
6508         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6509         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6510 }
6511
6512 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6513 {
6514         struct vcpu_vmx *vmx =
6515                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6516
6517         vmx->nested.preemption_timer_expired = true;
6518         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6519         kvm_vcpu_kick(&vmx->vcpu);
6520
6521         return HRTIMER_NORESTART;
6522 }
6523
6524 /*
6525  * Decode the memory-address operand of a vmx instruction, as recorded on an
6526  * exit caused by such an instruction (run by a guest hypervisor).
6527  * On success, returns 0. When the operand is invalid, returns 1 and throws
6528  * #UD or #GP.
6529  */
6530 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6531                                  unsigned long exit_qualification,
6532                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6533 {
6534         gva_t off;
6535         bool exn;
6536         struct kvm_segment s;
6537
6538         /*
6539          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6540          * Execution", on an exit, vmx_instruction_info holds most of the
6541          * addressing components of the operand. Only the displacement part
6542          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6543          * For how an actual address is calculated from all these components,
6544          * refer to Vol. 1, "Operand Addressing".
6545          */
6546         int  scaling = vmx_instruction_info & 3;
6547         int  addr_size = (vmx_instruction_info >> 7) & 7;
6548         bool is_reg = vmx_instruction_info & (1u << 10);
6549         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6550         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6551         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6552         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6553         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6554
6555         if (is_reg) {
6556                 kvm_queue_exception(vcpu, UD_VECTOR);
6557                 return 1;
6558         }
6559
6560         /* Addr = segment_base + offset */
6561         /* offset = base + [index * scale] + displacement */
6562         off = exit_qualification; /* holds the displacement */
6563         if (base_is_valid)
6564                 off += kvm_register_read(vcpu, base_reg);
6565         if (index_is_valid)
6566                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6567         vmx_get_segment(vcpu, &s, seg_reg);
6568         *ret = s.base + off;
6569
6570         if (addr_size == 1) /* 32 bit */
6571                 *ret &= 0xffffffff;
6572
6573         /* Checks for #GP/#SS exceptions. */
6574         exn = false;
6575         if (is_protmode(vcpu)) {
6576                 /* Protected mode: apply checks for segment validity in the
6577                  * following order:
6578                  * - segment type check (#GP(0) may be thrown)
6579                  * - usability check (#GP(0)/#SS(0))
6580                  * - limit check (#GP(0)/#SS(0))
6581                  */
6582                 if (wr)
6583                         /* #GP(0) if the destination operand is located in a
6584                          * read-only data segment or any code segment.
6585                          */
6586                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6587                 else
6588                         /* #GP(0) if the source operand is located in an
6589                          * execute-only code segment
6590                          */
6591                         exn = ((s.type & 0xa) == 8);
6592         }
6593         if (exn) {
6594                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6595                 return 1;
6596         }
6597         if (is_long_mode(vcpu)) {
6598                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6599                  * non-canonical form. This is an only check for long mode.
6600                  */
6601                 exn = is_noncanonical_address(*ret);
6602         } else if (is_protmode(vcpu)) {
6603                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6604                  */
6605                 exn = (s.unusable != 0);
6606                 /* Protected mode: #GP(0)/#SS(0) if the memory
6607                  * operand is outside the segment limit.
6608                  */
6609                 exn = exn || (off + sizeof(u64) > s.limit);
6610         }
6611         if (exn) {
6612                 kvm_queue_exception_e(vcpu,
6613                                       seg_reg == VCPU_SREG_SS ?
6614                                                 SS_VECTOR : GP_VECTOR,
6615                                       0);
6616                 return 1;
6617         }
6618
6619         return 0;
6620 }
6621
6622 /*
6623  * This function performs the various checks including
6624  * - if it's 4KB aligned
6625  * - No bits beyond the physical address width are set
6626  * - Returns 0 on success or else 1
6627  * (Intel SDM Section 30.3)
6628  */
6629 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6630                                   gpa_t *vmpointer)
6631 {
6632         gva_t gva;
6633         gpa_t vmptr;
6634         struct x86_exception e;
6635         struct page *page;
6636         struct vcpu_vmx *vmx = to_vmx(vcpu);
6637         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6638
6639         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6640                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6641                 return 1;
6642
6643         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6644                                 sizeof(vmptr), &e)) {
6645                 kvm_inject_page_fault(vcpu, &e);
6646                 return 1;
6647         }
6648
6649         switch (exit_reason) {
6650         case EXIT_REASON_VMON:
6651                 /*
6652                  * SDM 3: 24.11.5
6653                  * The first 4 bytes of VMXON region contain the supported
6654                  * VMCS revision identifier
6655                  *
6656                  * Note - IA32_VMX_BASIC[48] will never be 1
6657                  * for the nested case;
6658                  * which replaces physical address width with 32
6659                  *
6660                  */
6661                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6662                         nested_vmx_failInvalid(vcpu);
6663                         skip_emulated_instruction(vcpu);
6664                         return 1;
6665                 }
6666
6667                 page = nested_get_page(vcpu, vmptr);
6668                 if (page == NULL ||
6669                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6670                         nested_vmx_failInvalid(vcpu);
6671                         kunmap(page);
6672                         skip_emulated_instruction(vcpu);
6673                         return 1;
6674                 }
6675                 kunmap(page);
6676                 vmx->nested.vmxon_ptr = vmptr;
6677                 break;
6678         case EXIT_REASON_VMCLEAR:
6679                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6680                         nested_vmx_failValid(vcpu,
6681                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6682                         skip_emulated_instruction(vcpu);
6683                         return 1;
6684                 }
6685
6686                 if (vmptr == vmx->nested.vmxon_ptr) {
6687                         nested_vmx_failValid(vcpu,
6688                                              VMXERR_VMCLEAR_VMXON_POINTER);
6689                         skip_emulated_instruction(vcpu);
6690                         return 1;
6691                 }
6692                 break;
6693         case EXIT_REASON_VMPTRLD:
6694                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6695                         nested_vmx_failValid(vcpu,
6696                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6697                         skip_emulated_instruction(vcpu);
6698                         return 1;
6699                 }
6700
6701                 if (vmptr == vmx->nested.vmxon_ptr) {
6702                         nested_vmx_failValid(vcpu,
6703                                              VMXERR_VMCLEAR_VMXON_POINTER);
6704                         skip_emulated_instruction(vcpu);
6705                         return 1;
6706                 }
6707                 break;
6708         default:
6709                 return 1; /* shouldn't happen */
6710         }
6711
6712         if (vmpointer)
6713                 *vmpointer = vmptr;
6714         return 0;
6715 }
6716
6717 /*
6718  * Emulate the VMXON instruction.
6719  * Currently, we just remember that VMX is active, and do not save or even
6720  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6721  * do not currently need to store anything in that guest-allocated memory
6722  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6723  * argument is different from the VMXON pointer (which the spec says they do).
6724  */
6725 static int handle_vmon(struct kvm_vcpu *vcpu)
6726 {
6727         struct kvm_segment cs;
6728         struct vcpu_vmx *vmx = to_vmx(vcpu);
6729         struct vmcs *shadow_vmcs;
6730         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6731                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6732
6733         /* The Intel VMX Instruction Reference lists a bunch of bits that
6734          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6735          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6736          * Otherwise, we should fail with #UD. We test these now:
6737          */
6738         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6739             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6740             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6741                 kvm_queue_exception(vcpu, UD_VECTOR);
6742                 return 1;
6743         }
6744
6745         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6746         if (is_long_mode(vcpu) && !cs.l) {
6747                 kvm_queue_exception(vcpu, UD_VECTOR);
6748                 return 1;
6749         }
6750
6751         if (vmx_get_cpl(vcpu)) {
6752                 kvm_inject_gp(vcpu, 0);
6753                 return 1;
6754         }
6755
6756         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6757                 return 1;
6758
6759         if (vmx->nested.vmxon) {
6760                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6761                 skip_emulated_instruction(vcpu);
6762                 return 1;
6763         }
6764
6765         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6766                         != VMXON_NEEDED_FEATURES) {
6767                 kvm_inject_gp(vcpu, 0);
6768                 return 1;
6769         }
6770
6771         if (enable_shadow_vmcs) {
6772                 shadow_vmcs = alloc_vmcs();
6773                 if (!shadow_vmcs)
6774                         return -ENOMEM;
6775                 /* mark vmcs as shadow */
6776                 shadow_vmcs->revision_id |= (1u << 31);
6777                 /* init shadow vmcs */
6778                 vmcs_clear(shadow_vmcs);
6779                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6780         }
6781
6782         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6783         vmx->nested.vmcs02_num = 0;
6784
6785         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6786                      HRTIMER_MODE_REL);
6787         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6788
6789         vmx->nested.vmxon = true;
6790
6791         skip_emulated_instruction(vcpu);
6792         nested_vmx_succeed(vcpu);
6793         return 1;
6794 }
6795
6796 /*
6797  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6798  * for running VMX instructions (except VMXON, whose prerequisites are
6799  * slightly different). It also specifies what exception to inject otherwise.
6800  */
6801 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6802 {
6803         struct kvm_segment cs;
6804         struct vcpu_vmx *vmx = to_vmx(vcpu);
6805
6806         if (!vmx->nested.vmxon) {
6807                 kvm_queue_exception(vcpu, UD_VECTOR);
6808                 return 0;
6809         }
6810
6811         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6812         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6813             (is_long_mode(vcpu) && !cs.l)) {
6814                 kvm_queue_exception(vcpu, UD_VECTOR);
6815                 return 0;
6816         }
6817
6818         if (vmx_get_cpl(vcpu)) {
6819                 kvm_inject_gp(vcpu, 0);
6820                 return 0;
6821         }
6822
6823         return 1;
6824 }
6825
6826 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6827 {
6828         if (vmx->nested.current_vmptr == -1ull)
6829                 return;
6830
6831         /* current_vmptr and current_vmcs12 are always set/reset together */
6832         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6833                 return;
6834
6835         if (enable_shadow_vmcs) {
6836                 /* copy to memory all shadowed fields in case
6837                    they were modified */
6838                 copy_shadow_to_vmcs12(vmx);
6839                 vmx->nested.sync_shadow_vmcs = false;
6840                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6841                                 SECONDARY_EXEC_SHADOW_VMCS);
6842                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6843         }
6844         vmx->nested.posted_intr_nv = -1;
6845         kunmap(vmx->nested.current_vmcs12_page);
6846         nested_release_page(vmx->nested.current_vmcs12_page);
6847         vmx->nested.current_vmptr = -1ull;
6848         vmx->nested.current_vmcs12 = NULL;
6849 }
6850
6851 /*
6852  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6853  * just stops using VMX.
6854  */
6855 static void free_nested(struct vcpu_vmx *vmx)
6856 {
6857         if (!vmx->nested.vmxon)
6858                 return;
6859
6860         vmx->nested.vmxon = false;
6861         free_vpid(vmx->nested.vpid02);
6862         nested_release_vmcs12(vmx);
6863         if (enable_shadow_vmcs)
6864                 free_vmcs(vmx->nested.current_shadow_vmcs);
6865         /* Unpin physical memory we referred to in current vmcs02 */
6866         if (vmx->nested.apic_access_page) {
6867                 nested_release_page(vmx->nested.apic_access_page);
6868                 vmx->nested.apic_access_page = NULL;
6869         }
6870         if (vmx->nested.virtual_apic_page) {
6871                 nested_release_page(vmx->nested.virtual_apic_page);
6872                 vmx->nested.virtual_apic_page = NULL;
6873         }
6874         if (vmx->nested.pi_desc_page) {
6875                 kunmap(vmx->nested.pi_desc_page);
6876                 nested_release_page(vmx->nested.pi_desc_page);
6877                 vmx->nested.pi_desc_page = NULL;
6878                 vmx->nested.pi_desc = NULL;
6879         }
6880
6881         nested_free_all_saved_vmcss(vmx);
6882 }
6883
6884 /* Emulate the VMXOFF instruction */
6885 static int handle_vmoff(struct kvm_vcpu *vcpu)
6886 {
6887         if (!nested_vmx_check_permission(vcpu))
6888                 return 1;
6889         free_nested(to_vmx(vcpu));
6890         skip_emulated_instruction(vcpu);
6891         nested_vmx_succeed(vcpu);
6892         return 1;
6893 }
6894
6895 /* Emulate the VMCLEAR instruction */
6896 static int handle_vmclear(struct kvm_vcpu *vcpu)
6897 {
6898         struct vcpu_vmx *vmx = to_vmx(vcpu);
6899         gpa_t vmptr;
6900         struct vmcs12 *vmcs12;
6901         struct page *page;
6902
6903         if (!nested_vmx_check_permission(vcpu))
6904                 return 1;
6905
6906         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6907                 return 1;
6908
6909         if (vmptr == vmx->nested.current_vmptr)
6910                 nested_release_vmcs12(vmx);
6911
6912         page = nested_get_page(vcpu, vmptr);
6913         if (page == NULL) {
6914                 /*
6915                  * For accurate processor emulation, VMCLEAR beyond available
6916                  * physical memory should do nothing at all. However, it is
6917                  * possible that a nested vmx bug, not a guest hypervisor bug,
6918                  * resulted in this case, so let's shut down before doing any
6919                  * more damage:
6920                  */
6921                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6922                 return 1;
6923         }
6924         vmcs12 = kmap(page);
6925         vmcs12->launch_state = 0;
6926         kunmap(page);
6927         nested_release_page(page);
6928
6929         nested_free_vmcs02(vmx, vmptr);
6930
6931         skip_emulated_instruction(vcpu);
6932         nested_vmx_succeed(vcpu);
6933         return 1;
6934 }
6935
6936 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6937
6938 /* Emulate the VMLAUNCH instruction */
6939 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6940 {
6941         return nested_vmx_run(vcpu, true);
6942 }
6943
6944 /* Emulate the VMRESUME instruction */
6945 static int handle_vmresume(struct kvm_vcpu *vcpu)
6946 {
6947
6948         return nested_vmx_run(vcpu, false);
6949 }
6950
6951 enum vmcs_field_type {
6952         VMCS_FIELD_TYPE_U16 = 0,
6953         VMCS_FIELD_TYPE_U64 = 1,
6954         VMCS_FIELD_TYPE_U32 = 2,
6955         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6956 };
6957
6958 static inline int vmcs_field_type(unsigned long field)
6959 {
6960         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6961                 return VMCS_FIELD_TYPE_U32;
6962         return (field >> 13) & 0x3 ;
6963 }
6964
6965 static inline int vmcs_field_readonly(unsigned long field)
6966 {
6967         return (((field >> 10) & 0x3) == 1);
6968 }
6969
6970 /*
6971  * Read a vmcs12 field. Since these can have varying lengths and we return
6972  * one type, we chose the biggest type (u64) and zero-extend the return value
6973  * to that size. Note that the caller, handle_vmread, might need to use only
6974  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6975  * 64-bit fields are to be returned).
6976  */
6977 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6978                                   unsigned long field, u64 *ret)
6979 {
6980         short offset = vmcs_field_to_offset(field);
6981         char *p;
6982
6983         if (offset < 0)
6984                 return offset;
6985
6986         p = ((char *)(get_vmcs12(vcpu))) + offset;
6987
6988         switch (vmcs_field_type(field)) {
6989         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6990                 *ret = *((natural_width *)p);
6991                 return 0;
6992         case VMCS_FIELD_TYPE_U16:
6993                 *ret = *((u16 *)p);
6994                 return 0;
6995         case VMCS_FIELD_TYPE_U32:
6996                 *ret = *((u32 *)p);
6997                 return 0;
6998         case VMCS_FIELD_TYPE_U64:
6999                 *ret = *((u64 *)p);
7000                 return 0;
7001         default:
7002                 WARN_ON(1);
7003                 return -ENOENT;
7004         }
7005 }
7006
7007
7008 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7009                                    unsigned long field, u64 field_value){
7010         short offset = vmcs_field_to_offset(field);
7011         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7012         if (offset < 0)
7013                 return offset;
7014
7015         switch (vmcs_field_type(field)) {
7016         case VMCS_FIELD_TYPE_U16:
7017                 *(u16 *)p = field_value;
7018                 return 0;
7019         case VMCS_FIELD_TYPE_U32:
7020                 *(u32 *)p = field_value;
7021                 return 0;
7022         case VMCS_FIELD_TYPE_U64:
7023                 *(u64 *)p = field_value;
7024                 return 0;
7025         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7026                 *(natural_width *)p = field_value;
7027                 return 0;
7028         default:
7029                 WARN_ON(1);
7030                 return -ENOENT;
7031         }
7032
7033 }
7034
7035 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7036 {
7037         int i;
7038         unsigned long field;
7039         u64 field_value;
7040         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7041         const unsigned long *fields = shadow_read_write_fields;
7042         const int num_fields = max_shadow_read_write_fields;
7043
7044         preempt_disable();
7045
7046         vmcs_load(shadow_vmcs);
7047
7048         for (i = 0; i < num_fields; i++) {
7049                 field = fields[i];
7050                 switch (vmcs_field_type(field)) {
7051                 case VMCS_FIELD_TYPE_U16:
7052                         field_value = vmcs_read16(field);
7053                         break;
7054                 case VMCS_FIELD_TYPE_U32:
7055                         field_value = vmcs_read32(field);
7056                         break;
7057                 case VMCS_FIELD_TYPE_U64:
7058                         field_value = vmcs_read64(field);
7059                         break;
7060                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7061                         field_value = vmcs_readl(field);
7062                         break;
7063                 default:
7064                         WARN_ON(1);
7065                         continue;
7066                 }
7067                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7068         }
7069
7070         vmcs_clear(shadow_vmcs);
7071         vmcs_load(vmx->loaded_vmcs->vmcs);
7072
7073         preempt_enable();
7074 }
7075
7076 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7077 {
7078         const unsigned long *fields[] = {
7079                 shadow_read_write_fields,
7080                 shadow_read_only_fields
7081         };
7082         const int max_fields[] = {
7083                 max_shadow_read_write_fields,
7084                 max_shadow_read_only_fields
7085         };
7086         int i, q;
7087         unsigned long field;
7088         u64 field_value = 0;
7089         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7090
7091         vmcs_load(shadow_vmcs);
7092
7093         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7094                 for (i = 0; i < max_fields[q]; i++) {
7095                         field = fields[q][i];
7096                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7097
7098                         switch (vmcs_field_type(field)) {
7099                         case VMCS_FIELD_TYPE_U16:
7100                                 vmcs_write16(field, (u16)field_value);
7101                                 break;
7102                         case VMCS_FIELD_TYPE_U32:
7103                                 vmcs_write32(field, (u32)field_value);
7104                                 break;
7105                         case VMCS_FIELD_TYPE_U64:
7106                                 vmcs_write64(field, (u64)field_value);
7107                                 break;
7108                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7109                                 vmcs_writel(field, (long)field_value);
7110                                 break;
7111                         default:
7112                                 WARN_ON(1);
7113                                 break;
7114                         }
7115                 }
7116         }
7117
7118         vmcs_clear(shadow_vmcs);
7119         vmcs_load(vmx->loaded_vmcs->vmcs);
7120 }
7121
7122 /*
7123  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7124  * used before) all generate the same failure when it is missing.
7125  */
7126 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7127 {
7128         struct vcpu_vmx *vmx = to_vmx(vcpu);
7129         if (vmx->nested.current_vmptr == -1ull) {
7130                 nested_vmx_failInvalid(vcpu);
7131                 skip_emulated_instruction(vcpu);
7132                 return 0;
7133         }
7134         return 1;
7135 }
7136
7137 static int handle_vmread(struct kvm_vcpu *vcpu)
7138 {
7139         unsigned long field;
7140         u64 field_value;
7141         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7142         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7143         gva_t gva = 0;
7144
7145         if (!nested_vmx_check_permission(vcpu) ||
7146             !nested_vmx_check_vmcs12(vcpu))
7147                 return 1;
7148
7149         /* Decode instruction info and find the field to read */
7150         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7151         /* Read the field, zero-extended to a u64 field_value */
7152         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7153                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7154                 skip_emulated_instruction(vcpu);
7155                 return 1;
7156         }
7157         /*
7158          * Now copy part of this value to register or memory, as requested.
7159          * Note that the number of bits actually copied is 32 or 64 depending
7160          * on the guest's mode (32 or 64 bit), not on the given field's length.
7161          */
7162         if (vmx_instruction_info & (1u << 10)) {
7163                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7164                         field_value);
7165         } else {
7166                 if (get_vmx_mem_address(vcpu, exit_qualification,
7167                                 vmx_instruction_info, true, &gva))
7168                         return 1;
7169                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7170                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7171                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7172         }
7173
7174         nested_vmx_succeed(vcpu);
7175         skip_emulated_instruction(vcpu);
7176         return 1;
7177 }
7178
7179
7180 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7181 {
7182         unsigned long field;
7183         gva_t gva;
7184         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7185         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7186         /* The value to write might be 32 or 64 bits, depending on L1's long
7187          * mode, and eventually we need to write that into a field of several
7188          * possible lengths. The code below first zero-extends the value to 64
7189          * bit (field_value), and then copies only the approriate number of
7190          * bits into the vmcs12 field.
7191          */
7192         u64 field_value = 0;
7193         struct x86_exception e;
7194
7195         if (!nested_vmx_check_permission(vcpu) ||
7196             !nested_vmx_check_vmcs12(vcpu))
7197                 return 1;
7198
7199         if (vmx_instruction_info & (1u << 10))
7200                 field_value = kvm_register_readl(vcpu,
7201                         (((vmx_instruction_info) >> 3) & 0xf));
7202         else {
7203                 if (get_vmx_mem_address(vcpu, exit_qualification,
7204                                 vmx_instruction_info, false, &gva))
7205                         return 1;
7206                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7207                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7208                         kvm_inject_page_fault(vcpu, &e);
7209                         return 1;
7210                 }
7211         }
7212
7213
7214         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7215         if (vmcs_field_readonly(field)) {
7216                 nested_vmx_failValid(vcpu,
7217                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7218                 skip_emulated_instruction(vcpu);
7219                 return 1;
7220         }
7221
7222         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7223                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7224                 skip_emulated_instruction(vcpu);
7225                 return 1;
7226         }
7227
7228         nested_vmx_succeed(vcpu);
7229         skip_emulated_instruction(vcpu);
7230         return 1;
7231 }
7232
7233 /* Emulate the VMPTRLD instruction */
7234 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7235 {
7236         struct vcpu_vmx *vmx = to_vmx(vcpu);
7237         gpa_t vmptr;
7238
7239         if (!nested_vmx_check_permission(vcpu))
7240                 return 1;
7241
7242         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7243                 return 1;
7244
7245         if (vmx->nested.current_vmptr != vmptr) {
7246                 struct vmcs12 *new_vmcs12;
7247                 struct page *page;
7248                 page = nested_get_page(vcpu, vmptr);
7249                 if (page == NULL) {
7250                         nested_vmx_failInvalid(vcpu);
7251                         skip_emulated_instruction(vcpu);
7252                         return 1;
7253                 }
7254                 new_vmcs12 = kmap(page);
7255                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7256                         kunmap(page);
7257                         nested_release_page_clean(page);
7258                         nested_vmx_failValid(vcpu,
7259                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7260                         skip_emulated_instruction(vcpu);
7261                         return 1;
7262                 }
7263
7264                 nested_release_vmcs12(vmx);
7265                 vmx->nested.current_vmptr = vmptr;
7266                 vmx->nested.current_vmcs12 = new_vmcs12;
7267                 vmx->nested.current_vmcs12_page = page;
7268                 if (enable_shadow_vmcs) {
7269                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7270                                       SECONDARY_EXEC_SHADOW_VMCS);
7271                         vmcs_write64(VMCS_LINK_POINTER,
7272                                      __pa(vmx->nested.current_shadow_vmcs));
7273                         vmx->nested.sync_shadow_vmcs = true;
7274                 }
7275         }
7276
7277         nested_vmx_succeed(vcpu);
7278         skip_emulated_instruction(vcpu);
7279         return 1;
7280 }
7281
7282 /* Emulate the VMPTRST instruction */
7283 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7284 {
7285         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7286         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7287         gva_t vmcs_gva;
7288         struct x86_exception e;
7289
7290         if (!nested_vmx_check_permission(vcpu))
7291                 return 1;
7292
7293         if (get_vmx_mem_address(vcpu, exit_qualification,
7294                         vmx_instruction_info, true, &vmcs_gva))
7295                 return 1;
7296         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7297         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7298                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7299                                  sizeof(u64), &e)) {
7300                 kvm_inject_page_fault(vcpu, &e);
7301                 return 1;
7302         }
7303         nested_vmx_succeed(vcpu);
7304         skip_emulated_instruction(vcpu);
7305         return 1;
7306 }
7307
7308 /* Emulate the INVEPT instruction */
7309 static int handle_invept(struct kvm_vcpu *vcpu)
7310 {
7311         struct vcpu_vmx *vmx = to_vmx(vcpu);
7312         u32 vmx_instruction_info, types;
7313         unsigned long type;
7314         gva_t gva;
7315         struct x86_exception e;
7316         struct {
7317                 u64 eptp, gpa;
7318         } operand;
7319
7320         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7321               SECONDARY_EXEC_ENABLE_EPT) ||
7322             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7323                 kvm_queue_exception(vcpu, UD_VECTOR);
7324                 return 1;
7325         }
7326
7327         if (!nested_vmx_check_permission(vcpu))
7328                 return 1;
7329
7330         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7331                 kvm_queue_exception(vcpu, UD_VECTOR);
7332                 return 1;
7333         }
7334
7335         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7336         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7337
7338         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7339
7340         if (!(types & (1UL << type))) {
7341                 nested_vmx_failValid(vcpu,
7342                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7343                 return 1;
7344         }
7345
7346         /* According to the Intel VMX instruction reference, the memory
7347          * operand is read even if it isn't needed (e.g., for type==global)
7348          */
7349         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7350                         vmx_instruction_info, false, &gva))
7351                 return 1;
7352         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7353                                 sizeof(operand), &e)) {
7354                 kvm_inject_page_fault(vcpu, &e);
7355                 return 1;
7356         }
7357
7358         switch (type) {
7359         case VMX_EPT_EXTENT_GLOBAL:
7360                 kvm_mmu_sync_roots(vcpu);
7361                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7362                 nested_vmx_succeed(vcpu);
7363                 break;
7364         default:
7365                 /* Trap single context invalidation invept calls */
7366                 BUG_ON(1);
7367                 break;
7368         }
7369
7370         skip_emulated_instruction(vcpu);
7371         return 1;
7372 }
7373
7374 static int handle_invvpid(struct kvm_vcpu *vcpu)
7375 {
7376         struct vcpu_vmx *vmx = to_vmx(vcpu);
7377         u32 vmx_instruction_info;
7378         unsigned long type, types;
7379         gva_t gva;
7380         struct x86_exception e;
7381         int vpid;
7382
7383         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7384               SECONDARY_EXEC_ENABLE_VPID) ||
7385                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7386                 kvm_queue_exception(vcpu, UD_VECTOR);
7387                 return 1;
7388         }
7389
7390         if (!nested_vmx_check_permission(vcpu))
7391                 return 1;
7392
7393         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7394         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7395
7396         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7397
7398         if (!(types & (1UL << type))) {
7399                 nested_vmx_failValid(vcpu,
7400                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7401                 return 1;
7402         }
7403
7404         /* according to the intel vmx instruction reference, the memory
7405          * operand is read even if it isn't needed (e.g., for type==global)
7406          */
7407         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7408                         vmx_instruction_info, false, &gva))
7409                 return 1;
7410         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7411                                 sizeof(u32), &e)) {
7412                 kvm_inject_page_fault(vcpu, &e);
7413                 return 1;
7414         }
7415
7416         switch (type) {
7417         case VMX_VPID_EXTENT_ALL_CONTEXT:
7418                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7419                 nested_vmx_succeed(vcpu);
7420                 break;
7421         default:
7422                 /* Trap single context invalidation invvpid calls */
7423                 BUG_ON(1);
7424                 break;
7425         }
7426
7427         skip_emulated_instruction(vcpu);
7428         return 1;
7429 }
7430
7431 static int handle_pml_full(struct kvm_vcpu *vcpu)
7432 {
7433         unsigned long exit_qualification;
7434
7435         trace_kvm_pml_full(vcpu->vcpu_id);
7436
7437         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7438
7439         /*
7440          * PML buffer FULL happened while executing iret from NMI,
7441          * "blocked by NMI" bit has to be set before next VM entry.
7442          */
7443         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7444                         cpu_has_virtual_nmis() &&
7445                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7446                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7447                                 GUEST_INTR_STATE_NMI);
7448
7449         /*
7450          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7451          * here.., and there's no userspace involvement needed for PML.
7452          */
7453         return 1;
7454 }
7455
7456 static int handle_pcommit(struct kvm_vcpu *vcpu)
7457 {
7458         /* we never catch pcommit instruct for L1 guest. */
7459         WARN_ON(1);
7460         return 1;
7461 }
7462
7463 /*
7464  * The exit handlers return 1 if the exit was handled fully and guest execution
7465  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7466  * to be done to userspace and return 0.
7467  */
7468 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7469         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7470         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7471         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7472         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7473         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7474         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7475         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7476         [EXIT_REASON_CPUID]                   = handle_cpuid,
7477         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7478         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7479         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7480         [EXIT_REASON_HLT]                     = handle_halt,
7481         [EXIT_REASON_INVD]                    = handle_invd,
7482         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7483         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7484         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7485         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7486         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7487         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7488         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7489         [EXIT_REASON_VMREAD]                  = handle_vmread,
7490         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7491         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7492         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7493         [EXIT_REASON_VMON]                    = handle_vmon,
7494         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7495         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7496         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7497         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7498         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7499         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7500         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7501         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7502         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7503         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7504         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7505         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7506         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7507         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7508         [EXIT_REASON_INVEPT]                  = handle_invept,
7509         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7510         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7511         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7512         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7513         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7514 };
7515
7516 static const int kvm_vmx_max_exit_handlers =
7517         ARRAY_SIZE(kvm_vmx_exit_handlers);
7518
7519 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7520                                        struct vmcs12 *vmcs12)
7521 {
7522         unsigned long exit_qualification;
7523         gpa_t bitmap, last_bitmap;
7524         unsigned int port;
7525         int size;
7526         u8 b;
7527
7528         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7529                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7530
7531         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7532
7533         port = exit_qualification >> 16;
7534         size = (exit_qualification & 7) + 1;
7535
7536         last_bitmap = (gpa_t)-1;
7537         b = -1;
7538
7539         while (size > 0) {
7540                 if (port < 0x8000)
7541                         bitmap = vmcs12->io_bitmap_a;
7542                 else if (port < 0x10000)
7543                         bitmap = vmcs12->io_bitmap_b;
7544                 else
7545                         return true;
7546                 bitmap += (port & 0x7fff) / 8;
7547
7548                 if (last_bitmap != bitmap)
7549                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7550                                 return true;
7551                 if (b & (1 << (port & 7)))
7552                         return true;
7553
7554                 port++;
7555                 size--;
7556                 last_bitmap = bitmap;
7557         }
7558
7559         return false;
7560 }
7561
7562 /*
7563  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7564  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7565  * disinterest in the current event (read or write a specific MSR) by using an
7566  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7567  */
7568 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7569         struct vmcs12 *vmcs12, u32 exit_reason)
7570 {
7571         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7572         gpa_t bitmap;
7573
7574         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7575                 return true;
7576
7577         /*
7578          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7579          * for the four combinations of read/write and low/high MSR numbers.
7580          * First we need to figure out which of the four to use:
7581          */
7582         bitmap = vmcs12->msr_bitmap;
7583         if (exit_reason == EXIT_REASON_MSR_WRITE)
7584                 bitmap += 2048;
7585         if (msr_index >= 0xc0000000) {
7586                 msr_index -= 0xc0000000;
7587                 bitmap += 1024;
7588         }
7589
7590         /* Then read the msr_index'th bit from this bitmap: */
7591         if (msr_index < 1024*8) {
7592                 unsigned char b;
7593                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7594                         return true;
7595                 return 1 & (b >> (msr_index & 7));
7596         } else
7597                 return true; /* let L1 handle the wrong parameter */
7598 }
7599
7600 /*
7601  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7602  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7603  * intercept (via guest_host_mask etc.) the current event.
7604  */
7605 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7606         struct vmcs12 *vmcs12)
7607 {
7608         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7609         int cr = exit_qualification & 15;
7610         int reg = (exit_qualification >> 8) & 15;
7611         unsigned long val = kvm_register_readl(vcpu, reg);
7612
7613         switch ((exit_qualification >> 4) & 3) {
7614         case 0: /* mov to cr */
7615                 switch (cr) {
7616                 case 0:
7617                         if (vmcs12->cr0_guest_host_mask &
7618                             (val ^ vmcs12->cr0_read_shadow))
7619                                 return true;
7620                         break;
7621                 case 3:
7622                         if ((vmcs12->cr3_target_count >= 1 &&
7623                                         vmcs12->cr3_target_value0 == val) ||
7624                                 (vmcs12->cr3_target_count >= 2 &&
7625                                         vmcs12->cr3_target_value1 == val) ||
7626                                 (vmcs12->cr3_target_count >= 3 &&
7627                                         vmcs12->cr3_target_value2 == val) ||
7628                                 (vmcs12->cr3_target_count >= 4 &&
7629                                         vmcs12->cr3_target_value3 == val))
7630                                 return false;
7631                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7632                                 return true;
7633                         break;
7634                 case 4:
7635                         if (vmcs12->cr4_guest_host_mask &
7636                             (vmcs12->cr4_read_shadow ^ val))
7637                                 return true;
7638                         break;
7639                 case 8:
7640                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7641                                 return true;
7642                         break;
7643                 }
7644                 break;
7645         case 2: /* clts */
7646                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7647                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7648                         return true;
7649                 break;
7650         case 1: /* mov from cr */
7651                 switch (cr) {
7652                 case 3:
7653                         if (vmcs12->cpu_based_vm_exec_control &
7654                             CPU_BASED_CR3_STORE_EXITING)
7655                                 return true;
7656                         break;
7657                 case 8:
7658                         if (vmcs12->cpu_based_vm_exec_control &
7659                             CPU_BASED_CR8_STORE_EXITING)
7660                                 return true;
7661                         break;
7662                 }
7663                 break;
7664         case 3: /* lmsw */
7665                 /*
7666                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7667                  * cr0. Other attempted changes are ignored, with no exit.
7668                  */
7669                 if (vmcs12->cr0_guest_host_mask & 0xe &
7670                     (val ^ vmcs12->cr0_read_shadow))
7671                         return true;
7672                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7673                     !(vmcs12->cr0_read_shadow & 0x1) &&
7674                     (val & 0x1))
7675                         return true;
7676                 break;
7677         }
7678         return false;
7679 }
7680
7681 /*
7682  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7683  * should handle it ourselves in L0 (and then continue L2). Only call this
7684  * when in is_guest_mode (L2).
7685  */
7686 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7687 {
7688         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7689         struct vcpu_vmx *vmx = to_vmx(vcpu);
7690         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7691         u32 exit_reason = vmx->exit_reason;
7692
7693         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7694                                 vmcs_readl(EXIT_QUALIFICATION),
7695                                 vmx->idt_vectoring_info,
7696                                 intr_info,
7697                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7698                                 KVM_ISA_VMX);
7699
7700         if (vmx->nested.nested_run_pending)
7701                 return false;
7702
7703         if (unlikely(vmx->fail)) {
7704                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7705                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7706                 return true;
7707         }
7708
7709         switch (exit_reason) {
7710         case EXIT_REASON_EXCEPTION_NMI:
7711                 if (!is_exception(intr_info))
7712                         return false;
7713                 else if (is_page_fault(intr_info))
7714                         return enable_ept;
7715                 else if (is_no_device(intr_info) &&
7716                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7717                         return false;
7718                 return vmcs12->exception_bitmap &
7719                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7720         case EXIT_REASON_EXTERNAL_INTERRUPT:
7721                 return false;
7722         case EXIT_REASON_TRIPLE_FAULT:
7723                 return true;
7724         case EXIT_REASON_PENDING_INTERRUPT:
7725                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7726         case EXIT_REASON_NMI_WINDOW:
7727                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7728         case EXIT_REASON_TASK_SWITCH:
7729                 return true;
7730         case EXIT_REASON_CPUID:
7731                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7732                         return false;
7733                 return true;
7734         case EXIT_REASON_HLT:
7735                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7736         case EXIT_REASON_INVD:
7737                 return true;
7738         case EXIT_REASON_INVLPG:
7739                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7740         case EXIT_REASON_RDPMC:
7741                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7742         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7743                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7744         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7745         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7746         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7747         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7748         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7749         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7750                 /*
7751                  * VMX instructions trap unconditionally. This allows L1 to
7752                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7753                  */
7754                 return true;
7755         case EXIT_REASON_CR_ACCESS:
7756                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7757         case EXIT_REASON_DR_ACCESS:
7758                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7759         case EXIT_REASON_IO_INSTRUCTION:
7760                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7761         case EXIT_REASON_MSR_READ:
7762         case EXIT_REASON_MSR_WRITE:
7763                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7764         case EXIT_REASON_INVALID_STATE:
7765                 return true;
7766         case EXIT_REASON_MWAIT_INSTRUCTION:
7767                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7768         case EXIT_REASON_MONITOR_TRAP_FLAG:
7769                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7770         case EXIT_REASON_MONITOR_INSTRUCTION:
7771                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7772         case EXIT_REASON_PAUSE_INSTRUCTION:
7773                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7774                         nested_cpu_has2(vmcs12,
7775                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7776         case EXIT_REASON_MCE_DURING_VMENTRY:
7777                 return false;
7778         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7779                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7780         case EXIT_REASON_APIC_ACCESS:
7781                 return nested_cpu_has2(vmcs12,
7782                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7783         case EXIT_REASON_APIC_WRITE:
7784         case EXIT_REASON_EOI_INDUCED:
7785                 /* apic_write and eoi_induced should exit unconditionally. */
7786                 return true;
7787         case EXIT_REASON_EPT_VIOLATION:
7788                 /*
7789                  * L0 always deals with the EPT violation. If nested EPT is
7790                  * used, and the nested mmu code discovers that the address is
7791                  * missing in the guest EPT table (EPT12), the EPT violation
7792                  * will be injected with nested_ept_inject_page_fault()
7793                  */
7794                 return false;
7795         case EXIT_REASON_EPT_MISCONFIG:
7796                 /*
7797                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7798                  * table (shadow on EPT) or a merged EPT table that L0 built
7799                  * (EPT on EPT). So any problems with the structure of the
7800                  * table is L0's fault.
7801                  */
7802                 return false;
7803         case EXIT_REASON_WBINVD:
7804                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7805         case EXIT_REASON_XSETBV:
7806                 return true;
7807         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7808                 /*
7809                  * This should never happen, since it is not possible to
7810                  * set XSS to a non-zero value---neither in L1 nor in L2.
7811                  * If if it were, XSS would have to be checked against
7812                  * the XSS exit bitmap in vmcs12.
7813                  */
7814                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7815         case EXIT_REASON_PCOMMIT:
7816                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7817         default:
7818                 return true;
7819         }
7820 }
7821
7822 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7823 {
7824         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7825         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7826 }
7827
7828 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7829 {
7830         struct page *pml_pg;
7831
7832         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7833         if (!pml_pg)
7834                 return -ENOMEM;
7835
7836         vmx->pml_pg = pml_pg;
7837
7838         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7839         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7840
7841         return 0;
7842 }
7843
7844 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7845 {
7846         if (vmx->pml_pg) {
7847                 __free_page(vmx->pml_pg);
7848                 vmx->pml_pg = NULL;
7849         }
7850 }
7851
7852 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7853 {
7854         struct vcpu_vmx *vmx = to_vmx(vcpu);
7855         u64 *pml_buf;
7856         u16 pml_idx;
7857
7858         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7859
7860         /* Do nothing if PML buffer is empty */
7861         if (pml_idx == (PML_ENTITY_NUM - 1))
7862                 return;
7863
7864         /* PML index always points to next available PML buffer entity */
7865         if (pml_idx >= PML_ENTITY_NUM)
7866                 pml_idx = 0;
7867         else
7868                 pml_idx++;
7869
7870         pml_buf = page_address(vmx->pml_pg);
7871         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7872                 u64 gpa;
7873
7874                 gpa = pml_buf[pml_idx];
7875                 WARN_ON(gpa & (PAGE_SIZE - 1));
7876                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7877         }
7878
7879         /* reset PML index */
7880         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7881 }
7882
7883 /*
7884  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7885  * Called before reporting dirty_bitmap to userspace.
7886  */
7887 static void kvm_flush_pml_buffers(struct kvm *kvm)
7888 {
7889         int i;
7890         struct kvm_vcpu *vcpu;
7891         /*
7892          * We only need to kick vcpu out of guest mode here, as PML buffer
7893          * is flushed at beginning of all VMEXITs, and it's obvious that only
7894          * vcpus running in guest are possible to have unflushed GPAs in PML
7895          * buffer.
7896          */
7897         kvm_for_each_vcpu(i, vcpu, kvm)
7898                 kvm_vcpu_kick(vcpu);
7899 }
7900
7901 static void vmx_dump_sel(char *name, uint32_t sel)
7902 {
7903         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7904                name, vmcs_read32(sel),
7905                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7906                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7907                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7908 }
7909
7910 static void vmx_dump_dtsel(char *name, uint32_t limit)
7911 {
7912         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7913                name, vmcs_read32(limit),
7914                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7915 }
7916
7917 static void dump_vmcs(void)
7918 {
7919         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7920         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7921         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7922         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7923         u32 secondary_exec_control = 0;
7924         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7925         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7926         int i, n;
7927
7928         if (cpu_has_secondary_exec_ctrls())
7929                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7930
7931         pr_err("*** Guest State ***\n");
7932         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7933                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7934                vmcs_readl(CR0_GUEST_HOST_MASK));
7935         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7936                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7937         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7938         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7939             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7940         {
7941                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7942                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7943                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7944                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7945         }
7946         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7947                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7948         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7949                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7950         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7951                vmcs_readl(GUEST_SYSENTER_ESP),
7952                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7953         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7954         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7955         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7956         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7957         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7958         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7959         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7960         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7961         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7962         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7963         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7964             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7965                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7966                        efer, vmcs_readl(GUEST_IA32_PAT));
7967         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7968                vmcs_readl(GUEST_IA32_DEBUGCTL),
7969                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7970         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7971                 pr_err("PerfGlobCtl = 0x%016lx\n",
7972                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7973         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7974                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7975         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7976                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7977                vmcs_read32(GUEST_ACTIVITY_STATE));
7978         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7979                 pr_err("InterruptStatus = %04x\n",
7980                        vmcs_read16(GUEST_INTR_STATUS));
7981
7982         pr_err("*** Host State ***\n");
7983         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7984                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7985         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7986                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7987                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7988                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7989                vmcs_read16(HOST_TR_SELECTOR));
7990         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7991                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7992                vmcs_readl(HOST_TR_BASE));
7993         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7994                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7995         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7996                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7997                vmcs_readl(HOST_CR4));
7998         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7999                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8000                vmcs_read32(HOST_IA32_SYSENTER_CS),
8001                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8002         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8003                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
8004                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8005         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8006                 pr_err("PerfGlobCtl = 0x%016lx\n",
8007                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8008
8009         pr_err("*** Control State ***\n");
8010         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8011                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8012         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8013         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8014                vmcs_read32(EXCEPTION_BITMAP),
8015                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8016                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8017         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8018                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8019                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8020                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8021         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8022                vmcs_read32(VM_EXIT_INTR_INFO),
8023                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8024                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8025         pr_err("        reason=%08x qualification=%016lx\n",
8026                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8027         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8028                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8029                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8030         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8031         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8032                 pr_err("TSC Multiplier = 0x%016lx\n",
8033                        vmcs_readl(TSC_MULTIPLIER));
8034         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8035                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8036         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8037                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8038         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8039                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8040         n = vmcs_read32(CR3_TARGET_COUNT);
8041         for (i = 0; i + 1 < n; i += 4)
8042                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8043                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8044                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8045         if (i < n)
8046                 pr_err("CR3 target%u=%016lx\n",
8047                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8048         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8049                 pr_err("PLE Gap=%08x Window=%08x\n",
8050                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8051         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8052                 pr_err("Virtual processor ID = 0x%04x\n",
8053                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8054 }
8055
8056 /*
8057  * The guest has exited.  See if we can fix it or if we need userspace
8058  * assistance.
8059  */
8060 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8061 {
8062         struct vcpu_vmx *vmx = to_vmx(vcpu);
8063         u32 exit_reason = vmx->exit_reason;
8064         u32 vectoring_info = vmx->idt_vectoring_info;
8065
8066         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8067
8068         /*
8069          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8070          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8071          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8072          * mode as if vcpus is in root mode, the PML buffer must has been
8073          * flushed already.
8074          */
8075         if (enable_pml)
8076                 vmx_flush_pml_buffer(vcpu);
8077
8078         /* If guest state is invalid, start emulating */
8079         if (vmx->emulation_required)
8080                 return handle_invalid_guest_state(vcpu);
8081
8082         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8083                 nested_vmx_vmexit(vcpu, exit_reason,
8084                                   vmcs_read32(VM_EXIT_INTR_INFO),
8085                                   vmcs_readl(EXIT_QUALIFICATION));
8086                 return 1;
8087         }
8088
8089         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8090                 dump_vmcs();
8091                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8092                 vcpu->run->fail_entry.hardware_entry_failure_reason
8093                         = exit_reason;
8094                 return 0;
8095         }
8096
8097         if (unlikely(vmx->fail)) {
8098                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8099                 vcpu->run->fail_entry.hardware_entry_failure_reason
8100                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8101                 return 0;
8102         }
8103
8104         /*
8105          * Note:
8106          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8107          * delivery event since it indicates guest is accessing MMIO.
8108          * The vm-exit can be triggered again after return to guest that
8109          * will cause infinite loop.
8110          */
8111         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8112                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8113                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8114                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8115                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8116                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8117                 vcpu->run->internal.ndata = 2;
8118                 vcpu->run->internal.data[0] = vectoring_info;
8119                 vcpu->run->internal.data[1] = exit_reason;
8120                 return 0;
8121         }
8122
8123         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8124             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8125                                         get_vmcs12(vcpu))))) {
8126                 if (vmx_interrupt_allowed(vcpu)) {
8127                         vmx->soft_vnmi_blocked = 0;
8128                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8129                            vcpu->arch.nmi_pending) {
8130                         /*
8131                          * This CPU don't support us in finding the end of an
8132                          * NMI-blocked window if the guest runs with IRQs
8133                          * disabled. So we pull the trigger after 1 s of
8134                          * futile waiting, but inform the user about this.
8135                          */
8136                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8137                                "state on VCPU %d after 1 s timeout\n",
8138                                __func__, vcpu->vcpu_id);
8139                         vmx->soft_vnmi_blocked = 0;
8140                 }
8141         }
8142
8143         if (exit_reason < kvm_vmx_max_exit_handlers
8144             && kvm_vmx_exit_handlers[exit_reason])
8145                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8146         else {
8147                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8148                 kvm_queue_exception(vcpu, UD_VECTOR);
8149                 return 1;
8150         }
8151 }
8152
8153 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8154 {
8155         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8156
8157         if (is_guest_mode(vcpu) &&
8158                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8159                 return;
8160
8161         if (irr == -1 || tpr < irr) {
8162                 vmcs_write32(TPR_THRESHOLD, 0);
8163                 return;
8164         }
8165
8166         vmcs_write32(TPR_THRESHOLD, irr);
8167 }
8168
8169 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8170 {
8171         u32 sec_exec_control;
8172
8173         /*
8174          * There is not point to enable virtualize x2apic without enable
8175          * apicv
8176          */
8177         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8178                                 !vmx_cpu_uses_apicv(vcpu))
8179                 return;
8180
8181         if (!cpu_need_tpr_shadow(vcpu))
8182                 return;
8183
8184         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8185
8186         if (set) {
8187                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8188                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8189         } else {
8190                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8191                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8192         }
8193         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8194
8195         vmx_set_msr_bitmap(vcpu);
8196 }
8197
8198 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8199 {
8200         struct vcpu_vmx *vmx = to_vmx(vcpu);
8201
8202         /*
8203          * Currently we do not handle the nested case where L2 has an
8204          * APIC access page of its own; that page is still pinned.
8205          * Hence, we skip the case where the VCPU is in guest mode _and_
8206          * L1 prepared an APIC access page for L2.
8207          *
8208          * For the case where L1 and L2 share the same APIC access page
8209          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8210          * in the vmcs12), this function will only update either the vmcs01
8211          * or the vmcs02.  If the former, the vmcs02 will be updated by
8212          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8213          * the next L2->L1 exit.
8214          */
8215         if (!is_guest_mode(vcpu) ||
8216             !nested_cpu_has2(vmx->nested.current_vmcs12,
8217                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8218                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8219 }
8220
8221 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8222 {
8223         u16 status;
8224         u8 old;
8225
8226         if (isr == -1)
8227                 isr = 0;
8228
8229         status = vmcs_read16(GUEST_INTR_STATUS);
8230         old = status >> 8;
8231         if (isr != old) {
8232                 status &= 0xff;
8233                 status |= isr << 8;
8234                 vmcs_write16(GUEST_INTR_STATUS, status);
8235         }
8236 }
8237
8238 static void vmx_set_rvi(int vector)
8239 {
8240         u16 status;
8241         u8 old;
8242
8243         if (vector == -1)
8244                 vector = 0;
8245
8246         status = vmcs_read16(GUEST_INTR_STATUS);
8247         old = (u8)status & 0xff;
8248         if ((u8)vector != old) {
8249                 status &= ~0xff;
8250                 status |= (u8)vector;
8251                 vmcs_write16(GUEST_INTR_STATUS, status);
8252         }
8253 }
8254
8255 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8256 {
8257         if (!is_guest_mode(vcpu)) {
8258                 vmx_set_rvi(max_irr);
8259                 return;
8260         }
8261
8262         if (max_irr == -1)
8263                 return;
8264
8265         /*
8266          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8267          * handles it.
8268          */
8269         if (nested_exit_on_intr(vcpu))
8270                 return;
8271
8272         /*
8273          * Else, fall back to pre-APICv interrupt injection since L2
8274          * is run without virtual interrupt delivery.
8275          */
8276         if (!kvm_event_needs_reinjection(vcpu) &&
8277             vmx_interrupt_allowed(vcpu)) {
8278                 kvm_queue_interrupt(vcpu, max_irr, false);
8279                 vmx_inject_irq(vcpu);
8280         }
8281 }
8282
8283 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8284 {
8285         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8286         if (!vmx_cpu_uses_apicv(vcpu))
8287                 return;
8288
8289         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8290         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8291         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8292         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8293 }
8294
8295 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8296 {
8297         u32 exit_intr_info;
8298
8299         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8300               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8301                 return;
8302
8303         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8304         exit_intr_info = vmx->exit_intr_info;
8305
8306         /* Handle machine checks before interrupts are enabled */
8307         if (is_machine_check(exit_intr_info))
8308                 kvm_machine_check();
8309
8310         /* We need to handle NMIs before interrupts are enabled */
8311         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8312             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8313                 kvm_before_handle_nmi(&vmx->vcpu);
8314                 asm("int $2");
8315                 kvm_after_handle_nmi(&vmx->vcpu);
8316         }
8317 }
8318
8319 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8320 {
8321         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8322
8323         /*
8324          * If external interrupt exists, IF bit is set in rflags/eflags on the
8325          * interrupt stack frame, and interrupt will be enabled on a return
8326          * from interrupt handler.
8327          */
8328         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8329                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8330                 unsigned int vector;
8331                 unsigned long entry;
8332                 gate_desc *desc;
8333                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8334 #ifdef CONFIG_X86_64
8335                 unsigned long tmp;
8336 #endif
8337
8338                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8339                 desc = (gate_desc *)vmx->host_idt_base + vector;
8340                 entry = gate_offset(*desc);
8341                 asm volatile(
8342 #ifdef CONFIG_X86_64
8343                         "mov %%" _ASM_SP ", %[sp]\n\t"
8344                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8345                         "push $%c[ss]\n\t"
8346                         "push %[sp]\n\t"
8347 #endif
8348                         "pushf\n\t"
8349                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8350                         __ASM_SIZE(push) " $%c[cs]\n\t"
8351                         "call *%[entry]\n\t"
8352                         :
8353 #ifdef CONFIG_X86_64
8354                         [sp]"=&r"(tmp)
8355 #endif
8356                         :
8357                         [entry]"r"(entry),
8358                         [ss]"i"(__KERNEL_DS),
8359                         [cs]"i"(__KERNEL_CS)
8360                         );
8361         } else
8362                 local_irq_enable();
8363 }
8364
8365 static bool vmx_has_high_real_mode_segbase(void)
8366 {
8367         return enable_unrestricted_guest || emulate_invalid_guest_state;
8368 }
8369
8370 static bool vmx_mpx_supported(void)
8371 {
8372         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8373                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8374 }
8375
8376 static bool vmx_xsaves_supported(void)
8377 {
8378         return vmcs_config.cpu_based_2nd_exec_ctrl &
8379                 SECONDARY_EXEC_XSAVES;
8380 }
8381
8382 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8383 {
8384         u32 exit_intr_info;
8385         bool unblock_nmi;
8386         u8 vector;
8387         bool idtv_info_valid;
8388
8389         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8390
8391         if (cpu_has_virtual_nmis()) {
8392                 if (vmx->nmi_known_unmasked)
8393                         return;
8394                 /*
8395                  * Can't use vmx->exit_intr_info since we're not sure what
8396                  * the exit reason is.
8397                  */
8398                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8399                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8400                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8401                 /*
8402                  * SDM 3: 27.7.1.2 (September 2008)
8403                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8404                  * a guest IRET fault.
8405                  * SDM 3: 23.2.2 (September 2008)
8406                  * Bit 12 is undefined in any of the following cases:
8407                  *  If the VM exit sets the valid bit in the IDT-vectoring
8408                  *   information field.
8409                  *  If the VM exit is due to a double fault.
8410                  */
8411                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8412                     vector != DF_VECTOR && !idtv_info_valid)
8413                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8414                                       GUEST_INTR_STATE_NMI);
8415                 else
8416                         vmx->nmi_known_unmasked =
8417                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8418                                   & GUEST_INTR_STATE_NMI);
8419         } else if (unlikely(vmx->soft_vnmi_blocked))
8420                 vmx->vnmi_blocked_time +=
8421                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8422 }
8423
8424 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8425                                       u32 idt_vectoring_info,
8426                                       int instr_len_field,
8427                                       int error_code_field)
8428 {
8429         u8 vector;
8430         int type;
8431         bool idtv_info_valid;
8432
8433         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8434
8435         vcpu->arch.nmi_injected = false;
8436         kvm_clear_exception_queue(vcpu);
8437         kvm_clear_interrupt_queue(vcpu);
8438
8439         if (!idtv_info_valid)
8440                 return;
8441
8442         kvm_make_request(KVM_REQ_EVENT, vcpu);
8443
8444         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8445         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8446
8447         switch (type) {
8448         case INTR_TYPE_NMI_INTR:
8449                 vcpu->arch.nmi_injected = true;
8450                 /*
8451                  * SDM 3: 27.7.1.2 (September 2008)
8452                  * Clear bit "block by NMI" before VM entry if a NMI
8453                  * delivery faulted.
8454                  */
8455                 vmx_set_nmi_mask(vcpu, false);
8456                 break;
8457         case INTR_TYPE_SOFT_EXCEPTION:
8458                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8459                 /* fall through */
8460         case INTR_TYPE_HARD_EXCEPTION:
8461                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8462                         u32 err = vmcs_read32(error_code_field);
8463                         kvm_requeue_exception_e(vcpu, vector, err);
8464                 } else
8465                         kvm_requeue_exception(vcpu, vector);
8466                 break;
8467         case INTR_TYPE_SOFT_INTR:
8468                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8469                 /* fall through */
8470         case INTR_TYPE_EXT_INTR:
8471                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8472                 break;
8473         default:
8474                 break;
8475         }
8476 }
8477
8478 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8479 {
8480         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8481                                   VM_EXIT_INSTRUCTION_LEN,
8482                                   IDT_VECTORING_ERROR_CODE);
8483 }
8484
8485 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8486 {
8487         __vmx_complete_interrupts(vcpu,
8488                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8489                                   VM_ENTRY_INSTRUCTION_LEN,
8490                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8491
8492         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8493 }
8494
8495 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8496 {
8497         int i, nr_msrs;
8498         struct perf_guest_switch_msr *msrs;
8499
8500         msrs = perf_guest_get_msrs(&nr_msrs);
8501
8502         if (!msrs)
8503                 return;
8504
8505         for (i = 0; i < nr_msrs; i++)
8506                 if (msrs[i].host == msrs[i].guest)
8507                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8508                 else
8509                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8510                                         msrs[i].host);
8511 }
8512
8513 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8514 {
8515         struct vcpu_vmx *vmx = to_vmx(vcpu);
8516         unsigned long debugctlmsr, cr4;
8517
8518         /* Record the guest's net vcpu time for enforced NMI injections. */
8519         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8520                 vmx->entry_time = ktime_get();
8521
8522         /* Don't enter VMX if guest state is invalid, let the exit handler
8523            start emulation until we arrive back to a valid state */
8524         if (vmx->emulation_required)
8525                 return;
8526
8527         if (vmx->ple_window_dirty) {
8528                 vmx->ple_window_dirty = false;
8529                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8530         }
8531
8532         if (vmx->nested.sync_shadow_vmcs) {
8533                 copy_vmcs12_to_shadow(vmx);
8534                 vmx->nested.sync_shadow_vmcs = false;
8535         }
8536
8537         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8538                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8539         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8540                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8541
8542         cr4 = cr4_read_shadow();
8543         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8544                 vmcs_writel(HOST_CR4, cr4);
8545                 vmx->host_state.vmcs_host_cr4 = cr4;
8546         }
8547
8548         /* When single-stepping over STI and MOV SS, we must clear the
8549          * corresponding interruptibility bits in the guest state. Otherwise
8550          * vmentry fails as it then expects bit 14 (BS) in pending debug
8551          * exceptions being set, but that's not correct for the guest debugging
8552          * case. */
8553         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8554                 vmx_set_interrupt_shadow(vcpu, 0);
8555
8556         atomic_switch_perf_msrs(vmx);
8557         debugctlmsr = get_debugctlmsr();
8558
8559         vmx->__launched = vmx->loaded_vmcs->launched;
8560         asm(
8561                 /* Store host registers */
8562                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8563                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8564                 "push %%" _ASM_CX " \n\t"
8565                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8566                 "je 1f \n\t"
8567                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8568                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8569                 "1: \n\t"
8570                 /* Reload cr2 if changed */
8571                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8572                 "mov %%cr2, %%" _ASM_DX " \n\t"
8573                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8574                 "je 2f \n\t"
8575                 "mov %%" _ASM_AX", %%cr2 \n\t"
8576                 "2: \n\t"
8577                 /* Check if vmlaunch of vmresume is needed */
8578                 "cmpl $0, %c[launched](%0) \n\t"
8579                 /* Load guest registers.  Don't clobber flags. */
8580                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8581                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8582                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8583                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8584                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8585                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8586 #ifdef CONFIG_X86_64
8587                 "mov %c[r8](%0),  %%r8  \n\t"
8588                 "mov %c[r9](%0),  %%r9  \n\t"
8589                 "mov %c[r10](%0), %%r10 \n\t"
8590                 "mov %c[r11](%0), %%r11 \n\t"
8591                 "mov %c[r12](%0), %%r12 \n\t"
8592                 "mov %c[r13](%0), %%r13 \n\t"
8593                 "mov %c[r14](%0), %%r14 \n\t"
8594                 "mov %c[r15](%0), %%r15 \n\t"
8595 #endif
8596                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8597
8598                 /* Enter guest mode */
8599                 "jne 1f \n\t"
8600                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8601                 "jmp 2f \n\t"
8602                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8603                 "2: "
8604                 /* Save guest registers, load host registers, keep flags */
8605                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8606                 "pop %0 \n\t"
8607                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8608                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8609                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8610                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8611                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8612                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8613                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8614 #ifdef CONFIG_X86_64
8615                 "mov %%r8,  %c[r8](%0) \n\t"
8616                 "mov %%r9,  %c[r9](%0) \n\t"
8617                 "mov %%r10, %c[r10](%0) \n\t"
8618                 "mov %%r11, %c[r11](%0) \n\t"
8619                 "mov %%r12, %c[r12](%0) \n\t"
8620                 "mov %%r13, %c[r13](%0) \n\t"
8621                 "mov %%r14, %c[r14](%0) \n\t"
8622                 "mov %%r15, %c[r15](%0) \n\t"
8623 #endif
8624                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8625                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8626
8627                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8628                 "setbe %c[fail](%0) \n\t"
8629                 ".pushsection .rodata \n\t"
8630                 ".global vmx_return \n\t"
8631                 "vmx_return: " _ASM_PTR " 2b \n\t"
8632                 ".popsection"
8633               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8634                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8635                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8636                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8637                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8638                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8639                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8640                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8641                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8642                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8643                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8644 #ifdef CONFIG_X86_64
8645                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8646                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8647                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8648                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8649                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8650                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8651                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8652                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8653 #endif
8654                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8655                 [wordsize]"i"(sizeof(ulong))
8656               : "cc", "memory"
8657 #ifdef CONFIG_X86_64
8658                 , "rax", "rbx", "rdi", "rsi"
8659                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8660 #else
8661                 , "eax", "ebx", "edi", "esi"
8662 #endif
8663               );
8664
8665         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8666         if (debugctlmsr)
8667                 update_debugctlmsr(debugctlmsr);
8668
8669 #ifndef CONFIG_X86_64
8670         /*
8671          * The sysexit path does not restore ds/es, so we must set them to
8672          * a reasonable value ourselves.
8673          *
8674          * We can't defer this to vmx_load_host_state() since that function
8675          * may be executed in interrupt context, which saves and restore segments
8676          * around it, nullifying its effect.
8677          */
8678         loadsegment(ds, __USER_DS);
8679         loadsegment(es, __USER_DS);
8680 #endif
8681
8682         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8683                                   | (1 << VCPU_EXREG_RFLAGS)
8684                                   | (1 << VCPU_EXREG_PDPTR)
8685                                   | (1 << VCPU_EXREG_SEGMENTS)
8686                                   | (1 << VCPU_EXREG_CR3));
8687         vcpu->arch.regs_dirty = 0;
8688
8689         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8690
8691         vmx->loaded_vmcs->launched = 1;
8692
8693         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8694
8695         /*
8696          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8697          * we did not inject a still-pending event to L1 now because of
8698          * nested_run_pending, we need to re-enable this bit.
8699          */
8700         if (vmx->nested.nested_run_pending)
8701                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8702
8703         vmx->nested.nested_run_pending = 0;
8704
8705         vmx_complete_atomic_exit(vmx);
8706         vmx_recover_nmi_blocking(vmx);
8707         vmx_complete_interrupts(vmx);
8708 }
8709
8710 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8711 {
8712         struct vcpu_vmx *vmx = to_vmx(vcpu);
8713         int cpu;
8714
8715         if (vmx->loaded_vmcs == &vmx->vmcs01)
8716                 return;
8717
8718         cpu = get_cpu();
8719         vmx->loaded_vmcs = &vmx->vmcs01;
8720         vmx_vcpu_put(vcpu);
8721         vmx_vcpu_load(vcpu, cpu);
8722         vcpu->cpu = cpu;
8723         put_cpu();
8724 }
8725
8726 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8727 {
8728         struct vcpu_vmx *vmx = to_vmx(vcpu);
8729
8730         if (enable_pml)
8731                 vmx_destroy_pml_buffer(vmx);
8732         free_vpid(vmx->vpid);
8733         leave_guest_mode(vcpu);
8734         vmx_load_vmcs01(vcpu);
8735         free_nested(vmx);
8736         free_loaded_vmcs(vmx->loaded_vmcs);
8737         kfree(vmx->guest_msrs);
8738         kvm_vcpu_uninit(vcpu);
8739         kmem_cache_free(kvm_vcpu_cache, vmx);
8740 }
8741
8742 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8743 {
8744         int err;
8745         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8746         int cpu;
8747
8748         if (!vmx)
8749                 return ERR_PTR(-ENOMEM);
8750
8751         vmx->vpid = allocate_vpid();
8752
8753         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8754         if (err)
8755                 goto free_vcpu;
8756
8757         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8758         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8759                      > PAGE_SIZE);
8760
8761         err = -ENOMEM;
8762         if (!vmx->guest_msrs) {
8763                 goto uninit_vcpu;
8764         }
8765
8766         vmx->loaded_vmcs = &vmx->vmcs01;
8767         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8768         if (!vmx->loaded_vmcs->vmcs)
8769                 goto free_msrs;
8770         if (!vmm_exclusive)
8771                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8772         loaded_vmcs_init(vmx->loaded_vmcs);
8773         if (!vmm_exclusive)
8774                 kvm_cpu_vmxoff();
8775
8776         cpu = get_cpu();
8777         vmx_vcpu_load(&vmx->vcpu, cpu);
8778         vmx->vcpu.cpu = cpu;
8779         err = vmx_vcpu_setup(vmx);
8780         vmx_vcpu_put(&vmx->vcpu);
8781         put_cpu();
8782         if (err)
8783                 goto free_vmcs;
8784         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8785                 err = alloc_apic_access_page(kvm);
8786                 if (err)
8787                         goto free_vmcs;
8788         }
8789
8790         if (enable_ept) {
8791                 if (!kvm->arch.ept_identity_map_addr)
8792                         kvm->arch.ept_identity_map_addr =
8793                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8794                 err = init_rmode_identity_map(kvm);
8795                 if (err)
8796                         goto free_vmcs;
8797         }
8798
8799         if (nested) {
8800                 nested_vmx_setup_ctls_msrs(vmx);
8801                 vmx->nested.vpid02 = allocate_vpid();
8802         }
8803
8804         vmx->nested.posted_intr_nv = -1;
8805         vmx->nested.current_vmptr = -1ull;
8806         vmx->nested.current_vmcs12 = NULL;
8807
8808         /*
8809          * If PML is turned on, failure on enabling PML just results in failure
8810          * of creating the vcpu, therefore we can simplify PML logic (by
8811          * avoiding dealing with cases, such as enabling PML partially on vcpus
8812          * for the guest, etc.
8813          */
8814         if (enable_pml) {
8815                 err = vmx_create_pml_buffer(vmx);
8816                 if (err)
8817                         goto free_vmcs;
8818         }
8819
8820         return &vmx->vcpu;
8821
8822 free_vmcs:
8823         free_vpid(vmx->nested.vpid02);
8824         free_loaded_vmcs(vmx->loaded_vmcs);
8825 free_msrs:
8826         kfree(vmx->guest_msrs);
8827 uninit_vcpu:
8828         kvm_vcpu_uninit(&vmx->vcpu);
8829 free_vcpu:
8830         free_vpid(vmx->vpid);
8831         kmem_cache_free(kvm_vcpu_cache, vmx);
8832         return ERR_PTR(err);
8833 }
8834
8835 static void __init vmx_check_processor_compat(void *rtn)
8836 {
8837         struct vmcs_config vmcs_conf;
8838
8839         *(int *)rtn = 0;
8840         if (setup_vmcs_config(&vmcs_conf) < 0)
8841                 *(int *)rtn = -EIO;
8842         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8843                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8844                                 smp_processor_id());
8845                 *(int *)rtn = -EIO;
8846         }
8847 }
8848
8849 static int get_ept_level(void)
8850 {
8851         return VMX_EPT_DEFAULT_GAW + 1;
8852 }
8853
8854 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8855 {
8856         u8 cache;
8857         u64 ipat = 0;
8858
8859         /* For VT-d and EPT combination
8860          * 1. MMIO: always map as UC
8861          * 2. EPT with VT-d:
8862          *   a. VT-d without snooping control feature: can't guarantee the
8863          *      result, try to trust guest.
8864          *   b. VT-d with snooping control feature: snooping control feature of
8865          *      VT-d engine can guarantee the cache correctness. Just set it
8866          *      to WB to keep consistent with host. So the same as item 3.
8867          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8868          *    consistent with host MTRR
8869          */
8870         if (is_mmio) {
8871                 cache = MTRR_TYPE_UNCACHABLE;
8872                 goto exit;
8873         }
8874
8875         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8876                 ipat = VMX_EPT_IPAT_BIT;
8877                 cache = MTRR_TYPE_WRBACK;
8878                 goto exit;
8879         }
8880
8881         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8882                 ipat = VMX_EPT_IPAT_BIT;
8883                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8884                         cache = MTRR_TYPE_WRBACK;
8885                 else
8886                         cache = MTRR_TYPE_UNCACHABLE;
8887                 goto exit;
8888         }
8889
8890         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8891
8892 exit:
8893         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8894 }
8895
8896 static int vmx_get_lpage_level(void)
8897 {
8898         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8899                 return PT_DIRECTORY_LEVEL;
8900         else
8901                 /* For shadow and EPT supported 1GB page */
8902                 return PT_PDPE_LEVEL;
8903 }
8904
8905 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8906 {
8907         /*
8908          * These bits in the secondary execution controls field
8909          * are dynamic, the others are mostly based on the hypervisor
8910          * architecture and the guest's CPUID.  Do not touch the
8911          * dynamic bits.
8912          */
8913         u32 mask =
8914                 SECONDARY_EXEC_SHADOW_VMCS |
8915                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8916                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8917
8918         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8919
8920         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8921                      (new_ctl & ~mask) | (cur_ctl & mask));
8922 }
8923
8924 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8925 {
8926         struct kvm_cpuid_entry2 *best;
8927         struct vcpu_vmx *vmx = to_vmx(vcpu);
8928         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8929
8930         if (vmx_rdtscp_supported()) {
8931                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8932                 if (!rdtscp_enabled)
8933                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8934
8935                 if (nested) {
8936                         if (rdtscp_enabled)
8937                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8938                                         SECONDARY_EXEC_RDTSCP;
8939                         else
8940                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8941                                         ~SECONDARY_EXEC_RDTSCP;
8942                 }
8943         }
8944
8945         /* Exposing INVPCID only when PCID is exposed */
8946         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8947         if (vmx_invpcid_supported() &&
8948             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8949             !guest_cpuid_has_pcid(vcpu))) {
8950                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8951
8952                 if (best)
8953                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8954         }
8955
8956         if (cpu_has_secondary_exec_ctrls())
8957                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8958
8959         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8960                 if (guest_cpuid_has_pcommit(vcpu))
8961                         vmx->nested.nested_vmx_secondary_ctls_high |=
8962                                 SECONDARY_EXEC_PCOMMIT;
8963                 else
8964                         vmx->nested.nested_vmx_secondary_ctls_high &=
8965                                 ~SECONDARY_EXEC_PCOMMIT;
8966         }
8967 }
8968
8969 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8970 {
8971         if (func == 1 && nested)
8972                 entry->ecx |= bit(X86_FEATURE_VMX);
8973 }
8974
8975 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8976                 struct x86_exception *fault)
8977 {
8978         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8979         u32 exit_reason;
8980
8981         if (fault->error_code & PFERR_RSVD_MASK)
8982                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8983         else
8984                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8985         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8986         vmcs12->guest_physical_address = fault->address;
8987 }
8988
8989 /* Callbacks for nested_ept_init_mmu_context: */
8990
8991 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8992 {
8993         /* return the page table to be shadowed - in our case, EPT12 */
8994         return get_vmcs12(vcpu)->ept_pointer;
8995 }
8996
8997 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8998 {
8999         WARN_ON(mmu_is_nested(vcpu));
9000         kvm_init_shadow_ept_mmu(vcpu,
9001                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9002                         VMX_EPT_EXECUTE_ONLY_BIT);
9003         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9004         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9005         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9006
9007         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9008 }
9009
9010 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9011 {
9012         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9013 }
9014
9015 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9016                                             u16 error_code)
9017 {
9018         bool inequality, bit;
9019
9020         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9021         inequality =
9022                 (error_code & vmcs12->page_fault_error_code_mask) !=
9023                  vmcs12->page_fault_error_code_match;
9024         return inequality ^ bit;
9025 }
9026
9027 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9028                 struct x86_exception *fault)
9029 {
9030         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9031
9032         WARN_ON(!is_guest_mode(vcpu));
9033
9034         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9035                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9036                                   vmcs_read32(VM_EXIT_INTR_INFO),
9037                                   vmcs_readl(EXIT_QUALIFICATION));
9038         else
9039                 kvm_inject_page_fault(vcpu, fault);
9040 }
9041
9042 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9043                                         struct vmcs12 *vmcs12)
9044 {
9045         struct vcpu_vmx *vmx = to_vmx(vcpu);
9046         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9047
9048         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9049                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9050                     vmcs12->apic_access_addr >> maxphyaddr)
9051                         return false;
9052
9053                 /*
9054                  * Translate L1 physical address to host physical
9055                  * address for vmcs02. Keep the page pinned, so this
9056                  * physical address remains valid. We keep a reference
9057                  * to it so we can release it later.
9058                  */
9059                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9060                         nested_release_page(vmx->nested.apic_access_page);
9061                 vmx->nested.apic_access_page =
9062                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9063         }
9064
9065         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9066                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9067                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9068                         return false;
9069
9070                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9071                         nested_release_page(vmx->nested.virtual_apic_page);
9072                 vmx->nested.virtual_apic_page =
9073                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9074
9075                 /*
9076                  * Failing the vm entry is _not_ what the processor does
9077                  * but it's basically the only possibility we have.
9078                  * We could still enter the guest if CR8 load exits are
9079                  * enabled, CR8 store exits are enabled, and virtualize APIC
9080                  * access is disabled; in this case the processor would never
9081                  * use the TPR shadow and we could simply clear the bit from
9082                  * the execution control.  But such a configuration is useless,
9083                  * so let's keep the code simple.
9084                  */
9085                 if (!vmx->nested.virtual_apic_page)
9086                         return false;
9087         }
9088
9089         if (nested_cpu_has_posted_intr(vmcs12)) {
9090                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9091                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9092                         return false;
9093
9094                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9095                         kunmap(vmx->nested.pi_desc_page);
9096                         nested_release_page(vmx->nested.pi_desc_page);
9097                 }
9098                 vmx->nested.pi_desc_page =
9099                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9100                 if (!vmx->nested.pi_desc_page)
9101                         return false;
9102
9103                 vmx->nested.pi_desc =
9104                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9105                 if (!vmx->nested.pi_desc) {
9106                         nested_release_page_clean(vmx->nested.pi_desc_page);
9107                         return false;
9108                 }
9109                 vmx->nested.pi_desc =
9110                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9111                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9112                         (PAGE_SIZE - 1)));
9113         }
9114
9115         return true;
9116 }
9117
9118 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9119 {
9120         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9121         struct vcpu_vmx *vmx = to_vmx(vcpu);
9122
9123         if (vcpu->arch.virtual_tsc_khz == 0)
9124                 return;
9125
9126         /* Make sure short timeouts reliably trigger an immediate vmexit.
9127          * hrtimer_start does not guarantee this. */
9128         if (preemption_timeout <= 1) {
9129                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9130                 return;
9131         }
9132
9133         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9134         preemption_timeout *= 1000000;
9135         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9136         hrtimer_start(&vmx->nested.preemption_timer,
9137                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9138 }
9139
9140 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9141                                                 struct vmcs12 *vmcs12)
9142 {
9143         int maxphyaddr;
9144         u64 addr;
9145
9146         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9147                 return 0;
9148
9149         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9150                 WARN_ON(1);
9151                 return -EINVAL;
9152         }
9153         maxphyaddr = cpuid_maxphyaddr(vcpu);
9154
9155         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9156            ((addr + PAGE_SIZE) >> maxphyaddr))
9157                 return -EINVAL;
9158
9159         return 0;
9160 }
9161
9162 /*
9163  * Merge L0's and L1's MSR bitmap, return false to indicate that
9164  * we do not use the hardware.
9165  */
9166 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9167                                                struct vmcs12 *vmcs12)
9168 {
9169         int msr;
9170         struct page *page;
9171         unsigned long *msr_bitmap;
9172
9173         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9174                 return false;
9175
9176         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9177         if (!page) {
9178                 WARN_ON(1);
9179                 return false;
9180         }
9181         msr_bitmap = (unsigned long *)kmap(page);
9182         if (!msr_bitmap) {
9183                 nested_release_page_clean(page);
9184                 WARN_ON(1);
9185                 return false;
9186         }
9187
9188         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9189                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9190                         for (msr = 0x800; msr <= 0x8ff; msr++)
9191                                 nested_vmx_disable_intercept_for_msr(
9192                                         msr_bitmap,
9193                                         vmx_msr_bitmap_nested,
9194                                         msr, MSR_TYPE_R);
9195                 /* TPR is allowed */
9196                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9197                                 vmx_msr_bitmap_nested,
9198                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9199                                 MSR_TYPE_R | MSR_TYPE_W);
9200                 if (nested_cpu_has_vid(vmcs12)) {
9201                         /* EOI and self-IPI are allowed */
9202                         nested_vmx_disable_intercept_for_msr(
9203                                 msr_bitmap,
9204                                 vmx_msr_bitmap_nested,
9205                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9206                                 MSR_TYPE_W);
9207                         nested_vmx_disable_intercept_for_msr(
9208                                 msr_bitmap,
9209                                 vmx_msr_bitmap_nested,
9210                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9211                                 MSR_TYPE_W);
9212                 }
9213         } else {
9214                 /*
9215                  * Enable reading intercept of all the x2apic
9216                  * MSRs. We should not rely on vmcs12 to do any
9217                  * optimizations here, it may have been modified
9218                  * by L1.
9219                  */
9220                 for (msr = 0x800; msr <= 0x8ff; msr++)
9221                         __vmx_enable_intercept_for_msr(
9222                                 vmx_msr_bitmap_nested,
9223                                 msr,
9224                                 MSR_TYPE_R);
9225
9226                 __vmx_enable_intercept_for_msr(
9227                                 vmx_msr_bitmap_nested,
9228                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9229                                 MSR_TYPE_W);
9230                 __vmx_enable_intercept_for_msr(
9231                                 vmx_msr_bitmap_nested,
9232                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9233                                 MSR_TYPE_W);
9234                 __vmx_enable_intercept_for_msr(
9235                                 vmx_msr_bitmap_nested,
9236                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9237                                 MSR_TYPE_W);
9238         }
9239         kunmap(page);
9240         nested_release_page_clean(page);
9241
9242         return true;
9243 }
9244
9245 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9246                                            struct vmcs12 *vmcs12)
9247 {
9248         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9249             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9250             !nested_cpu_has_vid(vmcs12) &&
9251             !nested_cpu_has_posted_intr(vmcs12))
9252                 return 0;
9253
9254         /*
9255          * If virtualize x2apic mode is enabled,
9256          * virtualize apic access must be disabled.
9257          */
9258         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9259             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9260                 return -EINVAL;
9261
9262         /*
9263          * If virtual interrupt delivery is enabled,
9264          * we must exit on external interrupts.
9265          */
9266         if (nested_cpu_has_vid(vmcs12) &&
9267            !nested_exit_on_intr(vcpu))
9268                 return -EINVAL;
9269
9270         /*
9271          * bits 15:8 should be zero in posted_intr_nv,
9272          * the descriptor address has been already checked
9273          * in nested_get_vmcs12_pages.
9274          */
9275         if (nested_cpu_has_posted_intr(vmcs12) &&
9276            (!nested_cpu_has_vid(vmcs12) ||
9277             !nested_exit_intr_ack_set(vcpu) ||
9278             vmcs12->posted_intr_nv & 0xff00))
9279                 return -EINVAL;
9280
9281         /* tpr shadow is needed by all apicv features. */
9282         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9283                 return -EINVAL;
9284
9285         return 0;
9286 }
9287
9288 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9289                                        unsigned long count_field,
9290                                        unsigned long addr_field)
9291 {
9292         int maxphyaddr;
9293         u64 count, addr;
9294
9295         if (vmcs12_read_any(vcpu, count_field, &count) ||
9296             vmcs12_read_any(vcpu, addr_field, &addr)) {
9297                 WARN_ON(1);
9298                 return -EINVAL;
9299         }
9300         if (count == 0)
9301                 return 0;
9302         maxphyaddr = cpuid_maxphyaddr(vcpu);
9303         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9304             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9305                 pr_warn_ratelimited(
9306                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9307                         addr_field, maxphyaddr, count, addr);
9308                 return -EINVAL;
9309         }
9310         return 0;
9311 }
9312
9313 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9314                                                 struct vmcs12 *vmcs12)
9315 {
9316         if (vmcs12->vm_exit_msr_load_count == 0 &&
9317             vmcs12->vm_exit_msr_store_count == 0 &&
9318             vmcs12->vm_entry_msr_load_count == 0)
9319                 return 0; /* Fast path */
9320         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9321                                         VM_EXIT_MSR_LOAD_ADDR) ||
9322             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9323                                         VM_EXIT_MSR_STORE_ADDR) ||
9324             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9325                                         VM_ENTRY_MSR_LOAD_ADDR))
9326                 return -EINVAL;
9327         return 0;
9328 }
9329
9330 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9331                                        struct vmx_msr_entry *e)
9332 {
9333         /* x2APIC MSR accesses are not allowed */
9334         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9335                 return -EINVAL;
9336         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9337             e->index == MSR_IA32_UCODE_REV)
9338                 return -EINVAL;
9339         if (e->reserved != 0)
9340                 return -EINVAL;
9341         return 0;
9342 }
9343
9344 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9345                                      struct vmx_msr_entry *e)
9346 {
9347         if (e->index == MSR_FS_BASE ||
9348             e->index == MSR_GS_BASE ||
9349             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9350             nested_vmx_msr_check_common(vcpu, e))
9351                 return -EINVAL;
9352         return 0;
9353 }
9354
9355 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9356                                       struct vmx_msr_entry *e)
9357 {
9358         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9359             nested_vmx_msr_check_common(vcpu, e))
9360                 return -EINVAL;
9361         return 0;
9362 }
9363
9364 /*
9365  * Load guest's/host's msr at nested entry/exit.
9366  * return 0 for success, entry index for failure.
9367  */
9368 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9369 {
9370         u32 i;
9371         struct vmx_msr_entry e;
9372         struct msr_data msr;
9373
9374         msr.host_initiated = false;
9375         for (i = 0; i < count; i++) {
9376                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9377                                         &e, sizeof(e))) {
9378                         pr_warn_ratelimited(
9379                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9380                                 __func__, i, gpa + i * sizeof(e));
9381                         goto fail;
9382                 }
9383                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9384                         pr_warn_ratelimited(
9385                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9386                                 __func__, i, e.index, e.reserved);
9387                         goto fail;
9388                 }
9389                 msr.index = e.index;
9390                 msr.data = e.value;
9391                 if (kvm_set_msr(vcpu, &msr)) {
9392                         pr_warn_ratelimited(
9393                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9394                                 __func__, i, e.index, e.value);
9395                         goto fail;
9396                 }
9397         }
9398         return 0;
9399 fail:
9400         return i + 1;
9401 }
9402
9403 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9404 {
9405         u32 i;
9406         struct vmx_msr_entry e;
9407
9408         for (i = 0; i < count; i++) {
9409                 struct msr_data msr_info;
9410                 if (kvm_vcpu_read_guest(vcpu,
9411                                         gpa + i * sizeof(e),
9412                                         &e, 2 * sizeof(u32))) {
9413                         pr_warn_ratelimited(
9414                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9415                                 __func__, i, gpa + i * sizeof(e));
9416                         return -EINVAL;
9417                 }
9418                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9419                         pr_warn_ratelimited(
9420                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9421                                 __func__, i, e.index, e.reserved);
9422                         return -EINVAL;
9423                 }
9424                 msr_info.host_initiated = false;
9425                 msr_info.index = e.index;
9426                 if (kvm_get_msr(vcpu, &msr_info)) {
9427                         pr_warn_ratelimited(
9428                                 "%s cannot read MSR (%u, 0x%x)\n",
9429                                 __func__, i, e.index);
9430                         return -EINVAL;
9431                 }
9432                 if (kvm_vcpu_write_guest(vcpu,
9433                                          gpa + i * sizeof(e) +
9434                                              offsetof(struct vmx_msr_entry, value),
9435                                          &msr_info.data, sizeof(msr_info.data))) {
9436                         pr_warn_ratelimited(
9437                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9438                                 __func__, i, e.index, msr_info.data);
9439                         return -EINVAL;
9440                 }
9441         }
9442         return 0;
9443 }
9444
9445 /*
9446  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9447  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9448  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9449  * guest in a way that will both be appropriate to L1's requests, and our
9450  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9451  * function also has additional necessary side-effects, like setting various
9452  * vcpu->arch fields.
9453  */
9454 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9455 {
9456         struct vcpu_vmx *vmx = to_vmx(vcpu);
9457         u32 exec_control;
9458
9459         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9460         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9461         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9462         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9463         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9464         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9465         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9466         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9467         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9468         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9469         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9470         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9471         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9472         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9473         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9474         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9475         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9476         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9477         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9478         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9479         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9480         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9481         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9482         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9483         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9484         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9485         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9486         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9487         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9488         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9489         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9490         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9491         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9492         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9493         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9494         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9495
9496         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9497                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9498                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9499         } else {
9500                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9501                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9502         }
9503         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9504                 vmcs12->vm_entry_intr_info_field);
9505         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9506                 vmcs12->vm_entry_exception_error_code);
9507         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9508                 vmcs12->vm_entry_instruction_len);
9509         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9510                 vmcs12->guest_interruptibility_info);
9511         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9512         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9513         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9514                 vmcs12->guest_pending_dbg_exceptions);
9515         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9516         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9517
9518         if (nested_cpu_has_xsaves(vmcs12))
9519                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9520         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9521
9522         exec_control = vmcs12->pin_based_vm_exec_control;
9523         exec_control |= vmcs_config.pin_based_exec_ctrl;
9524         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9525
9526         if (nested_cpu_has_posted_intr(vmcs12)) {
9527                 /*
9528                  * Note that we use L0's vector here and in
9529                  * vmx_deliver_nested_posted_interrupt.
9530                  */
9531                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9532                 vmx->nested.pi_pending = false;
9533                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9534                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9535                         page_to_phys(vmx->nested.pi_desc_page) +
9536                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9537                         (PAGE_SIZE - 1)));
9538         } else
9539                 exec_control &= ~PIN_BASED_POSTED_INTR;
9540
9541         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9542
9543         vmx->nested.preemption_timer_expired = false;
9544         if (nested_cpu_has_preemption_timer(vmcs12))
9545                 vmx_start_preemption_timer(vcpu);
9546
9547         /*
9548          * Whether page-faults are trapped is determined by a combination of
9549          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9550          * If enable_ept, L0 doesn't care about page faults and we should
9551          * set all of these to L1's desires. However, if !enable_ept, L0 does
9552          * care about (at least some) page faults, and because it is not easy
9553          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9554          * to exit on each and every L2 page fault. This is done by setting
9555          * MASK=MATCH=0 and (see below) EB.PF=1.
9556          * Note that below we don't need special code to set EB.PF beyond the
9557          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9558          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9559          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9560          *
9561          * A problem with this approach (when !enable_ept) is that L1 may be
9562          * injected with more page faults than it asked for. This could have
9563          * caused problems, but in practice existing hypervisors don't care.
9564          * To fix this, we will need to emulate the PFEC checking (on the L1
9565          * page tables), using walk_addr(), when injecting PFs to L1.
9566          */
9567         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9568                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9569         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9570                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9571
9572         if (cpu_has_secondary_exec_ctrls()) {
9573                 exec_control = vmx_secondary_exec_control(vmx);
9574
9575                 /* Take the following fields only from vmcs12 */
9576                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9577                                   SECONDARY_EXEC_RDTSCP |
9578                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9579                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9580                                   SECONDARY_EXEC_PCOMMIT);
9581                 if (nested_cpu_has(vmcs12,
9582                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9583                         exec_control |= vmcs12->secondary_vm_exec_control;
9584
9585                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9586                         /*
9587                          * If translation failed, no matter: This feature asks
9588                          * to exit when accessing the given address, and if it
9589                          * can never be accessed, this feature won't do
9590                          * anything anyway.
9591                          */
9592                         if (!vmx->nested.apic_access_page)
9593                                 exec_control &=
9594                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9595                         else
9596                                 vmcs_write64(APIC_ACCESS_ADDR,
9597                                   page_to_phys(vmx->nested.apic_access_page));
9598                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9599                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9600                         exec_control |=
9601                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9602                         kvm_vcpu_reload_apic_access_page(vcpu);
9603                 }
9604
9605                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9606                         vmcs_write64(EOI_EXIT_BITMAP0,
9607                                 vmcs12->eoi_exit_bitmap0);
9608                         vmcs_write64(EOI_EXIT_BITMAP1,
9609                                 vmcs12->eoi_exit_bitmap1);
9610                         vmcs_write64(EOI_EXIT_BITMAP2,
9611                                 vmcs12->eoi_exit_bitmap2);
9612                         vmcs_write64(EOI_EXIT_BITMAP3,
9613                                 vmcs12->eoi_exit_bitmap3);
9614                         vmcs_write16(GUEST_INTR_STATUS,
9615                                 vmcs12->guest_intr_status);
9616                 }
9617
9618                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9619         }
9620
9621
9622         /*
9623          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9624          * Some constant fields are set here by vmx_set_constant_host_state().
9625          * Other fields are different per CPU, and will be set later when
9626          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9627          */
9628         vmx_set_constant_host_state(vmx);
9629
9630         /*
9631          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9632          * entry, but only if the current (host) sp changed from the value
9633          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9634          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9635          * here we just force the write to happen on entry.
9636          */
9637         vmx->host_rsp = 0;
9638
9639         exec_control = vmx_exec_control(vmx); /* L0's desires */
9640         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9641         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9642         exec_control &= ~CPU_BASED_TPR_SHADOW;
9643         exec_control |= vmcs12->cpu_based_vm_exec_control;
9644
9645         if (exec_control & CPU_BASED_TPR_SHADOW) {
9646                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9647                                 page_to_phys(vmx->nested.virtual_apic_page));
9648                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9649         }
9650
9651         if (cpu_has_vmx_msr_bitmap() &&
9652             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9653                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9654                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9655         } else
9656                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9657
9658         /*
9659          * Merging of IO bitmap not currently supported.
9660          * Rather, exit every time.
9661          */
9662         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9663         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9664
9665         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9666
9667         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9668          * bitwise-or of what L1 wants to trap for L2, and what we want to
9669          * trap. Note that CR0.TS also needs updating - we do this later.
9670          */
9671         update_exception_bitmap(vcpu);
9672         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9673         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9674
9675         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9676          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9677          * bits are further modified by vmx_set_efer() below.
9678          */
9679         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9680
9681         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9682          * emulated by vmx_set_efer(), below.
9683          */
9684         vm_entry_controls_init(vmx,
9685                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9686                         ~VM_ENTRY_IA32E_MODE) |
9687                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9688
9689         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9690                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9691                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9692         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9693                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9694
9695
9696         set_cr4_guest_host_mask(vmx);
9697
9698         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9699                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9700
9701         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9702                 vmcs_write64(TSC_OFFSET,
9703                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9704         else
9705                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9706
9707         if (enable_vpid) {
9708                 /*
9709                  * There is no direct mapping between vpid02 and vpid12, the
9710                  * vpid02 is per-vCPU for L0 and reused while the value of
9711                  * vpid12 is changed w/ one invvpid during nested vmentry.
9712                  * The vpid12 is allocated by L1 for L2, so it will not
9713                  * influence global bitmap(for vpid01 and vpid02 allocation)
9714                  * even if spawn a lot of nested vCPUs.
9715                  */
9716                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9717                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9718                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9719                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9720                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9721                         }
9722                 } else {
9723                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9724                         vmx_flush_tlb(vcpu);
9725                 }
9726
9727         }
9728
9729         if (nested_cpu_has_ept(vmcs12)) {
9730                 kvm_mmu_unload(vcpu);
9731                 nested_ept_init_mmu_context(vcpu);
9732         }
9733
9734         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9735                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9736         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9737                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9738         else
9739                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9740         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9741         vmx_set_efer(vcpu, vcpu->arch.efer);
9742
9743         /*
9744          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9745          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9746          * The CR0_READ_SHADOW is what L2 should have expected to read given
9747          * the specifications by L1; It's not enough to take
9748          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9749          * have more bits than L1 expected.
9750          */
9751         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9752         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9753
9754         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9755         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9756
9757         /* shadow page tables on either EPT or shadow page tables */
9758         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9759         kvm_mmu_reset_context(vcpu);
9760
9761         if (!enable_ept)
9762                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9763
9764         /*
9765          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9766          */
9767         if (enable_ept) {
9768                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9769                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9770                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9771                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9772         }
9773
9774         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9775         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9776 }
9777
9778 /*
9779  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9780  * for running an L2 nested guest.
9781  */
9782 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9783 {
9784         struct vmcs12 *vmcs12;
9785         struct vcpu_vmx *vmx = to_vmx(vcpu);
9786         int cpu;
9787         struct loaded_vmcs *vmcs02;
9788         bool ia32e;
9789         u32 msr_entry_idx;
9790
9791         if (!nested_vmx_check_permission(vcpu) ||
9792             !nested_vmx_check_vmcs12(vcpu))
9793                 return 1;
9794
9795         skip_emulated_instruction(vcpu);
9796         vmcs12 = get_vmcs12(vcpu);
9797
9798         if (enable_shadow_vmcs)
9799                 copy_shadow_to_vmcs12(vmx);
9800
9801         /*
9802          * The nested entry process starts with enforcing various prerequisites
9803          * on vmcs12 as required by the Intel SDM, and act appropriately when
9804          * they fail: As the SDM explains, some conditions should cause the
9805          * instruction to fail, while others will cause the instruction to seem
9806          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9807          * To speed up the normal (success) code path, we should avoid checking
9808          * for misconfigurations which will anyway be caught by the processor
9809          * when using the merged vmcs02.
9810          */
9811         if (vmcs12->launch_state == launch) {
9812                 nested_vmx_failValid(vcpu,
9813                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9814                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9815                 return 1;
9816         }
9817
9818         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9819             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9820                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9821                 return 1;
9822         }
9823
9824         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9825                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9826                 return 1;
9827         }
9828
9829         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9830                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9831                 return 1;
9832         }
9833
9834         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9835                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9836                 return 1;
9837         }
9838
9839         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9840                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9841                 return 1;
9842         }
9843
9844         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9845                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9846                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9847             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9848                                 vmx->nested.nested_vmx_secondary_ctls_low,
9849                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9850             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9851                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9852                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9853             !vmx_control_verify(vmcs12->vm_exit_controls,
9854                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9855                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9856             !vmx_control_verify(vmcs12->vm_entry_controls,
9857                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9858                                 vmx->nested.nested_vmx_entry_ctls_high))
9859         {
9860                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9861                 return 1;
9862         }
9863
9864         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9865             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9866                 nested_vmx_failValid(vcpu,
9867                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9868                 return 1;
9869         }
9870
9871         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9872             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9873                 nested_vmx_entry_failure(vcpu, vmcs12,
9874                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9875                 return 1;
9876         }
9877         if (vmcs12->vmcs_link_pointer != -1ull) {
9878                 nested_vmx_entry_failure(vcpu, vmcs12,
9879                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9880                 return 1;
9881         }
9882
9883         /*
9884          * If the load IA32_EFER VM-entry control is 1, the following checks
9885          * are performed on the field for the IA32_EFER MSR:
9886          * - Bits reserved in the IA32_EFER MSR must be 0.
9887          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9888          *   the IA-32e mode guest VM-exit control. It must also be identical
9889          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9890          *   CR0.PG) is 1.
9891          */
9892         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9893                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9894                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9895                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9896                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9897                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9898                         nested_vmx_entry_failure(vcpu, vmcs12,
9899                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9900                         return 1;
9901                 }
9902         }
9903
9904         /*
9905          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9906          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9907          * the values of the LMA and LME bits in the field must each be that of
9908          * the host address-space size VM-exit control.
9909          */
9910         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9911                 ia32e = (vmcs12->vm_exit_controls &
9912                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9913                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9914                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9915                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9916                         nested_vmx_entry_failure(vcpu, vmcs12,
9917                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9918                         return 1;
9919                 }
9920         }
9921
9922         /*
9923          * We're finally done with prerequisite checking, and can start with
9924          * the nested entry.
9925          */
9926
9927         vmcs02 = nested_get_current_vmcs02(vmx);
9928         if (!vmcs02)
9929                 return -ENOMEM;
9930
9931         enter_guest_mode(vcpu);
9932
9933         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9934
9935         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9936                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9937
9938         cpu = get_cpu();
9939         vmx->loaded_vmcs = vmcs02;
9940         vmx_vcpu_put(vcpu);
9941         vmx_vcpu_load(vcpu, cpu);
9942         vcpu->cpu = cpu;
9943         put_cpu();
9944
9945         vmx_segment_cache_clear(vmx);
9946
9947         prepare_vmcs02(vcpu, vmcs12);
9948
9949         msr_entry_idx = nested_vmx_load_msr(vcpu,
9950                                             vmcs12->vm_entry_msr_load_addr,
9951                                             vmcs12->vm_entry_msr_load_count);
9952         if (msr_entry_idx) {
9953                 leave_guest_mode(vcpu);
9954                 vmx_load_vmcs01(vcpu);
9955                 nested_vmx_entry_failure(vcpu, vmcs12,
9956                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9957                 return 1;
9958         }
9959
9960         vmcs12->launch_state = 1;
9961
9962         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9963                 return kvm_vcpu_halt(vcpu);
9964
9965         vmx->nested.nested_run_pending = 1;
9966
9967         /*
9968          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9969          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9970          * returned as far as L1 is concerned. It will only return (and set
9971          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9972          */
9973         return 1;
9974 }
9975
9976 /*
9977  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9978  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9979  * This function returns the new value we should put in vmcs12.guest_cr0.
9980  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9981  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9982  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9983  *     didn't trap the bit, because if L1 did, so would L0).
9984  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9985  *     been modified by L2, and L1 knows it. So just leave the old value of
9986  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9987  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9988  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9989  *     changed these bits, and therefore they need to be updated, but L0
9990  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9991  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9992  */
9993 static inline unsigned long
9994 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9995 {
9996         return
9997         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9998         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9999         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10000                         vcpu->arch.cr0_guest_owned_bits));
10001 }
10002
10003 static inline unsigned long
10004 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10005 {
10006         return
10007         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10008         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10009         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10010                         vcpu->arch.cr4_guest_owned_bits));
10011 }
10012
10013 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10014                                        struct vmcs12 *vmcs12)
10015 {
10016         u32 idt_vectoring;
10017         unsigned int nr;
10018
10019         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10020                 nr = vcpu->arch.exception.nr;
10021                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10022
10023                 if (kvm_exception_is_soft(nr)) {
10024                         vmcs12->vm_exit_instruction_len =
10025                                 vcpu->arch.event_exit_inst_len;
10026                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10027                 } else
10028                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10029
10030                 if (vcpu->arch.exception.has_error_code) {
10031                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10032                         vmcs12->idt_vectoring_error_code =
10033                                 vcpu->arch.exception.error_code;
10034                 }
10035
10036                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10037         } else if (vcpu->arch.nmi_injected) {
10038                 vmcs12->idt_vectoring_info_field =
10039                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10040         } else if (vcpu->arch.interrupt.pending) {
10041                 nr = vcpu->arch.interrupt.nr;
10042                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10043
10044                 if (vcpu->arch.interrupt.soft) {
10045                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10046                         vmcs12->vm_entry_instruction_len =
10047                                 vcpu->arch.event_exit_inst_len;
10048                 } else
10049                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10050
10051                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10052         }
10053 }
10054
10055 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10056 {
10057         struct vcpu_vmx *vmx = to_vmx(vcpu);
10058
10059         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10060             vmx->nested.preemption_timer_expired) {
10061                 if (vmx->nested.nested_run_pending)
10062                         return -EBUSY;
10063                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10064                 return 0;
10065         }
10066
10067         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10068                 if (vmx->nested.nested_run_pending ||
10069                     vcpu->arch.interrupt.pending)
10070                         return -EBUSY;
10071                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10072                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10073                                   INTR_INFO_VALID_MASK, 0);
10074                 /*
10075                  * The NMI-triggered VM exit counts as injection:
10076                  * clear this one and block further NMIs.
10077                  */
10078                 vcpu->arch.nmi_pending = 0;
10079                 vmx_set_nmi_mask(vcpu, true);
10080                 return 0;
10081         }
10082
10083         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10084             nested_exit_on_intr(vcpu)) {
10085                 if (vmx->nested.nested_run_pending)
10086                         return -EBUSY;
10087                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10088                 return 0;
10089         }
10090
10091         return vmx_complete_nested_posted_interrupt(vcpu);
10092 }
10093
10094 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10095 {
10096         ktime_t remaining =
10097                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10098         u64 value;
10099
10100         if (ktime_to_ns(remaining) <= 0)
10101                 return 0;
10102
10103         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10104         do_div(value, 1000000);
10105         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10106 }
10107
10108 /*
10109  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10110  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10111  * and this function updates it to reflect the changes to the guest state while
10112  * L2 was running (and perhaps made some exits which were handled directly by L0
10113  * without going back to L1), and to reflect the exit reason.
10114  * Note that we do not have to copy here all VMCS fields, just those that
10115  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10116  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10117  * which already writes to vmcs12 directly.
10118  */
10119 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10120                            u32 exit_reason, u32 exit_intr_info,
10121                            unsigned long exit_qualification)
10122 {
10123         /* update guest state fields: */
10124         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10125         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10126
10127         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10128         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10129         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10130
10131         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10132         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10133         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10134         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10135         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10136         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10137         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10138         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10139         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10140         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10141         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10142         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10143         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10144         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10145         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10146         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10147         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10148         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10149         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10150         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10151         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10152         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10153         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10154         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10155         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10156         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10157         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10158         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10159         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10160         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10161         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10162         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10163         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10164         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10165         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10166         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10167
10168         vmcs12->guest_interruptibility_info =
10169                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10170         vmcs12->guest_pending_dbg_exceptions =
10171                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10172         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10173                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10174         else
10175                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10176
10177         if (nested_cpu_has_preemption_timer(vmcs12)) {
10178                 if (vmcs12->vm_exit_controls &
10179                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10180                         vmcs12->vmx_preemption_timer_value =
10181                                 vmx_get_preemption_timer_value(vcpu);
10182                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10183         }
10184
10185         /*
10186          * In some cases (usually, nested EPT), L2 is allowed to change its
10187          * own CR3 without exiting. If it has changed it, we must keep it.
10188          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10189          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10190          *
10191          * Additionally, restore L2's PDPTR to vmcs12.
10192          */
10193         if (enable_ept) {
10194                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10195                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10196                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10197                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10198                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10199         }
10200
10201         if (nested_cpu_has_vid(vmcs12))
10202                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10203
10204         vmcs12->vm_entry_controls =
10205                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10206                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10207
10208         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10209                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10210                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10211         }
10212
10213         /* TODO: These cannot have changed unless we have MSR bitmaps and
10214          * the relevant bit asks not to trap the change */
10215         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10216                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10217         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10218                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10219         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10220         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10221         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10222         if (vmx_mpx_supported())
10223                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10224         if (nested_cpu_has_xsaves(vmcs12))
10225                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10226
10227         /* update exit information fields: */
10228
10229         vmcs12->vm_exit_reason = exit_reason;
10230         vmcs12->exit_qualification = exit_qualification;
10231
10232         vmcs12->vm_exit_intr_info = exit_intr_info;
10233         if ((vmcs12->vm_exit_intr_info &
10234              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10235             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10236                 vmcs12->vm_exit_intr_error_code =
10237                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10238         vmcs12->idt_vectoring_info_field = 0;
10239         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10240         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10241
10242         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10243                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10244                  * instead of reading the real value. */
10245                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10246
10247                 /*
10248                  * Transfer the event that L0 or L1 may wanted to inject into
10249                  * L2 to IDT_VECTORING_INFO_FIELD.
10250                  */
10251                 vmcs12_save_pending_event(vcpu, vmcs12);
10252         }
10253
10254         /*
10255          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10256          * preserved above and would only end up incorrectly in L1.
10257          */
10258         vcpu->arch.nmi_injected = false;
10259         kvm_clear_exception_queue(vcpu);
10260         kvm_clear_interrupt_queue(vcpu);
10261 }
10262
10263 /*
10264  * A part of what we need to when the nested L2 guest exits and we want to
10265  * run its L1 parent, is to reset L1's guest state to the host state specified
10266  * in vmcs12.
10267  * This function is to be called not only on normal nested exit, but also on
10268  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10269  * Failures During or After Loading Guest State").
10270  * This function should be called when the active VMCS is L1's (vmcs01).
10271  */
10272 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10273                                    struct vmcs12 *vmcs12)
10274 {
10275         struct kvm_segment seg;
10276
10277         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10278                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10279         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10280                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10281         else
10282                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10283         vmx_set_efer(vcpu, vcpu->arch.efer);
10284
10285         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10286         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10287         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10288         /*
10289          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10290          * actually changed, because it depends on the current state of
10291          * fpu_active (which may have changed).
10292          * Note that vmx_set_cr0 refers to efer set above.
10293          */
10294         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10295         /*
10296          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10297          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10298          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10299          */
10300         update_exception_bitmap(vcpu);
10301         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10302         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10303
10304         /*
10305          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10306          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10307          */
10308         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10309         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10310
10311         nested_ept_uninit_mmu_context(vcpu);
10312
10313         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10314         kvm_mmu_reset_context(vcpu);
10315
10316         if (!enable_ept)
10317                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10318
10319         if (enable_vpid) {
10320                 /*
10321                  * Trivially support vpid by letting L2s share their parent
10322                  * L1's vpid. TODO: move to a more elaborate solution, giving
10323                  * each L2 its own vpid and exposing the vpid feature to L1.
10324                  */
10325                 vmx_flush_tlb(vcpu);
10326         }
10327
10328
10329         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10330         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10331         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10332         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10333         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10334
10335         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10336         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10337                 vmcs_write64(GUEST_BNDCFGS, 0);
10338
10339         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10340                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10341                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10342         }
10343         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10344                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10345                         vmcs12->host_ia32_perf_global_ctrl);
10346
10347         /* Set L1 segment info according to Intel SDM
10348             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10349         seg = (struct kvm_segment) {
10350                 .base = 0,
10351                 .limit = 0xFFFFFFFF,
10352                 .selector = vmcs12->host_cs_selector,
10353                 .type = 11,
10354                 .present = 1,
10355                 .s = 1,
10356                 .g = 1
10357         };
10358         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10359                 seg.l = 1;
10360         else
10361                 seg.db = 1;
10362         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10363         seg = (struct kvm_segment) {
10364                 .base = 0,
10365                 .limit = 0xFFFFFFFF,
10366                 .type = 3,
10367                 .present = 1,
10368                 .s = 1,
10369                 .db = 1,
10370                 .g = 1
10371         };
10372         seg.selector = vmcs12->host_ds_selector;
10373         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10374         seg.selector = vmcs12->host_es_selector;
10375         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10376         seg.selector = vmcs12->host_ss_selector;
10377         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10378         seg.selector = vmcs12->host_fs_selector;
10379         seg.base = vmcs12->host_fs_base;
10380         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10381         seg.selector = vmcs12->host_gs_selector;
10382         seg.base = vmcs12->host_gs_base;
10383         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10384         seg = (struct kvm_segment) {
10385                 .base = vmcs12->host_tr_base,
10386                 .limit = 0x67,
10387                 .selector = vmcs12->host_tr_selector,
10388                 .type = 11,
10389                 .present = 1
10390         };
10391         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10392
10393         kvm_set_dr(vcpu, 7, 0x400);
10394         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10395
10396         if (cpu_has_vmx_msr_bitmap())
10397                 vmx_set_msr_bitmap(vcpu);
10398
10399         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10400                                 vmcs12->vm_exit_msr_load_count))
10401                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10402 }
10403
10404 /*
10405  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10406  * and modify vmcs12 to make it see what it would expect to see there if
10407  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10408  */
10409 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10410                               u32 exit_intr_info,
10411                               unsigned long exit_qualification)
10412 {
10413         struct vcpu_vmx *vmx = to_vmx(vcpu);
10414         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10415
10416         /* trying to cancel vmlaunch/vmresume is a bug */
10417         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10418
10419         leave_guest_mode(vcpu);
10420         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10421                        exit_qualification);
10422
10423         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10424                                  vmcs12->vm_exit_msr_store_count))
10425                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10426
10427         vmx_load_vmcs01(vcpu);
10428
10429         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10430             && nested_exit_intr_ack_set(vcpu)) {
10431                 int irq = kvm_cpu_get_interrupt(vcpu);
10432                 WARN_ON(irq < 0);
10433                 vmcs12->vm_exit_intr_info = irq |
10434                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10435         }
10436
10437         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10438                                        vmcs12->exit_qualification,
10439                                        vmcs12->idt_vectoring_info_field,
10440                                        vmcs12->vm_exit_intr_info,
10441                                        vmcs12->vm_exit_intr_error_code,
10442                                        KVM_ISA_VMX);
10443
10444         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10445         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10446         vmx_segment_cache_clear(vmx);
10447
10448         /* if no vmcs02 cache requested, remove the one we used */
10449         if (VMCS02_POOL_SIZE == 0)
10450                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10451
10452         load_vmcs12_host_state(vcpu, vmcs12);
10453
10454         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10455         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10456
10457         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10458         vmx->host_rsp = 0;
10459
10460         /* Unpin physical memory we referred to in vmcs02 */
10461         if (vmx->nested.apic_access_page) {
10462                 nested_release_page(vmx->nested.apic_access_page);
10463                 vmx->nested.apic_access_page = NULL;
10464         }
10465         if (vmx->nested.virtual_apic_page) {
10466                 nested_release_page(vmx->nested.virtual_apic_page);
10467                 vmx->nested.virtual_apic_page = NULL;
10468         }
10469         if (vmx->nested.pi_desc_page) {
10470                 kunmap(vmx->nested.pi_desc_page);
10471                 nested_release_page(vmx->nested.pi_desc_page);
10472                 vmx->nested.pi_desc_page = NULL;
10473                 vmx->nested.pi_desc = NULL;
10474         }
10475
10476         /*
10477          * We are now running in L2, mmu_notifier will force to reload the
10478          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10479          */
10480         kvm_vcpu_reload_apic_access_page(vcpu);
10481
10482         /*
10483          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10484          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10485          * success or failure flag accordingly.
10486          */
10487         if (unlikely(vmx->fail)) {
10488                 vmx->fail = 0;
10489                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10490         } else
10491                 nested_vmx_succeed(vcpu);
10492         if (enable_shadow_vmcs)
10493                 vmx->nested.sync_shadow_vmcs = true;
10494
10495         /* in case we halted in L2 */
10496         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10497 }
10498
10499 /*
10500  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10501  */
10502 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10503 {
10504         if (is_guest_mode(vcpu))
10505                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10506         free_nested(to_vmx(vcpu));
10507 }
10508
10509 /*
10510  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10511  * 23.7 "VM-entry failures during or after loading guest state" (this also
10512  * lists the acceptable exit-reason and exit-qualification parameters).
10513  * It should only be called before L2 actually succeeded to run, and when
10514  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10515  */
10516 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10517                         struct vmcs12 *vmcs12,
10518                         u32 reason, unsigned long qualification)
10519 {
10520         load_vmcs12_host_state(vcpu, vmcs12);
10521         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10522         vmcs12->exit_qualification = qualification;
10523         nested_vmx_succeed(vcpu);
10524         if (enable_shadow_vmcs)
10525                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10526 }
10527
10528 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10529                                struct x86_instruction_info *info,
10530                                enum x86_intercept_stage stage)
10531 {
10532         return X86EMUL_CONTINUE;
10533 }
10534
10535 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10536 {
10537         if (ple_gap)
10538                 shrink_ple_window(vcpu);
10539 }
10540
10541 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10542                                      struct kvm_memory_slot *slot)
10543 {
10544         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10545         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10546 }
10547
10548 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10549                                        struct kvm_memory_slot *slot)
10550 {
10551         kvm_mmu_slot_set_dirty(kvm, slot);
10552 }
10553
10554 static void vmx_flush_log_dirty(struct kvm *kvm)
10555 {
10556         kvm_flush_pml_buffers(kvm);
10557 }
10558
10559 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10560                                            struct kvm_memory_slot *memslot,
10561                                            gfn_t offset, unsigned long mask)
10562 {
10563         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10564 }
10565
10566 /*
10567  * This routine does the following things for vCPU which is going
10568  * to be blocked if VT-d PI is enabled.
10569  * - Store the vCPU to the wakeup list, so when interrupts happen
10570  *   we can find the right vCPU to wake up.
10571  * - Change the Posted-interrupt descriptor as below:
10572  *      'NDST' <-- vcpu->pre_pcpu
10573  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10574  * - If 'ON' is set during this process, which means at least one
10575  *   interrupt is posted for this vCPU, we cannot block it, in
10576  *   this case, return 1, otherwise, return 0.
10577  *
10578  */
10579 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10580 {
10581         unsigned long flags;
10582         unsigned int dest;
10583         struct pi_desc old, new;
10584         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10585
10586         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10587                 !irq_remapping_cap(IRQ_POSTING_CAP))
10588                 return 0;
10589
10590         vcpu->pre_pcpu = vcpu->cpu;
10591         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10592                           vcpu->pre_pcpu), flags);
10593         list_add_tail(&vcpu->blocked_vcpu_list,
10594                       &per_cpu(blocked_vcpu_on_cpu,
10595                       vcpu->pre_pcpu));
10596         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10597                                vcpu->pre_pcpu), flags);
10598
10599         do {
10600                 old.control = new.control = pi_desc->control;
10601
10602                 /*
10603                  * We should not block the vCPU if
10604                  * an interrupt is posted for it.
10605                  */
10606                 if (pi_test_on(pi_desc) == 1) {
10607                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10608                                           vcpu->pre_pcpu), flags);
10609                         list_del(&vcpu->blocked_vcpu_list);
10610                         spin_unlock_irqrestore(
10611                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10612                                         vcpu->pre_pcpu), flags);
10613                         vcpu->pre_pcpu = -1;
10614
10615                         return 1;
10616                 }
10617
10618                 WARN((pi_desc->sn == 1),
10619                      "Warning: SN field of posted-interrupts "
10620                      "is set before blocking\n");
10621
10622                 /*
10623                  * Since vCPU can be preempted during this process,
10624                  * vcpu->cpu could be different with pre_pcpu, we
10625                  * need to set pre_pcpu as the destination of wakeup
10626                  * notification event, then we can find the right vCPU
10627                  * to wakeup in wakeup handler if interrupts happen
10628                  * when the vCPU is in blocked state.
10629                  */
10630                 dest = cpu_physical_id(vcpu->pre_pcpu);
10631
10632                 if (x2apic_enabled())
10633                         new.ndst = dest;
10634                 else
10635                         new.ndst = (dest << 8) & 0xFF00;
10636
10637                 /* set 'NV' to 'wakeup vector' */
10638                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10639         } while (cmpxchg(&pi_desc->control, old.control,
10640                         new.control) != old.control);
10641
10642         return 0;
10643 }
10644
10645 static void vmx_post_block(struct kvm_vcpu *vcpu)
10646 {
10647         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10648         struct pi_desc old, new;
10649         unsigned int dest;
10650         unsigned long flags;
10651
10652         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10653                 !irq_remapping_cap(IRQ_POSTING_CAP))
10654                 return;
10655
10656         do {
10657                 old.control = new.control = pi_desc->control;
10658
10659                 dest = cpu_physical_id(vcpu->cpu);
10660
10661                 if (x2apic_enabled())
10662                         new.ndst = dest;
10663                 else
10664                         new.ndst = (dest << 8) & 0xFF00;
10665
10666                 /* Allow posting non-urgent interrupts */
10667                 new.sn = 0;
10668
10669                 /* set 'NV' to 'notification vector' */
10670                 new.nv = POSTED_INTR_VECTOR;
10671         } while (cmpxchg(&pi_desc->control, old.control,
10672                         new.control) != old.control);
10673
10674         if(vcpu->pre_pcpu != -1) {
10675                 spin_lock_irqsave(
10676                         &per_cpu(blocked_vcpu_on_cpu_lock,
10677                         vcpu->pre_pcpu), flags);
10678                 list_del(&vcpu->blocked_vcpu_list);
10679                 spin_unlock_irqrestore(
10680                         &per_cpu(blocked_vcpu_on_cpu_lock,
10681                         vcpu->pre_pcpu), flags);
10682                 vcpu->pre_pcpu = -1;
10683         }
10684 }
10685
10686 /*
10687  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10688  *
10689  * @kvm: kvm
10690  * @host_irq: host irq of the interrupt
10691  * @guest_irq: gsi of the interrupt
10692  * @set: set or unset PI
10693  * returns 0 on success, < 0 on failure
10694  */
10695 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10696                               uint32_t guest_irq, bool set)
10697 {
10698         struct kvm_kernel_irq_routing_entry *e;
10699         struct kvm_irq_routing_table *irq_rt;
10700         struct kvm_lapic_irq irq;
10701         struct kvm_vcpu *vcpu;
10702         struct vcpu_data vcpu_info;
10703         int idx, ret = -EINVAL;
10704
10705         if (!kvm_arch_has_assigned_device(kvm) ||
10706                 !irq_remapping_cap(IRQ_POSTING_CAP))
10707                 return 0;
10708
10709         idx = srcu_read_lock(&kvm->irq_srcu);
10710         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10711         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10712
10713         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10714                 if (e->type != KVM_IRQ_ROUTING_MSI)
10715                         continue;
10716                 /*
10717                  * VT-d PI cannot support posting multicast/broadcast
10718                  * interrupts to a vCPU, we still use interrupt remapping
10719                  * for these kind of interrupts.
10720                  *
10721                  * For lowest-priority interrupts, we only support
10722                  * those with single CPU as the destination, e.g. user
10723                  * configures the interrupts via /proc/irq or uses
10724                  * irqbalance to make the interrupts single-CPU.
10725                  *
10726                  * We will support full lowest-priority interrupt later.
10727                  */
10728
10729                 kvm_set_msi_irq(e, &irq);
10730                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10731                         continue;
10732
10733                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10734                 vcpu_info.vector = irq.vector;
10735
10736                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10737                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10738
10739                 if (set)
10740                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10741                 else {
10742                         /* suppress notification event before unposting */
10743                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10744                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10745                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10746                 }
10747
10748                 if (ret < 0) {
10749                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10750                                         __func__);
10751                         goto out;
10752                 }
10753         }
10754
10755         ret = 0;
10756 out:
10757         srcu_read_unlock(&kvm->irq_srcu, idx);
10758         return ret;
10759 }
10760
10761 static struct kvm_x86_ops vmx_x86_ops = {
10762         .cpu_has_kvm_support = cpu_has_kvm_support,
10763         .disabled_by_bios = vmx_disabled_by_bios,
10764         .hardware_setup = hardware_setup,
10765         .hardware_unsetup = hardware_unsetup,
10766         .check_processor_compatibility = vmx_check_processor_compat,
10767         .hardware_enable = hardware_enable,
10768         .hardware_disable = hardware_disable,
10769         .cpu_has_accelerated_tpr = report_flexpriority,
10770         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10771
10772         .vcpu_create = vmx_create_vcpu,
10773         .vcpu_free = vmx_free_vcpu,
10774         .vcpu_reset = vmx_vcpu_reset,
10775
10776         .prepare_guest_switch = vmx_save_host_state,
10777         .vcpu_load = vmx_vcpu_load,
10778         .vcpu_put = vmx_vcpu_put,
10779
10780         .update_bp_intercept = update_exception_bitmap,
10781         .get_msr = vmx_get_msr,
10782         .set_msr = vmx_set_msr,
10783         .get_segment_base = vmx_get_segment_base,
10784         .get_segment = vmx_get_segment,
10785         .set_segment = vmx_set_segment,
10786         .get_cpl = vmx_get_cpl,
10787         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10788         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10789         .decache_cr3 = vmx_decache_cr3,
10790         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10791         .set_cr0 = vmx_set_cr0,
10792         .set_cr3 = vmx_set_cr3,
10793         .set_cr4 = vmx_set_cr4,
10794         .set_efer = vmx_set_efer,
10795         .get_idt = vmx_get_idt,
10796         .set_idt = vmx_set_idt,
10797         .get_gdt = vmx_get_gdt,
10798         .set_gdt = vmx_set_gdt,
10799         .get_dr6 = vmx_get_dr6,
10800         .set_dr6 = vmx_set_dr6,
10801         .set_dr7 = vmx_set_dr7,
10802         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10803         .cache_reg = vmx_cache_reg,
10804         .get_rflags = vmx_get_rflags,
10805         .set_rflags = vmx_set_rflags,
10806         .fpu_activate = vmx_fpu_activate,
10807         .fpu_deactivate = vmx_fpu_deactivate,
10808
10809         .tlb_flush = vmx_flush_tlb,
10810
10811         .run = vmx_vcpu_run,
10812         .handle_exit = vmx_handle_exit,
10813         .skip_emulated_instruction = skip_emulated_instruction,
10814         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10815         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10816         .patch_hypercall = vmx_patch_hypercall,
10817         .set_irq = vmx_inject_irq,
10818         .set_nmi = vmx_inject_nmi,
10819         .queue_exception = vmx_queue_exception,
10820         .cancel_injection = vmx_cancel_injection,
10821         .interrupt_allowed = vmx_interrupt_allowed,
10822         .nmi_allowed = vmx_nmi_allowed,
10823         .get_nmi_mask = vmx_get_nmi_mask,
10824         .set_nmi_mask = vmx_set_nmi_mask,
10825         .enable_nmi_window = enable_nmi_window,
10826         .enable_irq_window = enable_irq_window,
10827         .update_cr8_intercept = update_cr8_intercept,
10828         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10829         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10830         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10831         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10832         .hwapic_irr_update = vmx_hwapic_irr_update,
10833         .hwapic_isr_update = vmx_hwapic_isr_update,
10834         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10835         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10836
10837         .set_tss_addr = vmx_set_tss_addr,
10838         .get_tdp_level = get_ept_level,
10839         .get_mt_mask = vmx_get_mt_mask,
10840
10841         .get_exit_info = vmx_get_exit_info,
10842
10843         .get_lpage_level = vmx_get_lpage_level,
10844
10845         .cpuid_update = vmx_cpuid_update,
10846
10847         .rdtscp_supported = vmx_rdtscp_supported,
10848         .invpcid_supported = vmx_invpcid_supported,
10849
10850         .set_supported_cpuid = vmx_set_supported_cpuid,
10851
10852         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10853
10854         .read_tsc_offset = vmx_read_tsc_offset,
10855         .write_tsc_offset = vmx_write_tsc_offset,
10856         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10857         .read_l1_tsc = vmx_read_l1_tsc,
10858
10859         .set_tdp_cr3 = vmx_set_cr3,
10860
10861         .check_intercept = vmx_check_intercept,
10862         .handle_external_intr = vmx_handle_external_intr,
10863         .mpx_supported = vmx_mpx_supported,
10864         .xsaves_supported = vmx_xsaves_supported,
10865
10866         .check_nested_events = vmx_check_nested_events,
10867
10868         .sched_in = vmx_sched_in,
10869
10870         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10871         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10872         .flush_log_dirty = vmx_flush_log_dirty,
10873         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10874
10875         .pre_block = vmx_pre_block,
10876         .post_block = vmx_post_block,
10877
10878         .pmu_ops = &intel_pmu_ops,
10879
10880         .update_pi_irte = vmx_update_pi_irte,
10881 };
10882
10883 static int __init vmx_init(void)
10884 {
10885         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10886                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10887         if (r)
10888                 return r;
10889
10890 #ifdef CONFIG_KEXEC_CORE
10891         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10892                            crash_vmclear_local_loaded_vmcss);
10893 #endif
10894
10895         return 0;
10896 }
10897
10898 static void __exit vmx_exit(void)
10899 {
10900 #ifdef CONFIG_KEXEC_CORE
10901         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10902         synchronize_rcu();
10903 #endif
10904
10905         kvm_exit();
10906 }
10907
10908 module_init(vmx_init)
10909 module_exit(vmx_exit)