kernel/arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         u64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static atomic_t pmc_refcount;
 139 static DEFINE_MUTEX(pmc_reserve_mutex);
 140
 141 #ifdef CONFIG_X86_LOCAL_APIC
 142
 143 static bool reserve_pmc_hardware(void)
 144 {
 145         int i;
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 149                         goto perfctr_fail;
 150         }
 151
 152         for (i = 0; i < x86_pmu.num_counters; i++) {
 153                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 154                         goto eventsel_fail;
 155         }
 156
 157         return true;
 158
 159 eventsel_fail:
 160         for (i--; i >= 0; i--)
 161                 release_evntsel_nmi(x86_pmu_config_addr(i));
 162
 163         i = x86_pmu.num_counters;
 164
 165 perfctr_fail:
 166         for (i--; i >= 0; i--)
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168
 169         return false;
 170 }
 171
 172 static void release_pmc_hardware(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < x86_pmu.num_counters; i++) {
 177                 release_perfctr_nmi(x86_pmu_event_addr(i));
 178                 release_evntsel_nmi(x86_pmu_config_addr(i));
 179         }
 180 }
 181
 182 #else
 183
 184 static bool reserve_pmc_hardware(void) { return true; }
 185 static void release_pmc_hardware(void) {}
 186
 187 #endif
 188
 189 static bool check_hw_exists(void)
 190 {
 191         u64 val, val_fail, val_new= ~0;
 192         int i, reg, reg_fail, ret = 0;
 193         int bios_fail = 0;
 194         int reg_safe = -1;
 195
 196         /*
 197          * Check to see if the BIOS enabled any of the counters, if so
 198          * complain and bail.
 199          */
 200         for (i = 0; i < x86_pmu.num_counters; i++) {
 201                 reg = x86_pmu_config_addr(i);
 202                 ret = rdmsrl_safe(reg, &val);
 203                 if (ret)
 204                         goto msr_fail;
 205                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 206                         bios_fail = 1;
 207                         val_fail = val;
 208                         reg_fail = reg;
 209                 } else {
 210                         reg_safe = i;
 211                 }
 212         }
 213
 214         if (x86_pmu.num_counters_fixed) {
 215                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 216                 ret = rdmsrl_safe(reg, &val);
 217                 if (ret)
 218                         goto msr_fail;
 219                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 220                         if (val & (0x03 << i*4)) {
 221                                 bios_fail = 1;
 222                                 val_fail = val;
 223                                 reg_fail = reg;
 224                         }
 225                 }
 226         }
 227
 228         /*
 229          * If all the counters are enabled, the below test will always
 230          * fail.  The tools will also become useless in this scenario.
 231          * Just fail and disable the hardware counters.
 232          */
 233
 234         if (reg_safe == -1) {
 235                 reg = reg_safe;
 236                 goto msr_fail;
 237         }
 238
 239         /*
 240          * Read the current value, change it and read it back to see if it
 241          * matches, this is needed to detect certain hardware emulators
 242          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 243          */
 244         reg = x86_pmu_event_addr(reg_safe);
 245         if (rdmsrl_safe(reg, &val))
 246                 goto msr_fail;
 247         val ^= 0xffffUL;
 248         ret = wrmsrl_safe(reg, val);
 249         ret |= rdmsrl_safe(reg, &val_new);
 250         if (ret || val != val_new)
 251                 goto msr_fail;
 252
 253         /*
 254          * We still allow the PMU driver to operate:
 255          */
 256         if (bios_fail) {
 257                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 258                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 259         }
 260
 261         return true;
 262
 263 msr_fail:
 264         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 265         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 266                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 267                 reg, val_new);
 268
 269         return false;
 270 }
 271
 272 static void hw_perf_event_destroy(struct perf_event *event)
 273 {
 274         x86_release_hardware();
 275         atomic_dec(&active_events);
 276 }
 277
 278 void hw_perf_lbr_event_destroy(struct perf_event *event)
 279 {
 280         hw_perf_event_destroy(event);
 281
 282         /* undo the lbr/bts event accounting */
 283         x86_del_exclusive(x86_lbr_exclusive_lbr);
 284 }
 285
 286 static inline int x86_pmu_initialized(void)
 287 {
 288         return x86_pmu.handle_irq != NULL;
 289 }
 290
 291 static inline int
 292 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 293 {
 294         struct perf_event_attr *attr = &event->attr;
 295         unsigned int cache_type, cache_op, cache_result;
 296         u64 config, val;
 297
 298         config = attr->config;
 299
 300         cache_type = (config >>  0) & 0xff;
 301         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 302                 return -EINVAL;
 303
 304         cache_op = (config >>  8) & 0xff;
 305         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 306                 return -EINVAL;
 307
 308         cache_result = (config >> 16) & 0xff;
 309         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 310                 return -EINVAL;
 311
 312         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 313
 314         if (val == 0)
 315                 return -ENOENT;
 316
 317         if (val == -1)
 318                 return -EINVAL;
 319
 320         hwc->config |= val;
 321         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 322         return x86_pmu_extra_regs(val, event);
 323 }
 324
 325 int x86_reserve_hardware(void)
 326 {
 327         int err = 0;
 328
 329         if (!atomic_inc_not_zero(&pmc_refcount)) {
 330                 mutex_lock(&pmc_reserve_mutex);
 331                 if (atomic_read(&pmc_refcount) == 0) {
 332                         if (!reserve_pmc_hardware())
 333                                 err = -EBUSY;
 334                         else
 335                                 reserve_ds_buffers();
 336                 }
 337                 if (!err)
 338                         atomic_inc(&pmc_refcount);
 339                 mutex_unlock(&pmc_reserve_mutex);
 340         }
 341
 342         return err;
 343 }
 344
 345 void x86_release_hardware(void)
 346 {
 347         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 348                 release_pmc_hardware();
 349                 release_ds_buffers();
 350                 mutex_unlock(&pmc_reserve_mutex);
 351         }
 352 }
 353
 354 /*
 355  * Check if we can create event of a certain type (that no conflicting events
 356  * are present).
 357  */
 358 int x86_add_exclusive(unsigned int what)
 359 {
 360         int i;
 361
 362         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 363                 mutex_lock(&pmc_reserve_mutex);
 364                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 365                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 366                                 goto fail_unlock;
 367                 }
 368                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 369                 mutex_unlock(&pmc_reserve_mutex);
 370         }
 371
 372         atomic_inc(&active_events);
 373         return 0;
 374
 375 fail_unlock:
 376         mutex_unlock(&pmc_reserve_mutex);
 377         return -EBUSY;
 378 }
 379
 380 void x86_del_exclusive(unsigned int what)
 381 {
 382         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 383         atomic_dec(&active_events);
 384 }
 385
 386 int x86_setup_perfctr(struct perf_event *event)
 387 {
 388         struct perf_event_attr *attr = &event->attr;
 389         struct hw_perf_event *hwc = &event->hw;
 390         u64 config;
 391
 392         if (!is_sampling_event(event)) {
 393                 hwc->sample_period = x86_pmu.max_period;
 394                 hwc->last_period = hwc->sample_period;
 395                 local64_set(&hwc->period_left, hwc->sample_period);
 396         }
 397
 398         if (attr->type == PERF_TYPE_RAW)
 399                 return x86_pmu_extra_regs(event->attr.config, event);
 400
 401         if (attr->type == PERF_TYPE_HW_CACHE)
 402                 return set_ext_hw_attr(hwc, event);
 403
 404         if (attr->config >= x86_pmu.max_events)
 405                 return -EINVAL;
 406
 407         /*
 408          * The generic map:
 409          */
 410         config = x86_pmu.event_map(attr->config);
 411
 412         if (config == 0)
 413                 return -ENOENT;
 414
 415         if (config == -1LL)
 416                 return -EINVAL;
 417
 418         /*
 419          * Branch tracing:
 420          */
 421         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 422             !attr->freq && hwc->sample_period == 1) {
 423                 /* BTS is not supported by this architecture. */
 424                 if (!x86_pmu.bts_active)
 425                         return -EOPNOTSUPP;
 426
 427                 /* BTS is currently only allowed for user-mode. */
 428                 if (!attr->exclude_kernel)
 429                         return -EOPNOTSUPP;
 430
 431                 /* disallow bts if conflicting events are present */
 432                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 433                         return -EBUSY;
 434
 435                 event->destroy = hw_perf_lbr_event_destroy;
 436         }
 437
 438         hwc->config |= config;
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * check that branch_sample_type is compatible with
 445  * settings needed for precise_ip > 1 which implies
 446  * using the LBR to capture ALL taken branches at the
 447  * priv levels of the measurement
 448  */
 449 static inline int precise_br_compat(struct perf_event *event)
 450 {
 451         u64 m = event->attr.branch_sample_type;
 452         u64 b = 0;
 453
 454         /* must capture all branches */
 455         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 456                 return 0;
 457
 458         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 459
 460         if (!event->attr.exclude_user)
 461                 b |= PERF_SAMPLE_BRANCH_USER;
 462
 463         if (!event->attr.exclude_kernel)
 464                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 465
 466         /*
 467          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 468          */
 469
 470         return m == b;
 471 }
 472
 473 int x86_pmu_hw_config(struct perf_event *event)
 474 {
 475         if (event->attr.precise_ip) {
 476                 int precise = 0;
 477
 478                 /* Support for constant skid */
 479                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 480                         precise++;
 481
 482                         /* Support for IP fixup */
 483                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 484                                 precise++;
 485                 }
 486
 487                 if (event->attr.precise_ip > precise)
 488                         return -EOPNOTSUPP;
 489         }
 490         /*
 491          * check that PEBS LBR correction does not conflict with
 492          * whatever the user is asking with attr->branch_sample_type
 493          */
 494         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 495                 u64 *br_type = &event->attr.branch_sample_type;
 496
 497                 if (has_branch_stack(event)) {
 498                         if (!precise_br_compat(event))
 499                                 return -EOPNOTSUPP;
 500
 501                         /* branch_sample_type is compatible */
 502
 503                 } else {
 504                         /*
 505                          * user did not specify  branch_sample_type
 506                          *
 507                          * For PEBS fixups, we capture all
 508                          * the branches at the priv level of the
 509                          * event.
 510                          */
 511                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 512
 513                         if (!event->attr.exclude_user)
 514                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 515
 516                         if (!event->attr.exclude_kernel)
 517                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 518                 }
 519         }
 520
 521         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 522                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 523
 524         /*
 525          * Generate PMC IRQs:
 526          * (keep 'enabled' bit clear for now)
 527          */
 528         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 529
 530         /*
 531          * Count user and OS events unless requested not to
 532          */
 533         if (!event->attr.exclude_user)
 534                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 535         if (!event->attr.exclude_kernel)
 536                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 537
 538         if (event->attr.type == PERF_TYPE_RAW)
 539                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 540
 541         if (event->attr.sample_period && x86_pmu.limit_period) {
 542                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 543                                 event->attr.sample_period)
 544                         return -EINVAL;
 545         }
 546
 547         return x86_setup_perfctr(event);
 548 }
 549
 550 /*
 551  * Setup the hardware configuration for a given attr_type
 552  */
 553 static int __x86_pmu_event_init(struct perf_event *event)
 554 {
 555         int err;
 556
 557         if (!x86_pmu_initialized())
 558                 return -ENODEV;
 559
 560         err = x86_reserve_hardware();
 561         if (err)
 562                 return err;
 563
 564         atomic_inc(&active_events);
 565         event->destroy = hw_perf_event_destroy;
 566
 567         event->hw.idx = -1;
 568         event->hw.last_cpu = -1;
 569         event->hw.last_tag = ~0ULL;
 570
 571         /* mark unused */
 572         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 573         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 574
 575         return x86_pmu.hw_config(event);
 576 }
 577
 578 void x86_pmu_disable_all(void)
 579 {
 580         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 581         int idx;
 582
 583         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 584                 u64 val;
 585
 586                 if (!test_bit(idx, cpuc->active_mask))
 587                         continue;
 588                 rdmsrl(x86_pmu_config_addr(idx), val);
 589                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 590                         continue;
 591                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 592                 wrmsrl(x86_pmu_config_addr(idx), val);
 593         }
 594 }
 595
 596 /*
 597  * There may be PMI landing after enabled=0. The PMI hitting could be before or
 598  * after disable_all.
 599  *
 600  * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 601  * It will not be re-enabled in the NMI handler again, because enabled=0. After
 602  * handling the NMI, disable_all will be called, which will not change the
 603  * state either. If PMI hits after disable_all, the PMU is already disabled
 604  * before entering NMI handler. The NMI handler will not change the state
 605  * either.
 606  *
 607  * So either situation is harmless.
 608  */
 609 static void x86_pmu_disable(struct pmu *pmu)
 610 {
 611         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 612
 613         if (!x86_pmu_initialized())
 614                 return;
 615
 616         if (!cpuc->enabled)
 617                 return;
 618
 619         cpuc->n_added = 0;
 620         cpuc->enabled = 0;
 621         barrier();
 622
 623         x86_pmu.disable_all();
 624 }
 625
 626 void x86_pmu_enable_all(int added)
 627 {
 628         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 629         int idx;
 630
 631         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 632                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 633
 634                 if (!test_bit(idx, cpuc->active_mask))
 635                         continue;
 636
 637                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 638         }
 639 }
 640
 641 static struct pmu pmu;
 642
 643 static inline int is_x86_event(struct perf_event *event)
 644 {
 645         return event->pmu == &pmu;
 646 }
 647
 648 /*
 649  * Event scheduler state:
 650  *
 651  * Assign events iterating over all events and counters, beginning
 652  * with events with least weights first. Keep the current iterator
 653  * state in struct sched_state.
 654  */
 655 struct sched_state {
 656         int     weight;
 657         int     event;          /* event index */
 658         int     counter;        /* counter index */
 659         int     unassigned;     /* number of events to be assigned left */
 660         int     nr_gp;          /* number of GP counters used */
 661         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 662 };
 663
 664 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 665 #define SCHED_STATES_MAX        2
 666
 667 struct perf_sched {
 668         int                     max_weight;
 669         int                     max_events;
 670         int                     max_gp;
 671         int                     saved_states;
 672         struct event_constraint **constraints;
 673         struct sched_state      state;
 674         struct sched_state      saved[SCHED_STATES_MAX];
 675 };
 676
 677 /*
 678  * Initialize interator that runs through all events and counters.
 679  */
 680 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 681                             int num, int wmin, int wmax, int gpmax)
 682 {
 683         int idx;
 684
 685         memset(sched, 0, sizeof(*sched));
 686         sched->max_events       = num;
 687         sched->max_weight       = wmax;
 688         sched->max_gp           = gpmax;
 689         sched->constraints      = constraints;
 690
 691         for (idx = 0; idx < num; idx++) {
 692                 if (constraints[idx]->weight == wmin)
 693                         break;
 694         }
 695
 696         sched->state.event      = idx;          /* start with min weight */
 697         sched->state.weight     = wmin;
 698         sched->state.unassigned = num;
 699 }
 700
 701 static void perf_sched_save_state(struct perf_sched *sched)
 702 {
 703         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 704                 return;
 705
 706         sched->saved[sched->saved_states] = sched->state;
 707         sched->saved_states++;
 708 }
 709
 710 static bool perf_sched_restore_state(struct perf_sched *sched)
 711 {
 712         if (!sched->saved_states)
 713                 return false;
 714
 715         sched->saved_states--;
 716         sched->state = sched->saved[sched->saved_states];
 717
 718         /* continue with next counter: */
 719         clear_bit(sched->state.counter++, sched->state.used);
 720
 721         return true;
 722 }
 723
 724 /*
 725  * Select a counter for the current event to schedule. Return true on
 726  * success.
 727  */
 728 static bool __perf_sched_find_counter(struct perf_sched *sched)
 729 {
 730         struct event_constraint *c;
 731         int idx;
 732
 733         if (!sched->state.unassigned)
 734                 return false;
 735
 736         if (sched->state.event >= sched->max_events)
 737                 return false;
 738
 739         c = sched->constraints[sched->state.event];
 740         /* Prefer fixed purpose counters */
 741         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 742                 idx = INTEL_PMC_IDX_FIXED;
 743                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 744                         if (!__test_and_set_bit(idx, sched->state.used))
 745                                 goto done;
 746                 }
 747         }
 748
 749         /* Grab the first unused counter starting with idx */
 750         idx = sched->state.counter;
 751         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 752                 if (!__test_and_set_bit(idx, sched->state.used)) {
 753                         if (sched->state.nr_gp++ >= sched->max_gp)
 754                                 return false;
 755
 756                         goto done;
 757                 }
 758         }
 759
 760         return false;
 761
 762 done:
 763         sched->state.counter = idx;
 764
 765         if (c->overlap)
 766                 perf_sched_save_state(sched);
 767
 768         return true;
 769 }
 770
 771 static bool perf_sched_find_counter(struct perf_sched *sched)
 772 {
 773         while (!__perf_sched_find_counter(sched)) {
 774                 if (!perf_sched_restore_state(sched))
 775                         return false;
 776         }
 777
 778         return true;
 779 }
 780
 781 /*
 782  * Go through all unassigned events and find the next one to schedule.
 783  * Take events with the least weight first. Return true on success.
 784  */
 785 static bool perf_sched_next_event(struct perf_sched *sched)
 786 {
 787         struct event_constraint *c;
 788
 789         if (!sched->state.unassigned || !--sched->state.unassigned)
 790                 return false;
 791
 792         do {
 793                 /* next event */
 794                 sched->state.event++;
 795                 if (sched->state.event >= sched->max_events) {
 796                         /* next weight */
 797                         sched->state.event = 0;
 798                         sched->state.weight++;
 799                         if (sched->state.weight > sched->max_weight)
 800                                 return false;
 801                 }
 802                 c = sched->constraints[sched->state.event];
 803         } while (c->weight != sched->state.weight);
 804
 805         sched->state.counter = 0;       /* start with first counter */
 806
 807         return true;
 808 }
 809
 810 /*
 811  * Assign a counter for each event.
 812  */
 813 int perf_assign_events(struct event_constraint **constraints, int n,
 814                         int wmin, int wmax, int gpmax, int *assign)
 815 {
 816         struct perf_sched sched;
 817
 818         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 819
 820         do {
 821                 if (!perf_sched_find_counter(&sched))
 822                         break;  /* failed */
 823                 if (assign)
 824                         assign[sched.state.event] = sched.state.counter;
 825         } while (perf_sched_next_event(&sched));
 826
 827         return sched.state.unassigned;
 828 }
 829 EXPORT_SYMBOL_GPL(perf_assign_events);
 830
 831 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 832 {
 833         struct event_constraint *c;
 834         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 835         struct perf_event *e;
 836         int i, wmin, wmax, unsched = 0;
 837         struct hw_perf_event *hwc;
 838
 839         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 840
 841         if (x86_pmu.start_scheduling)
 842                 x86_pmu.start_scheduling(cpuc);
 843
 844         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 845                 cpuc->event_constraint[i] = NULL;
 846                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 847                 cpuc->event_constraint[i] = c;
 848
 849                 wmin = min(wmin, c->weight);
 850                 wmax = max(wmax, c->weight);
 851         }
 852
 853         /*
 854          * fastpath, try to reuse previous register
 855          */
 856         for (i = 0; i < n; i++) {
 857                 hwc = &cpuc->event_list[i]->hw;
 858                 c = cpuc->event_constraint[i];
 859
 860                 /* never assigned */
 861                 if (hwc->idx == -1)
 862                         break;
 863
 864                 /* constraint still honored */
 865                 if (!test_bit(hwc->idx, c->idxmsk))
 866                         break;
 867
 868                 /* not already used */
 869                 if (test_bit(hwc->idx, used_mask))
 870                         break;
 871
 872                 __set_bit(hwc->idx, used_mask);
 873                 if (assign)
 874                         assign[i] = hwc->idx;
 875         }
 876
 877         /* slow path */
 878         if (i != n) {
 879                 int gpmax = x86_pmu.num_counters;
 880
 881                 /*
 882                  * Do not allow scheduling of more than half the available
 883                  * generic counters.
 884                  *
 885                  * This helps avoid counter starvation of sibling thread by
 886                  * ensuring at most half the counters cannot be in exclusive
 887                  * mode. There is no designated counters for the limits. Any
 888                  * N/2 counters can be used. This helps with events with
 889                  * specific counter constraints.
 890                  */
 891                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 892                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 893                         gpmax /= 2;
 894
 895                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 896                                              wmax, gpmax, assign);
 897         }
 898
 899         /*
 900          * In case of success (unsched = 0), mark events as committed,
 901          * so we do not put_constraint() in case new events are added
 902          * and fail to be scheduled
 903          *
 904          * We invoke the lower level commit callback to lock the resource
 905          *
 906          * We do not need to do all of this in case we are called to
 907          * validate an event group (assign == NULL)
 908          */
 909         if (!unsched && assign) {
 910                 for (i = 0; i < n; i++) {
 911                         e = cpuc->event_list[i];
 912                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 913                         if (x86_pmu.commit_scheduling)
 914                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 915                 }
 916         } else {
 917                 for (i = 0; i < n; i++) {
 918                         e = cpuc->event_list[i];
 919                         /*
 920                          * do not put_constraint() on comitted events,
 921                          * because they are good to go
 922                          */
 923                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 924                                 continue;
 925
 926                         /*
 927                          * release events that failed scheduling
 928                          */
 929                         if (x86_pmu.put_event_constraints)
 930                                 x86_pmu.put_event_constraints(cpuc, e);
 931                 }
 932         }
 933
 934         if (x86_pmu.stop_scheduling)
 935                 x86_pmu.stop_scheduling(cpuc);
 936
 937         return unsched ? -EINVAL : 0;
 938 }
 939
 940 /*
 941  * dogrp: true if must collect siblings events (group)
 942  * returns total number of events and error code
 943  */
 944 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 945 {
 946         struct perf_event *event;
 947         int n, max_count;
 948
 949         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 950
 951         /* current number of events already accepted */
 952         n = cpuc->n_events;
 953
 954         if (is_x86_event(leader)) {
 955                 if (n >= max_count)
 956                         return -EINVAL;
 957                 cpuc->event_list[n] = leader;
 958                 n++;
 959         }
 960         if (!dogrp)
 961                 return n;
 962
 963         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 964                 if (!is_x86_event(event) ||
 965                     event->state <= PERF_EVENT_STATE_OFF)
 966                         continue;
 967
 968                 if (n >= max_count)
 969                         return -EINVAL;
 970
 971                 cpuc->event_list[n] = event;
 972                 n++;
 973         }
 974         return n;
 975 }
 976
 977 static inline void x86_assign_hw_event(struct perf_event *event,
 978                                 struct cpu_hw_events *cpuc, int i)
 979 {
 980         struct hw_perf_event *hwc = &event->hw;
 981
 982         hwc->idx = cpuc->assign[i];
 983         hwc->last_cpu = smp_processor_id();
 984         hwc->last_tag = ++cpuc->tags[i];
 985
 986         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 987                 hwc->config_base = 0;
 988                 hwc->event_base = 0;
 989         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 990                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 991                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 992                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 993         } else {
 994                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 995                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 996                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 997         }
 998 }
 999
1000 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1001                                         struct cpu_hw_events *cpuc,
1002                                         int i)
1003 {
1004         return hwc->idx == cpuc->assign[i] &&
1005                 hwc->last_cpu == smp_processor_id() &&
1006                 hwc->last_tag == cpuc->tags[i];
1007 }
1008
1009 static void x86_pmu_start(struct perf_event *event, int flags);
1010
1011 static void x86_pmu_enable(struct pmu *pmu)
1012 {
1013         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1014         struct perf_event *event;
1015         struct hw_perf_event *hwc;
1016         int i, added = cpuc->n_added;
1017
1018         if (!x86_pmu_initialized())
1019                 return;
1020
1021         if (cpuc->enabled)
1022                 return;
1023
1024         if (cpuc->n_added) {
1025                 int n_running = cpuc->n_events - cpuc->n_added;
1026                 /*
1027                  * apply assignment obtained either from
1028                  * hw_perf_group_sched_in() or x86_pmu_enable()
1029                  *
1030                  * step1: save events moving to new counters
1031                  */
1032                 for (i = 0; i < n_running; i++) {
1033                         event = cpuc->event_list[i];
1034                         hwc = &event->hw;
1035
1036                         /*
1037                          * we can avoid reprogramming counter if:
1038                          * - assigned same counter as last time
1039                          * - running on same CPU as last time
1040                          * - no other event has used the counter since
1041                          */
1042                         if (hwc->idx == -1 ||
1043                             match_prev_assignment(hwc, cpuc, i))
1044                                 continue;
1045
1046                         /*
1047                          * Ensure we don't accidentally enable a stopped
1048                          * counter simply because we rescheduled.
1049                          */
1050                         if (hwc->state & PERF_HES_STOPPED)
1051                                 hwc->state |= PERF_HES_ARCH;
1052
1053                         x86_pmu_stop(event, PERF_EF_UPDATE);
1054                 }
1055
1056                 /*
1057                  * step2: reprogram moved events into new counters
1058                  */
1059                 for (i = 0; i < cpuc->n_events; i++) {
1060                         event = cpuc->event_list[i];
1061                         hwc = &event->hw;
1062
1063                         if (!match_prev_assignment(hwc, cpuc, i))
1064                                 x86_assign_hw_event(event, cpuc, i);
1065                         else if (i < n_running)
1066                                 continue;
1067
1068                         if (hwc->state & PERF_HES_ARCH)
1069                                 continue;
1070
1071                         x86_pmu_start(event, PERF_EF_RELOAD);
1072                 }
1073                 cpuc->n_added = 0;
1074                 perf_events_lapic_init();
1075         }
1076
1077         cpuc->enabled = 1;
1078         barrier();
1079
1080         x86_pmu.enable_all(added);
1081 }
1082
1083 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1084
1085 /*
1086  * Set the next IRQ period, based on the hwc->period_left value.
1087  * To be called with the event disabled in hw:
1088  */
1089 int x86_perf_event_set_period(struct perf_event *event)
1090 {
1091         struct hw_perf_event *hwc = &event->hw;
1092         s64 left = local64_read(&hwc->period_left);
1093         s64 period = hwc->sample_period;
1094         int ret = 0, idx = hwc->idx;
1095
1096         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1097                 return 0;
1098
1099         /*
1100          * If we are way outside a reasonable range then just skip forward:
1101          */
1102         if (unlikely(left <= -period)) {
1103                 left = period;
1104                 local64_set(&hwc->period_left, left);
1105                 hwc->last_period = period;
1106                 ret = 1;
1107         }
1108
1109         if (unlikely(left <= 0)) {
1110                 left += period;
1111                 local64_set(&hwc->period_left, left);
1112                 hwc->last_period = period;
1113                 ret = 1;
1114         }
1115         /*
1116          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1117          */
1118         if (unlikely(left < 2))
1119                 left = 2;
1120
1121         if (left > x86_pmu.max_period)
1122                 left = x86_pmu.max_period;
1123
1124         if (x86_pmu.limit_period)
1125                 left = x86_pmu.limit_period(event, left);
1126
1127         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1128
1129         if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1130             local64_read(&hwc->prev_count) != (u64)-left) {
1131                 /*
1132                  * The hw event starts counting from this event offset,
1133                  * mark it to be able to extra future deltas:
1134                  */
1135                 local64_set(&hwc->prev_count, (u64)-left);
1136
1137                 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1138         }
1139
1140         /*
1141          * Due to erratum on certan cpu we need
1142          * a second write to be sure the register
1143          * is updated properly
1144          */
1145         if (x86_pmu.perfctr_second_write) {
1146                 wrmsrl(hwc->event_base,
1147                         (u64)(-left) & x86_pmu.cntval_mask);
1148         }
1149
1150         perf_event_update_userpage(event);
1151
1152         return ret;
1153 }
1154
1155 void x86_pmu_enable_event(struct perf_event *event)
1156 {
1157         if (__this_cpu_read(cpu_hw_events.enabled))
1158                 __x86_pmu_enable_event(&event->hw,
1159                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1160 }
1161
1162 /*
1163  * Add a single event to the PMU.
1164  *
1165  * The event is added to the group of enabled events
1166  * but only if it can be scehduled with existing events.
1167  */
1168 static int x86_pmu_add(struct perf_event *event, int flags)
1169 {
1170         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1171         struct hw_perf_event *hwc;
1172         int assign[X86_PMC_IDX_MAX];
1173         int n, n0, ret;
1174
1175         hwc = &event->hw;
1176
1177         n0 = cpuc->n_events;
1178         ret = n = collect_events(cpuc, event, false);
1179         if (ret < 0)
1180                 goto out;
1181
1182         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1183         if (!(flags & PERF_EF_START))
1184                 hwc->state |= PERF_HES_ARCH;
1185
1186         /*
1187          * If group events scheduling transaction was started,
1188          * skip the schedulability test here, it will be performed
1189          * at commit time (->commit_txn) as a whole.
1190          */
1191         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1192                 goto done_collect;
1193
1194         ret = x86_pmu.schedule_events(cpuc, n, assign);
1195         if (ret)
1196                 goto out;
1197         /*
1198          * copy new assignment, now we know it is possible
1199          * will be used by hw_perf_enable()
1200          */
1201         memcpy(cpuc->assign, assign, n*sizeof(int));
1202
1203 done_collect:
1204         /*
1205          * Commit the collect_events() state. See x86_pmu_del() and
1206          * x86_pmu_*_txn().
1207          */
1208         cpuc->n_events = n;
1209         cpuc->n_added += n - n0;
1210         cpuc->n_txn += n - n0;
1211
1212         ret = 0;
1213 out:
1214         return ret;
1215 }
1216
1217 static void x86_pmu_start(struct perf_event *event, int flags)
1218 {
1219         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1220         int idx = event->hw.idx;
1221
1222         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1223                 return;
1224
1225         if (WARN_ON_ONCE(idx == -1))
1226                 return;
1227
1228         if (flags & PERF_EF_RELOAD) {
1229                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1230                 x86_perf_event_set_period(event);
1231         }
1232
1233         event->hw.state = 0;
1234
1235         cpuc->events[idx] = event;
1236         __set_bit(idx, cpuc->active_mask);
1237         __set_bit(idx, cpuc->running);
1238         x86_pmu.enable(event);
1239         perf_event_update_userpage(event);
1240 }
1241
1242 void perf_event_print_debug(void)
1243 {
1244         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1245         u64 pebs, debugctl;
1246         struct cpu_hw_events *cpuc;
1247         unsigned long flags;
1248         int cpu, idx;
1249
1250         if (!x86_pmu.num_counters)
1251                 return;
1252
1253         local_irq_save(flags);
1254
1255         cpu = smp_processor_id();
1256         cpuc = &per_cpu(cpu_hw_events, cpu);
1257
1258         if (x86_pmu.version >= 2) {
1259                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1260                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1261                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1262                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1263
1264                 pr_info("\n");
1265                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1266                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1267                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1268                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1269                 if (x86_pmu.pebs_constraints) {
1270                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1271                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1272                 }
1273                 if (x86_pmu.lbr_nr) {
1274                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1275                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1276                 }
1277         }
1278         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1279
1280         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1281                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1282                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1283
1284                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1285
1286                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1287                         cpu, idx, pmc_ctrl);
1288                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1289                         cpu, idx, pmc_count);
1290                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1291                         cpu, idx, prev_left);
1292         }
1293         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1294                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1295
1296                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1297                         cpu, idx, pmc_count);
1298         }
1299         local_irq_restore(flags);
1300 }
1301
1302 void x86_pmu_stop(struct perf_event *event, int flags)
1303 {
1304         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1305         struct hw_perf_event *hwc = &event->hw;
1306
1307         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1308                 x86_pmu.disable(event);
1309                 cpuc->events[hwc->idx] = NULL;
1310                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1311                 hwc->state |= PERF_HES_STOPPED;
1312         }
1313
1314         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1315                 /*
1316                  * Drain the remaining delta count out of a event
1317                  * that we are disabling:
1318                  */
1319                 x86_perf_event_update(event);
1320                 hwc->state |= PERF_HES_UPTODATE;
1321         }
1322 }
1323
1324 static void x86_pmu_del(struct perf_event *event, int flags)
1325 {
1326         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1327         int i;
1328
1329         /*
1330          * event is descheduled
1331          */
1332         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1333
1334         /*
1335          * If we're called during a txn, we don't need to do anything.
1336          * The events never got scheduled and ->cancel_txn will truncate
1337          * the event_list.
1338          *
1339          * XXX assumes any ->del() called during a TXN will only be on
1340          * an event added during that same TXN.
1341          */
1342         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1343                 return;
1344
1345         /*
1346          * Not a TXN, therefore cleanup properly.
1347          */
1348         x86_pmu_stop(event, PERF_EF_UPDATE);
1349
1350         for (i = 0; i < cpuc->n_events; i++) {
1351                 if (event == cpuc->event_list[i])
1352                         break;
1353         }
1354
1355         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1356                 return;
1357
1358         /* If we have a newly added event; make sure to decrease n_added. */
1359         if (i >= cpuc->n_events - cpuc->n_added)
1360                 --cpuc->n_added;
1361
1362         if (x86_pmu.put_event_constraints)
1363                 x86_pmu.put_event_constraints(cpuc, event);
1364
1365         /* Delete the array entry. */
1366         while (++i < cpuc->n_events) {
1367                 cpuc->event_list[i-1] = cpuc->event_list[i];
1368                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1369         }
1370         --cpuc->n_events;
1371
1372         perf_event_update_userpage(event);
1373 }
1374
1375 int x86_pmu_handle_irq(struct pt_regs *regs)
1376 {
1377         struct perf_sample_data data;
1378         struct cpu_hw_events *cpuc;
1379         struct perf_event *event;
1380         int idx, handled = 0;
1381         u64 val;
1382
1383         cpuc = this_cpu_ptr(&cpu_hw_events);
1384
1385         /*
1386          * Some chipsets need to unmask the LVTPC in a particular spot
1387          * inside the nmi handler.  As a result, the unmasking was pushed
1388          * into all the nmi handlers.
1389          *
1390          * This generic handler doesn't seem to have any issues where the
1391          * unmasking occurs so it was left at the top.
1392          */
1393         apic_write(APIC_LVTPC, APIC_DM_NMI);
1394
1395         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1396                 if (!test_bit(idx, cpuc->active_mask)) {
1397                         /*
1398                          * Though we deactivated the counter some cpus
1399                          * might still deliver spurious interrupts still
1400                          * in flight. Catch them:
1401                          */
1402                         if (__test_and_clear_bit(idx, cpuc->running))
1403                                 handled++;
1404                         continue;
1405                 }
1406
1407                 event = cpuc->events[idx];
1408
1409                 val = x86_perf_event_update(event);
1410                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1411                         continue;
1412
1413                 /*
1414                  * event overflow
1415                  */
1416                 handled++;
1417                 perf_sample_data_init(&data, 0, event->hw.last_period);
1418
1419                 if (!x86_perf_event_set_period(event))
1420                         continue;
1421
1422                 if (perf_event_overflow(event, &data, regs))
1423                         x86_pmu_stop(event, 0);
1424         }
1425
1426         if (handled)
1427                 inc_irq_stat(apic_perf_irqs);
1428
1429         return handled;
1430 }
1431
1432 void perf_events_lapic_init(void)
1433 {
1434         if (!x86_pmu.apic || !x86_pmu_initialized())
1435                 return;
1436
1437         /*
1438          * Always use NMI for PMU
1439          */
1440         apic_write(APIC_LVTPC, APIC_DM_NMI);
1441 }
1442
1443 static int
1444 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1445 {
1446         u64 start_clock;
1447         u64 finish_clock;
1448         int ret;
1449
1450         /*
1451          * All PMUs/events that share this PMI handler should make sure to
1452          * increment active_events for their events.
1453          */
1454         if (!atomic_read(&active_events))
1455                 return NMI_DONE;
1456
1457         start_clock = sched_clock();
1458         ret = x86_pmu.handle_irq(regs);
1459         finish_clock = sched_clock();
1460
1461         perf_sample_event_took(finish_clock - start_clock);
1462
1463         return ret;
1464 }
1465 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1466
1467 struct event_constraint emptyconstraint;
1468 struct event_constraint unconstrained;
1469
1470 static int
1471 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1472 {
1473         unsigned int cpu = (long)hcpu;
1474         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1475         int i, ret = NOTIFY_OK;
1476
1477         switch (action & ~CPU_TASKS_FROZEN) {
1478         case CPU_UP_PREPARE:
1479                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1480                         cpuc->kfree_on_online[i] = NULL;
1481                 if (x86_pmu.cpu_prepare)
1482                         ret = x86_pmu.cpu_prepare(cpu);
1483                 break;
1484
1485         case CPU_STARTING:
1486                 if (x86_pmu.cpu_starting)
1487                         x86_pmu.cpu_starting(cpu);
1488                 break;
1489
1490         case CPU_ONLINE:
1491                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1492                         kfree(cpuc->kfree_on_online[i]);
1493                         cpuc->kfree_on_online[i] = NULL;
1494                 }
1495                 break;
1496
1497         case CPU_DYING:
1498                 if (x86_pmu.cpu_dying)
1499                         x86_pmu.cpu_dying(cpu);
1500                 break;
1501
1502         case CPU_UP_CANCELED:
1503         case CPU_DEAD:
1504                 if (x86_pmu.cpu_dead)
1505                         x86_pmu.cpu_dead(cpu);
1506                 break;
1507
1508         default:
1509                 break;
1510         }
1511
1512         return ret;
1513 }
1514
1515 static void __init pmu_check_apic(void)
1516 {
1517         if (cpu_has_apic)
1518                 return;
1519
1520         x86_pmu.apic = 0;
1521         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1522         pr_info("no hardware sampling interrupt available.\n");
1523
1524         /*
1525          * If we have a PMU initialized but no APIC
1526          * interrupts, we cannot sample hardware
1527          * events (user-space has to fall back and
1528          * sample via a hrtimer based software event):
1529          */
1530         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1531
1532 }
1533
1534 static struct attribute_group x86_pmu_format_group = {
1535         .name = "format",
1536         .attrs = NULL,
1537 };
1538
1539 /*
1540  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1541  * out of events_attr attributes.
1542  */
1543 static void __init filter_events(struct attribute **attrs)
1544 {
1545         struct device_attribute *d;
1546         struct perf_pmu_events_attr *pmu_attr;
1547         int i, j;
1548
1549         for (i = 0; attrs[i]; i++) {
1550                 d = (struct device_attribute *)attrs[i];
1551                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1552                 /* str trumps id */
1553                 if (pmu_attr->event_str)
1554                         continue;
1555                 if (x86_pmu.event_map(i))
1556                         continue;
1557
1558                 for (j = i; attrs[j]; j++)
1559                         attrs[j] = attrs[j + 1];
1560
1561                 /* Check the shifted attr. */
1562                 i--;
1563         }
1564 }
1565
1566 /* Merge two pointer arrays */
1567 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1568 {
1569         struct attribute **new;
1570         int j, i;
1571
1572         for (j = 0; a[j]; j++)
1573                 ;
1574         for (i = 0; b[i]; i++)
1575                 j++;
1576         j++;
1577
1578         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1579         if (!new)
1580                 return NULL;
1581
1582         j = 0;
1583         for (i = 0; a[i]; i++)
1584                 new[j++] = a[i];
1585         for (i = 0; b[i]; i++)
1586                 new[j++] = b[i];
1587         new[j] = NULL;
1588
1589         return new;
1590 }
1591
1592 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1593                           char *page)
1594 {
1595         struct perf_pmu_events_attr *pmu_attr = \
1596                 container_of(attr, struct perf_pmu_events_attr, attr);
1597         u64 config = x86_pmu.event_map(pmu_attr->id);
1598
1599         /* string trumps id */
1600         if (pmu_attr->event_str)
1601                 return sprintf(page, "%s", pmu_attr->event_str);
1602
1603         return x86_pmu.events_sysfs_show(page, config);
1604 }
1605
1606 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1607 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1608 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1609 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1610 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1611 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1612 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1613 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1614 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1615 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1616
1617 static struct attribute *empty_attrs;
1618
1619 static struct attribute *events_attr[] = {
1620         EVENT_PTR(CPU_CYCLES),
1621         EVENT_PTR(INSTRUCTIONS),
1622         EVENT_PTR(CACHE_REFERENCES),
1623         EVENT_PTR(CACHE_MISSES),
1624         EVENT_PTR(BRANCH_INSTRUCTIONS),
1625         EVENT_PTR(BRANCH_MISSES),
1626         EVENT_PTR(BUS_CYCLES),
1627         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1628         EVENT_PTR(STALLED_CYCLES_BACKEND),
1629         EVENT_PTR(REF_CPU_CYCLES),
1630         NULL,
1631 };
1632
1633 static struct attribute_group x86_pmu_events_group = {
1634         .name = "events",
1635         .attrs = events_attr,
1636 };
1637
1638 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1639 {
1640         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1641         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1642         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1643         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1644         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1645         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1646         ssize_t ret;
1647
1648         /*
1649         * We have whole page size to spend and just little data
1650         * to write, so we can safely use sprintf.
1651         */
1652         ret = sprintf(page, "event=0x%02llx", event);
1653
1654         if (umask)
1655                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1656
1657         if (edge)
1658                 ret += sprintf(page + ret, ",edge");
1659
1660         if (pc)
1661                 ret += sprintf(page + ret, ",pc");
1662
1663         if (any)
1664                 ret += sprintf(page + ret, ",any");
1665
1666         if (inv)
1667                 ret += sprintf(page + ret, ",inv");
1668
1669         if (cmask)
1670                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1671
1672         ret += sprintf(page + ret, "\n");
1673
1674         return ret;
1675 }
1676
1677 static int __init init_hw_perf_events(void)
1678 {
1679         struct x86_pmu_quirk *quirk;
1680         int err;
1681
1682         pr_info("Performance Events: ");
1683
1684         switch (boot_cpu_data.x86_vendor) {
1685         case X86_VENDOR_INTEL:
1686                 err = intel_pmu_init();
1687                 break;
1688         case X86_VENDOR_AMD:
1689                 err = amd_pmu_init();
1690                 break;
1691         default:
1692                 err = -ENOTSUPP;
1693         }
1694         if (err != 0) {
1695                 pr_cont("no PMU driver, software events only.\n");
1696                 return 0;
1697         }
1698
1699         pmu_check_apic();
1700
1701         /* sanity check that the hardware exists or is emulated */
1702         if (!check_hw_exists())
1703                 return 0;
1704
1705         pr_cont("%s PMU driver.\n", x86_pmu.name);
1706
1707         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1708
1709         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1710                 quirk->func();
1711
1712         if (!x86_pmu.intel_ctrl)
1713                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1714
1715         perf_events_lapic_init();
1716         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1717
1718         unconstrained = (struct event_constraint)
1719                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1720                                    0, x86_pmu.num_counters, 0, 0);
1721
1722         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1723
1724         if (x86_pmu.event_attrs)
1725                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1726
1727         if (!x86_pmu.events_sysfs_show)
1728                 x86_pmu_events_group.attrs = &empty_attrs;
1729         else
1730                 filter_events(x86_pmu_events_group.attrs);
1731
1732         if (x86_pmu.cpu_events) {
1733                 struct attribute **tmp;
1734
1735                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1736                 if (!WARN_ON(!tmp))
1737                         x86_pmu_events_group.attrs = tmp;
1738         }
1739
1740         pr_info("... version:                %d\n",     x86_pmu.version);
1741         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1742         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1743         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1744         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1745         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1746         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1747
1748         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1749         perf_cpu_notifier(x86_pmu_notifier);
1750
1751         return 0;
1752 }
1753 early_initcall(init_hw_perf_events);
1754
1755 static inline void x86_pmu_read(struct perf_event *event)
1756 {
1757         x86_perf_event_update(event);
1758 }
1759
1760 /*
1761  * Start group events scheduling transaction
1762  * Set the flag to make pmu::enable() not perform the
1763  * schedulability test, it will be performed at commit time
1764  *
1765  * We only support PERF_PMU_TXN_ADD transactions. Save the
1766  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1767  * transactions.
1768  */
1769 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1770 {
1771         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1772
1773         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
1774
1775         cpuc->txn_flags = txn_flags;
1776         if (txn_flags & ~PERF_PMU_TXN_ADD)
1777                 return;
1778
1779         perf_pmu_disable(pmu);
1780         __this_cpu_write(cpu_hw_events.n_txn, 0);
1781 }
1782
1783 /*
1784  * Stop group events scheduling transaction
1785  * Clear the flag and pmu::enable() will perform the
1786  * schedulability test.
1787  */
1788 static void x86_pmu_cancel_txn(struct pmu *pmu)
1789 {
1790         unsigned int txn_flags;
1791         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1792
1793         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1794
1795         txn_flags = cpuc->txn_flags;
1796         cpuc->txn_flags = 0;
1797         if (txn_flags & ~PERF_PMU_TXN_ADD)
1798                 return;
1799
1800         /*
1801          * Truncate collected array by the number of events added in this
1802          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1803          */
1804         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1805         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1806         perf_pmu_enable(pmu);
1807 }
1808
1809 /*
1810  * Commit group events scheduling transaction
1811  * Perform the group schedulability test as a whole
1812  * Return 0 if success
1813  *
1814  * Does not cancel the transaction on failure; expects the caller to do this.
1815  */
1816 static int x86_pmu_commit_txn(struct pmu *pmu)
1817 {
1818         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1819         int assign[X86_PMC_IDX_MAX];
1820         int n, ret;
1821
1822         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1823
1824         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1825                 cpuc->txn_flags = 0;
1826                 return 0;
1827         }
1828
1829         n = cpuc->n_events;
1830
1831         if (!x86_pmu_initialized())
1832                 return -EAGAIN;
1833
1834         ret = x86_pmu.schedule_events(cpuc, n, assign);
1835         if (ret)
1836                 return ret;
1837
1838         /*
1839          * copy new assignment, now we know it is possible
1840          * will be used by hw_perf_enable()
1841          */
1842         memcpy(cpuc->assign, assign, n*sizeof(int));
1843
1844         cpuc->txn_flags = 0;
1845         perf_pmu_enable(pmu);
1846         return 0;
1847 }
1848 /*
1849  * a fake_cpuc is used to validate event groups. Due to
1850  * the extra reg logic, we need to also allocate a fake
1851  * per_core and per_cpu structure. Otherwise, group events
1852  * using extra reg may conflict without the kernel being
1853  * able to catch this when the last event gets added to
1854  * the group.
1855  */
1856 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1857 {
1858         kfree(cpuc->shared_regs);
1859         kfree(cpuc);
1860 }
1861
1862 static struct cpu_hw_events *allocate_fake_cpuc(void)
1863 {
1864         struct cpu_hw_events *cpuc;
1865         int cpu = raw_smp_processor_id();
1866
1867         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1868         if (!cpuc)
1869                 return ERR_PTR(-ENOMEM);
1870
1871         /* only needed, if we have extra_regs */
1872         if (x86_pmu.extra_regs) {
1873                 cpuc->shared_regs = allocate_shared_regs(cpu);
1874                 if (!cpuc->shared_regs)
1875                         goto error;
1876         }
1877         cpuc->is_fake = 1;
1878         return cpuc;
1879 error:
1880         free_fake_cpuc(cpuc);
1881         return ERR_PTR(-ENOMEM);
1882 }
1883
1884 /*
1885  * validate that we can schedule this event
1886  */
1887 static int validate_event(struct perf_event *event)
1888 {
1889         struct cpu_hw_events *fake_cpuc;
1890         struct event_constraint *c;
1891         int ret = 0;
1892
1893         fake_cpuc = allocate_fake_cpuc();
1894         if (IS_ERR(fake_cpuc))
1895                 return PTR_ERR(fake_cpuc);
1896
1897         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1898
1899         if (!c || !c->weight)
1900                 ret = -EINVAL;
1901
1902         if (x86_pmu.put_event_constraints)
1903                 x86_pmu.put_event_constraints(fake_cpuc, event);
1904
1905         free_fake_cpuc(fake_cpuc);
1906
1907         return ret;
1908 }
1909
1910 /*
1911  * validate a single event group
1912  *
1913  * validation include:
1914  *      - check events are compatible which each other
1915  *      - events do not compete for the same counter
1916  *      - number of events <= number of counters
1917  *
1918  * validation ensures the group can be loaded onto the
1919  * PMU if it was the only group available.
1920  */
1921 static int validate_group(struct perf_event *event)
1922 {
1923         struct perf_event *leader = event->group_leader;
1924         struct cpu_hw_events *fake_cpuc;
1925         int ret = -EINVAL, n;
1926
1927         fake_cpuc = allocate_fake_cpuc();
1928         if (IS_ERR(fake_cpuc))
1929                 return PTR_ERR(fake_cpuc);
1930         /*
1931          * the event is not yet connected with its
1932          * siblings therefore we must first collect
1933          * existing siblings, then add the new event
1934          * before we can simulate the scheduling
1935          */
1936         n = collect_events(fake_cpuc, leader, true);
1937         if (n < 0)
1938                 goto out;
1939
1940         fake_cpuc->n_events = n;
1941         n = collect_events(fake_cpuc, event, false);
1942         if (n < 0)
1943                 goto out;
1944
1945         fake_cpuc->n_events = n;
1946
1947         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1948
1949 out:
1950         free_fake_cpuc(fake_cpuc);
1951         return ret;
1952 }
1953
1954 static int x86_pmu_event_init(struct perf_event *event)
1955 {
1956         struct pmu *tmp;
1957         int err;
1958
1959         switch (event->attr.type) {
1960         case PERF_TYPE_RAW:
1961         case PERF_TYPE_HARDWARE:
1962         case PERF_TYPE_HW_CACHE:
1963                 break;
1964
1965         default:
1966                 return -ENOENT;
1967         }
1968
1969         err = __x86_pmu_event_init(event);
1970         if (!err) {
1971                 /*
1972                  * we temporarily connect event to its pmu
1973                  * such that validate_group() can classify
1974                  * it as an x86 event using is_x86_event()
1975                  */
1976                 tmp = event->pmu;
1977                 event->pmu = &pmu;
1978
1979                 if (event->group_leader != event)
1980                         err = validate_group(event);
1981                 else
1982                         err = validate_event(event);
1983
1984                 event->pmu = tmp;
1985         }
1986         if (err) {
1987                 if (event->destroy)
1988                         event->destroy(event);
1989         }
1990
1991         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1992                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1993
1994         return err;
1995 }
1996
1997 static void refresh_pce(void *ignored)
1998 {
1999         if (current->mm)
2000                 load_mm_cr4(current->mm);
2001 }
2002
2003 static void x86_pmu_event_mapped(struct perf_event *event)
2004 {
2005         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2006                 return;
2007
2008         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
2009                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2010 }
2011
2012 static void x86_pmu_event_unmapped(struct perf_event *event)
2013 {
2014         if (!current->mm)
2015                 return;
2016
2017         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2018                 return;
2019
2020         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
2021                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2022 }
2023
2024 static int x86_pmu_event_idx(struct perf_event *event)
2025 {
2026         int idx = event->hw.idx;
2027
2028         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2029                 return 0;
2030
2031         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2032                 idx -= INTEL_PMC_IDX_FIXED;
2033                 idx |= 1 << 30;
2034         }
2035
2036         return idx + 1;
2037 }
2038
2039 static ssize_t get_attr_rdpmc(struct device *cdev,
2040                               struct device_attribute *attr,
2041                               char *buf)
2042 {
2043         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2044 }
2045
2046 static ssize_t set_attr_rdpmc(struct device *cdev,
2047                               struct device_attribute *attr,
2048                               const char *buf, size_t count)
2049 {
2050         unsigned long val;
2051         ssize_t ret;
2052
2053         ret = kstrtoul(buf, 0, &val);
2054         if (ret)
2055                 return ret;
2056
2057         if (val > 2)
2058                 return -EINVAL;
2059
2060         if (x86_pmu.attr_rdpmc_broken)
2061                 return -ENOTSUPP;
2062
2063         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2064                 /*
2065                  * Changing into or out of always available, aka
2066                  * perf-event-bypassing mode.  This path is extremely slow,
2067                  * but only root can trigger it, so it's okay.
2068                  */
2069                 if (val == 2)
2070                         static_key_slow_inc(&rdpmc_always_available);
2071                 else
2072                         static_key_slow_dec(&rdpmc_always_available);
2073                 on_each_cpu(refresh_pce, NULL, 1);
2074         }
2075
2076         x86_pmu.attr_rdpmc = val;
2077
2078         return count;
2079 }
2080
2081 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2082
2083 static struct attribute *x86_pmu_attrs[] = {
2084         &dev_attr_rdpmc.attr,
2085         NULL,
2086 };
2087
2088 static struct attribute_group x86_pmu_attr_group = {
2089         .attrs = x86_pmu_attrs,
2090 };
2091
2092 static const struct attribute_group *x86_pmu_attr_groups[] = {
2093         &x86_pmu_attr_group,
2094         &x86_pmu_format_group,
2095         &x86_pmu_events_group,
2096         NULL,
2097 };
2098
2099 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2100 {
2101         if (x86_pmu.sched_task)
2102                 x86_pmu.sched_task(ctx, sched_in);
2103 }
2104
2105 void perf_check_microcode(void)
2106 {
2107         if (x86_pmu.check_microcode)
2108                 x86_pmu.check_microcode();
2109 }
2110 EXPORT_SYMBOL_GPL(perf_check_microcode);
2111
2112 static struct pmu pmu = {
2113         .pmu_enable             = x86_pmu_enable,
2114         .pmu_disable            = x86_pmu_disable,
2115
2116         .attr_groups            = x86_pmu_attr_groups,
2117
2118         .event_init             = x86_pmu_event_init,
2119
2120         .event_mapped           = x86_pmu_event_mapped,
2121         .event_unmapped         = x86_pmu_event_unmapped,
2122
2123         .add                    = x86_pmu_add,
2124         .del                    = x86_pmu_del,
2125         .start                  = x86_pmu_start,
2126         .stop                   = x86_pmu_stop,
2127         .read                   = x86_pmu_read,
2128
2129         .start_txn              = x86_pmu_start_txn,
2130         .cancel_txn             = x86_pmu_cancel_txn,
2131         .commit_txn             = x86_pmu_commit_txn,
2132
2133         .event_idx              = x86_pmu_event_idx,
2134         .sched_task             = x86_pmu_sched_task,
2135         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2136 };
2137
2138 void arch_perf_update_userpage(struct perf_event *event,
2139                                struct perf_event_mmap_page *userpg, u64 now)
2140 {
2141         struct cyc2ns_data *data;
2142
2143         userpg->cap_user_time = 0;
2144         userpg->cap_user_time_zero = 0;
2145         userpg->cap_user_rdpmc =
2146                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2147         userpg->pmc_width = x86_pmu.cntval_bits;
2148
2149         if (!sched_clock_stable())
2150                 return;
2151
2152         data = cyc2ns_read_begin();
2153
2154         /*
2155          * Internal timekeeping for enabled/running/stopped times
2156          * is always in the local_clock domain.
2157          */
2158         userpg->cap_user_time = 1;
2159         userpg->time_mult = data->cyc2ns_mul;
2160         userpg->time_shift = data->cyc2ns_shift;
2161         userpg->time_offset = data->cyc2ns_offset - now;
2162
2163         /*
2164          * cap_user_time_zero doesn't make sense when we're using a different
2165          * time base for the records.
2166          */
2167         if (event->clock == &local_clock) {
2168                 userpg->cap_user_time_zero = 1;
2169                 userpg->time_zero = data->cyc2ns_offset;
2170         }
2171
2172         cyc2ns_read_end(data);
2173 }
2174
2175 /*
2176  * callchain support
2177  */
2178
2179 static int backtrace_stack(void *data, char *name)
2180 {
2181         return 0;
2182 }
2183
2184 static void backtrace_address(void *data, unsigned long addr, int reliable)
2185 {
2186         struct perf_callchain_entry *entry = data;
2187
2188         perf_callchain_store(entry, addr);
2189 }
2190
2191 static const struct stacktrace_ops backtrace_ops = {
2192         .stack                  = backtrace_stack,
2193         .address                = backtrace_address,
2194         .walk_stack             = print_context_stack_bp,
2195 };
2196
2197 void
2198 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2199 {
2200         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2201                 /* TODO: We don't support guest os callchain now */
2202                 return;
2203         }
2204
2205         perf_callchain_store(entry, regs->ip);
2206
2207         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2208 }
2209
2210 static inline int
2211 valid_user_frame(const void __user *fp, unsigned long size)
2212 {
2213         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2214 }
2215
2216 static unsigned long get_segment_base(unsigned int segment)
2217 {
2218         struct desc_struct *desc;
2219         int idx = segment >> 3;
2220
2221         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2222 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2223                 struct ldt_struct *ldt;
2224
2225                 if (idx > LDT_ENTRIES)
2226                         return 0;
2227
2228                 /* IRQs are off, so this synchronizes with smp_store_release */
2229                 ldt = lockless_dereference(current->active_mm->context.ldt);
2230                 if (!ldt || idx > ldt->size)
2231                         return 0;
2232
2233                 desc = &ldt->entries[idx];
2234 #else
2235                 return 0;
2236 #endif
2237         } else {
2238                 if (idx > GDT_ENTRIES)
2239                         return 0;
2240
2241                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2242         }
2243
2244         return get_desc_base(desc);
2245 }
2246
2247 #ifdef CONFIG_IA32_EMULATION
2248
2249 #include <asm/compat.h>
2250
2251 static inline int
2252 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2253 {
2254         /* 32-bit process in 64-bit kernel. */
2255         unsigned long ss_base, cs_base;
2256         struct stack_frame_ia32 frame;
2257         const void __user *fp;
2258
2259         if (!test_thread_flag(TIF_IA32))
2260                 return 0;
2261
2262         cs_base = get_segment_base(regs->cs);
2263         ss_base = get_segment_base(regs->ss);
2264
2265         fp = compat_ptr(ss_base + regs->bp);
2266         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2267                 unsigned long bytes;
2268                 frame.next_frame     = 0;
2269                 frame.return_address = 0;
2270
2271                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2272                 if (bytes != 0)
2273                         break;
2274
2275                 if (!valid_user_frame(fp, sizeof(frame)))
2276                         break;
2277
2278                 perf_callchain_store(entry, cs_base + frame.return_address);
2279                 fp = compat_ptr(ss_base + frame.next_frame);
2280         }
2281         return 1;
2282 }
2283 #else
2284 static inline int
2285 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2286 {
2287     return 0;
2288 }
2289 #endif
2290
2291 void
2292 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2293 {
2294         struct stack_frame frame;
2295         const void __user *fp;
2296
2297         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2298                 /* TODO: We don't support guest os callchain now */
2299                 return;
2300         }
2301
2302         /*
2303          * We don't know what to do with VM86 stacks.. ignore them for now.
2304          */
2305         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2306                 return;
2307
2308         fp = (void __user *)regs->bp;
2309
2310         perf_callchain_store(entry, regs->ip);
2311
2312         if (!current->mm)
2313                 return;
2314
2315         if (perf_callchain_user32(regs, entry))
2316                 return;
2317
2318         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2319                 unsigned long bytes;
2320                 frame.next_frame             = NULL;
2321                 frame.return_address = 0;
2322
2323                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2324                 if (bytes != 0)
2325                         break;
2326
2327                 if (!valid_user_frame(fp, sizeof(frame)))
2328                         break;
2329
2330                 perf_callchain_store(entry, frame.return_address);
2331                 fp = frame.next_frame;
2332         }
2333 }
2334
2335 /*
2336  * Deal with code segment offsets for the various execution modes:
2337  *
2338  *   VM86 - the good olde 16 bit days, where the linear address is
2339  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2340  *
2341  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2342  *          to figure out what the 32bit base address is.
2343  *
2344  *    X32 - has TIF_X32 set, but is running in x86_64
2345  *
2346  * X86_64 - CS,DS,SS,ES are all zero based.
2347  */
2348 static unsigned long code_segment_base(struct pt_regs *regs)
2349 {
2350         /*
2351          * For IA32 we look at the GDT/LDT segment base to convert the
2352          * effective IP to a linear address.
2353          */
2354
2355 #ifdef CONFIG_X86_32
2356         /*
2357          * If we are in VM86 mode, add the segment offset to convert to a
2358          * linear address.
2359          */
2360         if (regs->flags & X86_VM_MASK)
2361                 return 0x10 * regs->cs;
2362
2363         if (user_mode(regs) && regs->cs != __USER_CS)
2364                 return get_segment_base(regs->cs);
2365 #else
2366         if (user_mode(regs) && !user_64bit_mode(regs) &&
2367             regs->cs != __USER32_CS)
2368                 return get_segment_base(regs->cs);
2369 #endif
2370         return 0;
2371 }
2372
2373 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2374 {
2375         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2376                 return perf_guest_cbs->get_guest_ip();
2377
2378         return regs->ip + code_segment_base(regs);
2379 }
2380
2381 unsigned long perf_misc_flags(struct pt_regs *regs)
2382 {
2383         int misc = 0;
2384
2385         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2386                 if (perf_guest_cbs->is_user_mode())
2387                         misc |= PERF_RECORD_MISC_GUEST_USER;
2388                 else
2389                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2390         } else {
2391                 if (user_mode(regs))
2392                         misc |= PERF_RECORD_MISC_USER;
2393                 else
2394                         misc |= PERF_RECORD_MISC_KERNEL;
2395         }
2396
2397         if (regs->flags & PERF_EFLAGS_EXACT)
2398                 misc |= PERF_RECORD_MISC_EXACT_IP;
2399
2400         return misc;
2401 }
2402
2403 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2404 {
2405         cap->version            = x86_pmu.version;
2406         cap->num_counters_gp    = x86_pmu.num_counters;
2407         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2408         cap->bit_width_gp       = x86_pmu.cntval_bits;
2409         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2410         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2411         cap->events_mask_len    = x86_pmu.events_mask_len;
2412 }
2413 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);