2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
10 #include <asm/processor.h>
11 #include <asm/traps.h>
12 #include <asm/tlbflush.h>
16 /* By default disabled */
17 int mce_p5_enabled __read_mostly;
19 /* Machine check handler for Pentium class Intel CPUs: */
20 static void pentium_machine_check(struct pt_regs *regs, long error_code)
22 enum ctx_state prev_state;
23 u32 loaddr, hi, lotype;
25 prev_state = ist_enter(regs);
27 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
28 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
31 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
32 smp_processor_id(), loaddr, lotype);
34 if (lotype & (1<<5)) {
36 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
40 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
42 ist_exit(regs, prev_state);
45 /* Set up machine check reporting for processors with Intel style MCE: */
46 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
50 /* Default P5 to off as its often misconnected: */
54 /* Check for MCE support: */
55 if (!cpu_has(c, X86_FEATURE_MCE))
58 machine_check_vector = pentium_machine_check;
59 /* Make sure the vector pointer is visible before we enable MCEs: */
62 /* Read registers before enabling: */
63 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
64 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
66 "Intel old style machine check architecture supported.\n");
69 cr4_set_bits(X86_CR4_MCE);
71 "Intel old style machine check reporting enabled on CPU#%d.\n",