kernel/arch/unicore32/include/mach/regs-nand.h

   1 /*
   2  * PKUnity NAND Controller Registers
   3  */
   4 /*
   5  * ID Reg. 0 NAND_IDR0
   6  */
   7 #define NAND_IDR0       (PKUNITY_NAND_BASE + 0x0000)
   8 /*
   9  * ID Reg. 1 NAND_IDR1
  10  */
  11 #define NAND_IDR1       (PKUNITY_NAND_BASE + 0x0004)
  12 /*
  13  * ID Reg. 2 NAND_IDR2
  14  */
  15 #define NAND_IDR2       (PKUNITY_NAND_BASE + 0x0008)
  16 /*
  17  * ID Reg. 3 NAND_IDR3
  18  */
  19 #define NAND_IDR3       (PKUNITY_NAND_BASE + 0x000C)
  20 /*
  21  * Page Address Reg 0 NAND_PAR0
  22  */
  23 #define NAND_PAR0       (PKUNITY_NAND_BASE + 0x0010)
  24 /*
  25  * Page Address Reg 1 NAND_PAR1
  26  */
  27 #define NAND_PAR1       (PKUNITY_NAND_BASE + 0x0014)
  28 /*
  29  * Page Address Reg 2 NAND_PAR2
  30  */
  31 #define NAND_PAR2       (PKUNITY_NAND_BASE + 0x0018)
  32 /*
  33  * ECC Enable Reg NAND_ECCEN
  34  */
  35 #define NAND_ECCEN      (PKUNITY_NAND_BASE + 0x001C)
  36 /*
  37  * Buffer Reg NAND_BUF
  38  */
  39 #define NAND_BUF        (PKUNITY_NAND_BASE + 0x0020)
  40 /*
  41  * ECC Status Reg NAND_ECCSR
  42  */
  43 #define NAND_ECCSR      (PKUNITY_NAND_BASE + 0x0024)
  44 /*
  45  * Command Reg NAND_CMD
  46  */
  47 #define NAND_CMD        (PKUNITY_NAND_BASE + 0x0028)
  48 /*
  49  * DMA Configure Reg NAND_DMACR
  50  */
  51 #define NAND_DMACR      (PKUNITY_NAND_BASE + 0x002C)
  52 /*
  53  * Interrupt Reg NAND_IR
  54  */
  55 #define NAND_IR         (PKUNITY_NAND_BASE + 0x0030)
  56 /*
  57  * Interrupt Mask Reg NAND_IMR
  58  */
  59 #define NAND_IMR        (PKUNITY_NAND_BASE + 0x0034)
  60 /*
  61  * Chip Enable Reg NAND_CHIPEN
  62  */
  63 #define NAND_CHIPEN     (PKUNITY_NAND_BASE + 0x0038)
  64 /*
  65  * Address Reg NAND_ADDR
  66  */
  67 #define NAND_ADDR       (PKUNITY_NAND_BASE + 0x003C)
  68
  69 /*
  70  * Command bits NAND_CMD_CMD_MASK
  71  */
  72 #define NAND_CMD_CMD_MASK               FMASK(4, 4)
  73 #define NAND_CMD_CMD_READPAGE           FIELD(0x0, 4, 4)
  74 #define NAND_CMD_CMD_ERASEBLOCK         FIELD(0x6, 4, 4)
  75 #define NAND_CMD_CMD_READSTATUS         FIELD(0x7, 4, 4)
  76 #define NAND_CMD_CMD_WRITEPAGE          FIELD(0x8, 4, 4)
  77 #define NAND_CMD_CMD_READID             FIELD(0x9, 4, 4)
  78 #define NAND_CMD_CMD_RESET              FIELD(0xf, 4, 4)
  79