kernel/arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/ioport.h>
  26 #include <linux/percpu.h>
  27 #include <linux/memblock.h>
  28 #include <linux/mmzone.h>
  29 #include <linux/gfp.h>
  30
  31 #include <asm/head.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/cpudata.h>
  51 #include <asm/setup.h>
  52 #include <asm/irq.h>
  53
  54 #include "init_64.h"
  55
  56 unsigned long kern_linear_pte_xor[4] __read_mostly;
  57 static unsigned long page_cache4v_flag;
  58
  59 /* A bitmap, two bits for every 256MB of physical memory.  These two
  60  * bits determine what page size we use for kernel linear
  61  * translations.  They form an index into kern_linear_pte_xor[].  The
  62  * value in the indexed slot is XOR'd with the TLB miss virtual
  63  * address to form the resulting TTE.  The mapping is:
  64  *
  65  *      0       ==>     4MB
  66  *      1       ==>     256MB
  67  *      2       ==>     2GB
  68  *      3       ==>     16GB
  69  *
  70  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  71  * support 2GB pages, and hopefully future cpus will support the 16GB
  72  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  73  * if these larger page sizes are not supported by the cpu.
  74  *
  75  * It would be nice to determine this from the machine description
  76  * 'cpu' properties, but we need to have this table setup before the
  77  * MDESC is initialized.
  78  */
  79
  80 #ifndef CONFIG_DEBUG_PAGEALLOC
  81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  82  * Space is allocated for this right after the trap table in
  83  * arch/sparc64/kernel/head.S
  84  */
  85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  86 #endif
  87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  88
  89 static unsigned long cpu_pgsz_mask;
  90
  91 #define MAX_BANKS       1024
  92
  93 static struct linux_prom64_registers pavail[MAX_BANKS];
  94 static int pavail_ents;
  95
  96 static int cmp_p64(const void *a, const void *b)
  97 {
  98         const struct linux_prom64_registers *x = a, *y = b;
  99
 100         if (x->phys_addr > y->phys_addr)
 101                 return 1;
 102         if (x->phys_addr < y->phys_addr)
 103                 return -1;
 104         return 0;
 105 }
 106
 107 static void __init read_obp_memory(const char *property,
 108                                    struct linux_prom64_registers *regs,
 109                                    int *num_ents)
 110 {
 111         phandle node = prom_finddevice("/memory");
 112         int prop_size = prom_getproplen(node, property);
 113         int ents, ret, i;
 114
 115         ents = prop_size / sizeof(struct linux_prom64_registers);
 116         if (ents > MAX_BANKS) {
 117                 prom_printf("The machine has more %s property entries than "
 118                             "this kernel can support (%d).\n",
 119                             property, MAX_BANKS);
 120                 prom_halt();
 121         }
 122
 123         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 124         if (ret == -1) {
 125                 prom_printf("Couldn't get %s property from /memory.\n",
 126                                 property);
 127                 prom_halt();
 128         }
 129
 130         /* Sanitize what we got from the firmware, by page aligning
 131          * everything.
 132          */
 133         for (i = 0; i < ents; i++) {
 134                 unsigned long base, size;
 135
 136                 base = regs[i].phys_addr;
 137                 size = regs[i].reg_size;
 138
 139                 size &= PAGE_MASK;
 140                 if (base & ~PAGE_MASK) {
 141                         unsigned long new_base = PAGE_ALIGN(base);
 142
 143                         size -= new_base - base;
 144                         if ((long) size < 0L)
 145                                 size = 0UL;
 146                         base = new_base;
 147                 }
 148                 if (size == 0UL) {
 149                         /* If it is empty, simply get rid of it.
 150                          * This simplifies the logic of the other
 151                          * functions that process these arrays.
 152                          */
 153                         memmove(&regs[i], &regs[i + 1],
 154                                 (ents - i - 1) * sizeof(regs[0]));
 155                         i--;
 156                         ents--;
 157                         continue;
 158                 }
 159                 regs[i].phys_addr = base;
 160                 regs[i].reg_size = size;
 161         }
 162
 163         *num_ents = ents;
 164
 165         sort(regs, ents, sizeof(struct linux_prom64_registers),
 166              cmp_p64, NULL);
 167 }
 168
 169 /* Kernel physical address base and size in bytes.  */
 170 unsigned long kern_base __read_mostly;
 171 unsigned long kern_size __read_mostly;
 172
 173 /* Initial ramdisk setup */
 174 extern unsigned long sparc_ramdisk_image64;
 175 extern unsigned int sparc_ramdisk_image;
 176 extern unsigned int sparc_ramdisk_size;
 177
 178 struct page *mem_map_zero __read_mostly;
 179 EXPORT_SYMBOL(mem_map_zero);
 180
 181 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 182
 183 unsigned long sparc64_kern_pri_context __read_mostly;
 184 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 185 unsigned long sparc64_kern_sec_context __read_mostly;
 186
 187 int num_kernel_image_mappings;
 188
 189 #ifdef CONFIG_DEBUG_DCFLUSH
 190 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 191 #ifdef CONFIG_SMP
 192 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 193 #endif
 194 #endif
 195
 196 inline void flush_dcache_page_impl(struct page *page)
 197 {
 198         BUG_ON(tlb_type == hypervisor);
 199 #ifdef CONFIG_DEBUG_DCFLUSH
 200         atomic_inc(&dcpage_flushes);
 201 #endif
 202
 203 #ifdef DCACHE_ALIASING_POSSIBLE
 204         __flush_dcache_page(page_address(page),
 205                             ((tlb_type == spitfire) &&
 206                              page_mapping(page) != NULL));
 207 #else
 208         if (page_mapping(page) != NULL &&
 209             tlb_type == spitfire)
 210                 __flush_icache_page(__pa(page_address(page)));
 211 #endif
 212 }
 213
 214 #define PG_dcache_dirty         PG_arch_1
 215 #define PG_dcache_cpu_shift     32UL
 216 #define PG_dcache_cpu_mask      \
 217         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 218
 219 #define dcache_dirty_cpu(page) \
 220         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 221
 222 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 223 {
 224         unsigned long mask = this_cpu;
 225         unsigned long non_cpu_bits;
 226
 227         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 228         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 229
 230         __asm__ __volatile__("1:\n\t"
 231                              "ldx       [%2], %%g7\n\t"
 232                              "and       %%g7, %1, %%g1\n\t"
 233                              "or        %%g1, %0, %%g1\n\t"
 234                              "casx      [%2], %%g7, %%g1\n\t"
 235                              "cmp       %%g7, %%g1\n\t"
 236                              "bne,pn    %%xcc, 1b\n\t"
 237                              " nop"
 238                              : /* no outputs */
 239                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 240                              : "g1", "g7");
 241 }
 242
 243 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 244 {
 245         unsigned long mask = (1UL << PG_dcache_dirty);
 246
 247         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 248                              "1:\n\t"
 249                              "ldx       [%2], %%g7\n\t"
 250                              "srlx      %%g7, %4, %%g1\n\t"
 251                              "and       %%g1, %3, %%g1\n\t"
 252                              "cmp       %%g1, %0\n\t"
 253                              "bne,pn    %%icc, 2f\n\t"
 254                              " andn     %%g7, %1, %%g1\n\t"
 255                              "casx      [%2], %%g7, %%g1\n\t"
 256                              "cmp       %%g7, %%g1\n\t"
 257                              "bne,pn    %%xcc, 1b\n\t"
 258                              " nop\n"
 259                              "2:"
 260                              : /* no outputs */
 261                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 262                                "i" (PG_dcache_cpu_mask),
 263                                "i" (PG_dcache_cpu_shift)
 264                              : "g1", "g7");
 265 }
 266
 267 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 268 {
 269         unsigned long tsb_addr = (unsigned long) ent;
 270
 271         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 272                 tsb_addr = __pa(tsb_addr);
 273
 274         __tsb_insert(tsb_addr, tag, pte);
 275 }
 276
 277 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 278
 279 static void flush_dcache(unsigned long pfn)
 280 {
 281         struct page *page;
 282
 283         page = pfn_to_page(pfn);
 284         if (page) {
 285                 unsigned long pg_flags;
 286
 287                 pg_flags = page->flags;
 288                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 289                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 290                                    PG_dcache_cpu_mask);
 291                         int this_cpu = get_cpu();
 292
 293                         /* This is just to optimize away some function calls
 294                          * in the SMP case.
 295                          */
 296                         if (cpu == this_cpu)
 297                                 flush_dcache_page_impl(page);
 298                         else
 299                                 smp_flush_dcache_page_impl(page, cpu);
 300
 301                         clear_dcache_dirty_cpu(page, cpu);
 302
 303                         put_cpu();
 304                 }
 305         }
 306 }
 307
 308 /* mm->context.lock must be held */
 309 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 310                                     unsigned long tsb_hash_shift, unsigned long address,
 311                                     unsigned long tte)
 312 {
 313         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 314         unsigned long tag;
 315
 316         if (unlikely(!tsb))
 317                 return;
 318
 319         tsb += ((address >> tsb_hash_shift) &
 320                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 321         tag = (address >> 22UL);
 322         tsb_insert(tsb, tag, tte);
 323 }
 324
 325 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 326 static inline bool is_hugetlb_pte(pte_t pte)
 327 {
 328         if ((tlb_type == hypervisor &&
 329              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 330             (tlb_type != hypervisor &&
 331              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
 332                 return true;
 333         return false;
 334 }
 335 #endif
 336
 337 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 338 {
 339         struct mm_struct *mm;
 340         unsigned long flags;
 341         pte_t pte = *ptep;
 342
 343         if (tlb_type != hypervisor) {
 344                 unsigned long pfn = pte_pfn(pte);
 345
 346                 if (pfn_valid(pfn))
 347                         flush_dcache(pfn);
 348         }
 349
 350         mm = vma->vm_mm;
 351
 352         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 353         if (!pte_accessible(mm, pte))
 354                 return;
 355
 356         spin_lock_irqsave(&mm->context.lock, flags);
 357
 358 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 359         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
 360                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
 361                                         address, pte_val(pte));
 362         else
 363 #endif
 364                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 365                                         address, pte_val(pte));
 366
 367         spin_unlock_irqrestore(&mm->context.lock, flags);
 368 }
 369
 370 void flush_dcache_page(struct page *page)
 371 {
 372         struct address_space *mapping;
 373         int this_cpu;
 374
 375         if (tlb_type == hypervisor)
 376                 return;
 377
 378         /* Do not bother with the expensive D-cache flush if it
 379          * is merely the zero page.  The 'bigcore' testcase in GDB
 380          * causes this case to run millions of times.
 381          */
 382         if (page == ZERO_PAGE(0))
 383                 return;
 384
 385         this_cpu = get_cpu();
 386
 387         mapping = page_mapping(page);
 388         if (mapping && !mapping_mapped(mapping)) {
 389                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 390                 if (dirty) {
 391                         int dirty_cpu = dcache_dirty_cpu(page);
 392
 393                         if (dirty_cpu == this_cpu)
 394                                 goto out;
 395                         smp_flush_dcache_page_impl(page, dirty_cpu);
 396                 }
 397                 set_dcache_dirty(page, this_cpu);
 398         } else {
 399                 /* We could delay the flush for the !page_mapping
 400                  * case too.  But that case is for exec env/arg
 401                  * pages and those are %99 certainly going to get
 402                  * faulted into the tlb (and thus flushed) anyways.
 403                  */
 404                 flush_dcache_page_impl(page);
 405         }
 406
 407 out:
 408         put_cpu();
 409 }
 410 EXPORT_SYMBOL(flush_dcache_page);
 411
 412 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 413 {
 414         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 415         if (tlb_type == spitfire) {
 416                 unsigned long kaddr;
 417
 418                 /* This code only runs on Spitfire cpus so this is
 419                  * why we can assume _PAGE_PADDR_4U.
 420                  */
 421                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 422                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 423
 424                         if (kaddr >= PAGE_OFFSET)
 425                                 paddr = kaddr & mask;
 426                         else {
 427                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 428                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 429                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 430                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 431
 432                                 paddr = pte_val(*ptep) & mask;
 433                         }
 434                         __flush_icache_page(paddr);
 435                 }
 436         }
 437 }
 438 EXPORT_SYMBOL(flush_icache_range);
 439
 440 void mmu_info(struct seq_file *m)
 441 {
 442         static const char *pgsz_strings[] = {
 443                 "8K", "64K", "512K", "4MB", "32MB",
 444                 "256MB", "2GB", "16GB",
 445         };
 446         int i, printed;
 447
 448         if (tlb_type == cheetah)
 449                 seq_printf(m, "MMU Type\t: Cheetah\n");
 450         else if (tlb_type == cheetah_plus)
 451                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 452         else if (tlb_type == spitfire)
 453                 seq_printf(m, "MMU Type\t: Spitfire\n");
 454         else if (tlb_type == hypervisor)
 455                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 456         else
 457                 seq_printf(m, "MMU Type\t: ???\n");
 458
 459         seq_printf(m, "MMU PGSZs\t: ");
 460         printed = 0;
 461         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 462                 if (cpu_pgsz_mask & (1UL << i)) {
 463                         seq_printf(m, "%s%s",
 464                                    printed ? "," : "", pgsz_strings[i]);
 465                         printed++;
 466                 }
 467         }
 468         seq_putc(m, '\n');
 469
 470 #ifdef CONFIG_DEBUG_DCFLUSH
 471         seq_printf(m, "DCPageFlushes\t: %d\n",
 472                    atomic_read(&dcpage_flushes));
 473 #ifdef CONFIG_SMP
 474         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 475                    atomic_read(&dcpage_flushes_xcall));
 476 #endif /* CONFIG_SMP */
 477 #endif /* CONFIG_DEBUG_DCFLUSH */
 478 }
 479
 480 struct linux_prom_translation prom_trans[512] __read_mostly;
 481 unsigned int prom_trans_ents __read_mostly;
 482
 483 unsigned long kern_locked_tte_data;
 484
 485 /* The obp translations are saved based on 8k pagesize, since obp can
 486  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 487  * HI_OBP_ADDRESS range are handled in ktlb.S.
 488  */
 489 static inline int in_obp_range(unsigned long vaddr)
 490 {
 491         return (vaddr >= LOW_OBP_ADDRESS &&
 492                 vaddr < HI_OBP_ADDRESS);
 493 }
 494
 495 static int cmp_ptrans(const void *a, const void *b)
 496 {
 497         const struct linux_prom_translation *x = a, *y = b;
 498
 499         if (x->virt > y->virt)
 500                 return 1;
 501         if (x->virt < y->virt)
 502                 return -1;
 503         return 0;
 504 }
 505
 506 /* Read OBP translations property into 'prom_trans[]'.  */
 507 static void __init read_obp_translations(void)
 508 {
 509         int n, node, ents, first, last, i;
 510
 511         node = prom_finddevice("/virtual-memory");
 512         n = prom_getproplen(node, "translations");
 513         if (unlikely(n == 0 || n == -1)) {
 514                 prom_printf("prom_mappings: Couldn't get size.\n");
 515                 prom_halt();
 516         }
 517         if (unlikely(n > sizeof(prom_trans))) {
 518                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 519                 prom_halt();
 520         }
 521
 522         if ((n = prom_getproperty(node, "translations",
 523                                   (char *)&prom_trans[0],
 524                                   sizeof(prom_trans))) == -1) {
 525                 prom_printf("prom_mappings: Couldn't get property.\n");
 526                 prom_halt();
 527         }
 528
 529         n = n / sizeof(struct linux_prom_translation);
 530
 531         ents = n;
 532
 533         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 534              cmp_ptrans, NULL);
 535
 536         /* Now kick out all the non-OBP entries.  */
 537         for (i = 0; i < ents; i++) {
 538                 if (in_obp_range(prom_trans[i].virt))
 539                         break;
 540         }
 541         first = i;
 542         for (; i < ents; i++) {
 543                 if (!in_obp_range(prom_trans[i].virt))
 544                         break;
 545         }
 546         last = i;
 547
 548         for (i = 0; i < (last - first); i++) {
 549                 struct linux_prom_translation *src = &prom_trans[i + first];
 550                 struct linux_prom_translation *dest = &prom_trans[i];
 551
 552                 *dest = *src;
 553         }
 554         for (; i < ents; i++) {
 555                 struct linux_prom_translation *dest = &prom_trans[i];
 556                 dest->virt = dest->size = dest->data = 0x0UL;
 557         }
 558
 559         prom_trans_ents = last - first;
 560
 561         if (tlb_type == spitfire) {
 562                 /* Clear diag TTE bits. */
 563                 for (i = 0; i < prom_trans_ents; i++)
 564                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 565         }
 566
 567         /* Force execute bit on.  */
 568         for (i = 0; i < prom_trans_ents; i++)
 569                 prom_trans[i].data |= (tlb_type == hypervisor ?
 570                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 571 }
 572
 573 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 574                                        unsigned long pte,
 575                                        unsigned long mmu)
 576 {
 577         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 578
 579         if (ret != 0) {
 580                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 581                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 582                 prom_halt();
 583         }
 584 }
 585
 586 static unsigned long kern_large_tte(unsigned long paddr);
 587
 588 static void __init remap_kernel(void)
 589 {
 590         unsigned long phys_page, tte_vaddr, tte_data;
 591         int i, tlb_ent = sparc64_highest_locked_tlbent();
 592
 593         tte_vaddr = (unsigned long) KERNBASE;
 594         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 595         tte_data = kern_large_tte(phys_page);
 596
 597         kern_locked_tte_data = tte_data;
 598
 599         /* Now lock us into the TLBs via Hypervisor or OBP. */
 600         if (tlb_type == hypervisor) {
 601                 for (i = 0; i < num_kernel_image_mappings; i++) {
 602                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 603                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 604                         tte_vaddr += 0x400000;
 605                         tte_data += 0x400000;
 606                 }
 607         } else {
 608                 for (i = 0; i < num_kernel_image_mappings; i++) {
 609                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 610                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 611                         tte_vaddr += 0x400000;
 612                         tte_data += 0x400000;
 613                 }
 614                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 615         }
 616         if (tlb_type == cheetah_plus) {
 617                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 618                                             CTX_CHEETAH_PLUS_NUC);
 619                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 620                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 621         }
 622 }
 623
 624
 625 static void __init inherit_prom_mappings(void)
 626 {
 627         /* Now fixup OBP's idea about where we really are mapped. */
 628         printk("Remapping the kernel... ");
 629         remap_kernel();
 630         printk("done.\n");
 631 }
 632
 633 void prom_world(int enter)
 634 {
 635         if (!enter)
 636                 set_fs(get_fs());
 637
 638         __asm__ __volatile__("flushw");
 639 }
 640
 641 void __flush_dcache_range(unsigned long start, unsigned long end)
 642 {
 643         unsigned long va;
 644
 645         if (tlb_type == spitfire) {
 646                 int n = 0;
 647
 648                 for (va = start; va < end; va += 32) {
 649                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 650                         if (++n >= 512)
 651                                 break;
 652                 }
 653         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 654                 start = __pa(start);
 655                 end = __pa(end);
 656                 for (va = start; va < end; va += 32)
 657                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 658                                              "membar #Sync"
 659                                              : /* no outputs */
 660                                              : "r" (va),
 661                                                "i" (ASI_DCACHE_INVALIDATE));
 662         }
 663 }
 664 EXPORT_SYMBOL(__flush_dcache_range);
 665
 666 /* get_new_mmu_context() uses "cache + 1".  */
 667 DEFINE_SPINLOCK(ctx_alloc_lock);
 668 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 669 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 670 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 671 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 672
 673 /* Caller does TLB context flushing on local CPU if necessary.
 674  * The caller also ensures that CTX_VALID(mm->context) is false.
 675  *
 676  * We must be careful about boundary cases so that we never
 677  * let the user have CTX 0 (nucleus) or we ever use a CTX
 678  * version of zero (and thus NO_CONTEXT would not be caught
 679  * by version mis-match tests in mmu_context.h).
 680  *
 681  * Always invoked with interrupts disabled.
 682  */
 683 void get_new_mmu_context(struct mm_struct *mm)
 684 {
 685         unsigned long ctx, new_ctx;
 686         unsigned long orig_pgsz_bits;
 687         int new_version;
 688
 689         spin_lock(&ctx_alloc_lock);
 690         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 691         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 692         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 693         new_version = 0;
 694         if (new_ctx >= (1 << CTX_NR_BITS)) {
 695                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 696                 if (new_ctx >= ctx) {
 697                         int i;
 698                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 699                                 CTX_FIRST_VERSION;
 700                         if (new_ctx == 1)
 701                                 new_ctx = CTX_FIRST_VERSION;
 702
 703                         /* Don't call memset, for 16 entries that's just
 704                          * plain silly...
 705                          */
 706                         mmu_context_bmap[0] = 3;
 707                         mmu_context_bmap[1] = 0;
 708                         mmu_context_bmap[2] = 0;
 709                         mmu_context_bmap[3] = 0;
 710                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 711                                 mmu_context_bmap[i + 0] = 0;
 712                                 mmu_context_bmap[i + 1] = 0;
 713                                 mmu_context_bmap[i + 2] = 0;
 714                                 mmu_context_bmap[i + 3] = 0;
 715                         }
 716                         new_version = 1;
 717                         goto out;
 718                 }
 719         }
 720         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 721         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 722 out:
 723         tlb_context_cache = new_ctx;
 724         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 725         spin_unlock(&ctx_alloc_lock);
 726
 727         if (unlikely(new_version))
 728                 smp_new_mmu_context_version();
 729 }
 730
 731 static int numa_enabled = 1;
 732 static int numa_debug;
 733
 734 static int __init early_numa(char *p)
 735 {
 736         if (!p)
 737                 return 0;
 738
 739         if (strstr(p, "off"))
 740                 numa_enabled = 0;
 741
 742         if (strstr(p, "debug"))
 743                 numa_debug = 1;
 744
 745         return 0;
 746 }
 747 early_param("numa", early_numa);
 748
 749 #define numadbg(f, a...) \
 750 do {    if (numa_debug) \
 751                 printk(KERN_INFO f, ## a); \
 752 } while (0)
 753
 754 static void __init find_ramdisk(unsigned long phys_base)
 755 {
 756 #ifdef CONFIG_BLK_DEV_INITRD
 757         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 758                 unsigned long ramdisk_image;
 759
 760                 /* Older versions of the bootloader only supported a
 761                  * 32-bit physical address for the ramdisk image
 762                  * location, stored at sparc_ramdisk_image.  Newer
 763                  * SILO versions set sparc_ramdisk_image to zero and
 764                  * provide a full 64-bit physical address at
 765                  * sparc_ramdisk_image64.
 766                  */
 767                 ramdisk_image = sparc_ramdisk_image;
 768                 if (!ramdisk_image)
 769                         ramdisk_image = sparc_ramdisk_image64;
 770
 771                 /* Another bootloader quirk.  The bootloader normalizes
 772                  * the physical address to KERNBASE, so we have to
 773                  * factor that back out and add in the lowest valid
 774                  * physical page address to get the true physical address.
 775                  */
 776                 ramdisk_image -= KERNBASE;
 777                 ramdisk_image += phys_base;
 778
 779                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 780                         ramdisk_image, sparc_ramdisk_size);
 781
 782                 initrd_start = ramdisk_image;
 783                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 784
 785                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 786
 787                 initrd_start += PAGE_OFFSET;
 788                 initrd_end += PAGE_OFFSET;
 789         }
 790 #endif
 791 }
 792
 793 struct node_mem_mask {
 794         unsigned long mask;
 795         unsigned long val;
 796 };
 797 static struct node_mem_mask node_masks[MAX_NUMNODES];
 798 static int num_node_masks;
 799
 800 #ifdef CONFIG_NEED_MULTIPLE_NODES
 801
 802 int numa_cpu_lookup_table[NR_CPUS];
 803 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 804
 805 struct mdesc_mblock {
 806         u64     base;
 807         u64     size;
 808         u64     offset; /* RA-to-PA */
 809 };
 810 static struct mdesc_mblock *mblocks;
 811 static int num_mblocks;
 812
 813 static unsigned long ra_to_pa(unsigned long addr)
 814 {
 815         int i;
 816
 817         for (i = 0; i < num_mblocks; i++) {
 818                 struct mdesc_mblock *m = &mblocks[i];
 819
 820                 if (addr >= m->base &&
 821                     addr < (m->base + m->size)) {
 822                         addr += m->offset;
 823                         break;
 824                 }
 825         }
 826         return addr;
 827 }
 828
 829 static int find_node(unsigned long addr)
 830 {
 831         int i;
 832
 833         addr = ra_to_pa(addr);
 834         for (i = 0; i < num_node_masks; i++) {
 835                 struct node_mem_mask *p = &node_masks[i];
 836
 837                 if ((addr & p->mask) == p->val)
 838                         return i;
 839         }
 840         /* The following condition has been observed on LDOM guests.*/
 841         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
 842                 " rule. Some physical memory will be owned by node 0.");
 843         return 0;
 844 }
 845
 846 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 847 {
 848         *nid = find_node(start);
 849         start += PAGE_SIZE;
 850         while (start < end) {
 851                 int n = find_node(start);
 852
 853                 if (n != *nid)
 854                         break;
 855                 start += PAGE_SIZE;
 856         }
 857
 858         if (start > end)
 859                 start = end;
 860
 861         return start;
 862 }
 863 #endif
 864
 865 /* This must be invoked after performing all of the necessary
 866  * memblock_set_node() calls for 'nid'.  We need to be able to get
 867  * correct data from get_pfn_range_for_nid().
 868  */
 869 static void __init allocate_node_data(int nid)
 870 {
 871         struct pglist_data *p;
 872         unsigned long start_pfn, end_pfn;
 873 #ifdef CONFIG_NEED_MULTIPLE_NODES
 874         unsigned long paddr;
 875
 876         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 877         if (!paddr) {
 878                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 879                 prom_halt();
 880         }
 881         NODE_DATA(nid) = __va(paddr);
 882         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 883
 884         NODE_DATA(nid)->node_id = nid;
 885 #endif
 886
 887         p = NODE_DATA(nid);
 888
 889         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 890         p->node_start_pfn = start_pfn;
 891         p->node_spanned_pages = end_pfn - start_pfn;
 892 }
 893
 894 static void init_node_masks_nonnuma(void)
 895 {
 896 #ifdef CONFIG_NEED_MULTIPLE_NODES
 897         int i;
 898 #endif
 899
 900         numadbg("Initializing tables for non-numa.\n");
 901
 902         node_masks[0].mask = node_masks[0].val = 0;
 903         num_node_masks = 1;
 904
 905 #ifdef CONFIG_NEED_MULTIPLE_NODES
 906         for (i = 0; i < NR_CPUS; i++)
 907                 numa_cpu_lookup_table[i] = 0;
 908
 909         cpumask_setall(&numa_cpumask_lookup_table[0]);
 910 #endif
 911 }
 912
 913 #ifdef CONFIG_NEED_MULTIPLE_NODES
 914 struct pglist_data *node_data[MAX_NUMNODES];
 915
 916 EXPORT_SYMBOL(numa_cpu_lookup_table);
 917 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 918 EXPORT_SYMBOL(node_data);
 919
 920 struct mdesc_mlgroup {
 921         u64     node;
 922         u64     latency;
 923         u64     match;
 924         u64     mask;
 925 };
 926 static struct mdesc_mlgroup *mlgroups;
 927 static int num_mlgroups;
 928
 929 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 930                                    u32 cfg_handle)
 931 {
 932         u64 arc;
 933
 934         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 935                 u64 target = mdesc_arc_target(md, arc);
 936                 const u64 *val;
 937
 938                 val = mdesc_get_property(md, target,
 939                                          "cfg-handle", NULL);
 940                 if (val && *val == cfg_handle)
 941                         return 0;
 942         }
 943         return -ENODEV;
 944 }
 945
 946 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 947                                     u32 cfg_handle)
 948 {
 949         u64 arc, candidate, best_latency = ~(u64)0;
 950
 951         candidate = MDESC_NODE_NULL;
 952         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 953                 u64 target = mdesc_arc_target(md, arc);
 954                 const char *name = mdesc_node_name(md, target);
 955                 const u64 *val;
 956
 957                 if (strcmp(name, "pio-latency-group"))
 958                         continue;
 959
 960                 val = mdesc_get_property(md, target, "latency", NULL);
 961                 if (!val)
 962                         continue;
 963
 964                 if (*val < best_latency) {
 965                         candidate = target;
 966                         best_latency = *val;
 967                 }
 968         }
 969
 970         if (candidate == MDESC_NODE_NULL)
 971                 return -ENODEV;
 972
 973         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 974 }
 975
 976 int of_node_to_nid(struct device_node *dp)
 977 {
 978         const struct linux_prom64_registers *regs;
 979         struct mdesc_handle *md;
 980         u32 cfg_handle;
 981         int count, nid;
 982         u64 grp;
 983
 984         /* This is the right thing to do on currently supported
 985          * SUN4U NUMA platforms as well, as the PCI controller does
 986          * not sit behind any particular memory controller.
 987          */
 988         if (!mlgroups)
 989                 return -1;
 990
 991         regs = of_get_property(dp, "reg", NULL);
 992         if (!regs)
 993                 return -1;
 994
 995         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 996
 997         md = mdesc_grab();
 998
 999         count = 0;
1000         nid = -1;
1001         mdesc_for_each_node_by_name(md, grp, "group") {
1002                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1003                         nid = count;
1004                         break;
1005                 }
1006                 count++;
1007         }
1008
1009         mdesc_release(md);
1010
1011         return nid;
1012 }
1013
1014 static void __init add_node_ranges(void)
1015 {
1016         struct memblock_region *reg;
1017
1018         for_each_memblock(memory, reg) {
1019                 unsigned long size = reg->size;
1020                 unsigned long start, end;
1021
1022                 start = reg->base;
1023                 end = start + size;
1024                 while (start < end) {
1025                         unsigned long this_end;
1026                         int nid;
1027
1028                         this_end = memblock_nid_range(start, end, &nid);
1029
1030                         numadbg("Setting memblock NUMA node nid[%d] "
1031                                 "start[%lx] end[%lx]\n",
1032                                 nid, start, this_end);
1033
1034                         memblock_set_node(start, this_end - start,
1035                                           &memblock.memory, nid);
1036                         start = this_end;
1037                 }
1038         }
1039 }
1040
1041 static int __init grab_mlgroups(struct mdesc_handle *md)
1042 {
1043         unsigned long paddr;
1044         int count = 0;
1045         u64 node;
1046
1047         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1048                 count++;
1049         if (!count)
1050                 return -ENOENT;
1051
1052         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1053                           SMP_CACHE_BYTES);
1054         if (!paddr)
1055                 return -ENOMEM;
1056
1057         mlgroups = __va(paddr);
1058         num_mlgroups = count;
1059
1060         count = 0;
1061         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1062                 struct mdesc_mlgroup *m = &mlgroups[count++];
1063                 const u64 *val;
1064
1065                 m->node = node;
1066
1067                 val = mdesc_get_property(md, node, "latency", NULL);
1068                 m->latency = *val;
1069                 val = mdesc_get_property(md, node, "address-match", NULL);
1070                 m->match = *val;
1071                 val = mdesc_get_property(md, node, "address-mask", NULL);
1072                 m->mask = *val;
1073
1074                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1075                         "match[%llx] mask[%llx]\n",
1076                         count - 1, m->node, m->latency, m->match, m->mask);
1077         }
1078
1079         return 0;
1080 }
1081
1082 static int __init grab_mblocks(struct mdesc_handle *md)
1083 {
1084         unsigned long paddr;
1085         int count = 0;
1086         u64 node;
1087
1088         mdesc_for_each_node_by_name(md, node, "mblock")
1089                 count++;
1090         if (!count)
1091                 return -ENOENT;
1092
1093         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1094                           SMP_CACHE_BYTES);
1095         if (!paddr)
1096                 return -ENOMEM;
1097
1098         mblocks = __va(paddr);
1099         num_mblocks = count;
1100
1101         count = 0;
1102         mdesc_for_each_node_by_name(md, node, "mblock") {
1103                 struct mdesc_mblock *m = &mblocks[count++];
1104                 const u64 *val;
1105
1106                 val = mdesc_get_property(md, node, "base", NULL);
1107                 m->base = *val;
1108                 val = mdesc_get_property(md, node, "size", NULL);
1109                 m->size = *val;
1110                 val = mdesc_get_property(md, node,
1111                                          "address-congruence-offset", NULL);
1112
1113                 /* The address-congruence-offset property is optional.
1114                  * Explicity zero it be identifty this.
1115                  */
1116                 if (val)
1117                         m->offset = *val;
1118                 else
1119                         m->offset = 0UL;
1120
1121                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1122                         count - 1, m->base, m->size, m->offset);
1123         }
1124
1125         return 0;
1126 }
1127
1128 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1129                                                u64 grp, cpumask_t *mask)
1130 {
1131         u64 arc;
1132
1133         cpumask_clear(mask);
1134
1135         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1136                 u64 target = mdesc_arc_target(md, arc);
1137                 const char *name = mdesc_node_name(md, target);
1138                 const u64 *id;
1139
1140                 if (strcmp(name, "cpu"))
1141                         continue;
1142                 id = mdesc_get_property(md, target, "id", NULL);
1143                 if (*id < nr_cpu_ids)
1144                         cpumask_set_cpu(*id, mask);
1145         }
1146 }
1147
1148 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1149 {
1150         int i;
1151
1152         for (i = 0; i < num_mlgroups; i++) {
1153                 struct mdesc_mlgroup *m = &mlgroups[i];
1154                 if (m->node == node)
1155                         return m;
1156         }
1157         return NULL;
1158 }
1159
1160 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1161                                       int index)
1162 {
1163         struct mdesc_mlgroup *candidate = NULL;
1164         u64 arc, best_latency = ~(u64)0;
1165         struct node_mem_mask *n;
1166
1167         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1168                 u64 target = mdesc_arc_target(md, arc);
1169                 struct mdesc_mlgroup *m = find_mlgroup(target);
1170                 if (!m)
1171                         continue;
1172                 if (m->latency < best_latency) {
1173                         candidate = m;
1174                         best_latency = m->latency;
1175                 }
1176         }
1177         if (!candidate)
1178                 return -ENOENT;
1179
1180         if (num_node_masks != index) {
1181                 printk(KERN_ERR "Inconsistent NUMA state, "
1182                        "index[%d] != num_node_masks[%d]\n",
1183                        index, num_node_masks);
1184                 return -EINVAL;
1185         }
1186
1187         n = &node_masks[num_node_masks++];
1188
1189         n->mask = candidate->mask;
1190         n->val = candidate->match;
1191
1192         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1193                 index, n->mask, n->val, candidate->latency);
1194
1195         return 0;
1196 }
1197
1198 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1199                                          int index)
1200 {
1201         cpumask_t mask;
1202         int cpu;
1203
1204         numa_parse_mdesc_group_cpus(md, grp, &mask);
1205
1206         for_each_cpu(cpu, &mask)
1207                 numa_cpu_lookup_table[cpu] = index;
1208         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1209
1210         if (numa_debug) {
1211                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1212                 for_each_cpu(cpu, &mask)
1213                         printk("%d ", cpu);
1214                 printk("]\n");
1215         }
1216
1217         return numa_attach_mlgroup(md, grp, index);
1218 }
1219
1220 static int __init numa_parse_mdesc(void)
1221 {
1222         struct mdesc_handle *md = mdesc_grab();
1223         int i, err, count;
1224         u64 node;
1225
1226         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1227         if (node == MDESC_NODE_NULL) {
1228                 mdesc_release(md);
1229                 return -ENOENT;
1230         }
1231
1232         err = grab_mblocks(md);
1233         if (err < 0)
1234                 goto out;
1235
1236         err = grab_mlgroups(md);
1237         if (err < 0)
1238                 goto out;
1239
1240         count = 0;
1241         mdesc_for_each_node_by_name(md, node, "group") {
1242                 err = numa_parse_mdesc_group(md, node, count);
1243                 if (err < 0)
1244                         break;
1245                 count++;
1246         }
1247
1248         add_node_ranges();
1249
1250         for (i = 0; i < num_node_masks; i++) {
1251                 allocate_node_data(i);
1252                 node_set_online(i);
1253         }
1254
1255         err = 0;
1256 out:
1257         mdesc_release(md);
1258         return err;
1259 }
1260
1261 static int __init numa_parse_jbus(void)
1262 {
1263         unsigned long cpu, index;
1264
1265         /* NUMA node id is encoded in bits 36 and higher, and there is
1266          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1267          */
1268         index = 0;
1269         for_each_present_cpu(cpu) {
1270                 numa_cpu_lookup_table[cpu] = index;
1271                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1272                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1273                 node_masks[index].val = cpu << 36UL;
1274
1275                 index++;
1276         }
1277         num_node_masks = index;
1278
1279         add_node_ranges();
1280
1281         for (index = 0; index < num_node_masks; index++) {
1282                 allocate_node_data(index);
1283                 node_set_online(index);
1284         }
1285
1286         return 0;
1287 }
1288
1289 static int __init numa_parse_sun4u(void)
1290 {
1291         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1292                 unsigned long ver;
1293
1294                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1295                 if ((ver >> 32UL) == __JALAPENO_ID ||
1296                     (ver >> 32UL) == __SERRANO_ID)
1297                         return numa_parse_jbus();
1298         }
1299         return -1;
1300 }
1301
1302 static int __init bootmem_init_numa(void)
1303 {
1304         int err = -1;
1305
1306         numadbg("bootmem_init_numa()\n");
1307
1308         if (numa_enabled) {
1309                 if (tlb_type == hypervisor)
1310                         err = numa_parse_mdesc();
1311                 else
1312                         err = numa_parse_sun4u();
1313         }
1314         return err;
1315 }
1316
1317 #else
1318
1319 static int bootmem_init_numa(void)
1320 {
1321         return -1;
1322 }
1323
1324 #endif
1325
1326 static void __init bootmem_init_nonnuma(void)
1327 {
1328         unsigned long top_of_ram = memblock_end_of_DRAM();
1329         unsigned long total_ram = memblock_phys_mem_size();
1330
1331         numadbg("bootmem_init_nonnuma()\n");
1332
1333         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1334                top_of_ram, total_ram);
1335         printk(KERN_INFO "Memory hole size: %ldMB\n",
1336                (top_of_ram - total_ram) >> 20);
1337
1338         init_node_masks_nonnuma();
1339         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1340         allocate_node_data(0);
1341         node_set_online(0);
1342 }
1343
1344 static unsigned long __init bootmem_init(unsigned long phys_base)
1345 {
1346         unsigned long end_pfn;
1347
1348         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1349         max_pfn = max_low_pfn = end_pfn;
1350         min_low_pfn = (phys_base >> PAGE_SHIFT);
1351
1352         if (bootmem_init_numa() < 0)
1353                 bootmem_init_nonnuma();
1354
1355         /* Dump memblock with node info. */
1356         memblock_dump_all();
1357
1358         /* XXX cpu notifier XXX */
1359
1360         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1361         sparse_init();
1362
1363         return end_pfn;
1364 }
1365
1366 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1367 static int pall_ents __initdata;
1368
1369 static unsigned long max_phys_bits = 40;
1370
1371 bool kern_addr_valid(unsigned long addr)
1372 {
1373         pgd_t *pgd;
1374         pud_t *pud;
1375         pmd_t *pmd;
1376         pte_t *pte;
1377
1378         if ((long)addr < 0L) {
1379                 unsigned long pa = __pa(addr);
1380
1381                 if ((addr >> max_phys_bits) != 0UL)
1382                         return false;
1383
1384                 return pfn_valid(pa >> PAGE_SHIFT);
1385         }
1386
1387         if (addr >= (unsigned long) KERNBASE &&
1388             addr < (unsigned long)&_end)
1389                 return true;
1390
1391         pgd = pgd_offset_k(addr);
1392         if (pgd_none(*pgd))
1393                 return 0;
1394
1395         pud = pud_offset(pgd, addr);
1396         if (pud_none(*pud))
1397                 return 0;
1398
1399         if (pud_large(*pud))
1400                 return pfn_valid(pud_pfn(*pud));
1401
1402         pmd = pmd_offset(pud, addr);
1403         if (pmd_none(*pmd))
1404                 return 0;
1405
1406         if (pmd_large(*pmd))
1407                 return pfn_valid(pmd_pfn(*pmd));
1408
1409         pte = pte_offset_kernel(pmd, addr);
1410         if (pte_none(*pte))
1411                 return 0;
1412
1413         return pfn_valid(pte_pfn(*pte));
1414 }
1415 EXPORT_SYMBOL(kern_addr_valid);
1416
1417 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1418                                               unsigned long vend,
1419                                               pud_t *pud)
1420 {
1421         const unsigned long mask16gb = (1UL << 34) - 1UL;
1422         u64 pte_val = vstart;
1423
1424         /* Each PUD is 8GB */
1425         if ((vstart & mask16gb) ||
1426             (vend - vstart <= mask16gb)) {
1427                 pte_val ^= kern_linear_pte_xor[2];
1428                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1429
1430                 return vstart + PUD_SIZE;
1431         }
1432
1433         pte_val ^= kern_linear_pte_xor[3];
1434         pte_val |= _PAGE_PUD_HUGE;
1435
1436         vend = vstart + mask16gb + 1UL;
1437         while (vstart < vend) {
1438                 pud_val(*pud) = pte_val;
1439
1440                 pte_val += PUD_SIZE;
1441                 vstart += PUD_SIZE;
1442                 pud++;
1443         }
1444         return vstart;
1445 }
1446
1447 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1448                                    bool guard)
1449 {
1450         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1451                 return true;
1452
1453         return false;
1454 }
1455
1456 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1457                                               unsigned long vend,
1458                                               pmd_t *pmd)
1459 {
1460         const unsigned long mask256mb = (1UL << 28) - 1UL;
1461         const unsigned long mask2gb = (1UL << 31) - 1UL;
1462         u64 pte_val = vstart;
1463
1464         /* Each PMD is 8MB */
1465         if ((vstart & mask256mb) ||
1466             (vend - vstart <= mask256mb)) {
1467                 pte_val ^= kern_linear_pte_xor[0];
1468                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1469
1470                 return vstart + PMD_SIZE;
1471         }
1472
1473         if ((vstart & mask2gb) ||
1474             (vend - vstart <= mask2gb)) {
1475                 pte_val ^= kern_linear_pte_xor[1];
1476                 pte_val |= _PAGE_PMD_HUGE;
1477                 vend = vstart + mask256mb + 1UL;
1478         } else {
1479                 pte_val ^= kern_linear_pte_xor[2];
1480                 pte_val |= _PAGE_PMD_HUGE;
1481                 vend = vstart + mask2gb + 1UL;
1482         }
1483
1484         while (vstart < vend) {
1485                 pmd_val(*pmd) = pte_val;
1486
1487                 pte_val += PMD_SIZE;
1488                 vstart += PMD_SIZE;
1489                 pmd++;
1490         }
1491
1492         return vstart;
1493 }
1494
1495 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1496                                    bool guard)
1497 {
1498         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1499                 return true;
1500
1501         return false;
1502 }
1503
1504 static unsigned long __ref kernel_map_range(unsigned long pstart,
1505                                             unsigned long pend, pgprot_t prot,
1506                                             bool use_huge)
1507 {
1508         unsigned long vstart = PAGE_OFFSET + pstart;
1509         unsigned long vend = PAGE_OFFSET + pend;
1510         unsigned long alloc_bytes = 0UL;
1511
1512         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1513                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1514                             vstart, vend);
1515                 prom_halt();
1516         }
1517
1518         while (vstart < vend) {
1519                 unsigned long this_end, paddr = __pa(vstart);
1520                 pgd_t *pgd = pgd_offset_k(vstart);
1521                 pud_t *pud;
1522                 pmd_t *pmd;
1523                 pte_t *pte;
1524
1525                 if (pgd_none(*pgd)) {
1526                         pud_t *new;
1527
1528                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1529                         alloc_bytes += PAGE_SIZE;
1530                         pgd_populate(&init_mm, pgd, new);
1531                 }
1532                 pud = pud_offset(pgd, vstart);
1533                 if (pud_none(*pud)) {
1534                         pmd_t *new;
1535
1536                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1537                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1538                                 continue;
1539                         }
1540                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1541                         alloc_bytes += PAGE_SIZE;
1542                         pud_populate(&init_mm, pud, new);
1543                 }
1544
1545                 pmd = pmd_offset(pud, vstart);
1546                 if (pmd_none(*pmd)) {
1547                         pte_t *new;
1548
1549                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1550                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1551                                 continue;
1552                         }
1553                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1554                         alloc_bytes += PAGE_SIZE;
1555                         pmd_populate_kernel(&init_mm, pmd, new);
1556                 }
1557
1558                 pte = pte_offset_kernel(pmd, vstart);
1559                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1560                 if (this_end > vend)
1561                         this_end = vend;
1562
1563                 while (vstart < this_end) {
1564                         pte_val(*pte) = (paddr | pgprot_val(prot));
1565
1566                         vstart += PAGE_SIZE;
1567                         paddr += PAGE_SIZE;
1568                         pte++;
1569                 }
1570         }
1571
1572         return alloc_bytes;
1573 }
1574
1575 static void __init flush_all_kernel_tsbs(void)
1576 {
1577         int i;
1578
1579         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1580                 struct tsb *ent = &swapper_tsb[i];
1581
1582                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1583         }
1584 #ifndef CONFIG_DEBUG_PAGEALLOC
1585         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1586                 struct tsb *ent = &swapper_4m_tsb[i];
1587
1588                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1589         }
1590 #endif
1591 }
1592
1593 extern unsigned int kvmap_linear_patch[1];
1594
1595 static void __init kernel_physical_mapping_init(void)
1596 {
1597         unsigned long i, mem_alloced = 0UL;
1598         bool use_huge = true;
1599
1600 #ifdef CONFIG_DEBUG_PAGEALLOC
1601         use_huge = false;
1602 #endif
1603         for (i = 0; i < pall_ents; i++) {
1604                 unsigned long phys_start, phys_end;
1605
1606                 phys_start = pall[i].phys_addr;
1607                 phys_end = phys_start + pall[i].reg_size;
1608
1609                 mem_alloced += kernel_map_range(phys_start, phys_end,
1610                                                 PAGE_KERNEL, use_huge);
1611         }
1612
1613         printk("Allocated %ld bytes for kernel page tables.\n",
1614                mem_alloced);
1615
1616         kvmap_linear_patch[0] = 0x01000000; /* nop */
1617         flushi(&kvmap_linear_patch[0]);
1618
1619         flush_all_kernel_tsbs();
1620
1621         __flush_tlb_all();
1622 }
1623
1624 #ifdef CONFIG_DEBUG_PAGEALLOC
1625 void __kernel_map_pages(struct page *page, int numpages, int enable)
1626 {
1627         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1628         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1629
1630         kernel_map_range(phys_start, phys_end,
1631                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1632
1633         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1634                                PAGE_OFFSET + phys_end);
1635
1636         /* we should perform an IPI and flush all tlbs,
1637          * but that can deadlock->flush only current cpu.
1638          */
1639         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1640                                  PAGE_OFFSET + phys_end);
1641 }
1642 #endif
1643
1644 unsigned long __init find_ecache_flush_span(unsigned long size)
1645 {
1646         int i;
1647
1648         for (i = 0; i < pavail_ents; i++) {
1649                 if (pavail[i].reg_size >= size)
1650                         return pavail[i].phys_addr;
1651         }
1652
1653         return ~0UL;
1654 }
1655
1656 unsigned long PAGE_OFFSET;
1657 EXPORT_SYMBOL(PAGE_OFFSET);
1658
1659 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1660 EXPORT_SYMBOL(VMALLOC_END);
1661
1662 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1663 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1664
1665 static void __init setup_page_offset(void)
1666 {
1667         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1668                 /* Cheetah/Panther support a full 64-bit virtual
1669                  * address, so we can use all that our page tables
1670                  * support.
1671                  */
1672                 sparc64_va_hole_top =    0xfff0000000000000UL;
1673                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1674
1675                 max_phys_bits = 42;
1676         } else if (tlb_type == hypervisor) {
1677                 switch (sun4v_chip_type) {
1678                 case SUN4V_CHIP_NIAGARA1:
1679                 case SUN4V_CHIP_NIAGARA2:
1680                         /* T1 and T2 support 48-bit virtual addresses.  */
1681                         sparc64_va_hole_top =    0xffff800000000000UL;
1682                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1683
1684                         max_phys_bits = 39;
1685                         break;
1686                 case SUN4V_CHIP_NIAGARA3:
1687                         /* T3 supports 48-bit virtual addresses.  */
1688                         sparc64_va_hole_top =    0xffff800000000000UL;
1689                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1690
1691                         max_phys_bits = 43;
1692                         break;
1693                 case SUN4V_CHIP_NIAGARA4:
1694                 case SUN4V_CHIP_NIAGARA5:
1695                 case SUN4V_CHIP_SPARC64X:
1696                 case SUN4V_CHIP_SPARC_M6:
1697                         /* T4 and later support 52-bit virtual addresses.  */
1698                         sparc64_va_hole_top =    0xfff8000000000000UL;
1699                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1700                         max_phys_bits = 47;
1701                         break;
1702                 case SUN4V_CHIP_SPARC_M7:
1703                 default:
1704                         /* M7 and later support 52-bit virtual addresses.  */
1705                         sparc64_va_hole_top =    0xfff8000000000000UL;
1706                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1707                         max_phys_bits = 49;
1708                         break;
1709                 }
1710         }
1711
1712         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1713                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1714                             max_phys_bits);
1715                 prom_halt();
1716         }
1717
1718         PAGE_OFFSET = sparc64_va_hole_top;
1719         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1720                        (sparc64_va_hole_bottom >> 2));
1721
1722         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1723                 PAGE_OFFSET, max_phys_bits);
1724         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1725                 VMALLOC_START, VMALLOC_END);
1726         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1727                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1728 }
1729
1730 static void __init tsb_phys_patch(void)
1731 {
1732         struct tsb_ldquad_phys_patch_entry *pquad;
1733         struct tsb_phys_patch_entry *p;
1734
1735         pquad = &__tsb_ldquad_phys_patch;
1736         while (pquad < &__tsb_ldquad_phys_patch_end) {
1737                 unsigned long addr = pquad->addr;
1738
1739                 if (tlb_type == hypervisor)
1740                         *(unsigned int *) addr = pquad->sun4v_insn;
1741                 else
1742                         *(unsigned int *) addr = pquad->sun4u_insn;
1743                 wmb();
1744                 __asm__ __volatile__("flush     %0"
1745                                      : /* no outputs */
1746                                      : "r" (addr));
1747
1748                 pquad++;
1749         }
1750
1751         p = &__tsb_phys_patch;
1752         while (p < &__tsb_phys_patch_end) {
1753                 unsigned long addr = p->addr;
1754
1755                 *(unsigned int *) addr = p->insn;
1756                 wmb();
1757                 __asm__ __volatile__("flush     %0"
1758                                      : /* no outputs */
1759                                      : "r" (addr));
1760
1761                 p++;
1762         }
1763 }
1764
1765 /* Don't mark as init, we give this to the Hypervisor.  */
1766 #ifndef CONFIG_DEBUG_PAGEALLOC
1767 #define NUM_KTSB_DESCR  2
1768 #else
1769 #define NUM_KTSB_DESCR  1
1770 #endif
1771 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1772
1773 /* The swapper TSBs are loaded with a base sequence of:
1774  *
1775  *      sethi   %uhi(SYMBOL), REG1
1776  *      sethi   %hi(SYMBOL), REG2
1777  *      or      REG1, %ulo(SYMBOL), REG1
1778  *      or      REG2, %lo(SYMBOL), REG2
1779  *      sllx    REG1, 32, REG1
1780  *      or      REG1, REG2, REG1
1781  *
1782  * When we use physical addressing for the TSB accesses, we patch the
1783  * first four instructions in the above sequence.
1784  */
1785
1786 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1787 {
1788         unsigned long high_bits, low_bits;
1789
1790         high_bits = (pa >> 32) & 0xffffffff;
1791         low_bits = (pa >> 0) & 0xffffffff;
1792
1793         while (start < end) {
1794                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1795
1796                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1797                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1798
1799                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1800                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1801
1802                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1803                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
1804
1805                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1806                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
1807
1808                 start++;
1809         }
1810 }
1811
1812 static void ktsb_phys_patch(void)
1813 {
1814         extern unsigned int __swapper_tsb_phys_patch;
1815         extern unsigned int __swapper_tsb_phys_patch_end;
1816         unsigned long ktsb_pa;
1817
1818         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1819         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1820                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1821 #ifndef CONFIG_DEBUG_PAGEALLOC
1822         {
1823         extern unsigned int __swapper_4m_tsb_phys_patch;
1824         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1825         ktsb_pa = (kern_base +
1826                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1827         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1828                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1829         }
1830 #endif
1831 }
1832
1833 static void __init sun4v_ktsb_init(void)
1834 {
1835         unsigned long ktsb_pa;
1836
1837         /* First KTSB for PAGE_SIZE mappings.  */
1838         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1839
1840         switch (PAGE_SIZE) {
1841         case 8 * 1024:
1842         default:
1843                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1844                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1845                 break;
1846
1847         case 64 * 1024:
1848                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1849                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1850                 break;
1851
1852         case 512 * 1024:
1853                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1854                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1855                 break;
1856
1857         case 4 * 1024 * 1024:
1858                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1859                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1860                 break;
1861         }
1862
1863         ktsb_descr[0].assoc = 1;
1864         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1865         ktsb_descr[0].ctx_idx = 0;
1866         ktsb_descr[0].tsb_base = ktsb_pa;
1867         ktsb_descr[0].resv = 0;
1868
1869 #ifndef CONFIG_DEBUG_PAGEALLOC
1870         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1871         ktsb_pa = (kern_base +
1872                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1873
1874         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1875         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1876                                     HV_PGSZ_MASK_256MB |
1877                                     HV_PGSZ_MASK_2GB |
1878                                     HV_PGSZ_MASK_16GB) &
1879                                    cpu_pgsz_mask);
1880         ktsb_descr[1].assoc = 1;
1881         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1882         ktsb_descr[1].ctx_idx = 0;
1883         ktsb_descr[1].tsb_base = ktsb_pa;
1884         ktsb_descr[1].resv = 0;
1885 #endif
1886 }
1887
1888 void sun4v_ktsb_register(void)
1889 {
1890         unsigned long pa, ret;
1891
1892         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1893
1894         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1895         if (ret != 0) {
1896                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1897                             "errors with %lx\n", pa, ret);
1898                 prom_halt();
1899         }
1900 }
1901
1902 static void __init sun4u_linear_pte_xor_finalize(void)
1903 {
1904 #ifndef CONFIG_DEBUG_PAGEALLOC
1905         /* This is where we would add Panther support for
1906          * 32MB and 256MB pages.
1907          */
1908 #endif
1909 }
1910
1911 static void __init sun4v_linear_pte_xor_finalize(void)
1912 {
1913         unsigned long pagecv_flag;
1914
1915         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1916          * enables MCD error. Do not set bit 9 on M7 processor.
1917          */
1918         switch (sun4v_chip_type) {
1919         case SUN4V_CHIP_SPARC_M7:
1920                 pagecv_flag = 0x00;
1921                 break;
1922         default:
1923                 pagecv_flag = _PAGE_CV_4V;
1924                 break;
1925         }
1926 #ifndef CONFIG_DEBUG_PAGEALLOC
1927         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1928                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1929                         PAGE_OFFSET;
1930                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
1931                                            _PAGE_P_4V | _PAGE_W_4V);
1932         } else {
1933                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1934         }
1935
1936         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1937                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1938                         PAGE_OFFSET;
1939                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
1940                                            _PAGE_P_4V | _PAGE_W_4V);
1941         } else {
1942                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1943         }
1944
1945         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1946                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1947                         PAGE_OFFSET;
1948                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
1949                                            _PAGE_P_4V | _PAGE_W_4V);
1950         } else {
1951                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1952         }
1953 #endif
1954 }
1955
1956 /* paging_init() sets up the page tables */
1957
1958 static unsigned long last_valid_pfn;
1959
1960 static void sun4u_pgprot_init(void);
1961 static void sun4v_pgprot_init(void);
1962
1963 static phys_addr_t __init available_memory(void)
1964 {
1965         phys_addr_t available = 0ULL;
1966         phys_addr_t pa_start, pa_end;
1967         u64 i;
1968
1969         for_each_free_mem_range(i, NUMA_NO_NODE, &pa_start, &pa_end, NULL)
1970                 available = available + (pa_end  - pa_start);
1971
1972         return available;
1973 }
1974
1975 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
1976 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
1977 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1978 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1979 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1980 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1981
1982 /* We need to exclude reserved regions. This exclusion will include
1983  * vmlinux and initrd. To be more precise the initrd size could be used to
1984  * compute a new lower limit because it is freed later during initialization.
1985  */
1986 static void __init reduce_memory(phys_addr_t limit_ram)
1987 {
1988         phys_addr_t avail_ram = available_memory();
1989         phys_addr_t pa_start, pa_end;
1990         u64 i;
1991
1992         if (limit_ram >= avail_ram)
1993                 return;
1994
1995         for_each_free_mem_range(i, NUMA_NO_NODE, &pa_start, &pa_end, NULL) {
1996                 phys_addr_t region_size = pa_end - pa_start;
1997                 phys_addr_t clip_start = pa_start;
1998
1999                 avail_ram = avail_ram - region_size;
2000                 /* Are we consuming too much? */
2001                 if (avail_ram < limit_ram) {
2002                         phys_addr_t give_back = limit_ram - avail_ram;
2003
2004                         region_size = region_size - give_back;
2005                         clip_start = clip_start + give_back;
2006                 }
2007
2008                 memblock_remove(clip_start, region_size);
2009
2010                 if (avail_ram <= limit_ram)
2011                         break;
2012                 i = 0UL;
2013         }
2014 }
2015
2016 void __init paging_init(void)
2017 {
2018         unsigned long end_pfn, shift, phys_base;
2019         unsigned long real_end, i;
2020         int node;
2021
2022         setup_page_offset();
2023
2024         /* These build time checkes make sure that the dcache_dirty_cpu()
2025          * page->flags usage will work.
2026          *
2027          * When a page gets marked as dcache-dirty, we store the
2028          * cpu number starting at bit 32 in the page->flags.  Also,
2029          * functions like clear_dcache_dirty_cpu use the cpu mask
2030          * in 13-bit signed-immediate instruction fields.
2031          */
2032
2033         /*
2034          * Page flags must not reach into upper 32 bits that are used
2035          * for the cpu number
2036          */
2037         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2038
2039         /*
2040          * The bit fields placed in the high range must not reach below
2041          * the 32 bit boundary. Otherwise we cannot place the cpu field
2042          * at the 32 bit boundary.
2043          */
2044         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2045                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2046
2047         BUILD_BUG_ON(NR_CPUS > 4096);
2048
2049         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2050         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2051
2052         /* Invalidate both kernel TSBs.  */
2053         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2054 #ifndef CONFIG_DEBUG_PAGEALLOC
2055         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2056 #endif
2057
2058         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2059          * bit on M7 processor. This is a conflicting usage of the same
2060          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2061          * Detection error on all pages and this will lead to problems
2062          * later. Kernel does not run with MCD enabled and hence rest
2063          * of the required steps to fully configure memory corruption
2064          * detection are not taken. We need to ensure TTE.mcde is not
2065          * set on M7 processor. Compute the value of cacheability
2066          * flag for use later taking this into consideration.
2067          */
2068         switch (sun4v_chip_type) {
2069         case SUN4V_CHIP_SPARC_M7:
2070                 page_cache4v_flag = _PAGE_CP_4V;
2071                 break;
2072         default:
2073                 page_cache4v_flag = _PAGE_CACHE_4V;
2074                 break;
2075         }
2076
2077         if (tlb_type == hypervisor)
2078                 sun4v_pgprot_init();
2079         else
2080                 sun4u_pgprot_init();
2081
2082         if (tlb_type == cheetah_plus ||
2083             tlb_type == hypervisor) {
2084                 tsb_phys_patch();
2085                 ktsb_phys_patch();
2086         }
2087
2088         if (tlb_type == hypervisor)
2089                 sun4v_patch_tlb_handlers();
2090
2091         /* Find available physical memory...
2092          *
2093          * Read it twice in order to work around a bug in openfirmware.
2094          * The call to grab this table itself can cause openfirmware to
2095          * allocate memory, which in turn can take away some space from
2096          * the list of available memory.  Reading it twice makes sure
2097          * we really do get the final value.
2098          */
2099         read_obp_translations();
2100         read_obp_memory("reg", &pall[0], &pall_ents);
2101         read_obp_memory("available", &pavail[0], &pavail_ents);
2102         read_obp_memory("available", &pavail[0], &pavail_ents);
2103
2104         phys_base = 0xffffffffffffffffUL;
2105         for (i = 0; i < pavail_ents; i++) {
2106                 phys_base = min(phys_base, pavail[i].phys_addr);
2107                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2108         }
2109
2110         memblock_reserve(kern_base, kern_size);
2111
2112         find_ramdisk(phys_base);
2113
2114         if (cmdline_memory_size)
2115                 reduce_memory(cmdline_memory_size);
2116
2117         memblock_allow_resize();
2118         memblock_dump_all();
2119
2120         set_bit(0, mmu_context_bmap);
2121
2122         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2123
2124         real_end = (unsigned long)_end;
2125         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2126         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2127                num_kernel_image_mappings);
2128
2129         /* Set kernel pgd to upper alias so physical page computations
2130          * work.
2131          */
2132         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2133
2134         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2135
2136         inherit_prom_mappings();
2137
2138         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2139         setup_tba();
2140
2141         __flush_tlb_all();
2142
2143         prom_build_devicetree();
2144         of_populate_present_mask();
2145 #ifndef CONFIG_SMP
2146         of_fill_in_cpu_data();
2147 #endif
2148
2149         if (tlb_type == hypervisor) {
2150                 sun4v_mdesc_init();
2151                 mdesc_populate_present_mask(cpu_all_mask);
2152 #ifndef CONFIG_SMP
2153                 mdesc_fill_in_cpu_data(cpu_all_mask);
2154 #endif
2155                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2156
2157                 sun4v_linear_pte_xor_finalize();
2158
2159                 sun4v_ktsb_init();
2160                 sun4v_ktsb_register();
2161         } else {
2162                 unsigned long impl, ver;
2163
2164                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2165                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2166
2167                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2168                 impl = ((ver >> 32) & 0xffff);
2169                 if (impl == PANTHER_IMPL)
2170                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2171                                           HV_PGSZ_MASK_256MB);
2172
2173                 sun4u_linear_pte_xor_finalize();
2174         }
2175
2176         /* Flush the TLBs and the 4M TSB so that the updated linear
2177          * pte XOR settings are realized for all mappings.
2178          */
2179         __flush_tlb_all();
2180 #ifndef CONFIG_DEBUG_PAGEALLOC
2181         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2182 #endif
2183         __flush_tlb_all();
2184
2185         /* Setup bootmem... */
2186         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2187
2188         /* Once the OF device tree and MDESC have been setup, we know
2189          * the list of possible cpus.  Therefore we can allocate the
2190          * IRQ stacks.
2191          */
2192         for_each_possible_cpu(i) {
2193                 node = cpu_to_node(i);
2194
2195                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2196                                                         THREAD_SIZE,
2197                                                         THREAD_SIZE, 0);
2198                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2199                                                         THREAD_SIZE,
2200                                                         THREAD_SIZE, 0);
2201         }
2202
2203         kernel_physical_mapping_init();
2204
2205         {
2206                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2207
2208                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2209
2210                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2211
2212                 free_area_init_nodes(max_zone_pfns);
2213         }
2214
2215         printk("Booting Linux...\n");
2216 }
2217
2218 int page_in_phys_avail(unsigned long paddr)
2219 {
2220         int i;
2221
2222         paddr &= PAGE_MASK;
2223
2224         for (i = 0; i < pavail_ents; i++) {
2225                 unsigned long start, end;
2226
2227                 start = pavail[i].phys_addr;
2228                 end = start + pavail[i].reg_size;
2229
2230                 if (paddr >= start && paddr < end)
2231                         return 1;
2232         }
2233         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2234                 return 1;
2235 #ifdef CONFIG_BLK_DEV_INITRD
2236         if (paddr >= __pa(initrd_start) &&
2237             paddr < __pa(PAGE_ALIGN(initrd_end)))
2238                 return 1;
2239 #endif
2240
2241         return 0;
2242 }
2243
2244 static void __init register_page_bootmem_info(void)
2245 {
2246 #ifdef CONFIG_NEED_MULTIPLE_NODES
2247         int i;
2248
2249         for_each_online_node(i)
2250                 if (NODE_DATA(i)->node_spanned_pages)
2251                         register_page_bootmem_info_node(NODE_DATA(i));
2252 #endif
2253 }
2254 void __init mem_init(void)
2255 {
2256         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2257
2258         register_page_bootmem_info();
2259         free_all_bootmem();
2260
2261         /*
2262          * Set up the zero page, mark it reserved, so that page count
2263          * is not manipulated when freeing the page from user ptes.
2264          */
2265         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2266         if (mem_map_zero == NULL) {
2267                 prom_printf("paging_init: Cannot alloc zero page.\n");
2268                 prom_halt();
2269         }
2270         mark_page_reserved(mem_map_zero);
2271
2272         mem_init_print_info(NULL);
2273
2274         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2275                 cheetah_ecache_flush_init();
2276 }
2277
2278 void free_initmem(void)
2279 {
2280         unsigned long addr, initend;
2281         int do_free = 1;
2282
2283         /* If the physical memory maps were trimmed by kernel command
2284          * line options, don't even try freeing this initmem stuff up.
2285          * The kernel image could have been in the trimmed out region
2286          * and if so the freeing below will free invalid page structs.
2287          */
2288         if (cmdline_memory_size)
2289                 do_free = 0;
2290
2291         /*
2292          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2293          */
2294         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2295         initend = (unsigned long)(__init_end) & PAGE_MASK;
2296         for (; addr < initend; addr += PAGE_SIZE) {
2297                 unsigned long page;
2298
2299                 page = (addr +
2300                         ((unsigned long) __va(kern_base)) -
2301                         ((unsigned long) KERNBASE));
2302                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2303
2304                 if (do_free)
2305                         free_reserved_page(virt_to_page(page));
2306         }
2307 }
2308
2309 #ifdef CONFIG_BLK_DEV_INITRD
2310 void free_initrd_mem(unsigned long start, unsigned long end)
2311 {
2312         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2313                            "initrd");
2314 }
2315 #endif
2316
2317 pgprot_t PAGE_KERNEL __read_mostly;
2318 EXPORT_SYMBOL(PAGE_KERNEL);
2319
2320 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2321 pgprot_t PAGE_COPY __read_mostly;
2322
2323 pgprot_t PAGE_SHARED __read_mostly;
2324 EXPORT_SYMBOL(PAGE_SHARED);
2325
2326 unsigned long pg_iobits __read_mostly;
2327
2328 unsigned long _PAGE_IE __read_mostly;
2329 EXPORT_SYMBOL(_PAGE_IE);
2330
2331 unsigned long _PAGE_E __read_mostly;
2332 EXPORT_SYMBOL(_PAGE_E);
2333
2334 unsigned long _PAGE_CACHE __read_mostly;
2335 EXPORT_SYMBOL(_PAGE_CACHE);
2336
2337 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2338 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2339                                int node)
2340 {
2341         unsigned long pte_base;
2342
2343         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2344                     _PAGE_CP_4U | _PAGE_CV_4U |
2345                     _PAGE_P_4U | _PAGE_W_4U);
2346         if (tlb_type == hypervisor)
2347                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2348                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2349
2350         pte_base |= _PAGE_PMD_HUGE;
2351
2352         vstart = vstart & PMD_MASK;
2353         vend = ALIGN(vend, PMD_SIZE);
2354         for (; vstart < vend; vstart += PMD_SIZE) {
2355                 pgd_t *pgd = pgd_offset_k(vstart);
2356                 unsigned long pte;
2357                 pud_t *pud;
2358                 pmd_t *pmd;
2359
2360                 if (pgd_none(*pgd)) {
2361                         pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2362
2363                         if (!new)
2364                                 return -ENOMEM;
2365                         pgd_populate(&init_mm, pgd, new);
2366                 }
2367
2368                 pud = pud_offset(pgd, vstart);
2369                 if (pud_none(*pud)) {
2370                         pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2371
2372                         if (!new)
2373                                 return -ENOMEM;
2374                         pud_populate(&init_mm, pud, new);
2375                 }
2376
2377                 pmd = pmd_offset(pud, vstart);
2378
2379                 pte = pmd_val(*pmd);
2380                 if (!(pte & _PAGE_VALID)) {
2381                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2382
2383                         if (!block)
2384                                 return -ENOMEM;
2385
2386                         pmd_val(*pmd) = pte_base | __pa(block);
2387                 }
2388         }
2389
2390         return 0;
2391 }
2392
2393 void vmemmap_free(unsigned long start, unsigned long end)
2394 {
2395 }
2396 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2397
2398 static void prot_init_common(unsigned long page_none,
2399                              unsigned long page_shared,
2400                              unsigned long page_copy,
2401                              unsigned long page_readonly,
2402                              unsigned long page_exec_bit)
2403 {
2404         PAGE_COPY = __pgprot(page_copy);
2405         PAGE_SHARED = __pgprot(page_shared);
2406
2407         protection_map[0x0] = __pgprot(page_none);
2408         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2409         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2410         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2411         protection_map[0x4] = __pgprot(page_readonly);
2412         protection_map[0x5] = __pgprot(page_readonly);
2413         protection_map[0x6] = __pgprot(page_copy);
2414         protection_map[0x7] = __pgprot(page_copy);
2415         protection_map[0x8] = __pgprot(page_none);
2416         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2417         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2418         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2419         protection_map[0xc] = __pgprot(page_readonly);
2420         protection_map[0xd] = __pgprot(page_readonly);
2421         protection_map[0xe] = __pgprot(page_shared);
2422         protection_map[0xf] = __pgprot(page_shared);
2423 }
2424
2425 static void __init sun4u_pgprot_init(void)
2426 {
2427         unsigned long page_none, page_shared, page_copy, page_readonly;
2428         unsigned long page_exec_bit;
2429         int i;
2430
2431         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2432                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2433                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2434                                 _PAGE_EXEC_4U);
2435         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2436                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2437                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2438                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2439
2440         _PAGE_IE = _PAGE_IE_4U;
2441         _PAGE_E = _PAGE_E_4U;
2442         _PAGE_CACHE = _PAGE_CACHE_4U;
2443
2444         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2445                      __ACCESS_BITS_4U | _PAGE_E_4U);
2446
2447 #ifdef CONFIG_DEBUG_PAGEALLOC
2448         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2449 #else
2450         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2451                 PAGE_OFFSET;
2452 #endif
2453         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2454                                    _PAGE_P_4U | _PAGE_W_4U);
2455
2456         for (i = 1; i < 4; i++)
2457                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2458
2459         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2460                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2461                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2462
2463
2464         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2465         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2466                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2467         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2468                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2469         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2470                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2471
2472         page_exec_bit = _PAGE_EXEC_4U;
2473
2474         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2475                          page_exec_bit);
2476 }
2477
2478 static void __init sun4v_pgprot_init(void)
2479 {
2480         unsigned long page_none, page_shared, page_copy, page_readonly;
2481         unsigned long page_exec_bit;
2482         int i;
2483
2484         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2485                                 page_cache4v_flag | _PAGE_P_4V |
2486                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2487                                 _PAGE_EXEC_4V);
2488         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2489
2490         _PAGE_IE = _PAGE_IE_4V;
2491         _PAGE_E = _PAGE_E_4V;
2492         _PAGE_CACHE = page_cache4v_flag;
2493
2494 #ifdef CONFIG_DEBUG_PAGEALLOC
2495         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2496 #else
2497         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2498                 PAGE_OFFSET;
2499 #endif
2500         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2501                                    _PAGE_W_4V);
2502
2503         for (i = 1; i < 4; i++)
2504                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2505
2506         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2507                      __ACCESS_BITS_4V | _PAGE_E_4V);
2508
2509         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2510                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2511                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2512                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2513
2514         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2515         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2516                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2517         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2518                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2519         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2520                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2521
2522         page_exec_bit = _PAGE_EXEC_4V;
2523
2524         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2525                          page_exec_bit);
2526 }
2527
2528 unsigned long pte_sz_bits(unsigned long sz)
2529 {
2530         if (tlb_type == hypervisor) {
2531                 switch (sz) {
2532                 case 8 * 1024:
2533                 default:
2534                         return _PAGE_SZ8K_4V;
2535                 case 64 * 1024:
2536                         return _PAGE_SZ64K_4V;
2537                 case 512 * 1024:
2538                         return _PAGE_SZ512K_4V;
2539                 case 4 * 1024 * 1024:
2540                         return _PAGE_SZ4MB_4V;
2541                 }
2542         } else {
2543                 switch (sz) {
2544                 case 8 * 1024:
2545                 default:
2546                         return _PAGE_SZ8K_4U;
2547                 case 64 * 1024:
2548                         return _PAGE_SZ64K_4U;
2549                 case 512 * 1024:
2550                         return _PAGE_SZ512K_4U;
2551                 case 4 * 1024 * 1024:
2552                         return _PAGE_SZ4MB_4U;
2553                 }
2554         }
2555 }
2556
2557 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2558 {
2559         pte_t pte;
2560
2561         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2562         pte_val(pte) |= (((unsigned long)space) << 32);
2563         pte_val(pte) |= pte_sz_bits(page_size);
2564
2565         return pte;
2566 }
2567
2568 static unsigned long kern_large_tte(unsigned long paddr)
2569 {
2570         unsigned long val;
2571
2572         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2573                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2574                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2575         if (tlb_type == hypervisor)
2576                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2577                        page_cache4v_flag | _PAGE_P_4V |
2578                        _PAGE_EXEC_4V | _PAGE_W_4V);
2579
2580         return val | paddr;
2581 }
2582
2583 /* If not locked, zap it. */
2584 void __flush_tlb_all(void)
2585 {
2586         unsigned long pstate;
2587         int i;
2588
2589         __asm__ __volatile__("flushw\n\t"
2590                              "rdpr      %%pstate, %0\n\t"
2591                              "wrpr      %0, %1, %%pstate"
2592                              : "=r" (pstate)
2593                              : "i" (PSTATE_IE));
2594         if (tlb_type == hypervisor) {
2595                 sun4v_mmu_demap_all();
2596         } else if (tlb_type == spitfire) {
2597                 for (i = 0; i < 64; i++) {
2598                         /* Spitfire Errata #32 workaround */
2599                         /* NOTE: Always runs on spitfire, so no
2600                          *       cheetah+ page size encodings.
2601                          */
2602                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2603                                              "flush     %%g6"
2604                                              : /* No outputs */
2605                                              : "r" (0),
2606                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2607
2608                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2609                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2610                                                      "membar #Sync"
2611                                                      : /* no outputs */
2612                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2613                                 spitfire_put_dtlb_data(i, 0x0UL);
2614                         }
2615
2616                         /* Spitfire Errata #32 workaround */
2617                         /* NOTE: Always runs on spitfire, so no
2618                          *       cheetah+ page size encodings.
2619                          */
2620                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2621                                              "flush     %%g6"
2622                                              : /* No outputs */
2623                                              : "r" (0),
2624                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2625
2626                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2627                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2628                                                      "membar #Sync"
2629                                                      : /* no outputs */
2630                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2631                                 spitfire_put_itlb_data(i, 0x0UL);
2632                         }
2633                 }
2634         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2635                 cheetah_flush_dtlb_all();
2636                 cheetah_flush_itlb_all();
2637         }
2638         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2639                              : : "r" (pstate));
2640 }
2641
2642 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2643                             unsigned long address)
2644 {
2645         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2646                                        __GFP_REPEAT | __GFP_ZERO);
2647         pte_t *pte = NULL;
2648
2649         if (page)
2650                 pte = (pte_t *) page_address(page);
2651
2652         return pte;
2653 }
2654
2655 pgtable_t pte_alloc_one(struct mm_struct *mm,
2656                         unsigned long address)
2657 {
2658         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2659                                        __GFP_REPEAT | __GFP_ZERO);
2660         if (!page)
2661                 return NULL;
2662         if (!pgtable_page_ctor(page)) {
2663                 free_hot_cold_page(page, 0);
2664                 return NULL;
2665         }
2666         return (pte_t *) page_address(page);
2667 }
2668
2669 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2670 {
2671         free_page((unsigned long)pte);
2672 }
2673
2674 static void __pte_free(pgtable_t pte)
2675 {
2676         struct page *page = virt_to_page(pte);
2677
2678         pgtable_page_dtor(page);
2679         __free_page(page);
2680 }
2681
2682 void pte_free(struct mm_struct *mm, pgtable_t pte)
2683 {
2684         __pte_free(pte);
2685 }
2686
2687 void pgtable_free(void *table, bool is_page)
2688 {
2689         if (is_page)
2690                 __pte_free(table);
2691         else
2692                 kmem_cache_free(pgtable_cache, table);
2693 }
2694
2695 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2696 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2697                           pmd_t *pmd)
2698 {
2699         unsigned long pte, flags;
2700         struct mm_struct *mm;
2701         pmd_t entry = *pmd;
2702
2703         if (!pmd_large(entry) || !pmd_young(entry))
2704                 return;
2705
2706         pte = pmd_val(entry);
2707
2708         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2709         if (!(pte & _PAGE_VALID))
2710                 return;
2711
2712         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2713         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2714
2715         mm = vma->vm_mm;
2716
2717         spin_lock_irqsave(&mm->context.lock, flags);
2718
2719         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2720                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2721                                         addr, pte);
2722
2723         spin_unlock_irqrestore(&mm->context.lock, flags);
2724 }
2725 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2726
2727 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2728 static void context_reload(void *__data)
2729 {
2730         struct mm_struct *mm = __data;
2731
2732         if (mm == current->mm)
2733                 load_secondary_context(mm);
2734 }
2735
2736 void hugetlb_setup(struct pt_regs *regs)
2737 {
2738         struct mm_struct *mm = current->mm;
2739         struct tsb_config *tp;
2740
2741         if (faulthandler_disabled() || !mm) {
2742                 const struct exception_table_entry *entry;
2743
2744                 entry = search_exception_tables(regs->tpc);
2745                 if (entry) {
2746                         regs->tpc = entry->fixup;
2747                         regs->tnpc = regs->tpc + 4;
2748                         return;
2749                 }
2750                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2751                 die_if_kernel("HugeTSB in atomic", regs);
2752         }
2753
2754         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2755         if (likely(tp->tsb == NULL))
2756                 tsb_grow(mm, MM_TSB_HUGE, 0);
2757
2758         tsb_context_switch(mm);
2759         smp_tsb_sync(mm);
2760
2761         /* On UltraSPARC-III+ and later, configure the second half of
2762          * the Data-TLB for huge pages.
2763          */
2764         if (tlb_type == cheetah_plus) {
2765                 unsigned long ctx;
2766
2767                 spin_lock(&ctx_alloc_lock);
2768                 ctx = mm->context.sparc64_ctx_val;
2769                 ctx &= ~CTX_PGSZ_MASK;
2770                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2771                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2772
2773                 if (ctx != mm->context.sparc64_ctx_val) {
2774                         /* When changing the page size fields, we
2775                          * must perform a context flush so that no
2776                          * stale entries match.  This flush must
2777                          * occur with the original context register
2778                          * settings.
2779                          */
2780                         do_flush_tlb_mm(mm);
2781
2782                         /* Reload the context register of all processors
2783                          * also executing in this address space.
2784                          */
2785                         mm->context.sparc64_ctx_val = ctx;
2786                         on_each_cpu(context_reload, mm, 0);
2787                 }
2788                 spin_unlock(&ctx_alloc_lock);
2789         }
2790 }
2791 #endif
2792
2793 static struct resource code_resource = {
2794         .name   = "Kernel code",
2795         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2796 };
2797
2798 static struct resource data_resource = {
2799         .name   = "Kernel data",
2800         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2801 };
2802
2803 static struct resource bss_resource = {
2804         .name   = "Kernel bss",
2805         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2806 };
2807
2808 static inline resource_size_t compute_kern_paddr(void *addr)
2809 {
2810         return (resource_size_t) (addr - KERNBASE + kern_base);
2811 }
2812
2813 static void __init kernel_lds_init(void)
2814 {
2815         code_resource.start = compute_kern_paddr(_text);
2816         code_resource.end   = compute_kern_paddr(_etext - 1);
2817         data_resource.start = compute_kern_paddr(_etext);
2818         data_resource.end   = compute_kern_paddr(_edata - 1);
2819         bss_resource.start  = compute_kern_paddr(__bss_start);
2820         bss_resource.end    = compute_kern_paddr(_end - 1);
2821 }
2822
2823 static int __init report_memory(void)
2824 {
2825         int i;
2826         struct resource *res;
2827
2828         kernel_lds_init();
2829
2830         for (i = 0; i < pavail_ents; i++) {
2831                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2832
2833                 if (!res) {
2834                         pr_warn("Failed to allocate source.\n");
2835                         break;
2836                 }
2837
2838                 res->name = "System RAM";
2839                 res->start = pavail[i].phys_addr;
2840                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2841                 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
2842
2843                 if (insert_resource(&iomem_resource, res) < 0) {
2844                         pr_warn("Resource insertion failed.\n");
2845                         break;
2846                 }
2847
2848                 insert_resource(res, &code_resource);
2849                 insert_resource(res, &data_resource);
2850                 insert_resource(res, &bss_resource);
2851         }
2852
2853         return 0;
2854 }
2855 arch_initcall(report_memory);
2856
2857 #ifdef CONFIG_SMP
2858 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2859 #else
2860 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2861 #endif
2862
2863 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2864 {
2865         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2866                 if (start < LOW_OBP_ADDRESS) {
2867                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2868                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2869                 }
2870                 if (end > HI_OBP_ADDRESS) {
2871                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2872                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2873                 }
2874         } else {
2875                 flush_tsb_kernel_range(start, end);
2876                 do_flush_tlb_kernel_range(start, end);
2877         }
2878 }