kernel/arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/ioport.h>
  26 #include <linux/percpu.h>
  27 #include <linux/memblock.h>
  28 #include <linux/mmzone.h>
  29 #include <linux/gfp.h>
  30
  31 #include <asm/head.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/cpudata.h>
  51 #include <asm/setup.h>
  52 #include <asm/irq.h>
  53
  54 #include "init_64.h"
  55
  56 unsigned long kern_linear_pte_xor[4] __read_mostly;
  57 static unsigned long page_cache4v_flag;
  58
  59 /* A bitmap, two bits for every 256MB of physical memory.  These two
  60  * bits determine what page size we use for kernel linear
  61  * translations.  They form an index into kern_linear_pte_xor[].  The
  62  * value in the indexed slot is XOR'd with the TLB miss virtual
  63  * address to form the resulting TTE.  The mapping is:
  64  *
  65  *      0       ==>     4MB
  66  *      1       ==>     256MB
  67  *      2       ==>     2GB
  68  *      3       ==>     16GB
  69  *
  70  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  71  * support 2GB pages, and hopefully future cpus will support the 16GB
  72  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  73  * if these larger page sizes are not supported by the cpu.
  74  *
  75  * It would be nice to determine this from the machine description
  76  * 'cpu' properties, but we need to have this table setup before the
  77  * MDESC is initialized.
  78  */
  79
  80 #ifndef CONFIG_DEBUG_PAGEALLOC
  81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  82  * Space is allocated for this right after the trap table in
  83  * arch/sparc64/kernel/head.S
  84  */
  85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  86 #endif
  87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  88
  89 static unsigned long cpu_pgsz_mask;
  90
  91 #define MAX_BANKS       1024
  92
  93 static struct linux_prom64_registers pavail[MAX_BANKS];
  94 static int pavail_ents;
  95
  96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
  97
  98 static int cmp_p64(const void *a, const void *b)
  99 {
 100         const struct linux_prom64_registers *x = a, *y = b;
 101
 102         if (x->phys_addr > y->phys_addr)
 103                 return 1;
 104         if (x->phys_addr < y->phys_addr)
 105                 return -1;
 106         return 0;
 107 }
 108
 109 static void __init read_obp_memory(const char *property,
 110                                    struct linux_prom64_registers *regs,
 111                                    int *num_ents)
 112 {
 113         phandle node = prom_finddevice("/memory");
 114         int prop_size = prom_getproplen(node, property);
 115         int ents, ret, i;
 116
 117         ents = prop_size / sizeof(struct linux_prom64_registers);
 118         if (ents > MAX_BANKS) {
 119                 prom_printf("The machine has more %s property entries than "
 120                             "this kernel can support (%d).\n",
 121                             property, MAX_BANKS);
 122                 prom_halt();
 123         }
 124
 125         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 126         if (ret == -1) {
 127                 prom_printf("Couldn't get %s property from /memory.\n",
 128                                 property);
 129                 prom_halt();
 130         }
 131
 132         /* Sanitize what we got from the firmware, by page aligning
 133          * everything.
 134          */
 135         for (i = 0; i < ents; i++) {
 136                 unsigned long base, size;
 137
 138                 base = regs[i].phys_addr;
 139                 size = regs[i].reg_size;
 140
 141                 size &= PAGE_MASK;
 142                 if (base & ~PAGE_MASK) {
 143                         unsigned long new_base = PAGE_ALIGN(base);
 144
 145                         size -= new_base - base;
 146                         if ((long) size < 0L)
 147                                 size = 0UL;
 148                         base = new_base;
 149                 }
 150                 if (size == 0UL) {
 151                         /* If it is empty, simply get rid of it.
 152                          * This simplifies the logic of the other
 153                          * functions that process these arrays.
 154                          */
 155                         memmove(&regs[i], &regs[i + 1],
 156                                 (ents - i - 1) * sizeof(regs[0]));
 157                         i--;
 158                         ents--;
 159                         continue;
 160                 }
 161                 regs[i].phys_addr = base;
 162                 regs[i].reg_size = size;
 163         }
 164
 165         *num_ents = ents;
 166
 167         sort(regs, ents, sizeof(struct linux_prom64_registers),
 168              cmp_p64, NULL);
 169 }
 170
 171 /* Kernel physical address base and size in bytes.  */
 172 unsigned long kern_base __read_mostly;
 173 unsigned long kern_size __read_mostly;
 174
 175 /* Initial ramdisk setup */
 176 extern unsigned long sparc_ramdisk_image64;
 177 extern unsigned int sparc_ramdisk_image;
 178 extern unsigned int sparc_ramdisk_size;
 179
 180 struct page *mem_map_zero __read_mostly;
 181 EXPORT_SYMBOL(mem_map_zero);
 182
 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 184
 185 unsigned long sparc64_kern_pri_context __read_mostly;
 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 187 unsigned long sparc64_kern_sec_context __read_mostly;
 188
 189 int num_kernel_image_mappings;
 190
 191 #ifdef CONFIG_DEBUG_DCFLUSH
 192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 193 #ifdef CONFIG_SMP
 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 195 #endif
 196 #endif
 197
 198 inline void flush_dcache_page_impl(struct page *page)
 199 {
 200         BUG_ON(tlb_type == hypervisor);
 201 #ifdef CONFIG_DEBUG_DCFLUSH
 202         atomic_inc(&dcpage_flushes);
 203 #endif
 204
 205 #ifdef DCACHE_ALIASING_POSSIBLE
 206         __flush_dcache_page(page_address(page),
 207                             ((tlb_type == spitfire) &&
 208                              page_mapping(page) != NULL));
 209 #else
 210         if (page_mapping(page) != NULL &&
 211             tlb_type == spitfire)
 212                 __flush_icache_page(__pa(page_address(page)));
 213 #endif
 214 }
 215
 216 #define PG_dcache_dirty         PG_arch_1
 217 #define PG_dcache_cpu_shift     32UL
 218 #define PG_dcache_cpu_mask      \
 219         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 220
 221 #define dcache_dirty_cpu(page) \
 222         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 223
 224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 225 {
 226         unsigned long mask = this_cpu;
 227         unsigned long non_cpu_bits;
 228
 229         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 230         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 231
 232         __asm__ __volatile__("1:\n\t"
 233                              "ldx       [%2], %%g7\n\t"
 234                              "and       %%g7, %1, %%g1\n\t"
 235                              "or        %%g1, %0, %%g1\n\t"
 236                              "casx      [%2], %%g7, %%g1\n\t"
 237                              "cmp       %%g7, %%g1\n\t"
 238                              "bne,pn    %%xcc, 1b\n\t"
 239                              " nop"
 240                              : /* no outputs */
 241                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 242                              : "g1", "g7");
 243 }
 244
 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 246 {
 247         unsigned long mask = (1UL << PG_dcache_dirty);
 248
 249         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 250                              "1:\n\t"
 251                              "ldx       [%2], %%g7\n\t"
 252                              "srlx      %%g7, %4, %%g1\n\t"
 253                              "and       %%g1, %3, %%g1\n\t"
 254                              "cmp       %%g1, %0\n\t"
 255                              "bne,pn    %%icc, 2f\n\t"
 256                              " andn     %%g7, %1, %%g1\n\t"
 257                              "casx      [%2], %%g7, %%g1\n\t"
 258                              "cmp       %%g7, %%g1\n\t"
 259                              "bne,pn    %%xcc, 1b\n\t"
 260                              " nop\n"
 261                              "2:"
 262                              : /* no outputs */
 263                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 264                                "i" (PG_dcache_cpu_mask),
 265                                "i" (PG_dcache_cpu_shift)
 266                              : "g1", "g7");
 267 }
 268
 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 270 {
 271         unsigned long tsb_addr = (unsigned long) ent;
 272
 273         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 274                 tsb_addr = __pa(tsb_addr);
 275
 276         __tsb_insert(tsb_addr, tag, pte);
 277 }
 278
 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 280
 281 static void flush_dcache(unsigned long pfn)
 282 {
 283         struct page *page;
 284
 285         page = pfn_to_page(pfn);
 286         if (page) {
 287                 unsigned long pg_flags;
 288
 289                 pg_flags = page->flags;
 290                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 291                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 292                                    PG_dcache_cpu_mask);
 293                         int this_cpu = get_cpu();
 294
 295                         /* This is just to optimize away some function calls
 296                          * in the SMP case.
 297                          */
 298                         if (cpu == this_cpu)
 299                                 flush_dcache_page_impl(page);
 300                         else
 301                                 smp_flush_dcache_page_impl(page, cpu);
 302
 303                         clear_dcache_dirty_cpu(page, cpu);
 304
 305                         put_cpu();
 306                 }
 307         }
 308 }
 309
 310 /* mm->context.lock must be held */
 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 312                                     unsigned long tsb_hash_shift, unsigned long address,
 313                                     unsigned long tte)
 314 {
 315         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 316         unsigned long tag;
 317
 318         if (unlikely(!tsb))
 319                 return;
 320
 321         tsb += ((address >> tsb_hash_shift) &
 322                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 323         tag = (address >> 22UL);
 324         tsb_insert(tsb, tag, tte);
 325 }
 326
 327 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 328 {
 329         struct mm_struct *mm;
 330         unsigned long flags;
 331         pte_t pte = *ptep;
 332
 333         if (tlb_type != hypervisor) {
 334                 unsigned long pfn = pte_pfn(pte);
 335
 336                 if (pfn_valid(pfn))
 337                         flush_dcache(pfn);
 338         }
 339
 340         mm = vma->vm_mm;
 341
 342         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 343         if (!pte_accessible(mm, pte))
 344                 return;
 345
 346         spin_lock_irqsave(&mm->context.lock, flags);
 347
 348 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 349         if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) &&
 350             is_hugetlb_pte(pte))
 351                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
 352                                         address, pte_val(pte));
 353         else
 354 #endif
 355                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 356                                         address, pte_val(pte));
 357
 358         spin_unlock_irqrestore(&mm->context.lock, flags);
 359 }
 360
 361 void flush_dcache_page(struct page *page)
 362 {
 363         struct address_space *mapping;
 364         int this_cpu;
 365
 366         if (tlb_type == hypervisor)
 367                 return;
 368
 369         /* Do not bother with the expensive D-cache flush if it
 370          * is merely the zero page.  The 'bigcore' testcase in GDB
 371          * causes this case to run millions of times.
 372          */
 373         if (page == ZERO_PAGE(0))
 374                 return;
 375
 376         this_cpu = get_cpu();
 377
 378         mapping = page_mapping(page);
 379         if (mapping && !mapping_mapped(mapping)) {
 380                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 381                 if (dirty) {
 382                         int dirty_cpu = dcache_dirty_cpu(page);
 383
 384                         if (dirty_cpu == this_cpu)
 385                                 goto out;
 386                         smp_flush_dcache_page_impl(page, dirty_cpu);
 387                 }
 388                 set_dcache_dirty(page, this_cpu);
 389         } else {
 390                 /* We could delay the flush for the !page_mapping
 391                  * case too.  But that case is for exec env/arg
 392                  * pages and those are %99 certainly going to get
 393                  * faulted into the tlb (and thus flushed) anyways.
 394                  */
 395                 flush_dcache_page_impl(page);
 396         }
 397
 398 out:
 399         put_cpu();
 400 }
 401 EXPORT_SYMBOL(flush_dcache_page);
 402
 403 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 404 {
 405         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 406         if (tlb_type == spitfire) {
 407                 unsigned long kaddr;
 408
 409                 /* This code only runs on Spitfire cpus so this is
 410                  * why we can assume _PAGE_PADDR_4U.
 411                  */
 412                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 413                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 414
 415                         if (kaddr >= PAGE_OFFSET)
 416                                 paddr = kaddr & mask;
 417                         else {
 418                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 419                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 420                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 421                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 422
 423                                 paddr = pte_val(*ptep) & mask;
 424                         }
 425                         __flush_icache_page(paddr);
 426                 }
 427         }
 428 }
 429 EXPORT_SYMBOL(flush_icache_range);
 430
 431 void mmu_info(struct seq_file *m)
 432 {
 433         static const char *pgsz_strings[] = {
 434                 "8K", "64K", "512K", "4MB", "32MB",
 435                 "256MB", "2GB", "16GB",
 436         };
 437         int i, printed;
 438
 439         if (tlb_type == cheetah)
 440                 seq_printf(m, "MMU Type\t: Cheetah\n");
 441         else if (tlb_type == cheetah_plus)
 442                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 443         else if (tlb_type == spitfire)
 444                 seq_printf(m, "MMU Type\t: Spitfire\n");
 445         else if (tlb_type == hypervisor)
 446                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 447         else
 448                 seq_printf(m, "MMU Type\t: ???\n");
 449
 450         seq_printf(m, "MMU PGSZs\t: ");
 451         printed = 0;
 452         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 453                 if (cpu_pgsz_mask & (1UL << i)) {
 454                         seq_printf(m, "%s%s",
 455                                    printed ? "," : "", pgsz_strings[i]);
 456                         printed++;
 457                 }
 458         }
 459         seq_putc(m, '\n');
 460
 461 #ifdef CONFIG_DEBUG_DCFLUSH
 462         seq_printf(m, "DCPageFlushes\t: %d\n",
 463                    atomic_read(&dcpage_flushes));
 464 #ifdef CONFIG_SMP
 465         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 466                    atomic_read(&dcpage_flushes_xcall));
 467 #endif /* CONFIG_SMP */
 468 #endif /* CONFIG_DEBUG_DCFLUSH */
 469 }
 470
 471 struct linux_prom_translation prom_trans[512] __read_mostly;
 472 unsigned int prom_trans_ents __read_mostly;
 473
 474 unsigned long kern_locked_tte_data;
 475
 476 /* The obp translations are saved based on 8k pagesize, since obp can
 477  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 478  * HI_OBP_ADDRESS range are handled in ktlb.S.
 479  */
 480 static inline int in_obp_range(unsigned long vaddr)
 481 {
 482         return (vaddr >= LOW_OBP_ADDRESS &&
 483                 vaddr < HI_OBP_ADDRESS);
 484 }
 485
 486 static int cmp_ptrans(const void *a, const void *b)
 487 {
 488         const struct linux_prom_translation *x = a, *y = b;
 489
 490         if (x->virt > y->virt)
 491                 return 1;
 492         if (x->virt < y->virt)
 493                 return -1;
 494         return 0;
 495 }
 496
 497 /* Read OBP translations property into 'prom_trans[]'.  */
 498 static void __init read_obp_translations(void)
 499 {
 500         int n, node, ents, first, last, i;
 501
 502         node = prom_finddevice("/virtual-memory");
 503         n = prom_getproplen(node, "translations");
 504         if (unlikely(n == 0 || n == -1)) {
 505                 prom_printf("prom_mappings: Couldn't get size.\n");
 506                 prom_halt();
 507         }
 508         if (unlikely(n > sizeof(prom_trans))) {
 509                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 510                 prom_halt();
 511         }
 512
 513         if ((n = prom_getproperty(node, "translations",
 514                                   (char *)&prom_trans[0],
 515                                   sizeof(prom_trans))) == -1) {
 516                 prom_printf("prom_mappings: Couldn't get property.\n");
 517                 prom_halt();
 518         }
 519
 520         n = n / sizeof(struct linux_prom_translation);
 521
 522         ents = n;
 523
 524         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 525              cmp_ptrans, NULL);
 526
 527         /* Now kick out all the non-OBP entries.  */
 528         for (i = 0; i < ents; i++) {
 529                 if (in_obp_range(prom_trans[i].virt))
 530                         break;
 531         }
 532         first = i;
 533         for (; i < ents; i++) {
 534                 if (!in_obp_range(prom_trans[i].virt))
 535                         break;
 536         }
 537         last = i;
 538
 539         for (i = 0; i < (last - first); i++) {
 540                 struct linux_prom_translation *src = &prom_trans[i + first];
 541                 struct linux_prom_translation *dest = &prom_trans[i];
 542
 543                 *dest = *src;
 544         }
 545         for (; i < ents; i++) {
 546                 struct linux_prom_translation *dest = &prom_trans[i];
 547                 dest->virt = dest->size = dest->data = 0x0UL;
 548         }
 549
 550         prom_trans_ents = last - first;
 551
 552         if (tlb_type == spitfire) {
 553                 /* Clear diag TTE bits. */
 554                 for (i = 0; i < prom_trans_ents; i++)
 555                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 556         }
 557
 558         /* Force execute bit on.  */
 559         for (i = 0; i < prom_trans_ents; i++)
 560                 prom_trans[i].data |= (tlb_type == hypervisor ?
 561                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 562 }
 563
 564 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 565                                        unsigned long pte,
 566                                        unsigned long mmu)
 567 {
 568         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 569
 570         if (ret != 0) {
 571                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 572                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 573                 prom_halt();
 574         }
 575 }
 576
 577 static unsigned long kern_large_tte(unsigned long paddr);
 578
 579 static void __init remap_kernel(void)
 580 {
 581         unsigned long phys_page, tte_vaddr, tte_data;
 582         int i, tlb_ent = sparc64_highest_locked_tlbent();
 583
 584         tte_vaddr = (unsigned long) KERNBASE;
 585         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 586         tte_data = kern_large_tte(phys_page);
 587
 588         kern_locked_tte_data = tte_data;
 589
 590         /* Now lock us into the TLBs via Hypervisor or OBP. */
 591         if (tlb_type == hypervisor) {
 592                 for (i = 0; i < num_kernel_image_mappings; i++) {
 593                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 594                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 595                         tte_vaddr += 0x400000;
 596                         tte_data += 0x400000;
 597                 }
 598         } else {
 599                 for (i = 0; i < num_kernel_image_mappings; i++) {
 600                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 601                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 602                         tte_vaddr += 0x400000;
 603                         tte_data += 0x400000;
 604                 }
 605                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 606         }
 607         if (tlb_type == cheetah_plus) {
 608                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 609                                             CTX_CHEETAH_PLUS_NUC);
 610                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 611                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 612         }
 613 }
 614
 615
 616 static void __init inherit_prom_mappings(void)
 617 {
 618         /* Now fixup OBP's idea about where we really are mapped. */
 619         printk("Remapping the kernel... ");
 620         remap_kernel();
 621         printk("done.\n");
 622 }
 623
 624 void prom_world(int enter)
 625 {
 626         if (!enter)
 627                 set_fs(get_fs());
 628
 629         __asm__ __volatile__("flushw");
 630 }
 631
 632 void __flush_dcache_range(unsigned long start, unsigned long end)
 633 {
 634         unsigned long va;
 635
 636         if (tlb_type == spitfire) {
 637                 int n = 0;
 638
 639                 for (va = start; va < end; va += 32) {
 640                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 641                         if (++n >= 512)
 642                                 break;
 643                 }
 644         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 645                 start = __pa(start);
 646                 end = __pa(end);
 647                 for (va = start; va < end; va += 32)
 648                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 649                                              "membar #Sync"
 650                                              : /* no outputs */
 651                                              : "r" (va),
 652                                                "i" (ASI_DCACHE_INVALIDATE));
 653         }
 654 }
 655 EXPORT_SYMBOL(__flush_dcache_range);
 656
 657 /* get_new_mmu_context() uses "cache + 1".  */
 658 DEFINE_SPINLOCK(ctx_alloc_lock);
 659 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 660 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 661 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 662 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 663
 664 /* Caller does TLB context flushing on local CPU if necessary.
 665  * The caller also ensures that CTX_VALID(mm->context) is false.
 666  *
 667  * We must be careful about boundary cases so that we never
 668  * let the user have CTX 0 (nucleus) or we ever use a CTX
 669  * version of zero (and thus NO_CONTEXT would not be caught
 670  * by version mis-match tests in mmu_context.h).
 671  *
 672  * Always invoked with interrupts disabled.
 673  */
 674 void get_new_mmu_context(struct mm_struct *mm)
 675 {
 676         unsigned long ctx, new_ctx;
 677         unsigned long orig_pgsz_bits;
 678         int new_version;
 679
 680         spin_lock(&ctx_alloc_lock);
 681         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 682         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 683         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 684         new_version = 0;
 685         if (new_ctx >= (1 << CTX_NR_BITS)) {
 686                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 687                 if (new_ctx >= ctx) {
 688                         int i;
 689                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 690                                 CTX_FIRST_VERSION;
 691                         if (new_ctx == 1)
 692                                 new_ctx = CTX_FIRST_VERSION;
 693
 694                         /* Don't call memset, for 16 entries that's just
 695                          * plain silly...
 696                          */
 697                         mmu_context_bmap[0] = 3;
 698                         mmu_context_bmap[1] = 0;
 699                         mmu_context_bmap[2] = 0;
 700                         mmu_context_bmap[3] = 0;
 701                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 702                                 mmu_context_bmap[i + 0] = 0;
 703                                 mmu_context_bmap[i + 1] = 0;
 704                                 mmu_context_bmap[i + 2] = 0;
 705                                 mmu_context_bmap[i + 3] = 0;
 706                         }
 707                         new_version = 1;
 708                         goto out;
 709                 }
 710         }
 711         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 712         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 713 out:
 714         tlb_context_cache = new_ctx;
 715         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 716         spin_unlock(&ctx_alloc_lock);
 717
 718         if (unlikely(new_version))
 719                 smp_new_mmu_context_version();
 720 }
 721
 722 static int numa_enabled = 1;
 723 static int numa_debug;
 724
 725 static int __init early_numa(char *p)
 726 {
 727         if (!p)
 728                 return 0;
 729
 730         if (strstr(p, "off"))
 731                 numa_enabled = 0;
 732
 733         if (strstr(p, "debug"))
 734                 numa_debug = 1;
 735
 736         return 0;
 737 }
 738 early_param("numa", early_numa);
 739
 740 #define numadbg(f, a...) \
 741 do {    if (numa_debug) \
 742                 printk(KERN_INFO f, ## a); \
 743 } while (0)
 744
 745 static void __init find_ramdisk(unsigned long phys_base)
 746 {
 747 #ifdef CONFIG_BLK_DEV_INITRD
 748         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 749                 unsigned long ramdisk_image;
 750
 751                 /* Older versions of the bootloader only supported a
 752                  * 32-bit physical address for the ramdisk image
 753                  * location, stored at sparc_ramdisk_image.  Newer
 754                  * SILO versions set sparc_ramdisk_image to zero and
 755                  * provide a full 64-bit physical address at
 756                  * sparc_ramdisk_image64.
 757                  */
 758                 ramdisk_image = sparc_ramdisk_image;
 759                 if (!ramdisk_image)
 760                         ramdisk_image = sparc_ramdisk_image64;
 761
 762                 /* Another bootloader quirk.  The bootloader normalizes
 763                  * the physical address to KERNBASE, so we have to
 764                  * factor that back out and add in the lowest valid
 765                  * physical page address to get the true physical address.
 766                  */
 767                 ramdisk_image -= KERNBASE;
 768                 ramdisk_image += phys_base;
 769
 770                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 771                         ramdisk_image, sparc_ramdisk_size);
 772
 773                 initrd_start = ramdisk_image;
 774                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 775
 776                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 777
 778                 initrd_start += PAGE_OFFSET;
 779                 initrd_end += PAGE_OFFSET;
 780         }
 781 #endif
 782 }
 783
 784 struct node_mem_mask {
 785         unsigned long mask;
 786         unsigned long val;
 787 };
 788 static struct node_mem_mask node_masks[MAX_NUMNODES];
 789 static int num_node_masks;
 790
 791 #ifdef CONFIG_NEED_MULTIPLE_NODES
 792
 793 int numa_cpu_lookup_table[NR_CPUS];
 794 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 795
 796 struct mdesc_mblock {
 797         u64     base;
 798         u64     size;
 799         u64     offset; /* RA-to-PA */
 800 };
 801 static struct mdesc_mblock *mblocks;
 802 static int num_mblocks;
 803 static int find_numa_node_for_addr(unsigned long pa,
 804                                    struct node_mem_mask *pnode_mask);
 805
 806 static unsigned long __init ra_to_pa(unsigned long addr)
 807 {
 808         int i;
 809
 810         for (i = 0; i < num_mblocks; i++) {
 811                 struct mdesc_mblock *m = &mblocks[i];
 812
 813                 if (addr >= m->base &&
 814                     addr < (m->base + m->size)) {
 815                         addr += m->offset;
 816                         break;
 817                 }
 818         }
 819         return addr;
 820 }
 821
 822 static int __init find_node(unsigned long addr)
 823 {
 824         static bool search_mdesc = true;
 825         static struct node_mem_mask last_mem_mask = { ~0UL, ~0UL };
 826         static int last_index;
 827         int i;
 828
 829         addr = ra_to_pa(addr);
 830         for (i = 0; i < num_node_masks; i++) {
 831                 struct node_mem_mask *p = &node_masks[i];
 832
 833                 if ((addr & p->mask) == p->val)
 834                         return i;
 835         }
 836         /* The following condition has been observed on LDOM guests because
 837          * node_masks only contains the best latency mask and value.
 838          * LDOM guest's mdesc can contain a single latency group to
 839          * cover multiple address range. Print warning message only if the
 840          * address cannot be found in node_masks nor mdesc.
 841          */
 842         if ((search_mdesc) &&
 843             ((addr & last_mem_mask.mask) != last_mem_mask.val)) {
 844                 /* find the available node in the mdesc */
 845                 last_index = find_numa_node_for_addr(addr, &last_mem_mask);
 846                 numadbg("find_node: latency group for address 0x%lx is %d\n",
 847                         addr, last_index);
 848                 if ((last_index < 0) || (last_index >= num_node_masks)) {
 849                         /* WARN_ONCE() and use default group 0 */
 850                         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node rule. Some physical memory will be owned by node 0.");
 851                         search_mdesc = false;
 852                         last_index = 0;
 853                 }
 854         }
 855
 856         return last_index;
 857 }
 858
 859 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
 860 {
 861         *nid = find_node(start);
 862         start += PAGE_SIZE;
 863         while (start < end) {
 864                 int n = find_node(start);
 865
 866                 if (n != *nid)
 867                         break;
 868                 start += PAGE_SIZE;
 869         }
 870
 871         if (start > end)
 872                 start = end;
 873
 874         return start;
 875 }
 876 #endif
 877
 878 /* This must be invoked after performing all of the necessary
 879  * memblock_set_node() calls for 'nid'.  We need to be able to get
 880  * correct data from get_pfn_range_for_nid().
 881  */
 882 static void __init allocate_node_data(int nid)
 883 {
 884         struct pglist_data *p;
 885         unsigned long start_pfn, end_pfn;
 886 #ifdef CONFIG_NEED_MULTIPLE_NODES
 887         unsigned long paddr;
 888
 889         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 890         if (!paddr) {
 891                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 892                 prom_halt();
 893         }
 894         NODE_DATA(nid) = __va(paddr);
 895         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 896
 897         NODE_DATA(nid)->node_id = nid;
 898 #endif
 899
 900         p = NODE_DATA(nid);
 901
 902         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 903         p->node_start_pfn = start_pfn;
 904         p->node_spanned_pages = end_pfn - start_pfn;
 905 }
 906
 907 static void init_node_masks_nonnuma(void)
 908 {
 909 #ifdef CONFIG_NEED_MULTIPLE_NODES
 910         int i;
 911 #endif
 912
 913         numadbg("Initializing tables for non-numa.\n");
 914
 915         node_masks[0].mask = node_masks[0].val = 0;
 916         num_node_masks = 1;
 917
 918 #ifdef CONFIG_NEED_MULTIPLE_NODES
 919         for (i = 0; i < NR_CPUS; i++)
 920                 numa_cpu_lookup_table[i] = 0;
 921
 922         cpumask_setall(&numa_cpumask_lookup_table[0]);
 923 #endif
 924 }
 925
 926 #ifdef CONFIG_NEED_MULTIPLE_NODES
 927 struct pglist_data *node_data[MAX_NUMNODES];
 928
 929 EXPORT_SYMBOL(numa_cpu_lookup_table);
 930 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 931 EXPORT_SYMBOL(node_data);
 932
 933 struct mdesc_mlgroup {
 934         u64     node;
 935         u64     latency;
 936         u64     match;
 937         u64     mask;
 938 };
 939 static struct mdesc_mlgroup *mlgroups;
 940 static int num_mlgroups;
 941
 942 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 943                                    u32 cfg_handle)
 944 {
 945         u64 arc;
 946
 947         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 948                 u64 target = mdesc_arc_target(md, arc);
 949                 const u64 *val;
 950
 951                 val = mdesc_get_property(md, target,
 952                                          "cfg-handle", NULL);
 953                 if (val && *val == cfg_handle)
 954                         return 0;
 955         }
 956         return -ENODEV;
 957 }
 958
 959 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 960                                     u32 cfg_handle)
 961 {
 962         u64 arc, candidate, best_latency = ~(u64)0;
 963
 964         candidate = MDESC_NODE_NULL;
 965         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 966                 u64 target = mdesc_arc_target(md, arc);
 967                 const char *name = mdesc_node_name(md, target);
 968                 const u64 *val;
 969
 970                 if (strcmp(name, "pio-latency-group"))
 971                         continue;
 972
 973                 val = mdesc_get_property(md, target, "latency", NULL);
 974                 if (!val)
 975                         continue;
 976
 977                 if (*val < best_latency) {
 978                         candidate = target;
 979                         best_latency = *val;
 980                 }
 981         }
 982
 983         if (candidate == MDESC_NODE_NULL)
 984                 return -ENODEV;
 985
 986         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 987 }
 988
 989 int of_node_to_nid(struct device_node *dp)
 990 {
 991         const struct linux_prom64_registers *regs;
 992         struct mdesc_handle *md;
 993         u32 cfg_handle;
 994         int count, nid;
 995         u64 grp;
 996
 997         /* This is the right thing to do on currently supported
 998          * SUN4U NUMA platforms as well, as the PCI controller does
 999          * not sit behind any particular memory controller.
1000          */
1001         if (!mlgroups)
1002                 return -1;
1003
1004         regs = of_get_property(dp, "reg", NULL);
1005         if (!regs)
1006                 return -1;
1007
1008         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1009
1010         md = mdesc_grab();
1011
1012         count = 0;
1013         nid = -1;
1014         mdesc_for_each_node_by_name(md, grp, "group") {
1015                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1016                         nid = count;
1017                         break;
1018                 }
1019                 count++;
1020         }
1021
1022         mdesc_release(md);
1023
1024         return nid;
1025 }
1026
1027 static void __init add_node_ranges(void)
1028 {
1029         struct memblock_region *reg;
1030
1031         for_each_memblock(memory, reg) {
1032                 unsigned long size = reg->size;
1033                 unsigned long start, end;
1034
1035                 start = reg->base;
1036                 end = start + size;
1037                 while (start < end) {
1038                         unsigned long this_end;
1039                         int nid;
1040
1041                         this_end = memblock_nid_range(start, end, &nid);
1042
1043                         numadbg("Setting memblock NUMA node nid[%d] "
1044                                 "start[%lx] end[%lx]\n",
1045                                 nid, start, this_end);
1046
1047                         memblock_set_node(start, this_end - start,
1048                                           &memblock.memory, nid);
1049                         start = this_end;
1050                 }
1051         }
1052 }
1053
1054 static int __init grab_mlgroups(struct mdesc_handle *md)
1055 {
1056         unsigned long paddr;
1057         int count = 0;
1058         u64 node;
1059
1060         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1061                 count++;
1062         if (!count)
1063                 return -ENOENT;
1064
1065         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1066                           SMP_CACHE_BYTES);
1067         if (!paddr)
1068                 return -ENOMEM;
1069
1070         mlgroups = __va(paddr);
1071         num_mlgroups = count;
1072
1073         count = 0;
1074         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1075                 struct mdesc_mlgroup *m = &mlgroups[count++];
1076                 const u64 *val;
1077
1078                 m->node = node;
1079
1080                 val = mdesc_get_property(md, node, "latency", NULL);
1081                 m->latency = *val;
1082                 val = mdesc_get_property(md, node, "address-match", NULL);
1083                 m->match = *val;
1084                 val = mdesc_get_property(md, node, "address-mask", NULL);
1085                 m->mask = *val;
1086
1087                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1088                         "match[%llx] mask[%llx]\n",
1089                         count - 1, m->node, m->latency, m->match, m->mask);
1090         }
1091
1092         return 0;
1093 }
1094
1095 static int __init grab_mblocks(struct mdesc_handle *md)
1096 {
1097         unsigned long paddr;
1098         int count = 0;
1099         u64 node;
1100
1101         mdesc_for_each_node_by_name(md, node, "mblock")
1102                 count++;
1103         if (!count)
1104                 return -ENOENT;
1105
1106         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1107                           SMP_CACHE_BYTES);
1108         if (!paddr)
1109                 return -ENOMEM;
1110
1111         mblocks = __va(paddr);
1112         num_mblocks = count;
1113
1114         count = 0;
1115         mdesc_for_each_node_by_name(md, node, "mblock") {
1116                 struct mdesc_mblock *m = &mblocks[count++];
1117                 const u64 *val;
1118
1119                 val = mdesc_get_property(md, node, "base", NULL);
1120                 m->base = *val;
1121                 val = mdesc_get_property(md, node, "size", NULL);
1122                 m->size = *val;
1123                 val = mdesc_get_property(md, node,
1124                                          "address-congruence-offset", NULL);
1125
1126                 /* The address-congruence-offset property is optional.
1127                  * Explicity zero it be identifty this.
1128                  */
1129                 if (val)
1130                         m->offset = *val;
1131                 else
1132                         m->offset = 0UL;
1133
1134                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1135                         count - 1, m->base, m->size, m->offset);
1136         }
1137
1138         return 0;
1139 }
1140
1141 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1142                                                u64 grp, cpumask_t *mask)
1143 {
1144         u64 arc;
1145
1146         cpumask_clear(mask);
1147
1148         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1149                 u64 target = mdesc_arc_target(md, arc);
1150                 const char *name = mdesc_node_name(md, target);
1151                 const u64 *id;
1152
1153                 if (strcmp(name, "cpu"))
1154                         continue;
1155                 id = mdesc_get_property(md, target, "id", NULL);
1156                 if (*id < nr_cpu_ids)
1157                         cpumask_set_cpu(*id, mask);
1158         }
1159 }
1160
1161 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1162 {
1163         int i;
1164
1165         for (i = 0; i < num_mlgroups; i++) {
1166                 struct mdesc_mlgroup *m = &mlgroups[i];
1167                 if (m->node == node)
1168                         return m;
1169         }
1170         return NULL;
1171 }
1172
1173 int __node_distance(int from, int to)
1174 {
1175         if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1176                 pr_warn("Returning default NUMA distance value for %d->%d\n",
1177                         from, to);
1178                 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1179         }
1180         return numa_latency[from][to];
1181 }
1182
1183 static int find_numa_node_for_addr(unsigned long pa,
1184                                    struct node_mem_mask *pnode_mask)
1185 {
1186         struct mdesc_handle *md = mdesc_grab();
1187         u64 node, arc;
1188         int i = 0;
1189
1190         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1191         if (node == MDESC_NODE_NULL)
1192                 goto out;
1193
1194         mdesc_for_each_node_by_name(md, node, "group") {
1195                 mdesc_for_each_arc(arc, md, node, MDESC_ARC_TYPE_FWD) {
1196                         u64 target = mdesc_arc_target(md, arc);
1197                         struct mdesc_mlgroup *m = find_mlgroup(target);
1198
1199                         if (!m)
1200                                 continue;
1201                         if ((pa & m->mask) == m->match) {
1202                                 if (pnode_mask) {
1203                                         pnode_mask->mask = m->mask;
1204                                         pnode_mask->val = m->match;
1205                                 }
1206                                 mdesc_release(md);
1207                                 return i;
1208                         }
1209                 }
1210                 i++;
1211         }
1212
1213 out:
1214         mdesc_release(md);
1215         return -1;
1216 }
1217
1218 static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1219 {
1220         int i;
1221
1222         for (i = 0; i < MAX_NUMNODES; i++) {
1223                 struct node_mem_mask *n = &node_masks[i];
1224
1225                 if ((grp->mask == n->mask) && (grp->match == n->val))
1226                         break;
1227         }
1228         return i;
1229 }
1230
1231 static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
1232                                           int index)
1233 {
1234         u64 arc;
1235
1236         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1237                 int tnode;
1238                 u64 target = mdesc_arc_target(md, arc);
1239                 struct mdesc_mlgroup *m = find_mlgroup(target);
1240
1241                 if (!m)
1242                         continue;
1243                 tnode = find_best_numa_node_for_mlgroup(m);
1244                 if (tnode == MAX_NUMNODES)
1245                         continue;
1246                 numa_latency[index][tnode] = m->latency;
1247         }
1248 }
1249
1250 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1251                                       int index)
1252 {
1253         struct mdesc_mlgroup *candidate = NULL;
1254         u64 arc, best_latency = ~(u64)0;
1255         struct node_mem_mask *n;
1256
1257         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1258                 u64 target = mdesc_arc_target(md, arc);
1259                 struct mdesc_mlgroup *m = find_mlgroup(target);
1260                 if (!m)
1261                         continue;
1262                 if (m->latency < best_latency) {
1263                         candidate = m;
1264                         best_latency = m->latency;
1265                 }
1266         }
1267         if (!candidate)
1268                 return -ENOENT;
1269
1270         if (num_node_masks != index) {
1271                 printk(KERN_ERR "Inconsistent NUMA state, "
1272                        "index[%d] != num_node_masks[%d]\n",
1273                        index, num_node_masks);
1274                 return -EINVAL;
1275         }
1276
1277         n = &node_masks[num_node_masks++];
1278
1279         n->mask = candidate->mask;
1280         n->val = candidate->match;
1281
1282         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1283                 index, n->mask, n->val, candidate->latency);
1284
1285         return 0;
1286 }
1287
1288 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1289                                          int index)
1290 {
1291         cpumask_t mask;
1292         int cpu;
1293
1294         numa_parse_mdesc_group_cpus(md, grp, &mask);
1295
1296         for_each_cpu(cpu, &mask)
1297                 numa_cpu_lookup_table[cpu] = index;
1298         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1299
1300         if (numa_debug) {
1301                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1302                 for_each_cpu(cpu, &mask)
1303                         printk("%d ", cpu);
1304                 printk("]\n");
1305         }
1306
1307         return numa_attach_mlgroup(md, grp, index);
1308 }
1309
1310 static int __init numa_parse_mdesc(void)
1311 {
1312         struct mdesc_handle *md = mdesc_grab();
1313         int i, j, err, count;
1314         u64 node;
1315
1316         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1317         if (node == MDESC_NODE_NULL) {
1318                 mdesc_release(md);
1319                 return -ENOENT;
1320         }
1321
1322         err = grab_mblocks(md);
1323         if (err < 0)
1324                 goto out;
1325
1326         err = grab_mlgroups(md);
1327         if (err < 0)
1328                 goto out;
1329
1330         count = 0;
1331         mdesc_for_each_node_by_name(md, node, "group") {
1332                 err = numa_parse_mdesc_group(md, node, count);
1333                 if (err < 0)
1334                         break;
1335                 count++;
1336         }
1337
1338         count = 0;
1339         mdesc_for_each_node_by_name(md, node, "group") {
1340                 find_numa_latencies_for_group(md, node, count);
1341                 count++;
1342         }
1343
1344         /* Normalize numa latency matrix according to ACPI SLIT spec. */
1345         for (i = 0; i < MAX_NUMNODES; i++) {
1346                 u64 self_latency = numa_latency[i][i];
1347
1348                 for (j = 0; j < MAX_NUMNODES; j++) {
1349                         numa_latency[i][j] =
1350                                 (numa_latency[i][j] * LOCAL_DISTANCE) /
1351                                 self_latency;
1352                 }
1353         }
1354
1355         add_node_ranges();
1356
1357         for (i = 0; i < num_node_masks; i++) {
1358                 allocate_node_data(i);
1359                 node_set_online(i);
1360         }
1361
1362         err = 0;
1363 out:
1364         mdesc_release(md);
1365         return err;
1366 }
1367
1368 static int __init numa_parse_jbus(void)
1369 {
1370         unsigned long cpu, index;
1371
1372         /* NUMA node id is encoded in bits 36 and higher, and there is
1373          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1374          */
1375         index = 0;
1376         for_each_present_cpu(cpu) {
1377                 numa_cpu_lookup_table[cpu] = index;
1378                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1379                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1380                 node_masks[index].val = cpu << 36UL;
1381
1382                 index++;
1383         }
1384         num_node_masks = index;
1385
1386         add_node_ranges();
1387
1388         for (index = 0; index < num_node_masks; index++) {
1389                 allocate_node_data(index);
1390                 node_set_online(index);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int __init numa_parse_sun4u(void)
1397 {
1398         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1399                 unsigned long ver;
1400
1401                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1402                 if ((ver >> 32UL) == __JALAPENO_ID ||
1403                     (ver >> 32UL) == __SERRANO_ID)
1404                         return numa_parse_jbus();
1405         }
1406         return -1;
1407 }
1408
1409 static int __init bootmem_init_numa(void)
1410 {
1411         int i, j;
1412         int err = -1;
1413
1414         numadbg("bootmem_init_numa()\n");
1415
1416         /* Some sane defaults for numa latency values */
1417         for (i = 0; i < MAX_NUMNODES; i++) {
1418                 for (j = 0; j < MAX_NUMNODES; j++)
1419                         numa_latency[i][j] = (i == j) ?
1420                                 LOCAL_DISTANCE : REMOTE_DISTANCE;
1421         }
1422
1423         if (numa_enabled) {
1424                 if (tlb_type == hypervisor)
1425                         err = numa_parse_mdesc();
1426                 else
1427                         err = numa_parse_sun4u();
1428         }
1429         return err;
1430 }
1431
1432 #else
1433
1434 static int bootmem_init_numa(void)
1435 {
1436         return -1;
1437 }
1438
1439 #endif
1440
1441 static void __init bootmem_init_nonnuma(void)
1442 {
1443         unsigned long top_of_ram = memblock_end_of_DRAM();
1444         unsigned long total_ram = memblock_phys_mem_size();
1445
1446         numadbg("bootmem_init_nonnuma()\n");
1447
1448         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1449                top_of_ram, total_ram);
1450         printk(KERN_INFO "Memory hole size: %ldMB\n",
1451                (top_of_ram - total_ram) >> 20);
1452
1453         init_node_masks_nonnuma();
1454         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1455         allocate_node_data(0);
1456         node_set_online(0);
1457 }
1458
1459 static unsigned long __init bootmem_init(unsigned long phys_base)
1460 {
1461         unsigned long end_pfn;
1462
1463         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1464         max_pfn = max_low_pfn = end_pfn;
1465         min_low_pfn = (phys_base >> PAGE_SHIFT);
1466
1467         if (bootmem_init_numa() < 0)
1468                 bootmem_init_nonnuma();
1469
1470         /* Dump memblock with node info. */
1471         memblock_dump_all();
1472
1473         /* XXX cpu notifier XXX */
1474
1475         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1476         sparse_init();
1477
1478         return end_pfn;
1479 }
1480
1481 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1482 static int pall_ents __initdata;
1483
1484 static unsigned long max_phys_bits = 40;
1485
1486 bool kern_addr_valid(unsigned long addr)
1487 {
1488         pgd_t *pgd;
1489         pud_t *pud;
1490         pmd_t *pmd;
1491         pte_t *pte;
1492
1493         if ((long)addr < 0L) {
1494                 unsigned long pa = __pa(addr);
1495
1496                 if ((addr >> max_phys_bits) != 0UL)
1497                         return false;
1498
1499                 return pfn_valid(pa >> PAGE_SHIFT);
1500         }
1501
1502         if (addr >= (unsigned long) KERNBASE &&
1503             addr < (unsigned long)&_end)
1504                 return true;
1505
1506         pgd = pgd_offset_k(addr);
1507         if (pgd_none(*pgd))
1508                 return 0;
1509
1510         pud = pud_offset(pgd, addr);
1511         if (pud_none(*pud))
1512                 return 0;
1513
1514         if (pud_large(*pud))
1515                 return pfn_valid(pud_pfn(*pud));
1516
1517         pmd = pmd_offset(pud, addr);
1518         if (pmd_none(*pmd))
1519                 return 0;
1520
1521         if (pmd_large(*pmd))
1522                 return pfn_valid(pmd_pfn(*pmd));
1523
1524         pte = pte_offset_kernel(pmd, addr);
1525         if (pte_none(*pte))
1526                 return 0;
1527
1528         return pfn_valid(pte_pfn(*pte));
1529 }
1530 EXPORT_SYMBOL(kern_addr_valid);
1531
1532 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1533                                               unsigned long vend,
1534                                               pud_t *pud)
1535 {
1536         const unsigned long mask16gb = (1UL << 34) - 1UL;
1537         u64 pte_val = vstart;
1538
1539         /* Each PUD is 8GB */
1540         if ((vstart & mask16gb) ||
1541             (vend - vstart <= mask16gb)) {
1542                 pte_val ^= kern_linear_pte_xor[2];
1543                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1544
1545                 return vstart + PUD_SIZE;
1546         }
1547
1548         pte_val ^= kern_linear_pte_xor[3];
1549         pte_val |= _PAGE_PUD_HUGE;
1550
1551         vend = vstart + mask16gb + 1UL;
1552         while (vstart < vend) {
1553                 pud_val(*pud) = pte_val;
1554
1555                 pte_val += PUD_SIZE;
1556                 vstart += PUD_SIZE;
1557                 pud++;
1558         }
1559         return vstart;
1560 }
1561
1562 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1563                                    bool guard)
1564 {
1565         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1566                 return true;
1567
1568         return false;
1569 }
1570
1571 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1572                                               unsigned long vend,
1573                                               pmd_t *pmd)
1574 {
1575         const unsigned long mask256mb = (1UL << 28) - 1UL;
1576         const unsigned long mask2gb = (1UL << 31) - 1UL;
1577         u64 pte_val = vstart;
1578
1579         /* Each PMD is 8MB */
1580         if ((vstart & mask256mb) ||
1581             (vend - vstart <= mask256mb)) {
1582                 pte_val ^= kern_linear_pte_xor[0];
1583                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1584
1585                 return vstart + PMD_SIZE;
1586         }
1587
1588         if ((vstart & mask2gb) ||
1589             (vend - vstart <= mask2gb)) {
1590                 pte_val ^= kern_linear_pte_xor[1];
1591                 pte_val |= _PAGE_PMD_HUGE;
1592                 vend = vstart + mask256mb + 1UL;
1593         } else {
1594                 pte_val ^= kern_linear_pte_xor[2];
1595                 pte_val |= _PAGE_PMD_HUGE;
1596                 vend = vstart + mask2gb + 1UL;
1597         }
1598
1599         while (vstart < vend) {
1600                 pmd_val(*pmd) = pte_val;
1601
1602                 pte_val += PMD_SIZE;
1603                 vstart += PMD_SIZE;
1604                 pmd++;
1605         }
1606
1607         return vstart;
1608 }
1609
1610 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1611                                    bool guard)
1612 {
1613         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1614                 return true;
1615
1616         return false;
1617 }
1618
1619 static unsigned long __ref kernel_map_range(unsigned long pstart,
1620                                             unsigned long pend, pgprot_t prot,
1621                                             bool use_huge)
1622 {
1623         unsigned long vstart = PAGE_OFFSET + pstart;
1624         unsigned long vend = PAGE_OFFSET + pend;
1625         unsigned long alloc_bytes = 0UL;
1626
1627         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1628                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1629                             vstart, vend);
1630                 prom_halt();
1631         }
1632
1633         while (vstart < vend) {
1634                 unsigned long this_end, paddr = __pa(vstart);
1635                 pgd_t *pgd = pgd_offset_k(vstart);
1636                 pud_t *pud;
1637                 pmd_t *pmd;
1638                 pte_t *pte;
1639
1640                 if (pgd_none(*pgd)) {
1641                         pud_t *new;
1642
1643                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1644                         alloc_bytes += PAGE_SIZE;
1645                         pgd_populate(&init_mm, pgd, new);
1646                 }
1647                 pud = pud_offset(pgd, vstart);
1648                 if (pud_none(*pud)) {
1649                         pmd_t *new;
1650
1651                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1652                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1653                                 continue;
1654                         }
1655                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1656                         alloc_bytes += PAGE_SIZE;
1657                         pud_populate(&init_mm, pud, new);
1658                 }
1659
1660                 pmd = pmd_offset(pud, vstart);
1661                 if (pmd_none(*pmd)) {
1662                         pte_t *new;
1663
1664                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1665                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1666                                 continue;
1667                         }
1668                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1669                         alloc_bytes += PAGE_SIZE;
1670                         pmd_populate_kernel(&init_mm, pmd, new);
1671                 }
1672
1673                 pte = pte_offset_kernel(pmd, vstart);
1674                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1675                 if (this_end > vend)
1676                         this_end = vend;
1677
1678                 while (vstart < this_end) {
1679                         pte_val(*pte) = (paddr | pgprot_val(prot));
1680
1681                         vstart += PAGE_SIZE;
1682                         paddr += PAGE_SIZE;
1683                         pte++;
1684                 }
1685         }
1686
1687         return alloc_bytes;
1688 }
1689
1690 static void __init flush_all_kernel_tsbs(void)
1691 {
1692         int i;
1693
1694         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1695                 struct tsb *ent = &swapper_tsb[i];
1696
1697                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1698         }
1699 #ifndef CONFIG_DEBUG_PAGEALLOC
1700         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1701                 struct tsb *ent = &swapper_4m_tsb[i];
1702
1703                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1704         }
1705 #endif
1706 }
1707
1708 extern unsigned int kvmap_linear_patch[1];
1709
1710 static void __init kernel_physical_mapping_init(void)
1711 {
1712         unsigned long i, mem_alloced = 0UL;
1713         bool use_huge = true;
1714
1715 #ifdef CONFIG_DEBUG_PAGEALLOC
1716         use_huge = false;
1717 #endif
1718         for (i = 0; i < pall_ents; i++) {
1719                 unsigned long phys_start, phys_end;
1720
1721                 phys_start = pall[i].phys_addr;
1722                 phys_end = phys_start + pall[i].reg_size;
1723
1724                 mem_alloced += kernel_map_range(phys_start, phys_end,
1725                                                 PAGE_KERNEL, use_huge);
1726         }
1727
1728         printk("Allocated %ld bytes for kernel page tables.\n",
1729                mem_alloced);
1730
1731         kvmap_linear_patch[0] = 0x01000000; /* nop */
1732         flushi(&kvmap_linear_patch[0]);
1733
1734         flush_all_kernel_tsbs();
1735
1736         __flush_tlb_all();
1737 }
1738
1739 #ifdef CONFIG_DEBUG_PAGEALLOC
1740 void __kernel_map_pages(struct page *page, int numpages, int enable)
1741 {
1742         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1743         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1744
1745         kernel_map_range(phys_start, phys_end,
1746                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1747
1748         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1749                                PAGE_OFFSET + phys_end);
1750
1751         /* we should perform an IPI and flush all tlbs,
1752          * but that can deadlock->flush only current cpu.
1753          */
1754         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1755                                  PAGE_OFFSET + phys_end);
1756 }
1757 #endif
1758
1759 unsigned long __init find_ecache_flush_span(unsigned long size)
1760 {
1761         int i;
1762
1763         for (i = 0; i < pavail_ents; i++) {
1764                 if (pavail[i].reg_size >= size)
1765                         return pavail[i].phys_addr;
1766         }
1767
1768         return ~0UL;
1769 }
1770
1771 unsigned long PAGE_OFFSET;
1772 EXPORT_SYMBOL(PAGE_OFFSET);
1773
1774 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1775 EXPORT_SYMBOL(VMALLOC_END);
1776
1777 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1778 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1779
1780 static void __init setup_page_offset(void)
1781 {
1782         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1783                 /* Cheetah/Panther support a full 64-bit virtual
1784                  * address, so we can use all that our page tables
1785                  * support.
1786                  */
1787                 sparc64_va_hole_top =    0xfff0000000000000UL;
1788                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1789
1790                 max_phys_bits = 42;
1791         } else if (tlb_type == hypervisor) {
1792                 switch (sun4v_chip_type) {
1793                 case SUN4V_CHIP_NIAGARA1:
1794                 case SUN4V_CHIP_NIAGARA2:
1795                         /* T1 and T2 support 48-bit virtual addresses.  */
1796                         sparc64_va_hole_top =    0xffff800000000000UL;
1797                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1798
1799                         max_phys_bits = 39;
1800                         break;
1801                 case SUN4V_CHIP_NIAGARA3:
1802                         /* T3 supports 48-bit virtual addresses.  */
1803                         sparc64_va_hole_top =    0xffff800000000000UL;
1804                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1805
1806                         max_phys_bits = 43;
1807                         break;
1808                 case SUN4V_CHIP_NIAGARA4:
1809                 case SUN4V_CHIP_NIAGARA5:
1810                 case SUN4V_CHIP_SPARC64X:
1811                 case SUN4V_CHIP_SPARC_M6:
1812                         /* T4 and later support 52-bit virtual addresses.  */
1813                         sparc64_va_hole_top =    0xfff8000000000000UL;
1814                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1815                         max_phys_bits = 47;
1816                         break;
1817                 case SUN4V_CHIP_SPARC_M7:
1818                 default:
1819                         /* M7 and later support 52-bit virtual addresses.  */
1820                         sparc64_va_hole_top =    0xfff8000000000000UL;
1821                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1822                         max_phys_bits = 49;
1823                         break;
1824                 }
1825         }
1826
1827         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1828                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1829                             max_phys_bits);
1830                 prom_halt();
1831         }
1832
1833         PAGE_OFFSET = sparc64_va_hole_top;
1834         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1835                        (sparc64_va_hole_bottom >> 2));
1836
1837         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1838                 PAGE_OFFSET, max_phys_bits);
1839         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1840                 VMALLOC_START, VMALLOC_END);
1841         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1842                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1843 }
1844
1845 static void __init tsb_phys_patch(void)
1846 {
1847         struct tsb_ldquad_phys_patch_entry *pquad;
1848         struct tsb_phys_patch_entry *p;
1849
1850         pquad = &__tsb_ldquad_phys_patch;
1851         while (pquad < &__tsb_ldquad_phys_patch_end) {
1852                 unsigned long addr = pquad->addr;
1853
1854                 if (tlb_type == hypervisor)
1855                         *(unsigned int *) addr = pquad->sun4v_insn;
1856                 else
1857                         *(unsigned int *) addr = pquad->sun4u_insn;
1858                 wmb();
1859                 __asm__ __volatile__("flush     %0"
1860                                      : /* no outputs */
1861                                      : "r" (addr));
1862
1863                 pquad++;
1864         }
1865
1866         p = &__tsb_phys_patch;
1867         while (p < &__tsb_phys_patch_end) {
1868                 unsigned long addr = p->addr;
1869
1870                 *(unsigned int *) addr = p->insn;
1871                 wmb();
1872                 __asm__ __volatile__("flush     %0"
1873                                      : /* no outputs */
1874                                      : "r" (addr));
1875
1876                 p++;
1877         }
1878 }
1879
1880 /* Don't mark as init, we give this to the Hypervisor.  */
1881 #ifndef CONFIG_DEBUG_PAGEALLOC
1882 #define NUM_KTSB_DESCR  2
1883 #else
1884 #define NUM_KTSB_DESCR  1
1885 #endif
1886 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1887
1888 /* The swapper TSBs are loaded with a base sequence of:
1889  *
1890  *      sethi   %uhi(SYMBOL), REG1
1891  *      sethi   %hi(SYMBOL), REG2
1892  *      or      REG1, %ulo(SYMBOL), REG1
1893  *      or      REG2, %lo(SYMBOL), REG2
1894  *      sllx    REG1, 32, REG1
1895  *      or      REG1, REG2, REG1
1896  *
1897  * When we use physical addressing for the TSB accesses, we patch the
1898  * first four instructions in the above sequence.
1899  */
1900
1901 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1902 {
1903         unsigned long high_bits, low_bits;
1904
1905         high_bits = (pa >> 32) & 0xffffffff;
1906         low_bits = (pa >> 0) & 0xffffffff;
1907
1908         while (start < end) {
1909                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1910
1911                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1912                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1913
1914                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1915                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1916
1917                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1918                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
1919
1920                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1921                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
1922
1923                 start++;
1924         }
1925 }
1926
1927 static void ktsb_phys_patch(void)
1928 {
1929         extern unsigned int __swapper_tsb_phys_patch;
1930         extern unsigned int __swapper_tsb_phys_patch_end;
1931         unsigned long ktsb_pa;
1932
1933         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1934         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1935                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1936 #ifndef CONFIG_DEBUG_PAGEALLOC
1937         {
1938         extern unsigned int __swapper_4m_tsb_phys_patch;
1939         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1940         ktsb_pa = (kern_base +
1941                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1942         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1943                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1944         }
1945 #endif
1946 }
1947
1948 static void __init sun4v_ktsb_init(void)
1949 {
1950         unsigned long ktsb_pa;
1951
1952         /* First KTSB for PAGE_SIZE mappings.  */
1953         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1954
1955         switch (PAGE_SIZE) {
1956         case 8 * 1024:
1957         default:
1958                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1959                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1960                 break;
1961
1962         case 64 * 1024:
1963                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1964                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1965                 break;
1966
1967         case 512 * 1024:
1968                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1969                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1970                 break;
1971
1972         case 4 * 1024 * 1024:
1973                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1974                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1975                 break;
1976         }
1977
1978         ktsb_descr[0].assoc = 1;
1979         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1980         ktsb_descr[0].ctx_idx = 0;
1981         ktsb_descr[0].tsb_base = ktsb_pa;
1982         ktsb_descr[0].resv = 0;
1983
1984 #ifndef CONFIG_DEBUG_PAGEALLOC
1985         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1986         ktsb_pa = (kern_base +
1987                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1988
1989         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1990         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1991                                     HV_PGSZ_MASK_256MB |
1992                                     HV_PGSZ_MASK_2GB |
1993                                     HV_PGSZ_MASK_16GB) &
1994                                    cpu_pgsz_mask);
1995         ktsb_descr[1].assoc = 1;
1996         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1997         ktsb_descr[1].ctx_idx = 0;
1998         ktsb_descr[1].tsb_base = ktsb_pa;
1999         ktsb_descr[1].resv = 0;
2000 #endif
2001 }
2002
2003 void sun4v_ktsb_register(void)
2004 {
2005         unsigned long pa, ret;
2006
2007         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2008
2009         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2010         if (ret != 0) {
2011                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2012                             "errors with %lx\n", pa, ret);
2013                 prom_halt();
2014         }
2015 }
2016
2017 static void __init sun4u_linear_pte_xor_finalize(void)
2018 {
2019 #ifndef CONFIG_DEBUG_PAGEALLOC
2020         /* This is where we would add Panther support for
2021          * 32MB and 256MB pages.
2022          */
2023 #endif
2024 }
2025
2026 static void __init sun4v_linear_pte_xor_finalize(void)
2027 {
2028         unsigned long pagecv_flag;
2029
2030         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2031          * enables MCD error. Do not set bit 9 on M7 processor.
2032          */
2033         switch (sun4v_chip_type) {
2034         case SUN4V_CHIP_SPARC_M7:
2035                 pagecv_flag = 0x00;
2036                 break;
2037         default:
2038                 pagecv_flag = _PAGE_CV_4V;
2039                 break;
2040         }
2041 #ifndef CONFIG_DEBUG_PAGEALLOC
2042         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2043                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2044                         PAGE_OFFSET;
2045                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2046                                            _PAGE_P_4V | _PAGE_W_4V);
2047         } else {
2048                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2049         }
2050
2051         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2052                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2053                         PAGE_OFFSET;
2054                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2055                                            _PAGE_P_4V | _PAGE_W_4V);
2056         } else {
2057                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2058         }
2059
2060         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2061                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2062                         PAGE_OFFSET;
2063                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2064                                            _PAGE_P_4V | _PAGE_W_4V);
2065         } else {
2066                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2067         }
2068 #endif
2069 }
2070
2071 /* paging_init() sets up the page tables */
2072
2073 static unsigned long last_valid_pfn;
2074
2075 static void sun4u_pgprot_init(void);
2076 static void sun4v_pgprot_init(void);
2077
2078 static phys_addr_t __init available_memory(void)
2079 {
2080         phys_addr_t available = 0ULL;
2081         phys_addr_t pa_start, pa_end;
2082         u64 i;
2083
2084         for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2085                                 &pa_end, NULL)
2086                 available = available + (pa_end  - pa_start);
2087
2088         return available;
2089 }
2090
2091 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2092 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2093 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2094 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2095 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2096 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2097
2098 /* We need to exclude reserved regions. This exclusion will include
2099  * vmlinux and initrd. To be more precise the initrd size could be used to
2100  * compute a new lower limit because it is freed later during initialization.
2101  */
2102 static void __init reduce_memory(phys_addr_t limit_ram)
2103 {
2104         phys_addr_t avail_ram = available_memory();
2105         phys_addr_t pa_start, pa_end;
2106         u64 i;
2107
2108         if (limit_ram >= avail_ram)
2109                 return;
2110
2111         for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2112                                 &pa_end, NULL) {
2113                 phys_addr_t region_size = pa_end - pa_start;
2114                 phys_addr_t clip_start = pa_start;
2115
2116                 avail_ram = avail_ram - region_size;
2117                 /* Are we consuming too much? */
2118                 if (avail_ram < limit_ram) {
2119                         phys_addr_t give_back = limit_ram - avail_ram;
2120
2121                         region_size = region_size - give_back;
2122                         clip_start = clip_start + give_back;
2123                 }
2124
2125                 memblock_remove(clip_start, region_size);
2126
2127                 if (avail_ram <= limit_ram)
2128                         break;
2129                 i = 0UL;
2130         }
2131 }
2132
2133 void __init paging_init(void)
2134 {
2135         unsigned long end_pfn, shift, phys_base;
2136         unsigned long real_end, i;
2137         int node;
2138
2139         setup_page_offset();
2140
2141         /* These build time checkes make sure that the dcache_dirty_cpu()
2142          * page->flags usage will work.
2143          *
2144          * When a page gets marked as dcache-dirty, we store the
2145          * cpu number starting at bit 32 in the page->flags.  Also,
2146          * functions like clear_dcache_dirty_cpu use the cpu mask
2147          * in 13-bit signed-immediate instruction fields.
2148          */
2149
2150         /*
2151          * Page flags must not reach into upper 32 bits that are used
2152          * for the cpu number
2153          */
2154         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2155
2156         /*
2157          * The bit fields placed in the high range must not reach below
2158          * the 32 bit boundary. Otherwise we cannot place the cpu field
2159          * at the 32 bit boundary.
2160          */
2161         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2162                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2163
2164         BUILD_BUG_ON(NR_CPUS > 4096);
2165
2166         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2167         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2168
2169         /* Invalidate both kernel TSBs.  */
2170         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2171 #ifndef CONFIG_DEBUG_PAGEALLOC
2172         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2173 #endif
2174
2175         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2176          * bit on M7 processor. This is a conflicting usage of the same
2177          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2178          * Detection error on all pages and this will lead to problems
2179          * later. Kernel does not run with MCD enabled and hence rest
2180          * of the required steps to fully configure memory corruption
2181          * detection are not taken. We need to ensure TTE.mcde is not
2182          * set on M7 processor. Compute the value of cacheability
2183          * flag for use later taking this into consideration.
2184          */
2185         switch (sun4v_chip_type) {
2186         case SUN4V_CHIP_SPARC_M7:
2187                 page_cache4v_flag = _PAGE_CP_4V;
2188                 break;
2189         default:
2190                 page_cache4v_flag = _PAGE_CACHE_4V;
2191                 break;
2192         }
2193
2194         if (tlb_type == hypervisor)
2195                 sun4v_pgprot_init();
2196         else
2197                 sun4u_pgprot_init();
2198
2199         if (tlb_type == cheetah_plus ||
2200             tlb_type == hypervisor) {
2201                 tsb_phys_patch();
2202                 ktsb_phys_patch();
2203         }
2204
2205         if (tlb_type == hypervisor)
2206                 sun4v_patch_tlb_handlers();
2207
2208         /* Find available physical memory...
2209          *
2210          * Read it twice in order to work around a bug in openfirmware.
2211          * The call to grab this table itself can cause openfirmware to
2212          * allocate memory, which in turn can take away some space from
2213          * the list of available memory.  Reading it twice makes sure
2214          * we really do get the final value.
2215          */
2216         read_obp_translations();
2217         read_obp_memory("reg", &pall[0], &pall_ents);
2218         read_obp_memory("available", &pavail[0], &pavail_ents);
2219         read_obp_memory("available", &pavail[0], &pavail_ents);
2220
2221         phys_base = 0xffffffffffffffffUL;
2222         for (i = 0; i < pavail_ents; i++) {
2223                 phys_base = min(phys_base, pavail[i].phys_addr);
2224                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2225         }
2226
2227         memblock_reserve(kern_base, kern_size);
2228
2229         find_ramdisk(phys_base);
2230
2231         if (cmdline_memory_size)
2232                 reduce_memory(cmdline_memory_size);
2233
2234         memblock_allow_resize();
2235         memblock_dump_all();
2236
2237         set_bit(0, mmu_context_bmap);
2238
2239         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2240
2241         real_end = (unsigned long)_end;
2242         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2243         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2244                num_kernel_image_mappings);
2245
2246         /* Set kernel pgd to upper alias so physical page computations
2247          * work.
2248          */
2249         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2250
2251         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2252
2253         inherit_prom_mappings();
2254
2255         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2256         setup_tba();
2257
2258         __flush_tlb_all();
2259
2260         prom_build_devicetree();
2261         of_populate_present_mask();
2262 #ifndef CONFIG_SMP
2263         of_fill_in_cpu_data();
2264 #endif
2265
2266         if (tlb_type == hypervisor) {
2267                 sun4v_mdesc_init();
2268                 mdesc_populate_present_mask(cpu_all_mask);
2269 #ifndef CONFIG_SMP
2270                 mdesc_fill_in_cpu_data(cpu_all_mask);
2271 #endif
2272                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2273
2274                 sun4v_linear_pte_xor_finalize();
2275
2276                 sun4v_ktsb_init();
2277                 sun4v_ktsb_register();
2278         } else {
2279                 unsigned long impl, ver;
2280
2281                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2282                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2283
2284                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2285                 impl = ((ver >> 32) & 0xffff);
2286                 if (impl == PANTHER_IMPL)
2287                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2288                                           HV_PGSZ_MASK_256MB);
2289
2290                 sun4u_linear_pte_xor_finalize();
2291         }
2292
2293         /* Flush the TLBs and the 4M TSB so that the updated linear
2294          * pte XOR settings are realized for all mappings.
2295          */
2296         __flush_tlb_all();
2297 #ifndef CONFIG_DEBUG_PAGEALLOC
2298         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2299 #endif
2300         __flush_tlb_all();
2301
2302         /* Setup bootmem... */
2303         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2304
2305         /* Once the OF device tree and MDESC have been setup, we know
2306          * the list of possible cpus.  Therefore we can allocate the
2307          * IRQ stacks.
2308          */
2309         for_each_possible_cpu(i) {
2310                 node = cpu_to_node(i);
2311
2312                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2313                                                         THREAD_SIZE,
2314                                                         THREAD_SIZE, 0);
2315                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2316                                                         THREAD_SIZE,
2317                                                         THREAD_SIZE, 0);
2318         }
2319
2320         kernel_physical_mapping_init();
2321
2322         {
2323                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2324
2325                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2326
2327                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2328
2329                 free_area_init_nodes(max_zone_pfns);
2330         }
2331
2332         printk("Booting Linux...\n");
2333 }
2334
2335 int page_in_phys_avail(unsigned long paddr)
2336 {
2337         int i;
2338
2339         paddr &= PAGE_MASK;
2340
2341         for (i = 0; i < pavail_ents; i++) {
2342                 unsigned long start, end;
2343
2344                 start = pavail[i].phys_addr;
2345                 end = start + pavail[i].reg_size;
2346
2347                 if (paddr >= start && paddr < end)
2348                         return 1;
2349         }
2350         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2351                 return 1;
2352 #ifdef CONFIG_BLK_DEV_INITRD
2353         if (paddr >= __pa(initrd_start) &&
2354             paddr < __pa(PAGE_ALIGN(initrd_end)))
2355                 return 1;
2356 #endif
2357
2358         return 0;
2359 }
2360
2361 static void __init register_page_bootmem_info(void)
2362 {
2363 #ifdef CONFIG_NEED_MULTIPLE_NODES
2364         int i;
2365
2366         for_each_online_node(i)
2367                 if (NODE_DATA(i)->node_spanned_pages)
2368                         register_page_bootmem_info_node(NODE_DATA(i));
2369 #endif
2370 }
2371 void __init mem_init(void)
2372 {
2373         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2374
2375         register_page_bootmem_info();
2376         free_all_bootmem();
2377
2378         /*
2379          * Set up the zero page, mark it reserved, so that page count
2380          * is not manipulated when freeing the page from user ptes.
2381          */
2382         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2383         if (mem_map_zero == NULL) {
2384                 prom_printf("paging_init: Cannot alloc zero page.\n");
2385                 prom_halt();
2386         }
2387         mark_page_reserved(mem_map_zero);
2388
2389         mem_init_print_info(NULL);
2390
2391         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2392                 cheetah_ecache_flush_init();
2393 }
2394
2395 void free_initmem(void)
2396 {
2397         unsigned long addr, initend;
2398         int do_free = 1;
2399
2400         /* If the physical memory maps were trimmed by kernel command
2401          * line options, don't even try freeing this initmem stuff up.
2402          * The kernel image could have been in the trimmed out region
2403          * and if so the freeing below will free invalid page structs.
2404          */
2405         if (cmdline_memory_size)
2406                 do_free = 0;
2407
2408         /*
2409          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2410          */
2411         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2412         initend = (unsigned long)(__init_end) & PAGE_MASK;
2413         for (; addr < initend; addr += PAGE_SIZE) {
2414                 unsigned long page;
2415
2416                 page = (addr +
2417                         ((unsigned long) __va(kern_base)) -
2418                         ((unsigned long) KERNBASE));
2419                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2420
2421                 if (do_free)
2422                         free_reserved_page(virt_to_page(page));
2423         }
2424 }
2425
2426 #ifdef CONFIG_BLK_DEV_INITRD
2427 void free_initrd_mem(unsigned long start, unsigned long end)
2428 {
2429         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2430                            "initrd");
2431 }
2432 #endif
2433
2434 pgprot_t PAGE_KERNEL __read_mostly;
2435 EXPORT_SYMBOL(PAGE_KERNEL);
2436
2437 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2438 pgprot_t PAGE_COPY __read_mostly;
2439
2440 pgprot_t PAGE_SHARED __read_mostly;
2441 EXPORT_SYMBOL(PAGE_SHARED);
2442
2443 unsigned long pg_iobits __read_mostly;
2444
2445 unsigned long _PAGE_IE __read_mostly;
2446 EXPORT_SYMBOL(_PAGE_IE);
2447
2448 unsigned long _PAGE_E __read_mostly;
2449 EXPORT_SYMBOL(_PAGE_E);
2450
2451 unsigned long _PAGE_CACHE __read_mostly;
2452 EXPORT_SYMBOL(_PAGE_CACHE);
2453
2454 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2455 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2456                                int node)
2457 {
2458         unsigned long pte_base;
2459
2460         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2461                     _PAGE_CP_4U | _PAGE_CV_4U |
2462                     _PAGE_P_4U | _PAGE_W_4U);
2463         if (tlb_type == hypervisor)
2464                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2465                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2466
2467         pte_base |= _PAGE_PMD_HUGE;
2468
2469         vstart = vstart & PMD_MASK;
2470         vend = ALIGN(vend, PMD_SIZE);
2471         for (; vstart < vend; vstart += PMD_SIZE) {
2472                 pgd_t *pgd = pgd_offset_k(vstart);
2473                 unsigned long pte;
2474                 pud_t *pud;
2475                 pmd_t *pmd;
2476
2477                 if (pgd_none(*pgd)) {
2478                         pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2479
2480                         if (!new)
2481                                 return -ENOMEM;
2482                         pgd_populate(&init_mm, pgd, new);
2483                 }
2484
2485                 pud = pud_offset(pgd, vstart);
2486                 if (pud_none(*pud)) {
2487                         pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2488
2489                         if (!new)
2490                                 return -ENOMEM;
2491                         pud_populate(&init_mm, pud, new);
2492                 }
2493
2494                 pmd = pmd_offset(pud, vstart);
2495
2496                 pte = pmd_val(*pmd);
2497                 if (!(pte & _PAGE_VALID)) {
2498                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2499
2500                         if (!block)
2501                                 return -ENOMEM;
2502
2503                         pmd_val(*pmd) = pte_base | __pa(block);
2504                 }
2505         }
2506
2507         return 0;
2508 }
2509
2510 void vmemmap_free(unsigned long start, unsigned long end)
2511 {
2512 }
2513 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2514
2515 static void prot_init_common(unsigned long page_none,
2516                              unsigned long page_shared,
2517                              unsigned long page_copy,
2518                              unsigned long page_readonly,
2519                              unsigned long page_exec_bit)
2520 {
2521         PAGE_COPY = __pgprot(page_copy);
2522         PAGE_SHARED = __pgprot(page_shared);
2523
2524         protection_map[0x0] = __pgprot(page_none);
2525         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2526         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2527         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2528         protection_map[0x4] = __pgprot(page_readonly);
2529         protection_map[0x5] = __pgprot(page_readonly);
2530         protection_map[0x6] = __pgprot(page_copy);
2531         protection_map[0x7] = __pgprot(page_copy);
2532         protection_map[0x8] = __pgprot(page_none);
2533         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2534         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2535         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2536         protection_map[0xc] = __pgprot(page_readonly);
2537         protection_map[0xd] = __pgprot(page_readonly);
2538         protection_map[0xe] = __pgprot(page_shared);
2539         protection_map[0xf] = __pgprot(page_shared);
2540 }
2541
2542 static void __init sun4u_pgprot_init(void)
2543 {
2544         unsigned long page_none, page_shared, page_copy, page_readonly;
2545         unsigned long page_exec_bit;
2546         int i;
2547
2548         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2549                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2550                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2551                                 _PAGE_EXEC_4U);
2552         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2553                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2554                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2555                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2556
2557         _PAGE_IE = _PAGE_IE_4U;
2558         _PAGE_E = _PAGE_E_4U;
2559         _PAGE_CACHE = _PAGE_CACHE_4U;
2560
2561         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2562                      __ACCESS_BITS_4U | _PAGE_E_4U);
2563
2564 #ifdef CONFIG_DEBUG_PAGEALLOC
2565         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2566 #else
2567         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2568                 PAGE_OFFSET;
2569 #endif
2570         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2571                                    _PAGE_P_4U | _PAGE_W_4U);
2572
2573         for (i = 1; i < 4; i++)
2574                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2575
2576         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2577                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2578                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2579
2580
2581         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2582         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2583                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2584         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2585                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2586         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2587                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2588
2589         page_exec_bit = _PAGE_EXEC_4U;
2590
2591         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2592                          page_exec_bit);
2593 }
2594
2595 static void __init sun4v_pgprot_init(void)
2596 {
2597         unsigned long page_none, page_shared, page_copy, page_readonly;
2598         unsigned long page_exec_bit;
2599         int i;
2600
2601         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2602                                 page_cache4v_flag | _PAGE_P_4V |
2603                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2604                                 _PAGE_EXEC_4V);
2605         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2606
2607         _PAGE_IE = _PAGE_IE_4V;
2608         _PAGE_E = _PAGE_E_4V;
2609         _PAGE_CACHE = page_cache4v_flag;
2610
2611 #ifdef CONFIG_DEBUG_PAGEALLOC
2612         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2613 #else
2614         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2615                 PAGE_OFFSET;
2616 #endif
2617         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2618                                    _PAGE_W_4V);
2619
2620         for (i = 1; i < 4; i++)
2621                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2622
2623         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2624                      __ACCESS_BITS_4V | _PAGE_E_4V);
2625
2626         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2627                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2628                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2629                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2630
2631         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2632         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2633                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2634         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2635                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2636         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2637                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2638
2639         page_exec_bit = _PAGE_EXEC_4V;
2640
2641         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2642                          page_exec_bit);
2643 }
2644
2645 unsigned long pte_sz_bits(unsigned long sz)
2646 {
2647         if (tlb_type == hypervisor) {
2648                 switch (sz) {
2649                 case 8 * 1024:
2650                 default:
2651                         return _PAGE_SZ8K_4V;
2652                 case 64 * 1024:
2653                         return _PAGE_SZ64K_4V;
2654                 case 512 * 1024:
2655                         return _PAGE_SZ512K_4V;
2656                 case 4 * 1024 * 1024:
2657                         return _PAGE_SZ4MB_4V;
2658                 }
2659         } else {
2660                 switch (sz) {
2661                 case 8 * 1024:
2662                 default:
2663                         return _PAGE_SZ8K_4U;
2664                 case 64 * 1024:
2665                         return _PAGE_SZ64K_4U;
2666                 case 512 * 1024:
2667                         return _PAGE_SZ512K_4U;
2668                 case 4 * 1024 * 1024:
2669                         return _PAGE_SZ4MB_4U;
2670                 }
2671         }
2672 }
2673
2674 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2675 {
2676         pte_t pte;
2677
2678         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2679         pte_val(pte) |= (((unsigned long)space) << 32);
2680         pte_val(pte) |= pte_sz_bits(page_size);
2681
2682         return pte;
2683 }
2684
2685 static unsigned long kern_large_tte(unsigned long paddr)
2686 {
2687         unsigned long val;
2688
2689         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2690                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2691                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2692         if (tlb_type == hypervisor)
2693                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2694                        page_cache4v_flag | _PAGE_P_4V |
2695                        _PAGE_EXEC_4V | _PAGE_W_4V);
2696
2697         return val | paddr;
2698 }
2699
2700 /* If not locked, zap it. */
2701 void __flush_tlb_all(void)
2702 {
2703         unsigned long pstate;
2704         int i;
2705
2706         __asm__ __volatile__("flushw\n\t"
2707                              "rdpr      %%pstate, %0\n\t"
2708                              "wrpr      %0, %1, %%pstate"
2709                              : "=r" (pstate)
2710                              : "i" (PSTATE_IE));
2711         if (tlb_type == hypervisor) {
2712                 sun4v_mmu_demap_all();
2713         } else if (tlb_type == spitfire) {
2714                 for (i = 0; i < 64; i++) {
2715                         /* Spitfire Errata #32 workaround */
2716                         /* NOTE: Always runs on spitfire, so no
2717                          *       cheetah+ page size encodings.
2718                          */
2719                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2720                                              "flush     %%g6"
2721                                              : /* No outputs */
2722                                              : "r" (0),
2723                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2724
2725                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2726                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2727                                                      "membar #Sync"
2728                                                      : /* no outputs */
2729                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2730                                 spitfire_put_dtlb_data(i, 0x0UL);
2731                         }
2732
2733                         /* Spitfire Errata #32 workaround */
2734                         /* NOTE: Always runs on spitfire, so no
2735                          *       cheetah+ page size encodings.
2736                          */
2737                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2738                                              "flush     %%g6"
2739                                              : /* No outputs */
2740                                              : "r" (0),
2741                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2742
2743                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2744                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2745                                                      "membar #Sync"
2746                                                      : /* no outputs */
2747                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2748                                 spitfire_put_itlb_data(i, 0x0UL);
2749                         }
2750                 }
2751         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2752                 cheetah_flush_dtlb_all();
2753                 cheetah_flush_itlb_all();
2754         }
2755         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2756                              : : "r" (pstate));
2757 }
2758
2759 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2760                             unsigned long address)
2761 {
2762         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2763                                        __GFP_REPEAT | __GFP_ZERO);
2764         pte_t *pte = NULL;
2765
2766         if (page)
2767                 pte = (pte_t *) page_address(page);
2768
2769         return pte;
2770 }
2771
2772 pgtable_t pte_alloc_one(struct mm_struct *mm,
2773                         unsigned long address)
2774 {
2775         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2776                                        __GFP_REPEAT | __GFP_ZERO);
2777         if (!page)
2778                 return NULL;
2779         if (!pgtable_page_ctor(page)) {
2780                 free_hot_cold_page(page, 0);
2781                 return NULL;
2782         }
2783         return (pte_t *) page_address(page);
2784 }
2785
2786 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2787 {
2788         free_page((unsigned long)pte);
2789 }
2790
2791 static void __pte_free(pgtable_t pte)
2792 {
2793         struct page *page = virt_to_page(pte);
2794
2795         pgtable_page_dtor(page);
2796         __free_page(page);
2797 }
2798
2799 void pte_free(struct mm_struct *mm, pgtable_t pte)
2800 {
2801         __pte_free(pte);
2802 }
2803
2804 void pgtable_free(void *table, bool is_page)
2805 {
2806         if (is_page)
2807                 __pte_free(table);
2808         else
2809                 kmem_cache_free(pgtable_cache, table);
2810 }
2811
2812 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2813 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2814                           pmd_t *pmd)
2815 {
2816         unsigned long pte, flags;
2817         struct mm_struct *mm;
2818         pmd_t entry = *pmd;
2819
2820         if (!pmd_large(entry) || !pmd_young(entry))
2821                 return;
2822
2823         pte = pmd_val(entry);
2824
2825         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2826         if (!(pte & _PAGE_VALID))
2827                 return;
2828
2829         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2830         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2831
2832         mm = vma->vm_mm;
2833
2834         spin_lock_irqsave(&mm->context.lock, flags);
2835
2836         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2837                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2838                                         addr, pte);
2839
2840         spin_unlock_irqrestore(&mm->context.lock, flags);
2841 }
2842 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2843
2844 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2845 static void context_reload(void *__data)
2846 {
2847         struct mm_struct *mm = __data;
2848
2849         if (mm == current->mm)
2850                 load_secondary_context(mm);
2851 }
2852
2853 void hugetlb_setup(struct pt_regs *regs)
2854 {
2855         struct mm_struct *mm = current->mm;
2856         struct tsb_config *tp;
2857
2858         if (faulthandler_disabled() || !mm) {
2859                 const struct exception_table_entry *entry;
2860
2861                 entry = search_exception_tables(regs->tpc);
2862                 if (entry) {
2863                         regs->tpc = entry->fixup;
2864                         regs->tnpc = regs->tpc + 4;
2865                         return;
2866                 }
2867                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2868                 die_if_kernel("HugeTSB in atomic", regs);
2869         }
2870
2871         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2872         if (likely(tp->tsb == NULL))
2873                 tsb_grow(mm, MM_TSB_HUGE, 0);
2874
2875         tsb_context_switch(mm);
2876         smp_tsb_sync(mm);
2877
2878         /* On UltraSPARC-III+ and later, configure the second half of
2879          * the Data-TLB for huge pages.
2880          */
2881         if (tlb_type == cheetah_plus) {
2882                 bool need_context_reload = false;
2883                 unsigned long ctx;
2884
2885                 spin_lock_irq(&ctx_alloc_lock);
2886                 ctx = mm->context.sparc64_ctx_val;
2887                 ctx &= ~CTX_PGSZ_MASK;
2888                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2889                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2890
2891                 if (ctx != mm->context.sparc64_ctx_val) {
2892                         /* When changing the page size fields, we
2893                          * must perform a context flush so that no
2894                          * stale entries match.  This flush must
2895                          * occur with the original context register
2896                          * settings.
2897                          */
2898                         do_flush_tlb_mm(mm);
2899
2900                         /* Reload the context register of all processors
2901                          * also executing in this address space.
2902                          */
2903                         mm->context.sparc64_ctx_val = ctx;
2904                         need_context_reload = true;
2905                 }
2906                 spin_unlock_irq(&ctx_alloc_lock);
2907
2908                 if (need_context_reload)
2909                         on_each_cpu(context_reload, mm, 0);
2910         }
2911 }
2912 #endif
2913
2914 static struct resource code_resource = {
2915         .name   = "Kernel code",
2916         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2917 };
2918
2919 static struct resource data_resource = {
2920         .name   = "Kernel data",
2921         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2922 };
2923
2924 static struct resource bss_resource = {
2925         .name   = "Kernel bss",
2926         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2927 };
2928
2929 static inline resource_size_t compute_kern_paddr(void *addr)
2930 {
2931         return (resource_size_t) (addr - KERNBASE + kern_base);
2932 }
2933
2934 static void __init kernel_lds_init(void)
2935 {
2936         code_resource.start = compute_kern_paddr(_text);
2937         code_resource.end   = compute_kern_paddr(_etext - 1);
2938         data_resource.start = compute_kern_paddr(_etext);
2939         data_resource.end   = compute_kern_paddr(_edata - 1);
2940         bss_resource.start  = compute_kern_paddr(__bss_start);
2941         bss_resource.end    = compute_kern_paddr(_end - 1);
2942 }
2943
2944 static int __init report_memory(void)
2945 {
2946         int i;
2947         struct resource *res;
2948
2949         kernel_lds_init();
2950
2951         for (i = 0; i < pavail_ents; i++) {
2952                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2953
2954                 if (!res) {
2955                         pr_warn("Failed to allocate source.\n");
2956                         break;
2957                 }
2958
2959                 res->name = "System RAM";
2960                 res->start = pavail[i].phys_addr;
2961                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2962                 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
2963
2964                 if (insert_resource(&iomem_resource, res) < 0) {
2965                         pr_warn("Resource insertion failed.\n");
2966                         break;
2967                 }
2968
2969                 insert_resource(res, &code_resource);
2970                 insert_resource(res, &data_resource);
2971                 insert_resource(res, &bss_resource);
2972         }
2973
2974         return 0;
2975 }
2976 arch_initcall(report_memory);
2977
2978 #ifdef CONFIG_SMP
2979 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2980 #else
2981 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2982 #endif
2983
2984 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2985 {
2986         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2987                 if (start < LOW_OBP_ADDRESS) {
2988                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2989                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2990                 }
2991                 if (end > HI_OBP_ADDRESS) {
2992                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2993                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2994                 }
2995         } else {
2996                 flush_tsb_kernel_range(start, end);
2997                 do_flush_tlb_kernel_range(start, end);
2998         }
2999 }