Upgrade to 4.4.50-rt62
[kvmfornfv.git] / kernel / arch / sparc / kernel / vmlinux.lds.S
1 /* ld script for sparc32/sparc64 kernel */
2
3 #include <asm-generic/vmlinux.lds.h>
4
5 #include <asm/page.h>
6 #include <asm/thread_info.h>
7
8 #ifdef CONFIG_SPARC32
9 #define INITIAL_ADDRESS  0x10000 + SIZEOF_HEADERS
10 #define TEXTSTART       0xf0004000
11
12 #define SMP_CACHE_BYTES_SHIFT 5
13
14 #else
15 #define SMP_CACHE_BYTES_SHIFT 6
16 #define INITIAL_ADDRESS 0x4000
17 #define TEXTSTART      0x0000000000404000
18
19 #endif
20
21 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
22
23 #ifdef CONFIG_SPARC32
24 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
25 OUTPUT_ARCH(sparc)
26 ENTRY(_start)
27 jiffies = jiffies_64 + 4;
28 #else
29 /* sparc64 */
30 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
31 OUTPUT_ARCH(sparc:v9a)
32 ENTRY(_start)
33 jiffies = jiffies_64;
34 #endif
35
36 #ifdef CONFIG_SPARC64
37 ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large")
38 #endif
39
40 SECTIONS
41 {
42 #ifdef CONFIG_SPARC64
43         swapper_pg_dir = 0x0000000000402000;
44 #endif
45         . = INITIAL_ADDRESS;
46         .text TEXTSTART :
47         {
48                 _text = .;
49                 HEAD_TEXT
50                 TEXT_TEXT
51                 SCHED_TEXT
52                 LOCK_TEXT
53                 KPROBES_TEXT
54                 IRQENTRY_TEXT
55                 *(.gnu.warning)
56         } = 0
57         _etext = .;
58
59         RO_DATA(PAGE_SIZE)
60
61         /* Start of data section */
62         _sdata = .;
63
64         .data1 : {
65                 *(.data1)
66         }
67         RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE)
68
69         /* End of data section */
70         _edata = .;
71
72         .fixup : {
73                 __start___fixup = .;
74                 *(.fixup)
75                 __stop___fixup = .;
76         }
77         EXCEPTION_TABLE(16)
78         NOTES
79
80         . = ALIGN(PAGE_SIZE);
81         __init_begin = ALIGN(PAGE_SIZE);
82         INIT_TEXT_SECTION(PAGE_SIZE)
83         __init_text_end = .;
84         INIT_DATA_SECTION(16)
85
86         . = ALIGN(4);
87         .tsb_ldquad_phys_patch : {
88                 __tsb_ldquad_phys_patch = .;
89                 *(.tsb_ldquad_phys_patch)
90                 __tsb_ldquad_phys_patch_end = .;
91         }
92
93         .tsb_phys_patch : {
94                 __tsb_phys_patch = .;
95                 *(.tsb_phys_patch)
96                 __tsb_phys_patch_end = .;
97         }
98
99         .cpuid_patch : {
100                 __cpuid_patch = .;
101                 *(.cpuid_patch)
102                 __cpuid_patch_end = .;
103         }
104
105         .sun4v_1insn_patch : {
106                 __sun4v_1insn_patch = .;
107                 *(.sun4v_1insn_patch)
108                 __sun4v_1insn_patch_end = .;
109         }
110         .sun4v_2insn_patch : {
111                 __sun4v_2insn_patch = .;
112                 *(.sun4v_2insn_patch)
113                 __sun4v_2insn_patch_end = .;
114         }
115         .leon_1insn_patch : {
116                 __leon_1insn_patch = .;
117                 *(.leon_1insn_patch)
118                 __leon_1insn_patch_end = .;
119         }
120         .swapper_tsb_phys_patch : {
121                 __swapper_tsb_phys_patch = .;
122                 *(.swapper_tsb_phys_patch)
123                 __swapper_tsb_phys_patch_end = .;
124         }
125         .swapper_4m_tsb_phys_patch : {
126                 __swapper_4m_tsb_phys_patch = .;
127                 *(.swapper_4m_tsb_phys_patch)
128                 __swapper_4m_tsb_phys_patch_end = .;
129         }
130         .popc_3insn_patch : {
131                 __popc_3insn_patch = .;
132                 *(.popc_3insn_patch)
133                 __popc_3insn_patch_end = .;
134         }
135         .popc_6insn_patch : {
136                 __popc_6insn_patch = .;
137                 *(.popc_6insn_patch)
138                 __popc_6insn_patch_end = .;
139         }
140         .pause_3insn_patch : {
141                 __pause_3insn_patch = .;
142                 *(.pause_3insn_patch)
143                 __pause_3insn_patch_end = .;
144         }
145         .sun_m7_2insn_patch : {
146                 __sun_m7_2insn_patch = .;
147                 *(.sun_m7_2insn_patch)
148                 __sun_m7_2insn_patch_end = .;
149         }
150         PERCPU_SECTION(SMP_CACHE_BYTES)
151
152         . = ALIGN(PAGE_SIZE);
153         __init_end = .;
154         BSS_SECTION(0, 0, 0)
155         _end = . ;
156
157         STABS_DEBUG
158         DWARF_DEBUG
159
160         DISCARDS
161 }