kernel/arch/sh/kernel/cpu/sh4a/setup-sh7734.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
   3
   4  * SH7734 Setup
   5  *
   6  * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7  * Copyright (C) 2011,2012 Renesas Solutions Corp.
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/init.h>
  16 #include <linux/serial.h>
  17 #include <linux/mm.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/sh_timer.h>
  21 #include <linux/io.h>
  22 #include <asm/clock.h>
  23 #include <asm/irq.h>
  24 #include <cpu/sh7734.h>
  25
  26 /* SCIF */
  27 static struct plat_sci_port scif0_platform_data = {
  28         .flags          = UPF_BOOT_AUTOCONF,
  29         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  30         .type           = PORT_SCIF,
  31         .regtype        = SCIx_SH4_SCIF_REGTYPE,
  32 };
  33
  34 static struct resource scif0_resources[] = {
  35         DEFINE_RES_MEM(0xffe40000, 0x100),
  36         DEFINE_RES_IRQ(evt2irq(0x8c0)),
  37 };
  38
  39 static struct platform_device scif0_device = {
  40         .name           = "sh-sci",
  41         .id             = 0,
  42         .resource       = scif0_resources,
  43         .num_resources  = ARRAY_SIZE(scif0_resources),
  44         .dev            = {
  45                 .platform_data  = &scif0_platform_data,
  46         },
  47 };
  48
  49 static struct plat_sci_port scif1_platform_data = {
  50         .flags          = UPF_BOOT_AUTOCONF,
  51         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  52         .type           = PORT_SCIF,
  53         .regtype        = SCIx_SH4_SCIF_REGTYPE,
  54 };
  55
  56 static struct resource scif1_resources[] = {
  57         DEFINE_RES_MEM(0xffe41000, 0x100),
  58         DEFINE_RES_IRQ(evt2irq(0x8e0)),
  59 };
  60
  61 static struct platform_device scif1_device = {
  62         .name           = "sh-sci",
  63         .id             = 1,
  64         .resource       = scif1_resources,
  65         .num_resources  = ARRAY_SIZE(scif1_resources),
  66         .dev            = {
  67                 .platform_data = &scif1_platform_data,
  68         },
  69 };
  70
  71 static struct plat_sci_port scif2_platform_data = {
  72         .flags          = UPF_BOOT_AUTOCONF,
  73         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  74         .type           = PORT_SCIF,
  75         .regtype        = SCIx_SH4_SCIF_REGTYPE,
  76 };
  77
  78 static struct resource scif2_resources[] = {
  79         DEFINE_RES_MEM(0xffe42000, 0x100),
  80         DEFINE_RES_IRQ(evt2irq(0x900)),
  81 };
  82
  83 static struct platform_device scif2_device = {
  84         .name           = "sh-sci",
  85         .id             = 2,
  86         .resource       = scif2_resources,
  87         .num_resources  = ARRAY_SIZE(scif2_resources),
  88         .dev            = {
  89                 .platform_data = &scif2_platform_data,
  90         },
  91 };
  92
  93 static struct plat_sci_port scif3_platform_data = {
  94         .flags          = UPF_BOOT_AUTOCONF,
  95         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
  96         .type           = PORT_SCIF,
  97         .regtype        = SCIx_SH4_SCIF_REGTYPE,
  98 };
  99
 100 static struct resource scif3_resources[] = {
 101         DEFINE_RES_MEM(0xffe43000, 0x100),
 102         DEFINE_RES_IRQ(evt2irq(0x920)),
 103 };
 104
 105 static struct platform_device scif3_device = {
 106         .name           = "sh-sci",
 107         .id             = 3,
 108         .resource       = scif3_resources,
 109         .num_resources  = ARRAY_SIZE(scif3_resources),
 110         .dev            = {
 111                 .platform_data  = &scif3_platform_data,
 112         },
 113 };
 114
 115 static struct plat_sci_port scif4_platform_data = {
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 118         .type           = PORT_SCIF,
 119         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 120 };
 121
 122 static struct resource scif4_resources[] = {
 123         DEFINE_RES_MEM(0xffe44000, 0x100),
 124         DEFINE_RES_IRQ(evt2irq(0x940)),
 125 };
 126
 127 static struct platform_device scif4_device = {
 128         .name           = "sh-sci",
 129         .id             = 4,
 130         .resource       = scif4_resources,
 131         .num_resources  = ARRAY_SIZE(scif4_resources),
 132         .dev            = {
 133                 .platform_data  = &scif4_platform_data,
 134         },
 135 };
 136
 137 static struct plat_sci_port scif5_platform_data = {
 138         .flags          = UPF_BOOT_AUTOCONF,
 139         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 140         .type           = PORT_SCIF,
 141         .regtype                = SCIx_SH4_SCIF_REGTYPE,
 142 };
 143
 144 static struct resource scif5_resources[] = {
 145         DEFINE_RES_MEM(0xffe43000, 0x100),
 146         DEFINE_RES_IRQ(evt2irq(0x960)),
 147 };
 148
 149 static struct platform_device scif5_device = {
 150         .name           = "sh-sci",
 151         .id             = 5,
 152         .resource       = scif5_resources,
 153         .num_resources  = ARRAY_SIZE(scif5_resources),
 154         .dev            = {
 155                 .platform_data  = &scif5_platform_data,
 156         },
 157 };
 158
 159 /* RTC */
 160 static struct resource rtc_resources[] = {
 161         [0] = {
 162                 .name   = "rtc",
 163                 .start  = 0xFFFC5000,
 164                 .end    = 0xFFFC5000 + 0x26 - 1,
 165                 .flags  = IORESOURCE_IO,
 166         },
 167         [1] = {
 168                 .start  = evt2irq(0xC00),
 169                 .flags  = IORESOURCE_IRQ,
 170         },
 171 };
 172
 173 static struct platform_device rtc_device = {
 174         .name           = "sh-rtc",
 175         .id             = -1,
 176         .num_resources  = ARRAY_SIZE(rtc_resources),
 177         .resource       = rtc_resources,
 178 };
 179
 180 /* I2C 0 */
 181 static struct resource i2c0_resources[] = {
 182         [0] = {
 183                 .name   = "IIC0",
 184                 .start  = 0xFFC70000,
 185                 .end    = 0xFFC7000A - 1,
 186                 .flags  = IORESOURCE_MEM,
 187         },
 188         [1] = {
 189                 .start  = evt2irq(0x860),
 190                 .flags  = IORESOURCE_IRQ,
 191         },
 192 };
 193
 194 static struct platform_device i2c0_device = {
 195         .name           = "i2c-sh7734",
 196         .id             = 0,
 197         .num_resources  = ARRAY_SIZE(i2c0_resources),
 198         .resource       = i2c0_resources,
 199 };
 200
 201 /* TMU */
 202 static struct sh_timer_config tmu0_platform_data = {
 203         .channels_mask = 7,
 204 };
 205
 206 static struct resource tmu0_resources[] = {
 207         DEFINE_RES_MEM(0xffd80000, 0x30),
 208         DEFINE_RES_IRQ(evt2irq(0x400)),
 209         DEFINE_RES_IRQ(evt2irq(0x420)),
 210         DEFINE_RES_IRQ(evt2irq(0x440)),
 211 };
 212
 213 static struct platform_device tmu0_device = {
 214         .name           = "sh-tmu",
 215         .id             = 0,
 216         .dev = {
 217                 .platform_data  = &tmu0_platform_data,
 218         },
 219         .resource       = tmu0_resources,
 220         .num_resources  = ARRAY_SIZE(tmu0_resources),
 221 };
 222
 223 static struct sh_timer_config tmu1_platform_data = {
 224         .channels_mask = 7,
 225 };
 226
 227 static struct resource tmu1_resources[] = {
 228         DEFINE_RES_MEM(0xffd81000, 0x30),
 229         DEFINE_RES_IRQ(evt2irq(0x480)),
 230         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 231         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 232 };
 233
 234 static struct platform_device tmu1_device = {
 235         .name           = "sh-tmu",
 236         .id             = 1,
 237         .dev = {
 238                 .platform_data  = &tmu1_platform_data,
 239         },
 240         .resource       = tmu1_resources,
 241         .num_resources  = ARRAY_SIZE(tmu1_resources),
 242 };
 243
 244 static struct sh_timer_config tmu2_platform_data = {
 245         .channels_mask = 7,
 246 };
 247
 248 static struct resource tmu2_resources[] = {
 249         DEFINE_RES_MEM(0xffd82000, 0x30),
 250         DEFINE_RES_IRQ(evt2irq(0x500)),
 251         DEFINE_RES_IRQ(evt2irq(0x520)),
 252         DEFINE_RES_IRQ(evt2irq(0x540)),
 253 };
 254
 255 static struct platform_device tmu2_device = {
 256         .name           = "sh-tmu",
 257         .id             = 2,
 258         .dev = {
 259                 .platform_data  = &tmu2_platform_data,
 260         },
 261         .resource       = tmu2_resources,
 262         .num_resources  = ARRAY_SIZE(tmu2_resources),
 263 };
 264
 265 static struct platform_device *sh7734_devices[] __initdata = {
 266         &scif0_device,
 267         &scif1_device,
 268         &scif2_device,
 269         &scif3_device,
 270         &scif4_device,
 271         &scif5_device,
 272         &tmu0_device,
 273         &tmu1_device,
 274         &tmu2_device,
 275         &rtc_device,
 276 };
 277
 278 static struct platform_device *sh7734_early_devices[] __initdata = {
 279         &scif0_device,
 280         &scif1_device,
 281         &scif2_device,
 282         &scif3_device,
 283         &scif4_device,
 284         &scif5_device,
 285         &tmu0_device,
 286         &tmu1_device,
 287         &tmu2_device,
 288 };
 289
 290 void __init plat_early_device_setup(void)
 291 {
 292         early_platform_add_devices(sh7734_early_devices,
 293                 ARRAY_SIZE(sh7734_early_devices));
 294 }
 295
 296 #define GROUP 0
 297 enum {
 298         UNUSED = 0,
 299
 300         /* interrupt sources */
 301
 302         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 303         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 304         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 305         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 306
 307         IRQ0, IRQ1, IRQ2, IRQ3,
 308         DU,
 309         TMU00, TMU10, TMU20, TMU21,
 310         TMU30, TMU40, TMU50, TMU51,
 311         TMU60, TMU70, TMU80,
 312         RESET_WDT,
 313         USB,
 314         HUDI,
 315         SHDMAC,
 316         SSI0, SSI1,     SSI2, SSI3,
 317         VIN0,
 318         RGPVG,
 319         _2DG,
 320         MMC,
 321         HSPI,
 322         LBSCATA,
 323         I2C0,
 324         RCAN0,
 325         MIMLB,
 326         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
 327         LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
 328         RCAN1,
 329         SDHI0, SDHI1,
 330         IEBUS,
 331         HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
 332         RTC,
 333         VIN1,
 334         LCDC,
 335         SRC0, SRC1,
 336         GETHER,
 337         SDHI2,
 338         GPIO0_3, GPIO4_5,
 339         STIF0, STIF1,
 340         ADMAC,
 341         HIF,
 342         FLCTL,
 343         ADC,
 344         MTU2,
 345         RSPI,
 346         QSPI,
 347         HSCIF,
 348         VEU3F_VE3,
 349
 350         /* Group */
 351         /* Mask */
 352         STIF_M,
 353         GPIO_M,
 354         HPBDMAC_M,
 355         LBSCDMAC_M,
 356         RCAN_M,
 357         SRC_M,
 358         SCIF_M,
 359         LCDC_M,
 360         _2DG_M,
 361         VIN_M,
 362         TMU_3_M,
 363         TMU_0_M,
 364
 365         /* Priority */
 366         RCAN_P,
 367         LBSCDMAC_P,
 368
 369         /* Common */
 370         SDHI,
 371         SSI,
 372         SPI,
 373 };
 374
 375 static struct intc_vect vectors[] __initdata = {
 376         INTC_VECT(DU, 0x3E0),
 377         INTC_VECT(TMU00, 0x400),
 378         INTC_VECT(TMU10, 0x420),
 379         INTC_VECT(TMU20, 0x440),
 380         INTC_VECT(TMU30, 0x480),
 381         INTC_VECT(TMU40, 0x4A0),
 382         INTC_VECT(TMU50, 0x4C0),
 383         INTC_VECT(TMU51, 0x4E0),
 384         INTC_VECT(TMU60, 0x500),
 385         INTC_VECT(TMU70, 0x520),
 386         INTC_VECT(TMU80, 0x540),
 387         INTC_VECT(RESET_WDT, 0x560),
 388         INTC_VECT(USB, 0x580),
 389         INTC_VECT(HUDI, 0x600),
 390         INTC_VECT(SHDMAC, 0x620),
 391         INTC_VECT(SSI0, 0x6C0),
 392         INTC_VECT(SSI1, 0x6E0),
 393         INTC_VECT(SSI2, 0x700),
 394         INTC_VECT(SSI3, 0x720),
 395         INTC_VECT(VIN0, 0x740),
 396         INTC_VECT(RGPVG, 0x760),
 397         INTC_VECT(_2DG, 0x780),
 398         INTC_VECT(MMC, 0x7A0),
 399         INTC_VECT(HSPI, 0x7E0),
 400         INTC_VECT(LBSCATA, 0x840),
 401         INTC_VECT(I2C0, 0x860),
 402         INTC_VECT(RCAN0, 0x880),
 403         INTC_VECT(SCIF0, 0x8A0),
 404         INTC_VECT(SCIF1, 0x8C0),
 405         INTC_VECT(SCIF2, 0x900),
 406         INTC_VECT(SCIF3, 0x920),
 407         INTC_VECT(SCIF4, 0x940),
 408         INTC_VECT(SCIF5, 0x960),
 409         INTC_VECT(LBSCDMAC0, 0x9E0),
 410         INTC_VECT(LBSCDMAC1, 0xA00),
 411         INTC_VECT(LBSCDMAC2, 0xA20),
 412         INTC_VECT(RCAN1, 0xA60),
 413         INTC_VECT(SDHI0, 0xAE0),
 414         INTC_VECT(SDHI1, 0xB00),
 415         INTC_VECT(IEBUS, 0xB20),
 416         INTC_VECT(HPBDMAC0_3, 0xB60),
 417         INTC_VECT(HPBDMAC4_10, 0xB80),
 418         INTC_VECT(HPBDMAC11_18, 0xBA0),
 419         INTC_VECT(HPBDMAC19_22, 0xBC0),
 420         INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
 421         INTC_VECT(RTC, 0xC00),
 422         INTC_VECT(VIN1, 0xC20),
 423         INTC_VECT(LCDC, 0xC40),
 424         INTC_VECT(SRC0, 0xC60),
 425         INTC_VECT(SRC1, 0xC80),
 426         INTC_VECT(GETHER, 0xCA0),
 427         INTC_VECT(SDHI2, 0xCC0),
 428         INTC_VECT(GPIO0_3, 0xCE0),
 429         INTC_VECT(GPIO4_5, 0xD00),
 430         INTC_VECT(STIF0, 0xD20),
 431         INTC_VECT(STIF1, 0xD40),
 432         INTC_VECT(ADMAC, 0xDA0),
 433         INTC_VECT(HIF, 0xDC0),
 434         INTC_VECT(FLCTL, 0xDE0),
 435         INTC_VECT(ADC, 0xE00),
 436         INTC_VECT(MTU2, 0xE20),
 437         INTC_VECT(RSPI, 0xE40),
 438         INTC_VECT(QSPI, 0xE60),
 439         INTC_VECT(HSCIF, 0xFC0),
 440         INTC_VECT(VEU3F_VE3, 0xF40),
 441 };
 442
 443 static struct intc_group groups[] __initdata = {
 444         /* Common */
 445         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
 446         INTC_GROUP(SPI, HSPI, RSPI, QSPI),
 447         INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
 448
 449         /* Mask group */
 450         INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
 451         INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
 452         INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
 453                         HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
 454         INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
 455         INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
 456         INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
 457         INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
 458                         HSCIF), /* 14 */
 459         INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
 460         INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
 461         INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
 462         INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
 463                         TMU60, TMU60, TMU70, TMU80), /* 2 */
 464         INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
 465
 466         /* Priority group*/
 467         INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
 468         INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
 469 };
 470
 471 static struct intc_mask_reg mask_registers[] __initdata = {
 472         { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
 473           { 0,
 474                 VEU3F_VE3,
 475                 SDHI, /* SDHI 0-2 */
 476                 ADMAC,
 477                 FLCTL,
 478                 RESET_WDT,
 479                 HIF,
 480                 ADC,
 481                 MTU2,
 482                 STIF_M, /* STIF 0,1 */
 483                 GPIO_M, /* GPIO 0-5*/
 484                 GETHER,
 485                 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
 486                 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
 487                 RCAN_M, /* RCAN, IEBUS */
 488                 SRC_M,  /* SRC 0,1 */
 489                 LBSCATA,
 490                 SCIF_M, /* SCIF 0-5, HSCIF */
 491                 LCDC_M, /* LCDC, MIMLB */
 492                 _2DG_M, /* 2DG, RGPVG */
 493                 SPI, /* HSPI, RSPI, QSPI */
 494                 VIN_M,  /* VIN0, 1 */
 495                 SSI,    /* SSI 0-3 */
 496                 USB,
 497                 SHDMAC,
 498                 HUDI,
 499                 MMC,
 500                 RTC,
 501                 I2C0, /* I2C */ /* I2C 0, 1*/
 502                 TMU_3_M, /* TMU30 - TMU80 */
 503                 TMU_0_M, /* TMU00 - TMU21 */
 504                 DU } },
 505 };
 506
 507 static struct intc_prio_reg prio_registers[] __initdata = {
 508         { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
 509                 { DU, TMU00, TMU10, TMU20 } },
 510         { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
 511                 { TMU30, TMU60, RTC, SDHI } },
 512         { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
 513                 { HUDI, SHDMAC, USB, SSI } },
 514         { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
 515                 { VIN0, SPI, _2DG, LBSCATA } },
 516         { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
 517                 { SCIF0, SCIF3, HSCIF, LCDC } },
 518         { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
 519                 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
 520         { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
 521                 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
 522         { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
 523                 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
 524         { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
 525                 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
 526         { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
 527                 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
 528         { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
 529                 { STIF0, STIF1, VEU3F_VE3, GETHER } },
 530         { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
 531                 { MTU2, RGPVG, MIMLB, IEBUS } },
 532 };
 533
 534 static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
 535         mask_registers, prio_registers, NULL);
 536
 537 /* Support for external interrupt pins in IRQ mode */
 538
 539 static struct intc_vect irq3210_vectors[] __initdata = {
 540         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 541         INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
 542 };
 543
 544 static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
 545         { 0xFF80201C, 32, 2, /* ICR1 */
 546         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 547 };
 548
 549 static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
 550         { 0xFF802024, 0, 32, /* INTREQ */
 551         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 552 };
 553
 554 static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
 555         { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
 556         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 557 };
 558
 559 static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
 560         { 0xFF802010, 0, 32, 4, /* INTPRI */
 561         { IRQ0, IRQ1, IRQ2, IRQ3, } },
 562 };
 563
 564 static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
 565         irq3210_vectors, NULL,
 566         irq3210_mask_registers, irq3210_prio_registers,
 567         irq3210_sense_registers, irq3210_ack_registers);
 568
 569 /* External interrupt pins in IRL mode */
 570
 571 static struct intc_vect vectors_irl3210[] __initdata = {
 572         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 573         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 574         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 575         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 576         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 577         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 578         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 579         INTC_VECT(IRL0_HHHL, 0x3c0),
 580 };
 581
 582 static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
 583         vectors_irl3210, NULL, mask_registers, NULL, NULL);
 584
 585 #define INTC_ICR0               0xFF802000
 586 #define INTC_INTMSK0    0xFF802044
 587 #define INTC_INTMSK1    0xFF802048
 588 #define INTC_INTMSKCLR0 0xFF802064
 589 #define INTC_INTMSKCLR1 0xFF802068
 590
 591 void __init plat_irq_setup(void)
 592 {
 593         /* disable IRQ3-0 */
 594         __raw_writel(0xF0000000, INTC_INTMSK0);
 595
 596         /* disable IRL3-0 */
 597         __raw_writel(0x80000000, INTC_INTMSK1);
 598
 599         /* select IRL mode for IRL3-0 */
 600         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
 601
 602         /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
 603         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 604
 605         register_intc_controller(&intc_desc);
 606 }
 607
 608 void __init plat_irq_setup_pins(int mode)
 609 {
 610         switch (mode) {
 611         case IRQ_MODE_IRQ3210:
 612                 /* select IRQ mode for IRL3-0 */
 613                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 614                 register_intc_controller(&intc_desc_irq3210);
 615                 break;
 616         case IRQ_MODE_IRL3210:
 617                 /* enable IRL0-3 but don't provide any masking */
 618                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 619                 __raw_writel(0xf0000000, INTC_INTMSKCLR0);
 620                 break;
 621         case IRQ_MODE_IRL3210_MASK:
 622                 /* enable IRL0-3 and mask using cpu intc controller */
 623                 __raw_writel(0x80000000, INTC_INTMSKCLR0);
 624                 register_intc_controller(&intc_desc_irl3210);
 625                 break;
 626         default:
 627                 BUG();
 628         }
 629 }