kernel/arch/powerpc/platforms/powernv/eeh-powernv.c

   1 /*
   2  * The file intends to implement the platform dependent EEH operations on
   3  * powernv platform. Actually, the powernv was created in order to fully
   4  * hypervisor support.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/atomic.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/export.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/msi.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/proc_fs.h>
  25 #include <linux/rbtree.h>
  26 #include <linux/sched.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <asm/eeh.h>
  31 #include <asm/eeh_event.h>
  32 #include <asm/firmware.h>
  33 #include <asm/io.h>
  34 #include <asm/iommu.h>
  35 #include <asm/machdep.h>
  36 #include <asm/msi_bitmap.h>
  37 #include <asm/opal.h>
  38 #include <asm/ppc-pci.h>
  39
  40 #include "powernv.h"
  41 #include "pci.h"
  42
  43 static bool pnv_eeh_nb_init = false;
  44 static int eeh_event_irq = -EINVAL;
  45
  46 static int pnv_eeh_init(void)
  47 {
  48         struct pci_controller *hose;
  49         struct pnv_phb *phb;
  50
  51         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
  52                 pr_warn("%s: OPALv3 is required !\n",
  53                         __func__);
  54                 return -EINVAL;
  55         }
  56
  57         /* Set probe mode */
  58         eeh_add_flag(EEH_PROBE_MODE_DEV);
  59
  60         /*
  61          * P7IOC blocks PCI config access to frozen PE, but PHB3
  62          * doesn't do that. So we have to selectively enable I/O
  63          * prior to collecting error log.
  64          */
  65         list_for_each_entry(hose, &hose_list, list_node) {
  66                 phb = hose->private_data;
  67
  68                 if (phb->model == PNV_PHB_MODEL_P7IOC)
  69                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
  70
  71                 /*
  72                  * PE#0 should be regarded as valid by EEH core
  73                  * if it's not the reserved one. Currently, we
  74                  * have the reserved PE#255 and PE#127 for PHB3
  75                  * and P7IOC separately. So we should regard
  76                  * PE#0 as valid for PHB3 and P7IOC.
  77                  */
  78                 if (phb->ioda.reserved_pe != 0)
  79                         eeh_add_flag(EEH_VALID_PE_ZERO);
  80
  81                 break;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static irqreturn_t pnv_eeh_event(int irq, void *data)
  88 {
  89         /*
  90          * We simply send a special EEH event if EEH has been
  91          * enabled. We don't care about EEH events until we've
  92          * finished processing the outstanding ones. Event processing
  93          * gets unmasked in next_error() if EEH is enabled.
  94          */
  95         disable_irq_nosync(irq);
  96
  97         if (eeh_enabled())
  98                 eeh_send_failure_event(NULL);
  99
 100         return IRQ_HANDLED;
 101 }
 102
 103 #ifdef CONFIG_DEBUG_FS
 104 static ssize_t pnv_eeh_ei_write(struct file *filp,
 105                                 const char __user *user_buf,
 106                                 size_t count, loff_t *ppos)
 107 {
 108         struct pci_controller *hose = filp->private_data;
 109         struct eeh_dev *edev;
 110         struct eeh_pe *pe;
 111         int pe_no, type, func;
 112         unsigned long addr, mask;
 113         char buf[50];
 114         int ret;
 115
 116         if (!eeh_ops || !eeh_ops->err_inject)
 117                 return -ENXIO;
 118
 119         /* Copy over argument buffer */
 120         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
 121         if (!ret)
 122                 return -EFAULT;
 123
 124         /* Retrieve parameters */
 125         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
 126                      &pe_no, &type, &func, &addr, &mask);
 127         if (ret != 5)
 128                 return -EINVAL;
 129
 130         /* Retrieve PE */
 131         edev = kzalloc(sizeof(*edev), GFP_KERNEL);
 132         if (!edev)
 133                 return -ENOMEM;
 134         edev->phb = hose;
 135         edev->pe_config_addr = pe_no;
 136         pe = eeh_pe_get(edev);
 137         kfree(edev);
 138         if (!pe)
 139                 return -ENODEV;
 140
 141         /* Do error injection */
 142         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
 143         return ret < 0 ? ret : count;
 144 }
 145
 146 static const struct file_operations pnv_eeh_ei_fops = {
 147         .open   = simple_open,
 148         .llseek = no_llseek,
 149         .write  = pnv_eeh_ei_write,
 150 };
 151
 152 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
 153 {
 154         struct pci_controller *hose = data;
 155         struct pnv_phb *phb = hose->private_data;
 156
 157         out_be64(phb->regs + offset, val);
 158         return 0;
 159 }
 160
 161 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
 162 {
 163         struct pci_controller *hose = data;
 164         struct pnv_phb *phb = hose->private_data;
 165
 166         *val = in_be64(phb->regs + offset);
 167         return 0;
 168 }
 169
 170 static int pnv_eeh_outb_dbgfs_set(void *data, u64 val)
 171 {
 172         return pnv_eeh_dbgfs_set(data, 0xD10, val);
 173 }
 174
 175 static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val)
 176 {
 177         return pnv_eeh_dbgfs_get(data, 0xD10, val);
 178 }
 179
 180 static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val)
 181 {
 182         return pnv_eeh_dbgfs_set(data, 0xD90, val);
 183 }
 184
 185 static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val)
 186 {
 187         return pnv_eeh_dbgfs_get(data, 0xD90, val);
 188 }
 189
 190 static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val)
 191 {
 192         return pnv_eeh_dbgfs_set(data, 0xE10, val);
 193 }
 194
 195 static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val)
 196 {
 197         return pnv_eeh_dbgfs_get(data, 0xE10, val);
 198 }
 199
 200 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get,
 201                         pnv_eeh_outb_dbgfs_set, "0x%llx\n");
 202 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get,
 203                         pnv_eeh_inbA_dbgfs_set, "0x%llx\n");
 204 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get,
 205                         pnv_eeh_inbB_dbgfs_set, "0x%llx\n");
 206 #endif /* CONFIG_DEBUG_FS */
 207
 208 /**
 209  * pnv_eeh_post_init - EEH platform dependent post initialization
 210  *
 211  * EEH platform dependent post initialization on powernv. When
 212  * the function is called, the EEH PEs and devices should have
 213  * been built. If the I/O cache staff has been built, EEH is
 214  * ready to supply service.
 215  */
 216 static int pnv_eeh_post_init(void)
 217 {
 218         struct pci_controller *hose;
 219         struct pnv_phb *phb;
 220         int ret = 0;
 221
 222         /* Register OPAL event notifier */
 223         if (!pnv_eeh_nb_init) {
 224                 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
 225                 if (eeh_event_irq < 0) {
 226                         pr_err("%s: Can't register OPAL event interrupt (%d)\n",
 227                                __func__, eeh_event_irq);
 228                         return eeh_event_irq;
 229                 }
 230
 231                 ret = request_irq(eeh_event_irq, pnv_eeh_event,
 232                                 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
 233                 if (ret < 0) {
 234                         irq_dispose_mapping(eeh_event_irq);
 235                         pr_err("%s: Can't request OPAL event interrupt (%d)\n",
 236                                __func__, eeh_event_irq);
 237                         return ret;
 238                 }
 239
 240                 pnv_eeh_nb_init = true;
 241         }
 242
 243         if (!eeh_enabled())
 244                 disable_irq(eeh_event_irq);
 245
 246         list_for_each_entry(hose, &hose_list, list_node) {
 247                 phb = hose->private_data;
 248
 249                 /*
 250                  * If EEH is enabled, we're going to rely on that.
 251                  * Otherwise, we restore to conventional mechanism
 252                  * to clear frozen PE during PCI config access.
 253                  */
 254                 if (eeh_enabled())
 255                         phb->flags |= PNV_PHB_FLAG_EEH;
 256                 else
 257                         phb->flags &= ~PNV_PHB_FLAG_EEH;
 258
 259                 /* Create debugfs entries */
 260 #ifdef CONFIG_DEBUG_FS
 261                 if (phb->has_dbgfs || !phb->dbgfs)
 262                         continue;
 263
 264                 phb->has_dbgfs = 1;
 265                 debugfs_create_file("err_injct", 0200,
 266                                     phb->dbgfs, hose,
 267                                     &pnv_eeh_ei_fops);
 268
 269                 debugfs_create_file("err_injct_outbound", 0600,
 270                                     phb->dbgfs, hose,
 271                                     &pnv_eeh_outb_dbgfs_ops);
 272                 debugfs_create_file("err_injct_inboundA", 0600,
 273                                     phb->dbgfs, hose,
 274                                     &pnv_eeh_inbA_dbgfs_ops);
 275                 debugfs_create_file("err_injct_inboundB", 0600,
 276                                     phb->dbgfs, hose,
 277                                     &pnv_eeh_inbB_dbgfs_ops);
 278 #endif /* CONFIG_DEBUG_FS */
 279         }
 280
 281         return ret;
 282 }
 283
 284 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
 285 {
 286         int pos = PCI_CAPABILITY_LIST;
 287         int cnt = 48;   /* Maximal number of capabilities */
 288         u32 status, id;
 289
 290         if (!pdn)
 291                 return 0;
 292
 293         /* Check if the device supports capabilities */
 294         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
 295         if (!(status & PCI_STATUS_CAP_LIST))
 296                 return 0;
 297
 298         while (cnt--) {
 299                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
 300                 if (pos < 0x40)
 301                         break;
 302
 303                 pos &= ~3;
 304                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
 305                 if (id == 0xff)
 306                         break;
 307
 308                 /* Found */
 309                 if (id == cap)
 310                         return pos;
 311
 312                 /* Next one */
 313                 pos += PCI_CAP_LIST_NEXT;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
 320 {
 321         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 322         u32 header;
 323         int pos = 256, ttl = (4096 - 256) / 8;
 324
 325         if (!edev || !edev->pcie_cap)
 326                 return 0;
 327         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 328                 return 0;
 329         else if (!header)
 330                 return 0;
 331
 332         while (ttl-- > 0) {
 333                 if (PCI_EXT_CAP_ID(header) == cap && pos)
 334                         return pos;
 335
 336                 pos = PCI_EXT_CAP_NEXT(header);
 337                 if (pos < 256)
 338                         break;
 339
 340                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 341                         break;
 342         }
 343
 344         return 0;
 345 }
 346
 347 /**
 348  * pnv_eeh_probe - Do probe on PCI device
 349  * @pdn: PCI device node
 350  * @data: unused
 351  *
 352  * When EEH module is installed during system boot, all PCI devices
 353  * are checked one by one to see if it supports EEH. The function
 354  * is introduced for the purpose. By default, EEH has been enabled
 355  * on all PCI devices. That's to say, we only need do necessary
 356  * initialization on the corresponding eeh device and create PE
 357  * accordingly.
 358  *
 359  * It's notable that's unsafe to retrieve the EEH device through
 360  * the corresponding PCI device. During the PCI device hotplug, which
 361  * was possiblly triggered by EEH core, the binding between EEH device
 362  * and the PCI device isn't built yet.
 363  */
 364 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
 365 {
 366         struct pci_controller *hose = pdn->phb;
 367         struct pnv_phb *phb = hose->private_data;
 368         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 369         uint32_t pcie_flags;
 370         int ret;
 371
 372         /*
 373          * When probing the root bridge, which doesn't have any
 374          * subordinate PCI devices. We don't have OF node for
 375          * the root bridge. So it's not reasonable to continue
 376          * the probing.
 377          */
 378         if (!edev || edev->pe)
 379                 return NULL;
 380
 381         /* Skip for PCI-ISA bridge */
 382         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
 383                 return NULL;
 384
 385         /* Initialize eeh device */
 386         edev->class_code = pdn->class_code;
 387         edev->mode      &= 0xFFFFFF00;
 388         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
 389         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
 390         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
 391         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
 392                 edev->mode |= EEH_DEV_BRIDGE;
 393                 if (edev->pcie_cap) {
 394                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
 395                                          2, &pcie_flags);
 396                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
 397                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
 398                                 edev->mode |= EEH_DEV_ROOT_PORT;
 399                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
 400                                 edev->mode |= EEH_DEV_DS_PORT;
 401                 }
 402         }
 403
 404         edev->config_addr    = (pdn->busno << 8) | (pdn->devfn);
 405         edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
 406
 407         /* Create PE */
 408         ret = eeh_add_to_parent_pe(edev);
 409         if (ret) {
 410                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
 411                         __func__, hose->global_number, pdn->busno,
 412                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
 413                 return NULL;
 414         }
 415
 416         /*
 417          * If the PE contains any one of following adapters, the
 418          * PCI config space can't be accessed when dumping EEH log.
 419          * Otherwise, we will run into fenced PHB caused by shortage
 420          * of outbound credits in the adapter. The PCI config access
 421          * should be blocked until PE reset. MMIO access is dropped
 422          * by hardware certainly. In order to drop PCI config requests,
 423          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
 424          * will be checked in the backend for PE state retrival. If
 425          * the PE becomes frozen for the first time and the flag has
 426          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
 427          * that PE to block its config space.
 428          *
 429          * Broadcom Austin 4-ports NICs (14e4:1657)
 430          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
 431          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
 432          */
 433         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 434              pdn->device_id == 0x1657) ||
 435             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 436              pdn->device_id == 0x168a) ||
 437             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 438              pdn->device_id == 0x168e))
 439                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
 440
 441         /*
 442          * Cache the PE primary bus, which can't be fetched when
 443          * full hotplug is in progress. In that case, all child
 444          * PCI devices of the PE are expected to be removed prior
 445          * to PE reset.
 446          */
 447         if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
 448                 edev->pe->bus = pci_find_bus(hose->global_number,
 449                                              pdn->busno);
 450                 if (edev->pe->bus)
 451                         edev->pe->state |= EEH_PE_PRI_BUS;
 452         }
 453
 454         /*
 455          * Enable EEH explicitly so that we will do EEH check
 456          * while accessing I/O stuff
 457          */
 458         eeh_add_flag(EEH_ENABLED);
 459
 460         /* Save memory bars */
 461         eeh_save_bars(edev);
 462
 463         return NULL;
 464 }
 465
 466 /**
 467  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
 468  * @pe: EEH PE
 469  * @option: operation to be issued
 470  *
 471  * The function is used to control the EEH functionality globally.
 472  * Currently, following options are support according to PAPR:
 473  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
 474  */
 475 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
 476 {
 477         struct pci_controller *hose = pe->phb;
 478         struct pnv_phb *phb = hose->private_data;
 479         bool freeze_pe = false;
 480         int opt;
 481         s64 rc;
 482
 483         switch (option) {
 484         case EEH_OPT_DISABLE:
 485                 return -EPERM;
 486         case EEH_OPT_ENABLE:
 487                 return 0;
 488         case EEH_OPT_THAW_MMIO:
 489                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
 490                 break;
 491         case EEH_OPT_THAW_DMA:
 492                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
 493                 break;
 494         case EEH_OPT_FREEZE_PE:
 495                 freeze_pe = true;
 496                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
 497                 break;
 498         default:
 499                 pr_warn("%s: Invalid option %d\n", __func__, option);
 500                 return -EINVAL;
 501         }
 502
 503         /* Freeze master and slave PEs if PHB supports compound PEs */
 504         if (freeze_pe) {
 505                 if (phb->freeze_pe) {
 506                         phb->freeze_pe(phb, pe->addr);
 507                         return 0;
 508                 }
 509
 510                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
 511                 if (rc != OPAL_SUCCESS) {
 512                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 513                                 __func__, rc, phb->hose->global_number,
 514                                 pe->addr);
 515                         return -EIO;
 516                 }
 517
 518                 return 0;
 519         }
 520
 521         /* Unfreeze master and slave PEs if PHB supports */
 522         if (phb->unfreeze_pe)
 523                 return phb->unfreeze_pe(phb, pe->addr, opt);
 524
 525         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
 526         if (rc != OPAL_SUCCESS) {
 527                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
 528                         __func__, rc, option, phb->hose->global_number,
 529                         pe->addr);
 530                 return -EIO;
 531         }
 532
 533         return 0;
 534 }
 535
 536 /**
 537  * pnv_eeh_get_pe_addr - Retrieve PE address
 538  * @pe: EEH PE
 539  *
 540  * Retrieve the PE address according to the given tranditional
 541  * PCI BDF (Bus/Device/Function) address.
 542  */
 543 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
 544 {
 545         return pe->addr;
 546 }
 547
 548 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
 549 {
 550         struct pnv_phb *phb = pe->phb->private_data;
 551         s64 rc;
 552
 553         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
 554                                          PNV_PCI_DIAG_BUF_SIZE);
 555         if (rc != OPAL_SUCCESS)
 556                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
 557                         __func__, rc, pe->phb->global_number);
 558 }
 559
 560 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
 561 {
 562         struct pnv_phb *phb = pe->phb->private_data;
 563         u8 fstate;
 564         __be16 pcierr;
 565         s64 rc;
 566         int result = 0;
 567
 568         rc = opal_pci_eeh_freeze_status(phb->opal_id,
 569                                         pe->addr,
 570                                         &fstate,
 571                                         &pcierr,
 572                                         NULL);
 573         if (rc != OPAL_SUCCESS) {
 574                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
 575                         __func__, rc, phb->hose->global_number);
 576                 return EEH_STATE_NOT_SUPPORT;
 577         }
 578
 579         /*
 580          * Check PHB state. If the PHB is frozen for the
 581          * first time, to dump the PHB diag-data.
 582          */
 583         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
 584                 result = (EEH_STATE_MMIO_ACTIVE  |
 585                           EEH_STATE_DMA_ACTIVE   |
 586                           EEH_STATE_MMIO_ENABLED |
 587                           EEH_STATE_DMA_ENABLED);
 588         } else if (!(pe->state & EEH_PE_ISOLATED)) {
 589                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 590                 pnv_eeh_get_phb_diag(pe);
 591
 592                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 593                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 594         }
 595
 596         return result;
 597 }
 598
 599 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
 600 {
 601         struct pnv_phb *phb = pe->phb->private_data;
 602         u8 fstate;
 603         __be16 pcierr;
 604         s64 rc;
 605         int result;
 606
 607         /*
 608          * We don't clobber hardware frozen state until PE
 609          * reset is completed. In order to keep EEH core
 610          * moving forward, we have to return operational
 611          * state during PE reset.
 612          */
 613         if (pe->state & EEH_PE_RESET) {
 614                 result = (EEH_STATE_MMIO_ACTIVE  |
 615                           EEH_STATE_DMA_ACTIVE   |
 616                           EEH_STATE_MMIO_ENABLED |
 617                           EEH_STATE_DMA_ENABLED);
 618                 return result;
 619         }
 620
 621         /*
 622          * Fetch PE state from hardware. If the PHB
 623          * supports compound PE, let it handle that.
 624          */
 625         if (phb->get_pe_state) {
 626                 fstate = phb->get_pe_state(phb, pe->addr);
 627         } else {
 628                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 629                                                 pe->addr,
 630                                                 &fstate,
 631                                                 &pcierr,
 632                                                 NULL);
 633                 if (rc != OPAL_SUCCESS) {
 634                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
 635                                 __func__, rc, phb->hose->global_number,
 636                                 pe->addr);
 637                         return EEH_STATE_NOT_SUPPORT;
 638                 }
 639         }
 640
 641         /* Figure out state */
 642         switch (fstate) {
 643         case OPAL_EEH_STOPPED_NOT_FROZEN:
 644                 result = (EEH_STATE_MMIO_ACTIVE  |
 645                           EEH_STATE_DMA_ACTIVE   |
 646                           EEH_STATE_MMIO_ENABLED |
 647                           EEH_STATE_DMA_ENABLED);
 648                 break;
 649         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 650                 result = (EEH_STATE_DMA_ACTIVE |
 651                           EEH_STATE_DMA_ENABLED);
 652                 break;
 653         case OPAL_EEH_STOPPED_DMA_FREEZE:
 654                 result = (EEH_STATE_MMIO_ACTIVE |
 655                           EEH_STATE_MMIO_ENABLED);
 656                 break;
 657         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 658                 result = 0;
 659                 break;
 660         case OPAL_EEH_STOPPED_RESET:
 661                 result = EEH_STATE_RESET_ACTIVE;
 662                 break;
 663         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 664                 result = EEH_STATE_UNAVAILABLE;
 665                 break;
 666         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 667                 result = EEH_STATE_NOT_SUPPORT;
 668                 break;
 669         default:
 670                 result = EEH_STATE_NOT_SUPPORT;
 671                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
 672                         __func__, phb->hose->global_number,
 673                         pe->addr, fstate);
 674         }
 675
 676         /*
 677          * If PHB supports compound PE, to freeze all
 678          * slave PEs for consistency.
 679          *
 680          * If the PE is switching to frozen state for the
 681          * first time, to dump the PHB diag-data.
 682          */
 683         if (!(result & EEH_STATE_NOT_SUPPORT) &&
 684             !(result & EEH_STATE_UNAVAILABLE) &&
 685             !(result & EEH_STATE_MMIO_ACTIVE) &&
 686             !(result & EEH_STATE_DMA_ACTIVE)  &&
 687             !(pe->state & EEH_PE_ISOLATED)) {
 688                 if (phb->freeze_pe)
 689                         phb->freeze_pe(phb, pe->addr);
 690
 691                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 692                 pnv_eeh_get_phb_diag(pe);
 693
 694                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 695                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 696         }
 697
 698         return result;
 699 }
 700
 701 /**
 702  * pnv_eeh_get_state - Retrieve PE state
 703  * @pe: EEH PE
 704  * @delay: delay while PE state is temporarily unavailable
 705  *
 706  * Retrieve the state of the specified PE. For IODA-compitable
 707  * platform, it should be retrieved from IODA table. Therefore,
 708  * we prefer passing down to hardware implementation to handle
 709  * it.
 710  */
 711 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
 712 {
 713         int ret;
 714
 715         if (pe->type & EEH_PE_PHB)
 716                 ret = pnv_eeh_get_phb_state(pe);
 717         else
 718                 ret = pnv_eeh_get_pe_state(pe);
 719
 720         if (!delay)
 721                 return ret;
 722
 723         /*
 724          * If the PE state is temporarily unavailable,
 725          * to inform the EEH core delay for default
 726          * period (1 second)
 727          */
 728         *delay = 0;
 729         if (ret & EEH_STATE_UNAVAILABLE)
 730                 *delay = 1000;
 731
 732         return ret;
 733 }
 734
 735 static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
 736 {
 737         s64 rc = OPAL_HARDWARE;
 738
 739         while (1) {
 740                 rc = opal_pci_poll(phb->opal_id);
 741                 if (rc <= 0)
 742                         break;
 743
 744                 if (system_state < SYSTEM_RUNNING)
 745                         udelay(1000 * rc);
 746                 else
 747                         msleep(rc);
 748         }
 749
 750         return rc;
 751 }
 752
 753 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
 754 {
 755         struct pnv_phb *phb = hose->private_data;
 756         s64 rc = OPAL_HARDWARE;
 757
 758         pr_debug("%s: Reset PHB#%x, option=%d\n",
 759                  __func__, hose->global_number, option);
 760
 761         /* Issue PHB complete reset request */
 762         if (option == EEH_RESET_FUNDAMENTAL ||
 763             option == EEH_RESET_HOT)
 764                 rc = opal_pci_reset(phb->opal_id,
 765                                     OPAL_RESET_PHB_COMPLETE,
 766                                     OPAL_ASSERT_RESET);
 767         else if (option == EEH_RESET_DEACTIVATE)
 768                 rc = opal_pci_reset(phb->opal_id,
 769                                     OPAL_RESET_PHB_COMPLETE,
 770                                     OPAL_DEASSERT_RESET);
 771         if (rc < 0)
 772                 goto out;
 773
 774         /*
 775          * Poll state of the PHB until the request is done
 776          * successfully. The PHB reset is usually PHB complete
 777          * reset followed by hot reset on root bus. So we also
 778          * need the PCI bus settlement delay.
 779          */
 780         rc = pnv_eeh_phb_poll(phb);
 781         if (option == EEH_RESET_DEACTIVATE) {
 782                 if (system_state < SYSTEM_RUNNING)
 783                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
 784                 else
 785                         msleep(EEH_PE_RST_SETTLE_TIME);
 786         }
 787 out:
 788         if (rc != OPAL_SUCCESS)
 789                 return -EIO;
 790
 791         return 0;
 792 }
 793
 794 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
 795 {
 796         struct pnv_phb *phb = hose->private_data;
 797         s64 rc = OPAL_HARDWARE;
 798
 799         pr_debug("%s: Reset PHB#%x, option=%d\n",
 800                  __func__, hose->global_number, option);
 801
 802         /*
 803          * During the reset deassert time, we needn't care
 804          * the reset scope because the firmware does nothing
 805          * for fundamental or hot reset during deassert phase.
 806          */
 807         if (option == EEH_RESET_FUNDAMENTAL)
 808                 rc = opal_pci_reset(phb->opal_id,
 809                                     OPAL_RESET_PCI_FUNDAMENTAL,
 810                                     OPAL_ASSERT_RESET);
 811         else if (option == EEH_RESET_HOT)
 812                 rc = opal_pci_reset(phb->opal_id,
 813                                     OPAL_RESET_PCI_HOT,
 814                                     OPAL_ASSERT_RESET);
 815         else if (option == EEH_RESET_DEACTIVATE)
 816                 rc = opal_pci_reset(phb->opal_id,
 817                                     OPAL_RESET_PCI_HOT,
 818                                     OPAL_DEASSERT_RESET);
 819         if (rc < 0)
 820                 goto out;
 821
 822         /* Poll state of the PHB until the request is done */
 823         rc = pnv_eeh_phb_poll(phb);
 824         if (option == EEH_RESET_DEACTIVATE)
 825                 msleep(EEH_PE_RST_SETTLE_TIME);
 826 out:
 827         if (rc != OPAL_SUCCESS)
 828                 return -EIO;
 829
 830         return 0;
 831 }
 832
 833 static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
 834 {
 835         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
 836         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 837         int aer = edev ? edev->aer_cap : 0;
 838         u32 ctrl;
 839
 840         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
 841                  __func__, pci_domain_nr(dev->bus),
 842                  dev->bus->number, option);
 843
 844         switch (option) {
 845         case EEH_RESET_FUNDAMENTAL:
 846         case EEH_RESET_HOT:
 847                 /* Don't report linkDown event */
 848                 if (aer) {
 849                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 850                                              4, &ctrl);
 851                         ctrl |= PCI_ERR_UNC_SURPDN;
 852                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 853                                               4, ctrl);
 854                 }
 855
 856                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 857                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 858                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 859
 860                 msleep(EEH_PE_RST_HOLD_TIME);
 861                 break;
 862         case EEH_RESET_DEACTIVATE:
 863                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 864                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 865                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 866
 867                 msleep(EEH_PE_RST_SETTLE_TIME);
 868
 869                 /* Continue reporting linkDown event */
 870                 if (aer) {
 871                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 872                                              4, &ctrl);
 873                         ctrl &= ~PCI_ERR_UNC_SURPDN;
 874                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 875                                               4, ctrl);
 876                 }
 877
 878                 break;
 879         }
 880
 881         return 0;
 882 }
 883
 884 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
 885 {
 886         struct pci_controller *hose;
 887
 888         if (pci_is_root_bus(dev->bus)) {
 889                 hose = pci_bus_to_host(dev->bus);
 890                 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
 891                 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
 892         } else {
 893                 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
 894                 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
 895         }
 896 }
 897
 898 /**
 899  * pnv_eeh_reset - Reset the specified PE
 900  * @pe: EEH PE
 901  * @option: reset option
 902  *
 903  * Do reset on the indicated PE. For PCI bus sensitive PE,
 904  * we need to reset the parent p2p bridge. The PHB has to
 905  * be reinitialized if the p2p bridge is root bridge. For
 906  * PCI device sensitive PE, we will try to reset the device
 907  * through FLR. For now, we don't have OPAL APIs to do HARD
 908  * reset yet, so all reset would be SOFT (HOT) reset.
 909  */
 910 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
 911 {
 912         struct pci_controller *hose = pe->phb;
 913         struct pci_bus *bus;
 914         int ret;
 915
 916         /*
 917          * For PHB reset, we always have complete reset. For those PEs whose
 918          * primary bus derived from root complex (root bus) or root port
 919          * (usually bus#1), we apply hot or fundamental reset on the root port.
 920          * For other PEs, we always have hot reset on the PE primary bus.
 921          *
 922          * Here, we have different design to pHyp, which always clear the
 923          * frozen state during PE reset. However, the good idea here from
 924          * benh is to keep frozen state before we get PE reset done completely
 925          * (until BAR restore). With the frozen state, HW drops illegal IO
 926          * or MMIO access, which can incur recrusive frozen PE during PE
 927          * reset. The side effect is that EEH core has to clear the frozen
 928          * state explicitly after BAR restore.
 929          */
 930         if (pe->type & EEH_PE_PHB) {
 931                 ret = pnv_eeh_phb_reset(hose, option);
 932         } else {
 933                 struct pnv_phb *phb;
 934                 s64 rc;
 935
 936                 /*
 937                  * The frozen PE might be caused by PAPR error injection
 938                  * registers, which are expected to be cleared after hitting
 939                  * frozen PE as stated in the hardware spec. Unfortunately,
 940                  * that's not true on P7IOC. So we have to clear it manually
 941                  * to avoid recursive EEH errors during recovery.
 942                  */
 943                 phb = hose->private_data;
 944                 if (phb->model == PNV_PHB_MODEL_P7IOC &&
 945                     (option == EEH_RESET_HOT ||
 946                     option == EEH_RESET_FUNDAMENTAL)) {
 947                         rc = opal_pci_reset(phb->opal_id,
 948                                             OPAL_RESET_PHB_ERROR,
 949                                             OPAL_ASSERT_RESET);
 950                         if (rc != OPAL_SUCCESS) {
 951                                 pr_warn("%s: Failure %lld clearing "
 952                                         "error injection registers\n",
 953                                         __func__, rc);
 954                                 return -EIO;
 955                         }
 956                 }
 957
 958                 bus = eeh_pe_bus_get(pe);
 959                 if (!bus) {
 960                         pr_err("%s: Cannot find PCI bus for PHB#%d-PE#%x\n",
 961                                __func__, pe->phb->global_number, pe->addr);
 962                         return -EIO;
 963                 }
 964                 if (pci_is_root_bus(bus) ||
 965                         pci_is_root_bus(bus->parent))
 966                         ret = pnv_eeh_root_reset(hose, option);
 967                 else
 968                         ret = pnv_eeh_bridge_reset(bus->self, option);
 969         }
 970
 971         return ret;
 972 }
 973
 974 /**
 975  * pnv_eeh_wait_state - Wait for PE state
 976  * @pe: EEH PE
 977  * @max_wait: maximal period in millisecond
 978  *
 979  * Wait for the state of associated PE. It might take some time
 980  * to retrieve the PE's state.
 981  */
 982 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
 983 {
 984         int ret;
 985         int mwait;
 986
 987         while (1) {
 988                 ret = pnv_eeh_get_state(pe, &mwait);
 989
 990                 /*
 991                  * If the PE's state is temporarily unavailable,
 992                  * we have to wait for the specified time. Otherwise,
 993                  * the PE's state will be returned immediately.
 994                  */
 995                 if (ret != EEH_STATE_UNAVAILABLE)
 996                         return ret;
 997
 998                 if (max_wait <= 0) {
 999                         pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1000                                 __func__, pe->addr, max_wait);
1001                         return EEH_STATE_NOT_SUPPORT;
1002                 }
1003
1004                 max_wait -= mwait;
1005                 msleep(mwait);
1006         }
1007
1008         return EEH_STATE_NOT_SUPPORT;
1009 }
1010
1011 /**
1012  * pnv_eeh_get_log - Retrieve error log
1013  * @pe: EEH PE
1014  * @severity: temporary or permanent error log
1015  * @drv_log: driver log to be combined with retrieved error log
1016  * @len: length of driver log
1017  *
1018  * Retrieve the temporary or permanent error from the PE.
1019  */
1020 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1021                            char *drv_log, unsigned long len)
1022 {
1023         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1024                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1025
1026         return 0;
1027 }
1028
1029 /**
1030  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1031  * @pe: EEH PE
1032  *
1033  * The function will be called to reconfigure the bridges included
1034  * in the specified PE so that the mulfunctional PE would be recovered
1035  * again.
1036  */
1037 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1038 {
1039         return 0;
1040 }
1041
1042 /**
1043  * pnv_pe_err_inject - Inject specified error to the indicated PE
1044  * @pe: the indicated PE
1045  * @type: error type
1046  * @func: specific error type
1047  * @addr: address
1048  * @mask: address mask
1049  *
1050  * The routine is called to inject specified error, which is
1051  * determined by @type and @func, to the indicated PE for
1052  * testing purpose.
1053  */
1054 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1055                               unsigned long addr, unsigned long mask)
1056 {
1057         struct pci_controller *hose = pe->phb;
1058         struct pnv_phb *phb = hose->private_data;
1059         s64 rc;
1060
1061         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1062             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1063                 pr_warn("%s: Invalid error type %d\n",
1064                         __func__, type);
1065                 return -ERANGE;
1066         }
1067
1068         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1069             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1070                 pr_warn("%s: Invalid error function %d\n",
1071                         __func__, func);
1072                 return -ERANGE;
1073         }
1074
1075         /* Firmware supports error injection ? */
1076         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1077                 pr_warn("%s: Firmware doesn't support error injection\n",
1078                         __func__);
1079                 return -ENXIO;
1080         }
1081
1082         /* Do error injection */
1083         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1084                                  type, func, addr, mask);
1085         if (rc != OPAL_SUCCESS) {
1086                 pr_warn("%s: Failure %lld injecting error "
1087                         "%d-%d to PHB#%x-PE#%x\n",
1088                         __func__, rc, type, func,
1089                         hose->global_number, pe->addr);
1090                 return -EIO;
1091         }
1092
1093         return 0;
1094 }
1095
1096 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1097 {
1098         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1099
1100         if (!edev || !edev->pe)
1101                 return false;
1102
1103         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1104                 return true;
1105
1106         return false;
1107 }
1108
1109 static int pnv_eeh_read_config(struct pci_dn *pdn,
1110                                int where, int size, u32 *val)
1111 {
1112         if (!pdn)
1113                 return PCIBIOS_DEVICE_NOT_FOUND;
1114
1115         if (pnv_eeh_cfg_blocked(pdn)) {
1116                 *val = 0xFFFFFFFF;
1117                 return PCIBIOS_SET_FAILED;
1118         }
1119
1120         return pnv_pci_cfg_read(pdn, where, size, val);
1121 }
1122
1123 static int pnv_eeh_write_config(struct pci_dn *pdn,
1124                                 int where, int size, u32 val)
1125 {
1126         if (!pdn)
1127                 return PCIBIOS_DEVICE_NOT_FOUND;
1128
1129         if (pnv_eeh_cfg_blocked(pdn))
1130                 return PCIBIOS_SET_FAILED;
1131
1132         return pnv_pci_cfg_write(pdn, where, size, val);
1133 }
1134
1135 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1136 {
1137         /* GEM */
1138         if (data->gemXfir || data->gemRfir ||
1139             data->gemRirqfir || data->gemMask || data->gemRwof)
1140                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1141                         be64_to_cpu(data->gemXfir),
1142                         be64_to_cpu(data->gemRfir),
1143                         be64_to_cpu(data->gemRirqfir),
1144                         be64_to_cpu(data->gemMask),
1145                         be64_to_cpu(data->gemRwof));
1146
1147         /* LEM */
1148         if (data->lemFir || data->lemErrMask ||
1149             data->lemAction0 || data->lemAction1 || data->lemWof)
1150                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1151                         be64_to_cpu(data->lemFir),
1152                         be64_to_cpu(data->lemErrMask),
1153                         be64_to_cpu(data->lemAction0),
1154                         be64_to_cpu(data->lemAction1),
1155                         be64_to_cpu(data->lemWof));
1156 }
1157
1158 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1159 {
1160         struct pnv_phb *phb = hose->private_data;
1161         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1162         long rc;
1163
1164         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1165         if (rc != OPAL_SUCCESS) {
1166                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1167                         __func__, phb->hub_id, rc);
1168                 return;
1169         }
1170
1171         switch (be16_to_cpu(data->type)) {
1172         case OPAL_P7IOC_DIAG_TYPE_RGC:
1173                 pr_info("P7IOC diag-data for RGC\n\n");
1174                 pnv_eeh_dump_hub_diag_common(data);
1175                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1176                         pr_info("  RGC: %016llx %016llx\n",
1177                                 be64_to_cpu(data->rgc.rgcStatus),
1178                                 be64_to_cpu(data->rgc.rgcLdcp));
1179                 break;
1180         case OPAL_P7IOC_DIAG_TYPE_BI:
1181                 pr_info("P7IOC diag-data for BI %s\n\n",
1182                         data->bi.biDownbound ? "Downbound" : "Upbound");
1183                 pnv_eeh_dump_hub_diag_common(data);
1184                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1185                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1186                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1187                                 be64_to_cpu(data->bi.biLdcp0),
1188                                 be64_to_cpu(data->bi.biLdcp1),
1189                                 be64_to_cpu(data->bi.biLdcp2),
1190                                 be64_to_cpu(data->bi.biFenceStatus));
1191                 break;
1192         case OPAL_P7IOC_DIAG_TYPE_CI:
1193                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1194                         data->ci.ciPort);
1195                 pnv_eeh_dump_hub_diag_common(data);
1196                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1197                         pr_info("  CI:  %016llx %016llx\n",
1198                                 be64_to_cpu(data->ci.ciPortStatus),
1199                                 be64_to_cpu(data->ci.ciPortLdcp));
1200                 break;
1201         case OPAL_P7IOC_DIAG_TYPE_MISC:
1202                 pr_info("P7IOC diag-data for MISC\n\n");
1203                 pnv_eeh_dump_hub_diag_common(data);
1204                 break;
1205         case OPAL_P7IOC_DIAG_TYPE_I2C:
1206                 pr_info("P7IOC diag-data for I2C\n\n");
1207                 pnv_eeh_dump_hub_diag_common(data);
1208                 break;
1209         default:
1210                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1211                         __func__, phb->hub_id, data->type);
1212         }
1213 }
1214
1215 static int pnv_eeh_get_pe(struct pci_controller *hose,
1216                           u16 pe_no, struct eeh_pe **pe)
1217 {
1218         struct pnv_phb *phb = hose->private_data;
1219         struct pnv_ioda_pe *pnv_pe;
1220         struct eeh_pe *dev_pe;
1221         struct eeh_dev edev;
1222
1223         /*
1224          * If PHB supports compound PE, to fetch
1225          * the master PE because slave PE is invisible
1226          * to EEH core.
1227          */
1228         pnv_pe = &phb->ioda.pe_array[pe_no];
1229         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1230                 pnv_pe = pnv_pe->master;
1231                 WARN_ON(!pnv_pe ||
1232                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1233                 pe_no = pnv_pe->pe_number;
1234         }
1235
1236         /* Find the PE according to PE# */
1237         memset(&edev, 0, sizeof(struct eeh_dev));
1238         edev.phb = hose;
1239         edev.pe_config_addr = pe_no;
1240         dev_pe = eeh_pe_get(&edev);
1241         if (!dev_pe)
1242                 return -EEXIST;
1243
1244         /* Freeze the (compound) PE */
1245         *pe = dev_pe;
1246         if (!(dev_pe->state & EEH_PE_ISOLATED))
1247                 phb->freeze_pe(phb, pe_no);
1248
1249         /*
1250          * At this point, we're sure the (compound) PE should
1251          * have been frozen. However, we still need poke until
1252          * hitting the frozen PE on top level.
1253          */
1254         dev_pe = dev_pe->parent;
1255         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1256                 int ret;
1257                 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1258                                     EEH_STATE_DMA_ACTIVE);
1259
1260                 ret = eeh_ops->get_state(dev_pe, NULL);
1261                 if (ret <= 0 || (ret & active_flags) == active_flags) {
1262                         dev_pe = dev_pe->parent;
1263                         continue;
1264                 }
1265
1266                 /* Frozen parent PE */
1267                 *pe = dev_pe;
1268                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1269                         phb->freeze_pe(phb, dev_pe->addr);
1270
1271                 /* Next one */
1272                 dev_pe = dev_pe->parent;
1273         }
1274
1275         return 0;
1276 }
1277
1278 /**
1279  * pnv_eeh_next_error - Retrieve next EEH error to handle
1280  * @pe: Affected PE
1281  *
1282  * The function is expected to be called by EEH core while it gets
1283  * special EEH event (without binding PE). The function calls to
1284  * OPAL APIs for next error to handle. The informational error is
1285  * handled internally by platform. However, the dead IOC, dead PHB,
1286  * fenced PHB and frozen PE should be handled by EEH core eventually.
1287  */
1288 static int pnv_eeh_next_error(struct eeh_pe **pe)
1289 {
1290         struct pci_controller *hose;
1291         struct pnv_phb *phb;
1292         struct eeh_pe *phb_pe, *parent_pe;
1293         __be64 frozen_pe_no;
1294         __be16 err_type, severity;
1295         int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1296         long rc;
1297         int state, ret = EEH_NEXT_ERR_NONE;
1298
1299         /*
1300          * While running here, it's safe to purge the event queue. The
1301          * event should still be masked.
1302          */
1303         eeh_remove_event(NULL, false);
1304
1305         list_for_each_entry(hose, &hose_list, list_node) {
1306                 /*
1307                  * If the subordinate PCI buses of the PHB has been
1308                  * removed or is exactly under error recovery, we
1309                  * needn't take care of it any more.
1310                  */
1311                 phb = hose->private_data;
1312                 phb_pe = eeh_phb_pe_get(hose);
1313                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1314                         continue;
1315
1316                 rc = opal_pci_next_error(phb->opal_id,
1317                                          &frozen_pe_no, &err_type, &severity);
1318                 if (rc != OPAL_SUCCESS) {
1319                         pr_devel("%s: Invalid return value on "
1320                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1321                                  __func__, hose->global_number, rc);
1322                         continue;
1323                 }
1324
1325                 /* If the PHB doesn't have error, stop processing */
1326                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1327                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1328                         pr_devel("%s: No error found on PHB#%x\n",
1329                                  __func__, hose->global_number);
1330                         continue;
1331                 }
1332
1333                 /*
1334                  * Processing the error. We're expecting the error with
1335                  * highest priority reported upon multiple errors on the
1336                  * specific PHB.
1337                  */
1338                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1339                         __func__, be16_to_cpu(err_type),
1340                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1341                         hose->global_number);
1342                 switch (be16_to_cpu(err_type)) {
1343                 case OPAL_EEH_IOC_ERROR:
1344                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1345                                 pr_err("EEH: dead IOC detected\n");
1346                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1347                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1348                                 pr_info("EEH: IOC informative error "
1349                                         "detected\n");
1350                                 pnv_eeh_get_and_dump_hub_diag(hose);
1351                                 ret = EEH_NEXT_ERR_NONE;
1352                         }
1353
1354                         break;
1355                 case OPAL_EEH_PHB_ERROR:
1356                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1357                                 *pe = phb_pe;
1358                                 pr_err("EEH: dead PHB#%x detected, "
1359                                        "location: %s\n",
1360                                         hose->global_number,
1361                                         eeh_pe_loc_get(phb_pe));
1362                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1363                         } else if (be16_to_cpu(severity) ==
1364                                    OPAL_EEH_SEV_PHB_FENCED) {
1365                                 *pe = phb_pe;
1366                                 pr_err("EEH: Fenced PHB#%x detected, "
1367                                        "location: %s\n",
1368                                         hose->global_number,
1369                                         eeh_pe_loc_get(phb_pe));
1370                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1371                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1372                                 pr_info("EEH: PHB#%x informative error "
1373                                         "detected, location: %s\n",
1374                                         hose->global_number,
1375                                         eeh_pe_loc_get(phb_pe));
1376                                 pnv_eeh_get_phb_diag(phb_pe);
1377                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1378                                 ret = EEH_NEXT_ERR_NONE;
1379                         }
1380
1381                         break;
1382                 case OPAL_EEH_PE_ERROR:
1383                         /*
1384                          * If we can't find the corresponding PE, we
1385                          * just try to unfreeze.
1386                          */
1387                         if (pnv_eeh_get_pe(hose,
1388                                 be64_to_cpu(frozen_pe_no), pe)) {
1389                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1390                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1391                                 pr_info("EEH: PHB location: %s\n",
1392                                         eeh_pe_loc_get(phb_pe));
1393
1394                                 /* Dump PHB diag-data */
1395                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1396                                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
1397                                 if (rc == OPAL_SUCCESS)
1398                                         pnv_pci_dump_phb_diag_data(hose,
1399                                                         phb->diag.blob);
1400
1401                                 /* Try best to clear it */
1402                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1403                                         be64_to_cpu(frozen_pe_no),
1404                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1405                                 ret = EEH_NEXT_ERR_NONE;
1406                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1407                                    eeh_pe_passed(*pe)) {
1408                                 ret = EEH_NEXT_ERR_NONE;
1409                         } else {
1410                                 pr_err("EEH: Frozen PE#%x "
1411                                        "on PHB#%x detected\n",
1412                                        (*pe)->addr,
1413                                         (*pe)->phb->global_number);
1414                                 pr_err("EEH: PE location: %s, "
1415                                        "PHB location: %s\n",
1416                                        eeh_pe_loc_get(*pe),
1417                                        eeh_pe_loc_get(phb_pe));
1418                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1419                         }
1420
1421                         break;
1422                 default:
1423                         pr_warn("%s: Unexpected error type %d\n",
1424                                 __func__, be16_to_cpu(err_type));
1425                 }
1426
1427                 /*
1428                  * EEH core will try recover from fenced PHB or
1429                  * frozen PE. In the time for frozen PE, EEH core
1430                  * enable IO path for that before collecting logs,
1431                  * but it ruins the site. So we have to dump the
1432                  * log in advance here.
1433                  */
1434                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1435                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1436                     !((*pe)->state & EEH_PE_ISOLATED)) {
1437                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1438                         pnv_eeh_get_phb_diag(*pe);
1439
1440                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1441                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1442                                                            (*pe)->data);
1443                 }
1444
1445                 /*
1446                  * We probably have the frozen parent PE out there and
1447                  * we need have to handle frozen parent PE firstly.
1448                  */
1449                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1450                         parent_pe = (*pe)->parent;
1451                         while (parent_pe) {
1452                                 /* Hit the ceiling ? */
1453                                 if (parent_pe->type & EEH_PE_PHB)
1454                                         break;
1455
1456                                 /* Frozen parent PE ? */
1457                                 state = eeh_ops->get_state(parent_pe, NULL);
1458                                 if (state > 0 &&
1459                                     (state & active_flags) != active_flags)
1460                                         *pe = parent_pe;
1461
1462                                 /* Next parent level */
1463                                 parent_pe = parent_pe->parent;
1464                         }
1465
1466                         /* We possibly migrate to another PE */
1467                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1468                 }
1469
1470                 /*
1471                  * If we have no errors on the specific PHB or only
1472                  * informative error there, we continue poking it.
1473                  * Otherwise, we need actions to be taken by upper
1474                  * layer.
1475                  */
1476                 if (ret > EEH_NEXT_ERR_INF)
1477                         break;
1478         }
1479
1480         /* Unmask the event */
1481         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1482                 enable_irq(eeh_event_irq);
1483
1484         return ret;
1485 }
1486
1487 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1488 {
1489         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1490         struct pnv_phb *phb;
1491         s64 ret;
1492
1493         if (!edev)
1494                 return -EEXIST;
1495
1496         phb = edev->phb->private_data;
1497         ret = opal_pci_reinit(phb->opal_id,
1498                               OPAL_REINIT_PCI_DEV, edev->config_addr);
1499         if (ret) {
1500                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1501                         __func__, edev->config_addr, ret);
1502                 return -EIO;
1503         }
1504
1505         return 0;
1506 }
1507
1508 static struct eeh_ops pnv_eeh_ops = {
1509         .name                   = "powernv",
1510         .init                   = pnv_eeh_init,
1511         .post_init              = pnv_eeh_post_init,
1512         .probe                  = pnv_eeh_probe,
1513         .set_option             = pnv_eeh_set_option,
1514         .get_pe_addr            = pnv_eeh_get_pe_addr,
1515         .get_state              = pnv_eeh_get_state,
1516         .reset                  = pnv_eeh_reset,
1517         .wait_state             = pnv_eeh_wait_state,
1518         .get_log                = pnv_eeh_get_log,
1519         .configure_bridge       = pnv_eeh_configure_bridge,
1520         .err_inject             = pnv_eeh_err_inject,
1521         .read_config            = pnv_eeh_read_config,
1522         .write_config           = pnv_eeh_write_config,
1523         .next_error             = pnv_eeh_next_error,
1524         .restore_config         = pnv_eeh_restore_config
1525 };
1526
1527 /**
1528  * eeh_powernv_init - Register platform dependent EEH operations
1529  *
1530  * EEH initialization on powernv platform. This function should be
1531  * called before any EEH related functions.
1532  */
1533 static int __init eeh_powernv_init(void)
1534 {
1535         int ret = -EINVAL;
1536
1537         eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
1538         ret = eeh_ops_register(&pnv_eeh_ops);
1539         if (!ret)
1540                 pr_info("EEH: PowerNV platform initialized\n");
1541         else
1542                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1543
1544         return ret;
1545 }
1546 machine_early_initcall(powernv, eeh_powernv_init);