kernel/arch/powerpc/kernel/setup_64.c

   1 /*
   2  *
   3  * Common boot and setup code.
   4  *
   5  * Copyright (C) 2001 PPC64 Team, IBM Corp
   6  *
   7  *      This program is free software; you can redistribute it and/or
   8  *      modify it under the terms of the GNU General Public License
   9  *      as published by the Free Software Foundation; either version
  10  *      2 of the License, or (at your option) any later version.
  11  */
  12
  13 #define DEBUG
  14
  15 #include <linux/export.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/reboot.h>
  21 #include <linux/delay.h>
  22 #include <linux/initrd.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/ioport.h>
  25 #include <linux/console.h>
  26 #include <linux/utsname.h>
  27 #include <linux/tty.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/notifier.h>
  30 #include <linux/cpu.h>
  31 #include <linux/unistd.h>
  32 #include <linux/serial.h>
  33 #include <linux/serial_8250.h>
  34 #include <linux/bootmem.h>
  35 #include <linux/pci.h>
  36 #include <linux/lockdep.h>
  37 #include <linux/memblock.h>
  38 #include <linux/hugetlb.h>
  39 #include <linux/memory.h>
  40 #include <linux/nmi.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/kdump.h>
  44 #include <asm/prom.h>
  45 #include <asm/processor.h>
  46 #include <asm/pgtable.h>
  47 #include <asm/smp.h>
  48 #include <asm/elf.h>
  49 #include <asm/machdep.h>
  50 #include <asm/paca.h>
  51 #include <asm/time.h>
  52 #include <asm/cputable.h>
  53 #include <asm/sections.h>
  54 #include <asm/btext.h>
  55 #include <asm/nvram.h>
  56 #include <asm/setup.h>
  57 #include <asm/rtas.h>
  58 #include <asm/iommu.h>
  59 #include <asm/serial.h>
  60 #include <asm/cache.h>
  61 #include <asm/page.h>
  62 #include <asm/mmu.h>
  63 #include <asm/firmware.h>
  64 #include <asm/xmon.h>
  65 #include <asm/udbg.h>
  66 #include <asm/kexec.h>
  67 #include <asm/mmu_context.h>
  68 #include <asm/code-patching.h>
  69 #include <asm/kvm_ppc.h>
  70 #include <asm/hugetlb.h>
  71 #include <asm/epapr_hcalls.h>
  72
  73 #ifdef DEBUG
  74 #define DBG(fmt...) udbg_printf(fmt)
  75 #else
  76 #define DBG(fmt...)
  77 #endif
  78
  79 int spinning_secondaries;
  80 u64 ppc64_pft_size;
  81
  82 /* Pick defaults since we might want to patch instructions
  83  * before we've read this from the device tree.
  84  */
  85 struct ppc64_caches ppc64_caches = {
  86         .dline_size = 0x40,
  87         .log_dline_size = 6,
  88         .iline_size = 0x40,
  89         .log_iline_size = 6
  90 };
  91 EXPORT_SYMBOL_GPL(ppc64_caches);
  92
  93 /*
  94  * These are used in binfmt_elf.c to put aux entries on the stack
  95  * for each elf executable being started.
  96  */
  97 int dcache_bsize;
  98 int icache_bsize;
  99 int ucache_bsize;
 100
 101 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
 102 static void setup_tlb_core_data(void)
 103 {
 104         int cpu;
 105
 106         BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
 107
 108         for_each_possible_cpu(cpu) {
 109                 int first = cpu_first_thread_sibling(cpu);
 110
 111                 paca[cpu].tcd_ptr = &paca[first].tcd;
 112
 113                 /*
 114                  * If we have threads, we need either tlbsrx.
 115                  * or e6500 tablewalk mode, or else TLB handlers
 116                  * will be racy and could produce duplicate entries.
 117                  */
 118                 if (smt_enabled_at_boot >= 2 &&
 119                     !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
 120                     book3e_htw_mode != PPC_HTW_E6500) {
 121                         /* Should we panic instead? */
 122                         WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
 123                                   __func__);
 124                 }
 125         }
 126 }
 127 #else
 128 static void setup_tlb_core_data(void)
 129 {
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_SMP
 134
 135 static char *smt_enabled_cmdline;
 136
 137 /* Look for ibm,smt-enabled OF option */
 138 static void check_smt_enabled(void)
 139 {
 140         struct device_node *dn;
 141         const char *smt_option;
 142
 143         /* Default to enabling all threads */
 144         smt_enabled_at_boot = threads_per_core;
 145
 146         /* Allow the command line to overrule the OF option */
 147         if (smt_enabled_cmdline) {
 148                 if (!strcmp(smt_enabled_cmdline, "on"))
 149                         smt_enabled_at_boot = threads_per_core;
 150                 else if (!strcmp(smt_enabled_cmdline, "off"))
 151                         smt_enabled_at_boot = 0;
 152                 else {
 153                         int smt;
 154                         int rc;
 155
 156                         rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
 157                         if (!rc)
 158                                 smt_enabled_at_boot =
 159                                         min(threads_per_core, smt);
 160                 }
 161         } else {
 162                 dn = of_find_node_by_path("/options");
 163                 if (dn) {
 164                         smt_option = of_get_property(dn, "ibm,smt-enabled",
 165                                                      NULL);
 166
 167                         if (smt_option) {
 168                                 if (!strcmp(smt_option, "on"))
 169                                         smt_enabled_at_boot = threads_per_core;
 170                                 else if (!strcmp(smt_option, "off"))
 171                                         smt_enabled_at_boot = 0;
 172                         }
 173
 174                         of_node_put(dn);
 175                 }
 176         }
 177 }
 178
 179 /* Look for smt-enabled= cmdline option */
 180 static int __init early_smt_enabled(char *p)
 181 {
 182         smt_enabled_cmdline = p;
 183         return 0;
 184 }
 185 early_param("smt-enabled", early_smt_enabled);
 186
 187 #else
 188 #define check_smt_enabled()
 189 #endif /* CONFIG_SMP */
 190
 191 /** Fix up paca fields required for the boot cpu */
 192 static void fixup_boot_paca(void)
 193 {
 194         /* The boot cpu is started */
 195         get_paca()->cpu_start = 1;
 196         /* Allow percpu accesses to work until we setup percpu data */
 197         get_paca()->data_offset = 0;
 198 }
 199
 200 static void cpu_ready_for_interrupts(void)
 201 {
 202         /* Set IR and DR in PACA MSR */
 203         get_paca()->kernel_msr = MSR_KERNEL;
 204
 205         /*
 206          * Enable AIL if supported, and we are in hypervisor mode. If we are
 207          * not in hypervisor mode, we enable relocation-on interrupts later
 208          * in pSeries_setup_arch() using the H_SET_MODE hcall.
 209          */
 210         if (cpu_has_feature(CPU_FTR_HVMODE) &&
 211             cpu_has_feature(CPU_FTR_ARCH_207S)) {
 212                 unsigned long lpcr = mfspr(SPRN_LPCR);
 213                 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
 214         }
 215 }
 216
 217 /*
 218  * Early initialization entry point. This is called by head.S
 219  * with MMU translation disabled. We rely on the "feature" of
 220  * the CPU that ignores the top 2 bits of the address in real
 221  * mode so we can access kernel globals normally provided we
 222  * only toy with things in the RMO region. From here, we do
 223  * some early parsing of the device-tree to setup out MEMBLOCK
 224  * data structures, and allocate & initialize the hash table
 225  * and segment tables so we can start running with translation
 226  * enabled.
 227  *
 228  * It is this function which will call the probe() callback of
 229  * the various platform types and copy the matching one to the
 230  * global ppc_md structure. Your platform can eventually do
 231  * some very early initializations from the probe() routine, but
 232  * this is not recommended, be very careful as, for example, the
 233  * device-tree is not accessible via normal means at this point.
 234  */
 235
 236 void __init early_setup(unsigned long dt_ptr)
 237 {
 238         static __initdata struct paca_struct boot_paca;
 239
 240         /* -------- printk is _NOT_ safe to use here ! ------- */
 241
 242         /* Identify CPU type */
 243         identify_cpu(0, mfspr(SPRN_PVR));
 244
 245         /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
 246         initialise_paca(&boot_paca, 0);
 247         setup_paca(&boot_paca);
 248         fixup_boot_paca();
 249
 250         /* Initialize lockdep early or else spinlocks will blow */
 251         lockdep_init();
 252
 253         /* -------- printk is now safe to use ------- */
 254
 255         /* Enable early debugging if any specified (see udbg.h) */
 256         udbg_early_init();
 257
 258         DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
 259
 260         /*
 261          * Do early initialization using the flattened device
 262          * tree, such as retrieving the physical memory map or
 263          * calculating/retrieving the hash table size.
 264          */
 265         early_init_devtree(__va(dt_ptr));
 266
 267         epapr_paravirt_early_init();
 268
 269         /* Now we know the logical id of our boot cpu, setup the paca. */
 270         setup_paca(&paca[boot_cpuid]);
 271         fixup_boot_paca();
 272
 273         /* Probe the machine type */
 274         probe_machine();
 275
 276         setup_kdump_trampoline();
 277
 278         DBG("Found, Initializing memory management...\n");
 279
 280         /* Initialize the hash table or TLB handling */
 281         early_init_mmu();
 282
 283         /*
 284          * At this point, we can let interrupts switch to virtual mode
 285          * (the MMU has been setup), so adjust the MSR in the PACA to
 286          * have IR and DR set and enable AIL if it exists
 287          */
 288         cpu_ready_for_interrupts();
 289
 290         /* Reserve large chunks of memory for use by CMA for KVM */
 291         kvm_cma_reserve();
 292
 293         /*
 294          * Reserve any gigantic pages requested on the command line.
 295          * memblock needs to have been initialized by the time this is
 296          * called since this will reserve memory.
 297          */
 298         reserve_hugetlb_gpages();
 299
 300         DBG(" <- early_setup()\n");
 301
 302 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
 303         /*
 304          * This needs to be done *last* (after the above DBG() even)
 305          *
 306          * Right after we return from this function, we turn on the MMU
 307          * which means the real-mode access trick that btext does will
 308          * no longer work, it needs to switch to using a real MMU
 309          * mapping. This call will ensure that it does
 310          */
 311         btext_map();
 312 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
 313 }
 314
 315 #ifdef CONFIG_SMP
 316 void early_setup_secondary(void)
 317 {
 318         /* Mark interrupts enabled in PACA */
 319         get_paca()->soft_enabled = 0;
 320
 321         /* Initialize the hash table or TLB handling */
 322         early_init_mmu_secondary();
 323
 324         /*
 325          * At this point, we can let interrupts switch to virtual mode
 326          * (the MMU has been setup), so adjust the MSR in the PACA to
 327          * have IR and DR set.
 328          */
 329         cpu_ready_for_interrupts();
 330 }
 331
 332 #endif /* CONFIG_SMP */
 333
 334 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 335 void smp_release_cpus(void)
 336 {
 337         unsigned long *ptr;
 338         int i;
 339
 340         DBG(" -> smp_release_cpus()\n");
 341
 342         /* All secondary cpus are spinning on a common spinloop, release them
 343          * all now so they can start to spin on their individual paca
 344          * spinloops. For non SMP kernels, the secondary cpus never get out
 345          * of the common spinloop.
 346          */
 347
 348         ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
 349                         - PHYSICAL_START);
 350         *ptr = ppc_function_entry(generic_secondary_smp_init);
 351
 352         /* And wait a bit for them to catch up */
 353         for (i = 0; i < 100000; i++) {
 354                 mb();
 355                 HMT_low();
 356                 if (spinning_secondaries == 0)
 357                         break;
 358                 udelay(1);
 359         }
 360         DBG("spinning_secondaries = %d\n", spinning_secondaries);
 361
 362         DBG(" <- smp_release_cpus()\n");
 363 }
 364 #endif /* CONFIG_SMP || CONFIG_KEXEC */
 365
 366 /*
 367  * Initialize some remaining members of the ppc64_caches and systemcfg
 368  * structures
 369  * (at least until we get rid of them completely). This is mostly some
 370  * cache informations about the CPU that will be used by cache flush
 371  * routines and/or provided to userland
 372  */
 373 static void __init initialize_cache_info(void)
 374 {
 375         struct device_node *np;
 376         unsigned long num_cpus = 0;
 377
 378         DBG(" -> initialize_cache_info()\n");
 379
 380         for_each_node_by_type(np, "cpu") {
 381                 num_cpus += 1;
 382
 383                 /*
 384                  * We're assuming *all* of the CPUs have the same
 385                  * d-cache and i-cache sizes... -Peter
 386                  */
 387                 if (num_cpus == 1) {
 388                         const __be32 *sizep, *lsizep;
 389                         u32 size, lsize;
 390
 391                         size = 0;
 392                         lsize = cur_cpu_spec->dcache_bsize;
 393                         sizep = of_get_property(np, "d-cache-size", NULL);
 394                         if (sizep != NULL)
 395                                 size = be32_to_cpu(*sizep);
 396                         lsizep = of_get_property(np, "d-cache-block-size",
 397                                                  NULL);
 398                         /* fallback if block size missing */
 399                         if (lsizep == NULL)
 400                                 lsizep = of_get_property(np,
 401                                                          "d-cache-line-size",
 402                                                          NULL);
 403                         if (lsizep != NULL)
 404                                 lsize = be32_to_cpu(*lsizep);
 405                         if (sizep == NULL || lsizep == NULL)
 406                                 DBG("Argh, can't find dcache properties ! "
 407                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 408
 409                         ppc64_caches.dsize = size;
 410                         ppc64_caches.dline_size = lsize;
 411                         ppc64_caches.log_dline_size = __ilog2(lsize);
 412                         ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
 413
 414                         size = 0;
 415                         lsize = cur_cpu_spec->icache_bsize;
 416                         sizep = of_get_property(np, "i-cache-size", NULL);
 417                         if (sizep != NULL)
 418                                 size = be32_to_cpu(*sizep);
 419                         lsizep = of_get_property(np, "i-cache-block-size",
 420                                                  NULL);
 421                         if (lsizep == NULL)
 422                                 lsizep = of_get_property(np,
 423                                                          "i-cache-line-size",
 424                                                          NULL);
 425                         if (lsizep != NULL)
 426                                 lsize = be32_to_cpu(*lsizep);
 427                         if (sizep == NULL || lsizep == NULL)
 428                                 DBG("Argh, can't find icache properties ! "
 429                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 430
 431                         ppc64_caches.isize = size;
 432                         ppc64_caches.iline_size = lsize;
 433                         ppc64_caches.log_iline_size = __ilog2(lsize);
 434                         ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
 435                 }
 436         }
 437
 438         DBG(" <- initialize_cache_info()\n");
 439 }
 440
 441
 442 /*
 443  * Do some initial setup of the system.  The parameters are those which
 444  * were passed in from the bootloader.
 445  */
 446 void __init setup_system(void)
 447 {
 448         DBG(" -> setup_system()\n");
 449
 450         /* Apply the CPUs-specific and firmware specific fixups to kernel
 451          * text (nop out sections not relevant to this CPU or this firmware)
 452          */
 453         do_feature_fixups(cur_cpu_spec->cpu_features,
 454                           &__start___ftr_fixup, &__stop___ftr_fixup);
 455         do_feature_fixups(cur_cpu_spec->mmu_features,
 456                           &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
 457         do_feature_fixups(powerpc_firmware_features,
 458                           &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
 459         do_lwsync_fixups(cur_cpu_spec->cpu_features,
 460                          &__start___lwsync_fixup, &__stop___lwsync_fixup);
 461         do_final_fixups();
 462
 463         /*
 464          * Unflatten the device-tree passed by prom_init or kexec
 465          */
 466         unflatten_device_tree();
 467
 468         /*
 469          * Fill the ppc64_caches & systemcfg structures with informations
 470          * retrieved from the device-tree.
 471          */
 472         initialize_cache_info();
 473
 474 #ifdef CONFIG_PPC_RTAS
 475         /*
 476          * Initialize RTAS if available
 477          */
 478         rtas_initialize();
 479 #endif /* CONFIG_PPC_RTAS */
 480
 481         /*
 482          * Check if we have an initrd provided via the device-tree
 483          */
 484         check_for_initrd();
 485
 486         /*
 487          * Do some platform specific early initializations, that includes
 488          * setting up the hash table pointers. It also sets up some interrupt-mapping
 489          * related options that will be used by finish_device_tree()
 490          */
 491         if (ppc_md.init_early)
 492                 ppc_md.init_early();
 493
 494         /*
 495          * We can discover serial ports now since the above did setup the
 496          * hash table management for us, thus ioremap works. We do that early
 497          * so that further code can be debugged
 498          */
 499         find_legacy_serial_ports();
 500
 501         /*
 502          * Register early console
 503          */
 504         register_early_udbg_console();
 505
 506         /*
 507          * Initialize xmon
 508          */
 509         xmon_setup();
 510
 511         smp_setup_cpu_maps();
 512         check_smt_enabled();
 513         setup_tlb_core_data();
 514
 515         /*
 516          * Freescale Book3e parts spin in a loop provided by firmware,
 517          * so smp_release_cpus() does nothing for them
 518          */
 519 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E)
 520         /* Release secondary cpus out of their spinloops at 0x60 now that
 521          * we can map physical -> logical CPU ids
 522          */
 523         smp_release_cpus();
 524 #endif
 525
 526         pr_info("Starting Linux PPC64 %s\n", init_utsname()->version);
 527
 528         pr_info("-----------------------------------------------------\n");
 529         pr_info("ppc64_pft_size    = 0x%llx\n", ppc64_pft_size);
 530         pr_info("phys_mem_size     = 0x%llx\n", memblock_phys_mem_size());
 531
 532         if (ppc64_caches.dline_size != 0x80)
 533                 pr_info("dcache_line_size  = 0x%x\n", ppc64_caches.dline_size);
 534         if (ppc64_caches.iline_size != 0x80)
 535                 pr_info("icache_line_size  = 0x%x\n", ppc64_caches.iline_size);
 536
 537         pr_info("cpu_features      = 0x%016lx\n", cur_cpu_spec->cpu_features);
 538         pr_info("  possible        = 0x%016lx\n", CPU_FTRS_POSSIBLE);
 539         pr_info("  always          = 0x%016lx\n", CPU_FTRS_ALWAYS);
 540         pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
 541                 cur_cpu_spec->cpu_user_features2);
 542         pr_info("mmu_features      = 0x%08x\n", cur_cpu_spec->mmu_features);
 543         pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
 544
 545 #ifdef CONFIG_PPC_STD_MMU_64
 546         if (htab_address)
 547                 pr_info("htab_address      = 0x%p\n", htab_address);
 548
 549         pr_info("htab_hash_mask    = 0x%lx\n", htab_hash_mask);
 550 #endif
 551
 552         if (PHYSICAL_START > 0)
 553                 pr_info("physical_start    = 0x%llx\n",
 554                        (unsigned long long)PHYSICAL_START);
 555         pr_info("-----------------------------------------------------\n");
 556
 557         DBG(" <- setup_system()\n");
 558 }
 559
 560 /* This returns the limit below which memory accesses to the linear
 561  * mapping are guarnateed not to cause a TLB or SLB miss. This is
 562  * used to allocate interrupt or emergency stacks for which our
 563  * exception entry path doesn't deal with being interrupted.
 564  */
 565 static u64 safe_stack_limit(void)
 566 {
 567 #ifdef CONFIG_PPC_BOOK3E
 568         /* Freescale BookE bolts the entire linear mapping */
 569         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 570                 return linear_map_top;
 571         /* Other BookE, we assume the first GB is bolted */
 572         return 1ul << 30;
 573 #else
 574         /* BookS, the first segment is bolted */
 575         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
 576                 return 1UL << SID_SHIFT_1T;
 577         return 1UL << SID_SHIFT;
 578 #endif
 579 }
 580
 581 static void __init irqstack_early_init(void)
 582 {
 583         u64 limit = safe_stack_limit();
 584         unsigned int i;
 585
 586         /*
 587          * Interrupt stacks must be in the first segment since we
 588          * cannot afford to take SLB misses on them.
 589          */
 590         for_each_possible_cpu(i) {
 591                 softirq_ctx[i] = (struct thread_info *)
 592                         __va(memblock_alloc_base(THREAD_SIZE,
 593                                             THREAD_SIZE, limit));
 594                 hardirq_ctx[i] = (struct thread_info *)
 595                         __va(memblock_alloc_base(THREAD_SIZE,
 596                                             THREAD_SIZE, limit));
 597         }
 598 }
 599
 600 #ifdef CONFIG_PPC_BOOK3E
 601 static void __init exc_lvl_early_init(void)
 602 {
 603         unsigned int i;
 604         unsigned long sp;
 605
 606         for_each_possible_cpu(i) {
 607                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 608                 critirq_ctx[i] = (struct thread_info *)__va(sp);
 609                 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
 610
 611                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 612                 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
 613                 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
 614
 615                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 616                 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
 617                 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
 618         }
 619
 620         if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 621                 patch_exception(0x040, exc_debug_debug_book3e);
 622 }
 623 #else
 624 #define exc_lvl_early_init()
 625 #endif
 626
 627 /*
 628  * Stack space used when we detect a bad kernel stack pointer, and
 629  * early in SMP boots before relocation is enabled. Exclusive emergency
 630  * stack for machine checks.
 631  */
 632 static void __init emergency_stack_init(void)
 633 {
 634         u64 limit;
 635         unsigned int i;
 636
 637         /*
 638          * Emergency stacks must be under 256MB, we cannot afford to take
 639          * SLB misses on them. The ABI also requires them to be 128-byte
 640          * aligned.
 641          *
 642          * Since we use these as temporary stacks during secondary CPU
 643          * bringup, we need to get at them in real mode. This means they
 644          * must also be within the RMO region.
 645          */
 646         limit = min(safe_stack_limit(), ppc64_rma_size);
 647
 648         for_each_possible_cpu(i) {
 649                 unsigned long sp;
 650                 sp  = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
 651                 sp += THREAD_SIZE;
 652                 paca[i].emergency_sp = __va(sp);
 653
 654 #ifdef CONFIG_PPC_BOOK3S_64
 655                 /* emergency stack for machine check exception handling. */
 656                 sp  = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
 657                 sp += THREAD_SIZE;
 658                 paca[i].mc_emergency_sp = __va(sp);
 659 #endif
 660         }
 661 }
 662
 663 /*
 664  * Called into from start_kernel this initializes memblock, which is used
 665  * to manage page allocation until mem_init is called.
 666  */
 667 void __init setup_arch(char **cmdline_p)
 668 {
 669         *cmdline_p = boot_command_line;
 670
 671         /*
 672          * Set cache line size based on type of cpu as a default.
 673          * Systems with OF can look in the properties on the cpu node(s)
 674          * for a possibly more accurate value.
 675          */
 676         dcache_bsize = ppc64_caches.dline_size;
 677         icache_bsize = ppc64_caches.iline_size;
 678
 679         if (ppc_md.panic)
 680                 setup_panic();
 681
 682         init_mm.start_code = (unsigned long)_stext;
 683         init_mm.end_code = (unsigned long) _etext;
 684         init_mm.end_data = (unsigned long) _edata;
 685         init_mm.brk = klimit;
 686 #ifdef CONFIG_PPC_64K_PAGES
 687         init_mm.context.pte_frag = NULL;
 688 #endif
 689         irqstack_early_init();
 690         exc_lvl_early_init();
 691         emergency_stack_init();
 692
 693         initmem_init();
 694
 695 #ifdef CONFIG_DUMMY_CONSOLE
 696         conswitchp = &dummy_con;
 697 #endif
 698
 699         if (ppc_md.setup_arch)
 700                 ppc_md.setup_arch();
 701
 702         paging_init();
 703
 704         /* Initialize the MMU context management stuff */
 705         mmu_context_init();
 706
 707         /* Interrupt code needs to be 64K-aligned */
 708         if ((unsigned long)_stext & 0xffff)
 709                 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
 710                       (unsigned long)_stext);
 711 }
 712
 713 #ifdef CONFIG_SMP
 714 #define PCPU_DYN_SIZE           ()
 715
 716 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
 717 {
 718         return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
 719                                     __pa(MAX_DMA_ADDRESS));
 720 }
 721
 722 static void __init pcpu_fc_free(void *ptr, size_t size)
 723 {
 724         free_bootmem(__pa(ptr), size);
 725 }
 726
 727 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
 728 {
 729         if (cpu_to_node(from) == cpu_to_node(to))
 730                 return LOCAL_DISTANCE;
 731         else
 732                 return REMOTE_DISTANCE;
 733 }
 734
 735 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
 736 EXPORT_SYMBOL(__per_cpu_offset);
 737
 738 void __init setup_per_cpu_areas(void)
 739 {
 740         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
 741         size_t atom_size;
 742         unsigned long delta;
 743         unsigned int cpu;
 744         int rc;
 745
 746         /*
 747          * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
 748          * to group units.  For larger mappings, use 1M atom which
 749          * should be large enough to contain a number of units.
 750          */
 751         if (mmu_linear_psize == MMU_PAGE_4K)
 752                 atom_size = PAGE_SIZE;
 753         else
 754                 atom_size = 1 << 20;
 755
 756         rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
 757                                     pcpu_fc_alloc, pcpu_fc_free);
 758         if (rc < 0)
 759                 panic("cannot initialize percpu area (err=%d)", rc);
 760
 761         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
 762         for_each_possible_cpu(cpu) {
 763                 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
 764                 paca[cpu].data_offset = __per_cpu_offset[cpu];
 765         }
 766 }
 767 #endif
 768
 769 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
 770 unsigned long memory_block_size_bytes(void)
 771 {
 772         if (ppc_md.memory_block_size)
 773                 return ppc_md.memory_block_size();
 774
 775         return MIN_MEMORY_BLOCK_SIZE;
 776 }
 777 #endif
 778
 779 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
 780 struct ppc_pci_io ppc_pci_io;
 781 EXPORT_SYMBOL(ppc_pci_io);
 782 #endif
 783
 784 #ifdef CONFIG_HARDLOCKUP_DETECTOR
 785 u64 hw_nmi_get_sample_period(int watchdog_thresh)
 786 {
 787         return ppc_proc_freq * watchdog_thresh;
 788 }
 789
 790 /*
 791  * The hardlockup detector breaks PMU event based branches and is likely
 792  * to get false positives in KVM guests, so disable it by default.
 793  */
 794 static int __init disable_hardlockup_detector(void)
 795 {
 796         hardlockup_detector_disable();
 797
 798         return 0;
 799 }
 800 early_initcall(disable_hardlockup_detector);
 801 #endif