2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
33 #ifndef CONFIG_PREEMPT_RT_FULL
34 _GLOBAL(call_do_softirq)
37 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
49 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
59 .tc ppc64_caches[TC],ppc64_caches
63 * Write any modified data cache blocks out to memory
64 * and invalidate the corresponding instruction cache blocks.
66 * flush_icache_range(unsigned long start, unsigned long stop)
68 * flush all bytes from start through stop-1 inclusive
71 _KPROBE(flush_icache_range)
75 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
77 * Flush the data cache to memory
79 * Different systems have different cache line sizes
80 * and in some cases i-cache and d-cache line sizes differ from
83 ld r10,PPC64_CACHES@toc(r2)
84 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
86 andc r6,r3,r5 /* round low to line bdy */
87 subf r8,r6,r4 /* compute length */
88 add r8,r8,r5 /* ensure we get enough */
89 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
90 srw. r8,r8,r9 /* compute line count */
91 beqlr /* nothing to do? */
98 /* Now invalidate the instruction cache */
100 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
102 andc r6,r3,r5 /* round low to line bdy */
103 subf r8,r6,r4 /* compute length */
105 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
106 srw. r8,r8,r9 /* compute line count */
107 beqlr /* nothing to do? */
116 * Like above, but only do the D-cache.
118 * flush_dcache_range(unsigned long start, unsigned long stop)
120 * flush all bytes from start to stop-1 inclusive
122 _GLOBAL(flush_dcache_range)
125 * Flush the data cache to memory
127 * Different systems have different cache line sizes
129 ld r10,PPC64_CACHES@toc(r2)
130 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
132 andc r6,r3,r5 /* round low to line bdy */
133 subf r8,r6,r4 /* compute length */
134 add r8,r8,r5 /* ensure we get enough */
135 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
136 srw. r8,r8,r9 /* compute line count */
137 beqlr /* nothing to do? */
146 * Like above, but works on non-mapped physical addresses.
147 * Use only for non-LPAR setups ! It also assumes real mode
148 * is cacheable. Used for flushing out the DART before using
149 * it as uncacheable memory
151 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
153 * flush all bytes from start to stop-1 inclusive
155 _GLOBAL(flush_dcache_phys_range)
156 ld r10,PPC64_CACHES@toc(r2)
157 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
159 andc r6,r3,r5 /* round low to line bdy */
160 subf r8,r6,r4 /* compute length */
161 add r8,r8,r5 /* ensure we get enough */
162 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
163 srw. r8,r8,r9 /* compute line count */
164 beqlr /* nothing to do? */
165 mfmsr r5 /* Disable MMU Data Relocation */
178 mtmsr r5 /* Re-enable MMU Data Relocation */
183 _GLOBAL(flush_inval_dcache_range)
184 ld r10,PPC64_CACHES@toc(r2)
185 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
187 andc r6,r3,r5 /* round low to line bdy */
188 subf r8,r6,r4 /* compute length */
189 add r8,r8,r5 /* ensure we get enough */
190 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
191 srw. r8,r8,r9 /* compute line count */
192 beqlr /* nothing to do? */
205 * Flush a particular page from the data cache to RAM.
206 * Note: this is necessary because the instruction cache does *not*
207 * snoop from the data cache.
209 * void __flush_dcache_icache(void *page)
211 _GLOBAL(__flush_dcache_icache)
213 * Flush the data cache to memory
215 * Different systems have different cache line sizes
221 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
223 /* Flush the dcache */
224 ld r7,PPC64_CACHES@toc(r2)
225 clrrdi r3,r3,PAGE_SHIFT /* Page align */
226 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
227 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
235 /* Now invalidate the icache */
237 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
238 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
248 rlwinm r7,r3,8,0xffffffff
250 rlwinm r9,r8,8,0xffffffff
251 rlwimi r7,r3,24,16,23
253 rlwimi r9,r8,24,16,23
259 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
289 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
291 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
294 * Do an IO access in real mode
325 * Do an IO access in real mode
354 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
356 #ifdef CONFIG_PPC_PASEMI
358 _GLOBAL(real_205_readb)
373 _GLOBAL(real_205_writeb)
388 #endif /* CONFIG_PPC_PASEMI */
391 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
393 * SCOM access functions for 970 (FX only for now)
395 * unsigned long scom970_read(unsigned int address);
396 * void scom970_write(unsigned int address, unsigned long value);
398 * The address passed in is the 24 bits register address. This code
399 * is 970 specific and will not check the status bits, so you should
400 * know what you are doing.
402 _GLOBAL(scom970_read)
409 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
410 * (including parity). On current CPUs they must be 0'd,
411 * and finally or in RW bit
416 /* do the actual scom read */
425 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
426 * that's the best we can do). Not implemented yet as we don't use
427 * the scom on any of the bogus CPUs yet, but may have to be done
431 /* restore interrupts */
436 _GLOBAL(scom970_write)
443 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
444 * (including parity). On current CPUs they must be 0'd.
450 mtspr SPRN_SCOMD,r4 /* write data */
452 mtspr SPRN_SCOMC,r3 /* write command */
457 /* restore interrupts */
460 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
462 /* kexec_wait(phys_cpu)
464 * wait for the flag to change, indicating this kernel is going away but
465 * the slave code for the next one is at addresses 0 to 100.
467 * This is used by all slaves, even those that did not find a matching
468 * paca in the secondary startup code.
470 * Physical (hardware) cpu id should be in r3.
475 addi r5,r5,kexec_flag-1b
478 #ifdef CONFIG_KEXEC /* use no memory without kexec */
482 #ifdef CONFIG_PPC_BOOK3S_64
485 clrrdi r11,r11,1 /* Clear MSR_LE */
490 /* Create TLB entry in book3e_secondary_core_init */
496 /* this can be in text because we won't change it until we are
497 * running in real anyways
504 #ifdef CONFIG_PPC_BOOK3E
506 * BOOK3E has no real MMU mode, so we have to setup the initial TLB
507 * for a core to identity map v:0 to p:0. This current implementation
508 * assumes that 1G is enough for kexec.
512 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
513 * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
519 mfspr r10,SPRN_TLB1CFG
520 andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
521 subi r10,r10,1 /* Last entry: no conflict with kernel text */
522 lis r9,MAS0_TLBSEL(1)@h
523 rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
525 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
526 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
527 #define M_IF_NEEDED MAS2_M
529 #define M_IF_NEEDED 0
533 lis r9,(MAS1_VALID|MAS1_IPROT)@h
534 ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
537 LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
540 LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
550 /* kexec_smp_wait(void)
552 * call with interrupts off
553 * note: this is a terminal routine, it does not save lr
555 * get phys id from paca
556 * switch to real mode
557 * mark the paca as no longer used
558 * join other cpus in kexec_wait(phys_id)
560 _GLOBAL(kexec_smp_wait)
561 lhz r3,PACAHWCPUID(r13)
564 li r4,KEXEC_STATE_REAL_MODE
565 stb r4,PACAKEXECSTATE(r13)
571 * switch to real mode (turn mmu off)
572 * we use the early kernel trick that the hardware ignores bits
573 * 0 and 1 (big endian) of the effective address in real mode
575 * don't overwrite r3 here, it is live for kexec_wait above.
577 real_mode: /* assume normal blr return */
578 #ifdef CONFIG_PPC_BOOK3E
579 /* Create an identity mapping. */
584 mflr r11 /* return address to SRR0 */
596 * kexec_sequence(newstack, start, image, control, clear_all())
598 * does the grungy work with stack switching and real mode switches
599 * also does simple calls to other code
602 _GLOBAL(kexec_sequence)
606 /* switch stacks to newstack -- &kexec_stack.stack */
607 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
613 /* save regs for local vars on new stack.
614 * yes, we won't go back, but ...
624 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
626 /* save args into preserved regs */
627 mr r31,r3 /* newstack (both) */
628 mr r30,r4 /* start (real) */
629 mr r29,r5 /* image (virt) */
630 mr r28,r6 /* control, unused */
631 mr r27,r7 /* clear_all() fn desc */
632 mr r26,r8 /* spare */
633 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
635 /* disable interrupts, we are overwriting kernel data next */
636 #ifdef CONFIG_PPC_BOOK3E
644 /* copy dest pages, flush whole dest image */
646 bl kexec_copy_flush /* (image) */
651 /* copy 0x100 bytes starting at start to 0 */
653 mr r4,r30 /* start, aka phys mem offset */
656 bl copy_and_flush /* (dest, src, copy limit, start offset) */
657 1: /* assume normal blr return */
659 /* release other cpus to the new kernel secondary start at 0x60 */
662 stw r6,kexec_flag-1b(5)
664 #ifndef CONFIG_PPC_BOOK3E
665 /* clear out hardware hash page table and tlb */
666 #if !defined(_CALL_ELF) || _CALL_ELF != 2
667 ld r12,0(r27) /* deref function descriptor */
672 bctrl /* ppc_md.hpte_clear_all(void); */
673 #endif /* !CONFIG_PPC_BOOK3E */
676 * kexec image calling is:
677 * the first 0x100 bytes of the entry point are copied to 0
679 * all slaves branch to slave = 0x60 (absolute)
680 * slave(phys_cpu_id);
682 * master goes to start = entry point
683 * start(phys_cpu_id, start, 0);
686 * a wrapper is needed to call existing kernels, here is an approximate
687 * description of one method:
690 * start will be near the boot_block (maybe 0x100 bytes before it?)
691 * it will have a 0x60, which will b to boot_block, where it will wait
692 * and 0 will store phys into struct boot-block and load r3 from there,
693 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
696 * boot block will have all cpus scanning device tree to see if they
697 * are the boot cpu ?????
698 * other device tree differences (prop sizes, va vs pa, etc)...
700 mr r3,r25 # my phys cpu
701 mr r4,r30 # start, aka phys mem offset
704 blr /* image->start(physid, image->start, 0); */
705 #endif /* CONFIG_KEXEC */
707 #ifdef CONFIG_MODULES
708 #if defined(_CALL_ELF) && _CALL_ELF == 2
710 #ifdef CONFIG_MODVERSIONS
712 .section "___kcrctab+TOC.","a"
713 .globl __kcrctab_TOC.
719 * Export a fake .TOC. since both modpost and depmod will complain otherwise.
720 * Both modpost and depmod strip the leading . so we do the same here.
722 .section "__ksymtab_strings","a"
726 .section "___ksymtab+TOC.","a"
727 /* This symbol name is important: it's used by modpost to find exported syms */
728 .globl __ksymtab_TOC.
730 .llong 0 /* .value */
731 .llong __kstrtab_TOC.