kernel/arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * OPAL API definitions.
   3  *
   4  * Copyright 2011-2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_EMPTY              -16
  35 #define OPAL_I2C_TIMEOUT        -17
  36 #define OPAL_I2C_INVALID_CMD    -18
  37 #define OPAL_I2C_LBUS_PARITY    -19
  38 #define OPAL_I2C_BKEND_OVERRUN  -20
  39 #define OPAL_I2C_BKEND_ACCESS   -21
  40 #define OPAL_I2C_ARBT_LOST      -22
  41 #define OPAL_I2C_NACK_RCVD      -23
  42 #define OPAL_I2C_STOP_ERR       -24
  43
  44 /* API Tokens (in r0) */
  45 #define OPAL_INVALID_CALL                      -1
  46 #define OPAL_TEST                               0
  47 #define OPAL_CONSOLE_WRITE                      1
  48 #define OPAL_CONSOLE_READ                       2
  49 #define OPAL_RTC_READ                           3
  50 #define OPAL_RTC_WRITE                          4
  51 #define OPAL_CEC_POWER_DOWN                     5
  52 #define OPAL_CEC_REBOOT                         6
  53 #define OPAL_READ_NVRAM                         7
  54 #define OPAL_WRITE_NVRAM                        8
  55 #define OPAL_HANDLE_INTERRUPT                   9
  56 #define OPAL_POLL_EVENTS                        10
  57 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  58 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  59 #define OPAL_PCI_CONFIG_READ_BYTE               13
  60 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  61 #define OPAL_PCI_CONFIG_READ_WORD               15
  62 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  64 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  65 #define OPAL_SET_XIVE                           19
  66 #define OPAL_GET_XIVE                           20
  67 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  69 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  70 #define OPAL_PCI_SHPC                           24
  71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  72 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  73 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  74 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  77 #define OPAL_PCI_SET_PE                         31
  78 #define OPAL_PCI_SET_PELTV                      32
  79 #define OPAL_PCI_SET_MVE                        33
  80 #define OPAL_PCI_SET_MVE_ENABLE                 34
  81 #define OPAL_PCI_GET_XIVE_REISSUE               35
  82 #define OPAL_PCI_SET_XIVE_REISSUE               36
  83 #define OPAL_PCI_SET_XIVE_PE                    37
  84 #define OPAL_GET_XIVE_SOURCE                    38
  85 #define OPAL_GET_MSI_32                         39
  86 #define OPAL_GET_MSI_64                         40
  87 #define OPAL_START_CPU                          41
  88 #define OPAL_QUERY_CPU_STATUS                   42
  89 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
  90 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  92 #define OPAL_PCI_RESET                          49
  93 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  94 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  95 #define OPAL_PCI_FENCE_PHB                      52
  96 #define OPAL_PCI_REINIT                         53
  97 #define OPAL_PCI_MASK_PE_ERROR                  54
  98 #define OPAL_SET_SLOT_LED_STATUS                55
  99 #define OPAL_GET_EPOW_STATUS                    56
 100 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 101 #define OPAL_RESERVED1                          58
 102 #define OPAL_RESERVED2                          59
 103 #define OPAL_PCI_NEXT_ERROR                     60
 104 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 105 #define OPAL_PCI_POLL                           62
 106 #define OPAL_PCI_MSI_EOI                        63
 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 108 #define OPAL_XSCOM_READ                         65
 109 #define OPAL_XSCOM_WRITE                        66
 110 #define OPAL_LPC_READ                           67
 111 #define OPAL_LPC_WRITE                          68
 112 #define OPAL_RETURN_CPU                         69
 113 #define OPAL_REINIT_CPUS                        70
 114 #define OPAL_ELOG_READ                          71
 115 #define OPAL_ELOG_WRITE                         72
 116 #define OPAL_ELOG_ACK                           73
 117 #define OPAL_ELOG_RESEND                        74
 118 #define OPAL_ELOG_SIZE                          75
 119 #define OPAL_FLASH_VALIDATE                     76
 120 #define OPAL_FLASH_MANAGE                       77
 121 #define OPAL_FLASH_UPDATE                       78
 122 #define OPAL_RESYNC_TIMEBASE                    79
 123 #define OPAL_CHECK_TOKEN                        80
 124 #define OPAL_DUMP_INIT                          81
 125 #define OPAL_DUMP_INFO                          82
 126 #define OPAL_DUMP_READ                          83
 127 #define OPAL_DUMP_ACK                           84
 128 #define OPAL_GET_MSG                            85
 129 #define OPAL_CHECK_ASYNC_COMPLETION             86
 130 #define OPAL_SYNC_HOST_REBOOT                   87
 131 #define OPAL_SENSOR_READ                        88
 132 #define OPAL_GET_PARAM                          89
 133 #define OPAL_SET_PARAM                          90
 134 #define OPAL_DUMP_RESEND                        91
 135 #define OPAL_ELOG_SEND                          92      /* Deprecated */
 136 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
 137 #define OPAL_DUMP_INFO2                         94
 138 #define OPAL_WRITE_OPPANEL_ASYNC                95
 139 #define OPAL_PCI_ERR_INJECT                     96
 140 #define OPAL_PCI_EEH_FREEZE_SET                 97
 141 #define OPAL_HANDLE_HMI                         98
 142 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 143 #define OPAL_SLW_SET_REG                        100
 144 #define OPAL_REGISTER_DUMP_REGION               101
 145 #define OPAL_UNREGISTER_DUMP_REGION             102
 146 #define OPAL_WRITE_TPO                          103
 147 #define OPAL_READ_TPO                           104
 148 #define OPAL_GET_DPO_STATUS                     105
 149 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
 150 #define OPAL_IPMI_SEND                          107
 151 #define OPAL_IPMI_RECV                          108
 152 #define OPAL_I2C_REQUEST                        109
 153 #define OPAL_FLASH_READ                         110
 154 #define OPAL_FLASH_WRITE                        111
 155 #define OPAL_FLASH_ERASE                        112
 156 #define OPAL_LAST                               112
 157
 158 /* Device tree flags */
 159
 160 /* Flags set in power-mgmt nodes in device tree if
 161  * respective idle states are supported in the platform.
 162  */
 163 #define OPAL_PM_NAP_ENABLED             0x00010000
 164 #define OPAL_PM_SLEEP_ENABLED           0x00020000
 165 #define OPAL_PM_WINKLE_ENABLED          0x00040000
 166 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
 167
 168 #ifndef __ASSEMBLY__
 169
 170 /* Other enums */
 171 enum OpalFreezeState {
 172         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 173         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 174         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 175         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 176         OPAL_EEH_STOPPED_RESET = 4,
 177         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 178         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 179 };
 180
 181 enum OpalEehFreezeActionToken {
 182         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 183         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 184         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 185
 186         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 187         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 188         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 189 };
 190
 191 enum OpalPciStatusToken {
 192         OPAL_EEH_NO_ERROR       = 0,
 193         OPAL_EEH_IOC_ERROR      = 1,
 194         OPAL_EEH_PHB_ERROR      = 2,
 195         OPAL_EEH_PE_ERROR       = 3,
 196         OPAL_EEH_PE_MMIO_ERROR  = 4,
 197         OPAL_EEH_PE_DMA_ERROR   = 5
 198 };
 199
 200 enum OpalPciErrorSeverity {
 201         OPAL_EEH_SEV_NO_ERROR   = 0,
 202         OPAL_EEH_SEV_IOC_DEAD   = 1,
 203         OPAL_EEH_SEV_PHB_DEAD   = 2,
 204         OPAL_EEH_SEV_PHB_FENCED = 3,
 205         OPAL_EEH_SEV_PE_ER      = 4,
 206         OPAL_EEH_SEV_INF        = 5
 207 };
 208
 209 enum OpalErrinjectType {
 210         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 211         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 212 };
 213
 214 enum OpalErrinjectFunc {
 215         /* IOA bus specific errors */
 216         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 217         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 218         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 219         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 220         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 221         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 222         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 223         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 224         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 225         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 226         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 227         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 228         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 229         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 230         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 231         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 232         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 233         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 234         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 235         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 236 };
 237
 238 enum OpalMmioWindowType {
 239         OPAL_M32_WINDOW_TYPE = 1,
 240         OPAL_M64_WINDOW_TYPE = 2,
 241         OPAL_IO_WINDOW_TYPE  = 3
 242 };
 243
 244 enum OpalExceptionHandler {
 245         OPAL_MACHINE_CHECK_HANDLER          = 1,
 246         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 247         OPAL_SOFTPATCH_HANDLER              = 3
 248 };
 249
 250 enum OpalPendingState {
 251         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
 252         OPAL_EVENT_NVRAM           = 0x2,
 253         OPAL_EVENT_RTC             = 0x4,
 254         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
 255         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
 256         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 257         OPAL_EVENT_ERROR_LOG       = 0x40,
 258         OPAL_EVENT_EPOW            = 0x80,
 259         OPAL_EVENT_LED_STATUS      = 0x100,
 260         OPAL_EVENT_PCI_ERROR       = 0x200,
 261         OPAL_EVENT_DUMP_AVAIL      = 0x400,
 262         OPAL_EVENT_MSG_PENDING     = 0x800,
 263 };
 264
 265 enum OpalThreadStatus {
 266         OPAL_THREAD_INACTIVE = 0x0,
 267         OPAL_THREAD_STARTED = 0x1,
 268         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 269 };
 270
 271 enum OpalPciBusCompare {
 272         OpalPciBusAny   = 0,    /* Any bus number match */
 273         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 274         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 275         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 276         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 277         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 278         OpalPciBusAll   = 7,    /* Match bus number exactly */
 279 };
 280
 281 enum OpalDeviceCompare {
 282         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 283         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 284 };
 285
 286 enum OpalFuncCompare {
 287         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 288         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 289 };
 290
 291 enum OpalPeAction {
 292         OPAL_UNMAP_PE = 0,
 293         OPAL_MAP_PE = 1
 294 };
 295
 296 enum OpalPeltvAction {
 297         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 298         OPAL_ADD_PE_TO_DOMAIN = 1
 299 };
 300
 301 enum OpalMveEnableAction {
 302         OPAL_DISABLE_MVE = 0,
 303         OPAL_ENABLE_MVE = 1
 304 };
 305
 306 enum OpalM64Action {
 307         OPAL_DISABLE_M64 = 0,
 308         OPAL_ENABLE_M64_SPLIT = 1,
 309         OPAL_ENABLE_M64_NON_SPLIT = 2
 310 };
 311
 312 enum OpalPciResetScope {
 313         OPAL_RESET_PHB_COMPLETE         = 1,
 314         OPAL_RESET_PCI_LINK             = 2,
 315         OPAL_RESET_PHB_ERROR            = 3,
 316         OPAL_RESET_PCI_HOT              = 4,
 317         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 318         OPAL_RESET_PCI_IODA_TABLE       = 6
 319 };
 320
 321 enum OpalPciReinitScope {
 322         /*
 323          * Note: we chose values that do not overlap
 324          * OpalPciResetScope as OPAL v2 used the same
 325          * enum for both
 326          */
 327         OPAL_REINIT_PCI_DEV = 1000
 328 };
 329
 330 enum OpalPciResetState {
 331         OPAL_DEASSERT_RESET = 0,
 332         OPAL_ASSERT_RESET   = 1
 333 };
 334
 335 /*
 336  * Address cycle types for LPC accesses. These also correspond
 337  * to the content of the first cell of the "reg" property for
 338  * device nodes on the LPC bus
 339  */
 340 enum OpalLPCAddressType {
 341         OPAL_LPC_MEM    = 0,
 342         OPAL_LPC_IO     = 1,
 343         OPAL_LPC_FW     = 2,
 344 };
 345
 346 enum opal_msg_type {
 347         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 348                                          * additional params function-specific
 349                                          */
 350         OPAL_MSG_MEM_ERR,
 351         OPAL_MSG_EPOW,
 352         OPAL_MSG_SHUTDOWN,              /* params[0] = 1 reboot, 0 shutdown */
 353         OPAL_MSG_HMI_EVT,
 354         OPAL_MSG_DPO,
 355         OPAL_MSG_TYPE_MAX,
 356 };
 357
 358 struct opal_msg {
 359         __be32 msg_type;
 360         __be32 reserved;
 361         __be64 params[8];
 362 };
 363
 364 /* System parameter permission */
 365 enum OpalSysparamPerm {
 366         OPAL_SYSPARAM_READ  = 0x1,
 367         OPAL_SYSPARAM_WRITE = 0x2,
 368         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 369 };
 370
 371 enum {
 372         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 373 };
 374
 375 struct opal_ipmi_msg {
 376         uint8_t version;
 377         uint8_t netfn;
 378         uint8_t cmd;
 379         uint8_t data[];
 380 };
 381
 382 /* FSP memory errors handling */
 383 enum OpalMemErr_Version {
 384         OpalMemErr_V1 = 1,
 385 };
 386
 387 enum OpalMemErrType {
 388         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 389         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 390 };
 391
 392 /* Memory Reilience error type */
 393 enum OpalMemErr_ResilErrType {
 394         OPAL_MEM_RESILIENCE_CE          = 0,
 395         OPAL_MEM_RESILIENCE_UE,
 396         OPAL_MEM_RESILIENCE_UE_SCRUB,
 397 };
 398
 399 /* Dynamic Memory Deallocation type */
 400 enum OpalMemErr_DynErrType {
 401         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 402 };
 403
 404 struct OpalMemoryErrorData {
 405         enum OpalMemErr_Version version:8;      /* 0x00 */
 406         enum OpalMemErrType     type:8;         /* 0x01 */
 407         __be16                  flags;          /* 0x02 */
 408         uint8_t                 reserved_1[4];  /* 0x04 */
 409
 410         union {
 411                 /* Memory Resilience corrected/uncorrected error info */
 412                 struct {
 413                         enum OpalMemErr_ResilErrType    resil_err_type:8;
 414                         uint8_t                         reserved_1[7];
 415                         __be64                          physical_address_start;
 416                         __be64                          physical_address_end;
 417                 } resilience;
 418                 /* Dynamic memory deallocation error info */
 419                 struct {
 420                         enum OpalMemErr_DynErrType      dyn_err_type:8;
 421                         uint8_t                         reserved_1[7];
 422                         __be64                          physical_address_start;
 423                         __be64                          physical_address_end;
 424                 } dyn_dealloc;
 425         } u;
 426 };
 427
 428 /* HMI interrupt event */
 429 enum OpalHMI_Version {
 430         OpalHMIEvt_V1 = 1,
 431 };
 432
 433 enum OpalHMI_Severity {
 434         OpalHMI_SEV_NO_ERROR = 0,
 435         OpalHMI_SEV_WARNING = 1,
 436         OpalHMI_SEV_ERROR_SYNC = 2,
 437         OpalHMI_SEV_FATAL = 3,
 438 };
 439
 440 enum OpalHMI_Disposition {
 441         OpalHMI_DISPOSITION_RECOVERED = 0,
 442         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 443 };
 444
 445 enum OpalHMI_ErrType {
 446         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 447         OpalHMI_ERROR_PROC_RECOV_DONE,
 448         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 449         OpalHMI_ERROR_PROC_RECOV_MASKED,
 450         OpalHMI_ERROR_TFAC,
 451         OpalHMI_ERROR_TFMR_PARITY,
 452         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 453         OpalHMI_ERROR_XSCOM_FAIL,
 454         OpalHMI_ERROR_XSCOM_DONE,
 455         OpalHMI_ERROR_SCOM_FIR,
 456         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 457         OpalHMI_ERROR_HYP_RESOURCE,
 458         OpalHMI_ERROR_CAPP_RECOVERY,
 459 };
 460
 461 struct OpalHMIEvent {
 462         uint8_t         version;        /* 0x00 */
 463         uint8_t         severity;       /* 0x01 */
 464         uint8_t         type;           /* 0x02 */
 465         uint8_t         disposition;    /* 0x03 */
 466         uint8_t         reserved_1[4];  /* 0x04 */
 467
 468         __be64          hmer;
 469         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 470         __be64          tfmr;
 471 };
 472
 473 enum {
 474         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 475         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 476         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 477         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 478         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 479         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 480         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 481 };
 482
 483 struct OpalIoP7IOCErrorData {
 484         __be16 type;
 485
 486         /* GEM */
 487         __be64 gemXfir;
 488         __be64 gemRfir;
 489         __be64 gemRirqfir;
 490         __be64 gemMask;
 491         __be64 gemRwof;
 492
 493         /* LEM */
 494         __be64 lemFir;
 495         __be64 lemErrMask;
 496         __be64 lemAction0;
 497         __be64 lemAction1;
 498         __be64 lemWof;
 499
 500         union {
 501                 struct OpalIoP7IOCRgcErrorData {
 502                         __be64 rgcStatus;       /* 3E1C10 */
 503                         __be64 rgcLdcp;         /* 3E1C18 */
 504                 }rgc;
 505                 struct OpalIoP7IOCBiErrorData {
 506                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 507                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 508                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 509                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 510
 511                         uint8_t biDownbound;    /* BI Downbound or Upbound */
 512                 }bi;
 513                 struct OpalIoP7IOCCiErrorData {
 514                         __be64 ciPortStatus;    /* 3Dn008 */
 515                         __be64 ciPortLdcp;      /* 3Dn010 */
 516
 517                         uint8_t ciPort;         /* Index of CI port: 0/1 */
 518                 }ci;
 519         };
 520 };
 521
 522 /**
 523  * This structure defines the overlay which will be used to store PHB error
 524  * data upon request.
 525  */
 526 enum {
 527         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 528 };
 529
 530 enum {
 531         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 532         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 533 };
 534
 535 enum {
 536         OPAL_P7IOC_NUM_PEST_REGS = 128,
 537         OPAL_PHB3_NUM_PEST_REGS = 256
 538 };
 539
 540 struct OpalIoPhbErrorCommon {
 541         __be32 version;
 542         __be32 ioType;
 543         __be32 len;
 544 };
 545
 546 struct OpalIoP7IOCPhbErrorData {
 547         struct OpalIoPhbErrorCommon common;
 548
 549         __be32 brdgCtl;
 550
 551         // P7IOC utl regs
 552         __be32 portStatusReg;
 553         __be32 rootCmplxStatus;
 554         __be32 busAgentStatus;
 555
 556         // P7IOC cfg regs
 557         __be32 deviceStatus;
 558         __be32 slotStatus;
 559         __be32 linkStatus;
 560         __be32 devCmdStatus;
 561         __be32 devSecStatus;
 562
 563         // cfg AER regs
 564         __be32 rootErrorStatus;
 565         __be32 uncorrErrorStatus;
 566         __be32 corrErrorStatus;
 567         __be32 tlpHdr1;
 568         __be32 tlpHdr2;
 569         __be32 tlpHdr3;
 570         __be32 tlpHdr4;
 571         __be32 sourceId;
 572
 573         __be32 rsv3;
 574
 575         // Record data about the call to allocate a buffer.
 576         __be64 errorClass;
 577         __be64 correlator;
 578
 579         //P7IOC MMIO Error Regs
 580         __be64 p7iocPlssr;                // n120
 581         __be64 p7iocCsr;                  // n110
 582         __be64 lemFir;                    // nC00
 583         __be64 lemErrorMask;              // nC18
 584         __be64 lemWOF;                    // nC40
 585         __be64 phbErrorStatus;            // nC80
 586         __be64 phbFirstErrorStatus;       // nC88
 587         __be64 phbErrorLog0;              // nCC0
 588         __be64 phbErrorLog1;              // nCC8
 589         __be64 mmioErrorStatus;           // nD00
 590         __be64 mmioFirstErrorStatus;      // nD08
 591         __be64 mmioErrorLog0;             // nD40
 592         __be64 mmioErrorLog1;             // nD48
 593         __be64 dma0ErrorStatus;           // nD80
 594         __be64 dma0FirstErrorStatus;      // nD88
 595         __be64 dma0ErrorLog0;             // nDC0
 596         __be64 dma0ErrorLog1;             // nDC8
 597         __be64 dma1ErrorStatus;           // nE00
 598         __be64 dma1FirstErrorStatus;      // nE08
 599         __be64 dma1ErrorLog0;             // nE40
 600         __be64 dma1ErrorLog1;             // nE48
 601         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 602         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 603 };
 604
 605 struct OpalIoPhb3ErrorData {
 606         struct OpalIoPhbErrorCommon common;
 607
 608         __be32 brdgCtl;
 609
 610         /* PHB3 UTL regs */
 611         __be32 portStatusReg;
 612         __be32 rootCmplxStatus;
 613         __be32 busAgentStatus;
 614
 615         /* PHB3 cfg regs */
 616         __be32 deviceStatus;
 617         __be32 slotStatus;
 618         __be32 linkStatus;
 619         __be32 devCmdStatus;
 620         __be32 devSecStatus;
 621
 622         /* cfg AER regs */
 623         __be32 rootErrorStatus;
 624         __be32 uncorrErrorStatus;
 625         __be32 corrErrorStatus;
 626         __be32 tlpHdr1;
 627         __be32 tlpHdr2;
 628         __be32 tlpHdr3;
 629         __be32 tlpHdr4;
 630         __be32 sourceId;
 631
 632         __be32 rsv3;
 633
 634         /* Record data about the call to allocate a buffer */
 635         __be64 errorClass;
 636         __be64 correlator;
 637
 638         /* PHB3 MMIO Error Regs */
 639         __be64 nFir;                    /* 000 */
 640         __be64 nFirMask;                /* 003 */
 641         __be64 nFirWOF;         /* 008 */
 642         __be64 phbPlssr;                /* 120 */
 643         __be64 phbCsr;          /* 110 */
 644         __be64 lemFir;          /* C00 */
 645         __be64 lemErrorMask;            /* C18 */
 646         __be64 lemWOF;          /* C40 */
 647         __be64 phbErrorStatus;  /* C80 */
 648         __be64 phbFirstErrorStatus;     /* C88 */
 649         __be64 phbErrorLog0;            /* CC0 */
 650         __be64 phbErrorLog1;            /* CC8 */
 651         __be64 mmioErrorStatus; /* D00 */
 652         __be64 mmioFirstErrorStatus;    /* D08 */
 653         __be64 mmioErrorLog0;           /* D40 */
 654         __be64 mmioErrorLog1;           /* D48 */
 655         __be64 dma0ErrorStatus; /* D80 */
 656         __be64 dma0FirstErrorStatus;    /* D88 */
 657         __be64 dma0ErrorLog0;           /* DC0 */
 658         __be64 dma0ErrorLog1;           /* DC8 */
 659         __be64 dma1ErrorStatus; /* E00 */
 660         __be64 dma1FirstErrorStatus;    /* E08 */
 661         __be64 dma1ErrorLog0;           /* E40 */
 662         __be64 dma1ErrorLog1;           /* E48 */
 663         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 664         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 665 };
 666
 667 enum {
 668         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 669         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 670 };
 671
 672 typedef struct oppanel_line {
 673         __be64 line;
 674         __be64 line_len;
 675 } oppanel_line_t;
 676
 677 /*
 678  * SG entries
 679  *
 680  * WARNING: The current implementation requires each entry
 681  * to represent a block that is 4k aligned *and* each block
 682  * size except the last one in the list to be as well.
 683  */
 684 struct opal_sg_entry {
 685         __be64 data;
 686         __be64 length;
 687 };
 688
 689 /*
 690  * Candiate image SG list.
 691  *
 692  * length = VER | length
 693  */
 694 struct opal_sg_list {
 695         __be64 length;
 696         __be64 next;
 697         struct opal_sg_entry entry[];
 698 };
 699
 700 /*
 701  * Dump region ID range usable by the OS
 702  */
 703 #define OPAL_DUMP_REGION_HOST_START             0x80
 704 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 705 #define OPAL_DUMP_REGION_HOST_END               0xFF
 706
 707 /* CAPI modes for PHB */
 708 enum {
 709         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 710         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 711         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 712         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 713 };
 714
 715 /* OPAL I2C request */
 716 struct opal_i2c_request {
 717         uint8_t type;
 718 #define OPAL_I2C_RAW_READ       0
 719 #define OPAL_I2C_RAW_WRITE      1
 720 #define OPAL_I2C_SM_READ        2
 721 #define OPAL_I2C_SM_WRITE       3
 722         uint8_t flags;
 723 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
 724         uint8_t subaddr_sz;             /* Max 4 */
 725         uint8_t reserved;
 726         __be16 addr;                    /* 7 or 10 bit address */
 727         __be16 reserved2;
 728         __be32 subaddr;         /* Sub-address if any */
 729         __be32 size;                    /* Data size */
 730         __be64 buffer_ra;               /* Buffer real address */
 731 };
 732
 733 #endif /* __ASSEMBLY__ */
 734
 735 #endif /* __OPAL_API_H */