kernel/arch/powerpc/boot/dts/tqm8548-bigflash.dts

   1 /*
   2  * TQM8548 Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /dts-v1/;
  14
  15 / {
  16         model = "tqc,tqm8548";
  17         compatible = "tqc,tqm8548";
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 ethernet0 = &enet0;
  23                 ethernet1 = &enet1;
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 PowerPC,8548@0 {
  38                         device_type = "cpu";
  39                         reg = <0>;
  40                         d-cache-line-size = <32>;       // 32 bytes
  41                         i-cache-line-size = <32>;       // 32 bytes
  42                         d-cache-size = <0x8000>;        // L1, 32K
  43                         i-cache-size = <0x8000>;        // L1, 32K
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x00000000 0x00000000>;  // Filled in by U-Boot
  51         };
  52
  53         soc@a0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 ranges = <0x0 0xa0000000 0x100000>;
  58                 bus-frequency = <0>;
  59                 compatible = "fsl,mpc8548-immr", "simple-bus";
  60
  61                 ecm-law@0 {
  62                         compatible = "fsl,ecm-law";
  63                         reg = <0x0 0x1000>;
  64                         fsl,num-laws = <10>;
  65                 };
  66
  67                 ecm@1000 {
  68                         compatible = "fsl,mpc8548-ecm", "fsl,ecm";
  69                         reg = <0x1000 0x1000>;
  70                         interrupts = <17 2>;
  71                         interrupt-parent = <&mpic>;
  72                 };
  73
  74                 memory-controller@2000 {
  75                         compatible = "fsl,mpc8548-memory-controller";
  76                         reg = <0x2000 0x1000>;
  77                         interrupt-parent = <&mpic>;
  78                         interrupts = <18 2>;
  79                 };
  80
  81                 L2: l2-cache-controller@20000 {
  82                         compatible = "fsl,mpc8548-l2-cache-controller";
  83                         reg = <0x20000 0x1000>;
  84                         cache-line-size = <32>; // 32 bytes
  85                         cache-size = <0x80000>; // L2, 512K
  86                         interrupt-parent = <&mpic>;
  87                         interrupts = <16 2>;
  88                 };
  89
  90                 i2c@3000 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         cell-index = <0>;
  94                         compatible = "fsl-i2c";
  95                         reg = <0x3000 0x100>;
  96                         interrupts = <43 2>;
  97                         interrupt-parent = <&mpic>;
  98                         dfsrr;
  99
 100                         dtt@48 {
 101                                 compatible = "national,lm75";
 102                                 reg = <0x48>;
 103                         };
 104
 105                         rtc@68 {
 106                                 compatible = "dallas,ds1337";
 107                                 reg = <0x68>;
 108                         };
 109                 };
 110
 111                 i2c@3100 {
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         cell-index = <1>;
 115                         compatible = "fsl-i2c";
 116                         reg = <0x3100 0x100>;
 117                         interrupts = <43 2>;
 118                         interrupt-parent = <&mpic>;
 119                         dfsrr;
 120                 };
 121
 122                 dma@21300 {
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 126                         reg = <0x21300 0x4>;
 127                         ranges = <0x0 0x21100 0x200>;
 128                         cell-index = <0>;
 129                         dma-channel@0 {
 130                                 compatible = "fsl,mpc8548-dma-channel",
 131                                                 "fsl,eloplus-dma-channel";
 132                                 reg = <0x0 0x80>;
 133                                 cell-index = <0>;
 134                                 interrupt-parent = <&mpic>;
 135                                 interrupts = <20 2>;
 136                         };
 137                         dma-channel@80 {
 138                                 compatible = "fsl,mpc8548-dma-channel",
 139                                                 "fsl,eloplus-dma-channel";
 140                                 reg = <0x80 0x80>;
 141                                 cell-index = <1>;
 142                                 interrupt-parent = <&mpic>;
 143                                 interrupts = <21 2>;
 144                         };
 145                         dma-channel@100 {
 146                                 compatible = "fsl,mpc8548-dma-channel",
 147                                                 "fsl,eloplus-dma-channel";
 148                                 reg = <0x100 0x80>;
 149                                 cell-index = <2>;
 150                                 interrupt-parent = <&mpic>;
 151                                 interrupts = <22 2>;
 152                         };
 153                         dma-channel@180 {
 154                                 compatible = "fsl,mpc8548-dma-channel",
 155                                                 "fsl,eloplus-dma-channel";
 156                                 reg = <0x180 0x80>;
 157                                 cell-index = <3>;
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <23 2>;
 160                         };
 161                 };
 162
 163                 enet0: ethernet@24000 {
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         cell-index = <0>;
 167                         device_type = "network";
 168                         model = "eTSEC";
 169                         compatible = "gianfar";
 170                         reg = <0x24000 0x1000>;
 171                         ranges = <0x0 0x24000 0x1000>;
 172                         local-mac-address = [ 00 00 00 00 00 00 ];
 173                         interrupts = <29 2 30 2 34 2>;
 174                         interrupt-parent = <&mpic>;
 175                         tbi-handle = <&tbi0>;
 176                         phy-handle = <&phy2>;
 177
 178                         mdio@520 {
 179                                 #address-cells = <1>;
 180                                 #size-cells = <0>;
 181                                 compatible = "fsl,gianfar-mdio";
 182                                 reg = <0x520 0x20>;
 183
 184                                 phy1: ethernet-phy@0 {
 185                                         interrupt-parent = <&mpic>;
 186                                         interrupts = <8 1>;
 187                                         reg = <1>;
 188                                 };
 189                                 phy2: ethernet-phy@1 {
 190                                         interrupt-parent = <&mpic>;
 191                                         interrupts = <8 1>;
 192                                         reg = <2>;
 193                                 };
 194                                 phy3: ethernet-phy@3 {
 195                                         interrupt-parent = <&mpic>;
 196                                         interrupts = <8 1>;
 197                                         reg = <3>;
 198                                 };
 199                                 phy4: ethernet-phy@4 {
 200                                         interrupt-parent = <&mpic>;
 201                                         interrupts = <8 1>;
 202                                         reg = <4>;
 203                                 };
 204                                 phy5: ethernet-phy@5 {
 205                                         interrupt-parent = <&mpic>;
 206                                         interrupts = <8 1>;
 207                                         reg = <5>;
 208                                 };
 209                                 tbi0: tbi-phy@11 {
 210                                         reg = <0x11>;
 211                                         device_type = "tbi-phy";
 212                                 };
 213                         };
 214                 };
 215
 216                 enet1: ethernet@25000 {
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219                         cell-index = <1>;
 220                         device_type = "network";
 221                         model = "eTSEC";
 222                         compatible = "gianfar";
 223                         reg = <0x25000 0x1000>;
 224                         ranges = <0x0 0x25000 0x1000>;
 225                         local-mac-address = [ 00 00 00 00 00 00 ];
 226                         interrupts = <35 2 36 2 40 2>;
 227                         interrupt-parent = <&mpic>;
 228                         tbi-handle = <&tbi1>;
 229                         phy-handle = <&phy1>;
 230
 231                         mdio@520 {
 232                                 #address-cells = <1>;
 233                                 #size-cells = <0>;
 234                                 compatible = "fsl,gianfar-tbi";
 235                                 reg = <0x520 0x20>;
 236
 237                                 tbi1: tbi-phy@11 {
 238                                         reg = <0x11>;
 239                                         device_type = "tbi-phy";
 240                                 };
 241                         };
 242                 };
 243
 244                 enet2: ethernet@26000 {
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         cell-index = <2>;
 248                         device_type = "network";
 249                         model = "eTSEC";
 250                         compatible = "gianfar";
 251                         reg = <0x26000 0x1000>;
 252                         ranges = <0x0 0x26000 0x1000>;
 253                         local-mac-address = [ 00 00 00 00 00 00 ];
 254                         interrupts = <31 2 32 2 33 2>;
 255                         interrupt-parent = <&mpic>;
 256                         tbi-handle = <&tbi2>;
 257                         phy-handle = <&phy4>;
 258
 259                         mdio@520 {
 260                                 #address-cells = <1>;
 261                                 #size-cells = <0>;
 262                                 compatible = "fsl,gianfar-tbi";
 263                                 reg = <0x520 0x20>;
 264
 265                                 tbi2: tbi-phy@11 {
 266                                         reg = <0x11>;
 267                                         device_type = "tbi-phy";
 268                                 };
 269                         };
 270                 };
 271
 272                 enet3: ethernet@27000 {
 273                         #address-cells = <1>;
 274                         #size-cells = <1>;
 275                         cell-index = <3>;
 276                         device_type = "network";
 277                         model = "eTSEC";
 278                         compatible = "gianfar";
 279                         reg = <0x27000 0x1000>;
 280                         ranges = <0x0 0x27000 0x1000>;
 281                         local-mac-address = [ 00 00 00 00 00 00 ];
 282                         interrupts = <37 2 38 2 39 2>;
 283                         interrupt-parent = <&mpic>;
 284                         tbi-handle = <&tbi3>;
 285                         phy-handle = <&phy5>;
 286
 287                         mdio@520 {
 288                                 #address-cells = <1>;
 289                                 #size-cells = <0>;
 290                                 compatible = "fsl,gianfar-tbi";
 291                                 reg = <0x520 0x20>;
 292
 293                                 tbi3: tbi-phy@11 {
 294                                         reg = <0x11>;
 295                                         device_type = "tbi-phy";
 296                                 };
 297                         };
 298                 };
 299
 300                 serial0: serial@4500 {
 301                         cell-index = <0>;
 302                         device_type = "serial";
 303                         compatible = "fsl,ns16550", "ns16550";
 304                         reg = <0x4500 0x100>;   // reg base, size
 305                         clock-frequency = <0>;  // should we fill in in uboot?
 306                         current-speed = <115200>;
 307                         interrupts = <42 2>;
 308                         interrupt-parent = <&mpic>;
 309                 };
 310
 311                 serial1: serial@4600 {
 312                         cell-index = <1>;
 313                         device_type = "serial";
 314                         compatible = "fsl,ns16550", "ns16550";
 315                         reg = <0x4600 0x100>;   // reg base, size
 316                         clock-frequency = <0>;  // should we fill in in uboot?
 317                         current-speed = <115200>;
 318                         interrupts = <42 2>;
 319                         interrupt-parent = <&mpic>;
 320                 };
 321
 322                 global-utilities@e0000 {        // global utilities reg
 323                         compatible = "fsl,mpc8548-guts";
 324                         reg = <0xe0000 0x1000>;
 325                         fsl,has-rstcr;
 326                 };
 327
 328                 mpic: pic@40000 {
 329                         interrupt-controller;
 330                         #address-cells = <0>;
 331                         #interrupt-cells = <2>;
 332                         reg = <0x40000 0x40000>;
 333                         compatible = "chrp,open-pic";
 334                         device_type = "open-pic";
 335                 };
 336         };
 337
 338         localbus@a0005000 {
 339                 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
 340                              "simple-bus";
 341                 #address-cells = <2>;
 342                 #size-cells = <1>;
 343                 reg = <0xa0005000 0x100>;       // BRx, ORx, etc.
 344                 interrupt-parent = <&mpic>;
 345                 interrupts = <19 2>;
 346
 347                 ranges = <
 348                         0 0x0 0xfc000000 0x04000000     // NOR FLASH bank 1
 349                         1 0x0 0xf8000000 0x08000000     // NOR FLASH bank 0
 350                         2 0x0 0xa3000000 0x00008000     // CAN (2 x CC770)
 351                         3 0x0 0xa3010000 0x00008000     // NAND FLASH
 352
 353                 >;
 354
 355                 flash@1,0 {
 356                         #address-cells = <1>;
 357                         #size-cells = <1>;
 358                         compatible = "cfi-flash";
 359                         reg = <1 0x0 0x8000000>;
 360                         bank-width = <4>;
 361                         device-width = <1>;
 362
 363                         partition@0 {
 364                                 label = "kernel";
 365                                 reg = <0x00000000 0x00200000>;
 366                         };
 367                         partition@200000 {
 368                                 label = "root";
 369                                 reg = <0x00200000 0x00300000>;
 370                         };
 371                         partition@500000 {
 372                                 label = "user";
 373                                 reg = <0x00500000 0x07a00000>;
 374                         };
 375                         partition@7f00000 {
 376                                 label = "env1";
 377                                 reg = <0x07f00000 0x00040000>;
 378                         };
 379                         partition@7f40000 {
 380                                 label = "env2";
 381                                 reg = <0x07f40000 0x00040000>;
 382                         };
 383                         partition@7f80000 {
 384                                 label = "u-boot";
 385                                 reg = <0x07f80000 0x00080000>;
 386                                 read-only;
 387                         };
 388                 };
 389
 390                 /* Note: CAN support needs be enabled in U-Boot */
 391                 can@2,0 {
 392                         compatible = "bosch,cc770"; // Bosch CC770
 393                         reg = <2 0x0 0x100>;
 394                         interrupts = <4 1>;
 395                         interrupt-parent = <&mpic>;
 396                         bosch,external-clock-frequency = <16000000>;
 397                         bosch,disconnect-rx1-input;
 398                         bosch,disconnect-tx1-output;
 399                         bosch,iso-low-speed-mux;
 400                         bosch,clock-out-frequency = <16000000>;
 401                 };
 402
 403                 can@2,100 {
 404                         compatible = "bosch,cc770"; // Bosch CC770
 405                         reg = <2 0x100 0x100>;
 406                         interrupts = <4 1>;
 407                         interrupt-parent = <&mpic>;
 408                         bosch,external-clock-frequency = <16000000>;
 409                         bosch,disconnect-rx1-input;
 410                         bosch,disconnect-tx1-output;
 411                         bosch,iso-low-speed-mux;
 412                 };
 413
 414                 /* Note: NAND support needs to be enabled in U-Boot */
 415                 upm@3,0 {
 416                         #address-cells = <0>;
 417                         #size-cells = <0>;
 418                         compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
 419                         reg = <3 0x0 0x800>;
 420                         fsl,upm-addr-offset = <0x10>;
 421                         fsl,upm-cmd-offset = <0x08>;
 422                         /* Micron MT29F8G08FAB multi-chip device */
 423                         fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
 424                         fsl,upm-wait-flags = <0x5>;
 425                         chip-delay = <25>; // in micro-seconds
 426
 427                         nand@0 {
 428                                 #address-cells = <1>;
 429                                 #size-cells = <1>;
 430
 431                                 partition@0 {
 432                                             label = "fs";
 433                                             reg = <0x00000000 0x10000000>;
 434                                 };
 435                         };
 436                 };
 437         };
 438
 439         pci0: pci@a0008000 {
 440                 #interrupt-cells = <1>;
 441                 #size-cells = <2>;
 442                 #address-cells = <3>;
 443                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 444                 device_type = "pci";
 445                 reg = <0xa0008000 0x1000>;
 446                 clock-frequency = <33333333>;
 447                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 448                 interrupt-map = <
 449                                 /* IDSEL 28 */
 450                                  0xe000 0 0 1 &mpic 2 1
 451                                  0xe000 0 0 2 &mpic 3 1
 452                                  0xe000 0 0 3 &mpic 6 1
 453                                  0xe000 0 0 4 &mpic 5 1
 454
 455                                 /* IDSEL 11 */
 456                                  0x5800 0 0 1 &mpic 6 1
 457                                  0x5800 0 0 2 &mpic 5 1
 458                                  >;
 459
 460                 interrupt-parent = <&mpic>;
 461                 interrupts = <24 2>;
 462                 bus-range = <0 0>;
 463                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
 464                           0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
 465         };
 466
 467         pci1: pcie@a000a000 {
 468                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 469                 interrupt-map = <
 470                         /* IDSEL 0x0 (PEX) */
 471                         0x00000 0 0 1 &mpic 0 1
 472                         0x00000 0 0 2 &mpic 1 1
 473                         0x00000 0 0 3 &mpic 2 1
 474                         0x00000 0 0 4 &mpic 3 1>;
 475
 476                 interrupt-parent = <&mpic>;
 477                 interrupts = <26 2>;
 478                 bus-range = <0 0xff>;
 479                 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
 480                           0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
 481                 clock-frequency = <33333333>;
 482                 #interrupt-cells = <1>;
 483                 #size-cells = <2>;
 484                 #address-cells = <3>;
 485                 reg = <0xa000a000 0x1000>;
 486                 compatible = "fsl,mpc8548-pcie";
 487                 device_type = "pci";
 488                 pcie@0 {
 489                         reg = <0 0 0 0 0>;
 490                         #size-cells = <2>;
 491                         #address-cells = <3>;
 492                         device_type = "pci";
 493                         ranges = <0x02000000 0 0xb0000000 0x02000000 0
 494                                   0xb0000000 0 0x10000000
 495                                   0x01000000 0 0x00000000 0x01000000 0
 496                                   0x00000000 0 0x08000000>;
 497                 };
 498         };
 499 };