kernel/arch/powerpc/boot/dts/t208xqds.dtsi

   1 /*
   2  * T2080/T2081 QDS Device Tree Source
   3  *
   4  * Copyright 2013 - 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 / {
  36         model = "fsl,T2080QDS";
  37         compatible = "fsl,T2080QDS";
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40         interrupt-parent = <&mpic>;
  41
  42         reserved-memory {
  43                 #address-cells = <2>;
  44                 #size-cells = <2>;
  45                 ranges;
  46
  47                 bman_fbpr: bman-fbpr {
  48                         size = <0 0x1000000>;
  49                         alignment = <0 0x1000000>;
  50                 };
  51         };
  52
  53         ifc: localbus@ffe124000 {
  54                 reg = <0xf 0xfe124000 0 0x2000>;
  55                 ranges = <0 0 0xf 0xe8000000 0x08000000
  56                           2 0 0xf 0xff800000 0x00010000
  57                           3 0 0xf 0xffdf0000 0x00008000>;
  58
  59                 nor@0,0 {
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         compatible = "cfi-flash";
  63                         reg = <0x0 0x0 0x8000000>;
  64                         bank-width = <2>;
  65                         device-width = <1>;
  66                 };
  67
  68                 nand@2,0 {
  69                         #address-cells = <1>;
  70                         #size-cells = <1>;
  71                         compatible = "fsl,ifc-nand";
  72                         reg = <0x2 0x0 0x10000>;
  73                 };
  74
  75                 boardctrl: board-control@3,0 {
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         compatible = "fsl,fpga-qixis";
  79                         reg = <3 0 0x300>;
  80                         ranges = <0 3 0 0x300>;
  81                 };
  82         };
  83
  84         memory {
  85                 device_type = "memory";
  86         };
  87
  88         dcsr: dcsr@f00000000 {
  89                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  90         };
  91
  92         bportals: bman-portals@ff4000000 {
  93                 ranges = <0x0 0xf 0xf4000000 0x2000000>;
  94         };
  95
  96         soc: soc@ffe000000 {
  97                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  98                 reg = <0xf 0xfe000000 0 0x00001000>;
  99                 spi@110000 {
 100                         flash@0 {
 101                                 #address-cells = <1>;
 102                                 #size-cells = <1>;
 103                                 compatible = "micron,n25q128a11"; /* 16MB */
 104                                 reg = <0>;
 105                                 spi-max-frequency = <40000000>; /* input clock */
 106                         };
 107
 108                         flash@1 {
 109                                 #address-cells = <1>;
 110                                 #size-cells = <1>;
 111                                 compatible = "sst,sst25wf040";
 112                                 reg = <1>;
 113                                 spi-max-frequency = <35000000>;
 114                         };
 115
 116                         flash@2 {
 117                                 #address-cells = <1>;
 118                                 #size-cells = <1>;
 119                                 compatible = "eon,en25s64";
 120                                 reg = <2>;
 121                                 spi-max-frequency = <35000000>;
 122                         };
 123                 };
 124
 125                 i2c@118000 {
 126                         pca9547@77 {
 127                                 compatible = "nxp,pca9547";
 128                                 reg = <0x77>;
 129                                 #address-cells = <1>;
 130                                 #size-cells = <0>;
 131
 132                                 i2c@0 {
 133                                         #address-cells = <1>;
 134                                         #size-cells = <0>;
 135                                         reg = <0x0>;
 136
 137                                         eeprom@50 {
 138                                                 compatible = "at24,24c512";
 139                                                 reg = <0x50>;
 140                                         };
 141
 142                                         eeprom@51 {
 143                                                 compatible = "at24,24c02";
 144                                                 reg = <0x51>;
 145                                         };
 146
 147                                         eeprom@57 {
 148                                                 compatible = "at24,24c02";
 149                                                 reg = <0x57>;
 150                                         };
 151
 152                                         rtc@68 {
 153                                                 compatible = "dallas,ds3232";
 154                                                 reg = <0x68>;
 155                                                 interrupts = <0xb 0x1 0 0>;
 156                                         };
 157                                 };
 158
 159                                 i2c@1 {
 160                                         #address-cells = <1>;
 161                                         #size-cells = <0>;
 162                                         reg = <0x1>;
 163
 164                                         eeprom@55 {
 165                                                 compatible = "at24,24c02";
 166                                                 reg = <0x55>;
 167                                         };
 168                                 };
 169
 170                                 i2c@2 {
 171                                         #address-cells = <1>;
 172                                         #size-cells = <0>;
 173                                         reg = <0x2>;
 174
 175                                         ina220@40 {
 176                                                 compatible = "ti,ina220";
 177                                                 reg = <0x40>;
 178                                                 shunt-resistor = <1000>;
 179                                         };
 180
 181                                         ina220@41 {
 182                                                 compatible = "ti,ina220";
 183                                                 reg = <0x41>;
 184                                                 shunt-resistor = <1000>;
 185                                         };
 186                                 };
 187
 188                                 i2c@3 {
 189                                         #address-cells = <1>;
 190                                         #size-cells = <0>;
 191                                         reg = <0x3>;
 192
 193                                         adt7461@4c {
 194                                                 compatible = "adi,adt7461";
 195                                                 reg = <0x4c>;
 196                                         };
 197                                 };
 198                         };
 199                 };
 200
 201                 sdhc@114000 {
 202                         voltage-ranges = <1800 1800 3300 3300>;
 203                 };
 204         };
 205
 206         pci0: pcie@ffe240000 {
 207                 reg = <0xf 0xfe240000 0 0x10000>;
 208                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 209                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 210                 pcie@0 {
 211                         ranges = <0x02000000 0 0xe0000000
 212                                   0x02000000 0 0xe0000000
 213                                   0 0x20000000
 214
 215                                   0x01000000 0 0x00000000
 216                                   0x01000000 0 0x00000000
 217                                   0 0x00010000>;
 218                 };
 219         };
 220
 221         pci1: pcie@ffe250000 {
 222                 reg = <0xf 0xfe250000 0 0x10000>;
 223                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
 224                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 225                 pcie@0 {
 226                         ranges = <0x02000000 0 0xe0000000
 227                                   0x02000000 0 0xe0000000
 228                                   0 0x20000000
 229
 230                                   0x01000000 0 0x00000000
 231                                   0x01000000 0 0x00000000
 232                                   0 0x00010000>;
 233                 };
 234         };
 235
 236         pci2: pcie@ffe260000 {
 237                 reg = <0xf 0xfe260000 0 0x1000>;
 238                 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
 239                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 240                 pcie@0 {
 241                         ranges = <0x02000000 0 0xe0000000
 242                                   0x02000000 0 0xe0000000
 243                                   0 0x20000000
 244
 245                                   0x01000000 0 0x00000000
 246                                   0x01000000 0 0x00000000
 247                                   0 0x00010000>;
 248                 };
 249         };
 250
 251         pci3: pcie@ffe270000 {
 252                 reg = <0xf 0xfe270000 0 0x10000>;
 253                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
 254                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 255                 pcie@0 {
 256                         ranges = <0x02000000 0 0xe0000000
 257                                   0x02000000 0 0xe0000000
 258                                   0 0x20000000
 259
 260                                   0x01000000 0 0x00000000
 261                                   0x01000000 0 0x00000000
 262                                   0 0x00010000>;
 263                 };
 264         };
 265 };