kernel/arch/powerpc/boot/dts/p4080ds.dts

   1 /*
   2  * P4080DS Device Tree Source
   3  *
   4  * Copyright 2009 - 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "fsl/p4080si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,P4080DS";
  39         compatible = "fsl,P4080DS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         memory {
  45                 device_type = "memory";
  46         };
  47
  48         reserved-memory {
  49                 #address-cells = <2>;
  50                 #size-cells = <2>;
  51                 ranges;
  52
  53                 bman_fbpr: bman-fbpr {
  54                         size = <0 0x1000000>;
  55                         alignment = <0 0x1000000>;
  56                 };
  57         };
  58
  59         dcsr: dcsr@f00000000 {
  60                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  61         };
  62
  63         bportals: bman-portals@ff4000000 {
  64                 ranges = <0x0 0xf 0xf4000000 0x200000>;
  65         };
  66
  67         soc: soc@ffe000000 {
  68                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  69                 reg = <0xf 0xfe000000 0 0x00001000>;
  70
  71                 spi@110000 {
  72                         flash@0 {
  73                                 #address-cells = <1>;
  74                                 #size-cells = <1>;
  75                                 compatible = "spansion,s25sl12801";
  76                                 reg = <0>;
  77                                 spi-max-frequency = <40000000>; /* input clock */
  78                                 partition@u-boot {
  79                                         label = "u-boot";
  80                                         reg = <0x00000000 0x00100000>;
  81                                         read-only;
  82                                 };
  83                                 partition@kernel {
  84                                         label = "kernel";
  85                                         reg = <0x00100000 0x00500000>;
  86                                         read-only;
  87                                 };
  88                                 partition@dtb {
  89                                         label = "dtb";
  90                                         reg = <0x00600000 0x00100000>;
  91                                         read-only;
  92                                 };
  93                                 partition@fs {
  94                                         label = "file system";
  95                                         reg = <0x00700000 0x00900000>;
  96                                 };
  97                         };
  98                 };
  99
 100                 i2c@118100 {
 101                         eeprom@51 {
 102                                 compatible = "at24,24c256";
 103                                 reg = <0x51>;
 104                         };
 105                         eeprom@52 {
 106                                 compatible = "at24,24c256";
 107                                 reg = <0x52>;
 108                         };
 109                         rtc@68 {
 110                                 compatible = "dallas,ds3232";
 111                                 reg = <0x68>;
 112                                 interrupts = <0x1 0x1 0 0>;
 113                         };
 114                         adt7461@4c {
 115                                 compatible = "adi,adt7461";
 116                                 reg = <0x4c>;
 117                         };
 118                 };
 119
 120                 usb0: usb@210000 {
 121                         phy_type = "ulpi";
 122                 };
 123
 124                 usb1: usb@211000 {
 125                         dr_mode = "host";
 126                         phy_type = "ulpi";
 127                 };
 128         };
 129
 130         rio: rapidio@ffe0c0000 {
 131                 reg = <0xf 0xfe0c0000 0 0x11000>;
 132
 133                 port1 {
 134                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 135                 };
 136                 port2 {
 137                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 138                 };
 139         };
 140
 141         lbc: localbus@ffe124000 {
 142                 reg = <0xf 0xfe124000 0 0x1000>;
 143                 ranges = <0 0 0xf 0xe8000000 0x08000000
 144                           3 0 0xf 0xffdf0000 0x00008000>;
 145
 146                 flash@0,0 {
 147                         compatible = "cfi-flash";
 148                         reg = <0 0 0x08000000>;
 149                         bank-width = <2>;
 150                         device-width = <2>;
 151                 };
 152
 153                 board-control@3,0 {
 154                         compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
 155                         reg = <3 0 0x30>;
 156                 };
 157         };
 158
 159         pci0: pcie@ffe200000 {
 160                 reg = <0xf 0xfe200000 0 0x1000>;
 161                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 162                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 163                 pcie@0 {
 164                         ranges = <0x02000000 0 0xe0000000
 165                                   0x02000000 0 0xe0000000
 166                                   0 0x20000000
 167
 168                                   0x01000000 0 0x00000000
 169                                   0x01000000 0 0x00000000
 170                                   0 0x00010000>;
 171                 };
 172         };
 173
 174         pci1: pcie@ffe201000 {
 175                 reg = <0xf 0xfe201000 0 0x1000>;
 176                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 177                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 178                 pcie@0 {
 179                         ranges = <0x02000000 0 0xe0000000
 180                                   0x02000000 0 0xe0000000
 181                                   0 0x20000000
 182
 183                                   0x01000000 0 0x00000000
 184                                   0x01000000 0 0x00000000
 185                                   0 0x00010000>;
 186                 };
 187         };
 188
 189         pci2: pcie@ffe202000 {
 190                 reg = <0xf 0xfe202000 0 0x1000>;
 191                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 192                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 193                 pcie@0 {
 194                         ranges = <0x02000000 0 0xe0000000
 195                                   0x02000000 0 0xe0000000
 196                                   0 0x20000000
 197
 198                                   0x01000000 0 0x00000000
 199                                   0x01000000 0 0x00000000
 200                                   0 0x00010000>;
 201                 };
 202         };
 203
 204 };
 205
 206 /include/ "fsl/p4080si-post.dtsi"